CMOS device and preparation method thereof
By forming trenches in the N-well and P-well regions of the CMOS device and forming multiple silicon-germanium epitaxial layers, combined with the high-temperature annealing process, the problem that the existing technology cannot simultaneously improve the mobility of PMOS and NMOS transistors is solved, and the synchronous improvement of the performance of CMOS devices is achieved.
Patent Information
- Application Number
- CN202510330823.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-19
- Publication Date
- 2025-06-13
AI Technical Summary
The existing strain process technology cannot simultaneously improve the hole mobility of PMOS transistors and the electron mobility of NMOS transistors, resulting in limited improvement in CMOS device performance.
By forming trenches at different locations in the N-well region and the P-well region, and forming multiple silicon germanium epitaxial layers in the trenches in sequence in combination with multiple epitaxial processes, forming the source and drain of the PMOS transistor, and the active channel layer of the NMOS transistor, and finally performing a high-temperature annealing process to repair the lattice, forming a large extrusion pressure and outward expansion stress.
The synchronous improvement of PMOS and NMOS transistor performance is achieved, significantly improving the channel mobility of PMOS transistors and the channel mobility of NMOS transistors.
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Figure CN120152371A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor integrated circuit manufacturing, and particularly to a CMOS device and a method for manufacturing the same. Background Art
[0002] In the field of semiconductor technology, along the path provided by Moore's Law, people have been using the equal-proportion scaling of CMOS devices to increase device speed. However, as the size of CMOS devices continues to shrink, a series of problems centered around the short-channel effect have emerged in the conventional equal-proportion scaling method. In order to improve the performance of NMOS and PMOS transistors in CMOS devices, strain engineering technology has received increasing attention in the industry.
[0003] The so-called strain engineering technology is to introduce local unidirectional tensile or compressive stress into the conductive channels of NMOS and PMOS transistors, improve the carrier mobility in the conductive channels of NMOS and PMOS transistors, so that the drive current increases significantly when the thickness of the gate dielectric layer becomes thinner or remains unchanged, and finally improve the performance of CMOS devices. Among them, introducing compressive stress into PMOS transistors to increase the mobility of holes is called local unidirectional compressive strain, and introducing tensile stress into NMOS transistors to improve the mobility of electrons is called local unidirectional tensile strain.
[0004] In the existing strain process technology, generally, a silicon nitride thin film layer is deposited to introduce compressive stress and tensile stress, thereby improving the mobility of holes and electrons, and thus improving the performance of NMOS and PMOS transistors. However, it can only improve the performance of a single type of MOS transistor, and correspondingly, it will have a certain negative impact on the other type of MOS transistor, that is, it is impossible to simultaneously improve the channel migration rates of PMOS and NMOS transistors. Summary of the Invention
[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a CMOS device and a method for manufacturing the same, which are used to solve the problem that the existing strain process technology cannot simultaneously improve the hole mobility of PMOS transistors and the electron mobility of NMOS transistors.
[0006] To achieve the above object and other related objects, the present invention provides a method for manufacturing a CMOS device, which at least includes the following steps:
[0007] Provide a substrate, on which a first epitaxial layer, a P-well region and an N-well region located in the first epitaxial layer are formed, and a shallow trench isolation is formed between the P-well region and the N-well region;
[0008] A plurality of first trenches are formed in the N-well region, and second trenches are formed in the P-well region;
[0009] A second epitaxial layer, a third epitaxial layer, and a fourth epitaxial layer are sequentially formed in the first trenches and the second trenches. The source and drain of the PMOS are formed in the first trenches, and the channel region of the NMOS is formed in the second trenches;
[0010] An insulating layer, a gate oxide layer, and a polysilicon gate are formed on the surface of the first epitaxial layer and are located on the NMOS and the PMOS;
[0011] An annealing process treatment at 600 - 1000 °C is performed to form a CMOS device.
[0012] Optionally, the steps of forming the first trenches and the second trenches are as follows: First, an oxide layer is formed on the surface of the first epitaxial layer, and the oxide layer is partially etched to form a first opening and a second opening. Based on the first opening, dry etching and wet etching are performed on the N-well region to form a plurality of first trenches, and based on the second opening, dry etching and wet etching are performed on the P-well region to form second trenches.
[0013] Optionally, the width of the first trenches is less than the width of the second trenches, and the depth of the first trenches is equal to the depth of the second trenches.
[0014] Optionally, the width of the first trenches is 50 - 100 nm, the width of the second trenches is 100 - 200 nm, and the depth of the first trenches and the second trenches is 80 - 100 nm.
[0015] Optionally, the number of the first trenches is two, and the first trenches are symmetrically distributed about the central axis of the N-well region. The number of the second trenches is one, and the central axis of the second trenches coincides with the central axis of the P-well region.
[0016] Optionally, the second epitaxial layer is a boron-doped germanium-silicon layer, wherein the boron doping concentration is 5% - 10%, the germanium concentration is 20%, the thickness of the second epitaxial layer is 10 - 15 nm, and the source and drain of the PMOS and the NMOS are both formed in the second epitaxial layer.
[0017] Optionally, the third epitaxial layer is a boron-doped germanium-silicon layer, wherein the boron doping concentration is 1% - 2%, the germanium concentration is 35% - 50%, and the thickness of the third epitaxial layer is 45 - 50 nm.
[0018] Optionally, the fourth epitaxial layer is a boron-doped silicon-germanium layer, wherein the boron doping concentration is 0.4% - 0.6%, the germanium concentration is 30%, the thickness of the fourth epitaxial layer is 25 - 35 nm, and the fourth epitaxial layer serves as an active channel layer.
[0019] Optionally, the shapes of the first trench and the second trench are Sigma-shaped or rectangular.
[0020] In addition, the present invention also provides a CMOS device formed by using the above-mentioned preparation method of the CMOS device.
[0021] As described above, a CMOS device and a preparation method thereof according to the present invention have the following beneficial effects: compared with the prior art which mainly realizes each functional region of the channel through ion implantation, the present invention forms trenches at different positions in the N-well region and the P-well region, and then combines multiple epitaxial processes to sequentially form multiple silicon-germanium epitaxial layers in the trenches. Among them, the source and drain of the PMOS transistor are formed in the second epitaxial layer, and the active channel layer of the NMOS transistor is formed in the fourth epitaxial layer. Through the high-temperature annealing process, the lattice of the multiple silicon-germanium epitaxial layers is further repaired, so that a large extrusion force is formed in the PMOS transistor, greatly improving the channel mobility of the PMOS transistor. Correspondingly, a large outward expansion stress is formed in the NMOS transistor, greatly improving the channel mobility of the NMOS transistor, realizing the synchronous improvement of the performance of the PMOS and NMOS transistors. Description of the Drawings
[0022] Figure 1 It shows a process flow chart of the preparation method of the CMOS device in the present invention.
[0023] Figures 2 to 10 It shows a schematic diagram of the device structure corresponding to each step of the preparation method of the CMOS device in the embodiment of the present invention.
[0024] Description of Component Labels
[0025] 10. Substrate; 11. First epitaxial layer; 12. N-well region; 13. P-well region; 14. Shallow trench isolation; 15. Oxide layer; 151. First opening; 152. Second opening; 161. First trench; 162. Second trench; 171. Second epitaxial layer; 172. Third epitaxial layer; 173. Fourth epitaxial layer; 18. Intermediate insulating layer; 191. Gate oxide layer; 192. Polysilicon gate; S1 - S5: Steps. Detailed Embodiments
[0026] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0027] When detailing the embodiments of the present invention, for ease of explanation, the schematic diagrams showing the device structure are enlarged locally in a non-general proportion, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention herein. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.
[0028] For convenience of description, spatial relationship terms such as "under", "below", "lower than", "beneath", "above", "on" etc. may be used herein to describe the relationship between an element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to encompass other directions of the device in use or operation, in addition to the directions depicted in the drawings.
[0029] In the context of the present application, the structure in which the first feature is "above" the second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
[0030] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in its actual implementation can be arbitrarily changed, and the component layout type may also be more complex.
[0031] As Figure 1 shown, this embodiment provides a method for fabricating a CMOS device, and the fabrication method includes the following steps:
[0032] S1: Provide a substrate 10, on which a first epitaxial layer 11 is formed, and a P-well region 13 and an N-well region 12 are formed in the first epitaxial layer 11, and a shallow trench isolation 14 is formed between the P-well region 13 and the N-well region 12;
[0033] S2: Form a plurality of first trenches 161 in the N-well region 12, and form second trenches 162 in the P-well region 13;
[0034] S3: Sequentially form a second epitaxial layer 171, a third epitaxial layer 172, and a fourth epitaxial layer 173 in the first trench 161 and the second trench 162, form the source and drain of the PMOS in the first trench 161, and form the channel region of the NMOS in the second trench 162;
[0035] S4: Form an insulating layer on the surface of the substrate 10, and form a gate oxide layer 191 and a polysilicon gate 192 on the NMOS and the PMOS;
[0036] S5: Perform an annealing process at 600 - 1000 °C to form a CMOS device.
[0037] The following further introduces the manufacturing method of the CMOS device in conjunction with the accompanying drawings, specifically as follows:
[0038] In step S1, please refer to Figure 1 and Figure 2 , provide a substrate 10, on which a first epitaxial layer 11, a P-well region 13 and an N-well region 12 located in the first epitaxial layer 11 are formed, and a shallow trench isolation 14 is formed between the P-well region 13 and the N-well region 12.
[0039] As an example, the substrate 10 can be a common silicon substrate 10. In other embodiments, the material of the substrate 10 can also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide or indium gallium arsenide. The substrate 10 provides a process platform for the subsequent formation of the CMOS device. Preferably, as Figure 2 shown, the substrate 10 can be a doped semiconductor substrate 10.
[0040] As Figure 2 shown, a first epitaxial layer 11 is formed on the front surface of the substrate 10 through an epitaxial process, and local ion implantation is performed on the first epitaxial layer 11 to achieve deep well doping, thereby forming a P-well region 13 and an N-well region 12. Specifically, when the doping ions of the first epitaxial layer 11 are P-type ions, such as B, BF2, Ga or In, a P-well region 13 is formed; when the doping ions of the first epitaxial layer 11 are N-type ions, such as P, As or Sb, an N-well region 12 is formed. Among them, the doping concentrations of the substrate 10 and the first epitaxial layer 11 decrease in sequence. For example, the substrate 10 is heavily doped and the first epitaxial layer 11 is lightly doped.
[0041] As Figure 2 shown, a shallow trench isolation 14 is also formed in the first epitaxial layer 11. The shallow trench isolation 14 is used for device isolation. The material for forming the shallow trench isolation 14 can be silicon oxide, and the material for forming the shallow trench isolation 14 can also be silicon nitride or silicon oxynitride.
[0042] Specifically, in this embodiment, a stress buffer layer and a first hard mask layer are first formed on the front surface of the first epitaxial layer 11. The material of the stress buffer layer is silicon dioxide, and its structure is dense, which can buffer the stress concentration problem that may be caused by the direct contact between the first hard mask layer and the substrate 10, and protect the substrate 10 from damage. The first hard mask layer can be formed by using processes well-known in the art, including but not limited to chemical vapor deposition process or atomic layer deposition process. Then, the patterned first shielding layer is formed on the first hard mask layer, and the first hard mask layer is etched using the patterned first shielding layer as a mask. The patterned first shielding layer is removed using an ashing process, and then the stress buffer layer and the first epitaxial layer 11 are sequentially dry-etched to form shallow trench isolation 14 in the first epitaxial layer 11. Figure 2 Only three shallow trench isolations 14 are exemplified herein. In practical applications, it should not be limited thereto, and the number of shallow trench isolations 14 can be set according to actual needs. Then, the first hard mask layer and the stress buffer layer are removed and a planarization process is performed to make the top surface of the first epitaxial layer 11 relatively flat. The planarization can be achieved by using a chemical mechanical polishing process.
[0043] Furthermore, a high-density plasma chemical vapor deposition technique can also be used to fill the isolation dielectric layer in the shallow trench isolation 14 to achieve a better isolation effect between different MOS devices.
[0044] In step S2, please refer to Figure 1 、 Figures 3 to 5 , a plurality of first trenches 161 are formed in the N-well region 12, and second trenches 162 are formed in the P-well region 13.
[0045] As an example, the steps of forming the first trenches 161 and the second trenches 162 are as follows: First, an oxide layer 15 is formed on the surface of the first epitaxial layer 11, and the oxide layer 15 is partially etched to form a first opening 151 and a second opening 152. Based on the first opening 151, the N-well region 12 is dry-etched and wet-etched to form a plurality of first trenches 161, and based on the second opening 152, the P-well region 13 is dry-etched and wet-etched to form second trenches 162.
[0046] In a specific embodiment, as Figure 3 shown, an oxide layer 15 is formed on the front surface of the first epitaxial layer 11 using processes including but not limited to chemical vapor deposition process or atomic layer deposition process. The material of the oxide layer 15 is silicon dioxide with a dense structure. As Figure 4As shown, then, a patterned photoresist layer is formed on the oxide layer 15, and the oxide layer 15 is etched using the patterned photoresist layer as a mask, thereby forming a first opening 151 on the N-well region 12 and a second opening 152 on the P-well region 13, and then the photoresist layer is removed using an ashing process.
[0047] As Figure 5 shown, using the oxide layer 15 as a mask, the N-well region 12 and the P-well region 13 are respectively subjected to dry etching and wet etching, thereby forming a plurality of first trenches 161 in the N-well region 12 and a second trench 162 in the P-well region 13. Among them, Figure 5 only 2 first trenches 161 and 1 second trench 162 are illustrated in the figure. The 2 first trenches 161 are symmetrically distributed about the central axis of the N-well region 12, and the central axis of the 1 second trench 162 coincides with the central axis of the P-well region 13. In practical applications, it should not be limited to this, and the number of the first trenches 161 and the second trenches 162 can be set according to actual needs.
[0048] As an example, the shapes of the first trench 161 and the second trench 162 are Sigma-shaped or rectangular. Specifically, in this embodiment, the process for forming the first trench 161 and the second trench 162 can be a dry etching process or a process combining dry etching and wet etching. Among them, when using the dry etching process, since the dry etching has the characteristic of isotropy, the formed first trench 161 and second trench 162 are standard rectangles; when using the process combining dry etching and wet etching, since the etching rate of the etching solution for wet etching is different in different crystal orientations, the first trench 161 and the second trench 162 with a Sigma shape can be formed.
[0049] As an example, the width of the first trench 161 is smaller than the width of the second trench 162, and the depth of the first trench 161 is equal to the depth of the second trench 162. The width of the first trench 161 is 50 - 100 nm, the width of the second trench 162 is 100 - 200 nm, and the depth of the first trench 161 and the second trench 162 is 80 - 100 nm.
[0050] Specifically, the first trench 161 is used to form the source and drain of the PMOS transistor, so as to form a relatively large extrusion force in the PMOS transistor. The second trench 162 is used to form the active channel layer of the NMOS transistor, so as to form a relatively large outward expansion stress in the NMOS transistor. Therefore, the width of the first trench 161 is set to be smaller than that of the second trench 162, so that a relatively large extrusion force can be formed in the PMOS transistor and a relatively large outward expansion stress can be formed in the NMOS transistor for the multiple epitaxial layers formed subsequently. In this embodiment, the width of the first trench 161 is 50 - 100 nm. For example, the width of the first trench 161 is 50 nm, 75 nm or 100 nm; the width of the second trench 162 is 100 - 200 nm. For example, the width of the second trench 162 is 100 nm, 150 nm or 200 nm; the depth of the first trench 161 and the second trench 162 is 80 - 100 nm. For example, the depth of the first trench 161 and the second trench 162 is 80 nm, 90 nm or 100 nm, and there is no limitation thereto. Preferably, the depth of the first trench 161 is equal to that of the second trench 162, which can also save the etching process and simplify the operation steps.
[0051] In step S3, please refer to Figure 1 , Figures 6 to 9 , a second epitaxial layer 171, a third epitaxial layer 172 and a fourth epitaxial layer 173 are sequentially formed in the first trench 161 and the second trench 162. The source and drain of the PMOS are formed in the first trench 161, and the channel region of the NMOS is formed in the second trench 162.
[0052] As Figure 6 shown, an epitaxial process including but not limited to chemical vapor deposition process or atomic layer deposition process is used to form the second epitaxial layer 171 in the first trench 161 and the second trench 162. The second epitaxial layer 171 covers the bottoms and sidewalls of the first trench 161 and the second trench 162 and the surface of the epitaxial layer. Among them, the second epitaxial layer 171 is a boron-doped germanium-silicon layer, the boron doping concentration is 5% - 10%, the concentration of germanium is 20%, and the thickness of the second epitaxial layer 171 is 10 - 15 nm.
[0053] As Figure 7As shown, an epitaxial process including but not limited to a chemical vapor deposition process or an atomic layer deposition process is used to form a third epitaxial layer 172 on the second epitaxial layer 171, and the third epitaxial layer 172 covers the surface of the second epitaxial layer 171. The third epitaxial layer 172 is a boron-doped germanium-silicon layer. Since the lattice constant of germanium is greater than that of silicon, after a subsequent high-temperature annealing process, the second epitaxial layer 171 and the third epitaxial layer 172 in the first groove will cause a large compressive stress, greatly improving the channel mobility of the PMOS transistor. Among them, the doping concentration of boron is 1% - 2%, the concentration of germanium is 35% - 50%, and the thickness of the third epitaxial layer 172 is 45 - 50 nm.
[0054] As Figure 8 shown, an epitaxial process including but not limited to a chemical vapor deposition process or an atomic layer deposition process is used to form a fourth epitaxial layer 173 on the third epitaxial layer 172. The fourth epitaxial layer 173 covers the surface of the third epitaxial layer 172, and the fourth epitaxial layer 173 will fill the first trench 161 and the second trench 162, thereby forming an active channel layer. The fourth epitaxial layer 173 is a boron-doped germanium-silicon layer. Among them, in order to improve the conductivity of the active channel layer, the doping concentration of boron is set to 0.4% - 0.6%, the concentration of germanium is 30%, and the thickness of the fourth epitaxial layer 173 is 25 - 35 nm.
[0055] Then, as Figure 9 shown, a planarization process is performed on the surface of the first epitaxial layer 11 to remove the second epitaxial layer 171, the third epitaxial layer 172, and the fourth epitaxial layer 173 on the top of the first epitaxial layer 11, so that the top of the first epitaxial layer 11 has a relatively flat surface. Among them, the planarization can be achieved by a chemical mechanical polishing process.
[0056] Furthermore, ion implantation is performed on the source region and the drain region in the second epitaxial layer 171 in the N-well region 12, and ion implantation is performed on the source region and the drain region on both sides of the P-well region 13, thereby respectively forming the source and drain of the PMOS transistor and the source and drain of the NMOS transistor. These two can be performed simultaneously or separately, which is not limited here.
[0057] In step S4, please refer to Figure 1 and Figure 10 , an insulating layer is formed on the surface of the first epitaxial layer 11, and a gate oxide layer 191 and a polysilicon gate 192 are formed on the NMOS and the PMOS.
[0058] As an example, as Figure 10As shown, a gate oxide layer 191 and a polysilicon gate 192 are formed on the top of the first epitaxial layer 11 through a gate oxide process. Using photoresist as a mask, the excess dielectric and polysilicon outside the gate oxide layer 191 and the polysilicon gate 192 are etched away. Among them, the polysilicon gate 192 is disposed directly above the gate oxide layer 191, the gate oxide layer 191 is disposed on the top of the first epitaxial layer 11, and the gate oxide layer 191 covers the epitaxial layer, part of the P-well region 13 and part of the N-well region 12.
[0059] As an example, as Figure 10 shown, an intermediate insulating layer 18 is deposited on the surface of the polysilicon gate 192 by a CVD method, and the intermediate insulating layer 18 covers the polysilicon gate 192, the gate oxide layer 191 and the first epitaxial layer 11.
[0060] In step S5, please refer to Figure 1 , and an annealing process treatment at 600 - 1000 °C is performed to form a CMOS device.
[0061] Specifically, an annealing process treatment is performed on the device after the gate oxide layer 191 and the polysilicon gate 192 are formed. The annealing process treatment can be a rapid annealing process. The annealing temperature is controlled at 600 - 1000 °C, and the annealing time is controlled at 10 - 20 s. Thus, the lattice of the second epitaxial layer 171, the third epitaxial layer 172 and the fourth epitaxial layer 173 can be further repaired. In particular, during the repair process of the second epitaxial layer 171 and the third epitaxial layer 172, a relatively large compressive stress will be formed. The magnitude of this compressive stress is about 1.0 - 2.0 GPa. Under the action of this compressive stress, the channel mobility of the PMOS transistor can be greatly improved. Correspondingly, the fourth epitaxial layer 173, as the active channel layer of the NMOS transistor, will also exhibit a stress of outward expansion, thereby greatly improving the channel mobility of the NMOS transistor.
[0062] In another embodiment of the present invention, a CMOS device is further proposed. As Figure 10 shown, the CMOS device is formed by using the preparation method of the CMOS device described above.
[0063] In summary, a CMOS device and a manufacturing method thereof proposed by the present invention respectively form a first trench and a second trench at different positions in an N-well region and a P-well region, and a plurality of silicon-germanium epitaxial layers are sequentially formed in the first trench and the second trench by combining multiple epitaxial processes. Among them, source and drain electrodes of a PMOS transistor are formed in a second epitaxial layer of the first trench, and an active channel layer of an NMOS transistor is formed in a fourth epitaxial layer of the second trench. Through a high-temperature annealing process, the lattice of the second epitaxial layer, the third epitaxial layer, and the fourth epitaxial layer can be further repaired, so as to form a large extrusion force in the PMOS transistor to greatly improve the channel mobility of the PMOS transistor, and correspondingly form a large outward-expanding stress in the NMOS transistor to greatly improve the channel mobility of the NMOS transistor, ultimately achieving a synchronous improvement in the performance of PMOS and NMOS transistors.
[0064] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.
Claims
1. A method for preparing a CMOS device, characterized in that: The preparation method comprises at least the following steps: Providing a substrate, on which a first epitaxial layer and a P-well region and an N-well region located in the first epitaxial layer are formed, and a shallow trench isolation is formed between the P-well region and the N-well region; A plurality of first trenches are formed in the N-well region, and a second trench is formed in the P-well region; forming a second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer in the first trench and the second trench in sequence, forming a source and a drain of a PMOS in the first trench, and forming a channel region of an NMOS in the second trench; forming an insulating layer and a gate oxide layer and a polysilicon gate located on the NMOS and the PMOS on the surface of the first epitaxial layer; An annealing process at 600-1000° C. is performed to form a CMOS device.
2. The method for preparing a CMOS device according to claim 1, characterized in that: The steps of forming the first groove and the second groove are: first forming an oxide layer on the surface of the first epitaxial layer, partially etching the oxide layer to form a first opening and a second opening, dry etching and wet etching the N-well region based on the first opening to form a plurality of first grooves, and dry etching and wet etching the P-well region based on the second opening to form a second groove.
3. The method for preparing a CMOS device according to claim 1, wherein: The width of the first trench is smaller than the width of the second trench, and the depth of the first trench is equal to the depth of the second trench.
4. The method for preparing a CMOS device according to claim 3, characterized in that: The width of the first groove is 50-100 nm, the width of the second groove is 100-200 nm, and the depth of the first groove and the second groove is 80-100 nm.
5. The method for preparing a CMOS device according to claim 1, wherein: The number of the first trenches is two, and the first trenches are symmetrically distributed about the central axis of the N-well region. The number of the second trench is one, and the central axis of the second trench coincides with the central axis of the P-well region.
6. The method for preparing a CMOS device according to claim 1, wherein: The second epitaxial layer is a boron-doped germanium silicon layer, wherein the concentration of boron doping is 5% to 10%, the concentration of germanium is 20%, the thickness of the second epitaxial layer is 10 to 15 nm, and the source and drain of the PMOS and the NMOS are both formed in the second epitaxial layer.
7. The method for preparing a CMOS device according to claim 1, wherein: The third epitaxial layer is a boron-doped germanium silicon layer, wherein the concentration of boron doping is 1% to 2%, the concentration of germanium is 35% to 50%, and the thickness of the third epitaxial layer is 45 to 50 nm.
8. The method for preparing a CMOS device according to claim 1, wherein: The fourth epitaxial layer is a boron-doped germanium silicon layer, wherein the concentration of boron doping is 0.4% to 0.6%, the concentration of germanium is 30%, the thickness of the fourth epitaxial layer is 25 to 35 nm, and the fourth epitaxial layer serves as an active channel layer.
9. The method for preparing a CMOS device according to any one of claims 1 to 8, characterized in that: The first groove and the second groove are in a Sigma shape or a rectangular shape.
10. A CMOS device, characterized in that: The CMOS device is formed by the method for preparing the CMOS device according to any one of claims 1 to 9.