Wake-up circuit, chip and electronic product

Abstract

The application provides a wake-up circuit, a chip and an electronic product, which comprise: a first wake-up module, which generates a start signal when an input signal is valid; a low-frequency clock generation module, which generates a low-frequency clock signal when the start signal is valid; a filtering module, which filters the input signal and outputs a filtered signal; a second wake-up module, which judges the filtered signal based on the low-frequency clock signal, generates a wake-up signal, and generates a timeout signal to reset the filtering module and the second wake-up module when the wake-up is not completed within a preset time; and a control module, which generates a reset signal of the first wake-up module when the wake-up is successful or the wake-up is timed out. The application adopts a two-stage wake-up mechanism, enhances the anti-interference ability of the input signal, avoids false wake-up caused by identification errors, and further reduces power consumption. Meanwhile, the wake-up circuit is turned off when the wake-up is successful or the wake-up is timed out, so that the wake-up circuit enters a low-power state and the input signal is detected and identified again at the first stage, further reducing power consumption.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic circuits, in particular to a wake-up circuit, a chip and an electronic product. BACKGROUND

[0002] With the continuous development of the field of integrated circuits, the requirement for power consumption is getting higher and higher. Taking a vehicle-mounted MCU chip as an example, the reliable wake-up mechanism of the low-power mode of the vehicle-mounted MCU chip is the premise of the low-power application of the vehicle-mounted MCU. In the application, a digital interface signal is usually used to wake up the MCU chip from the low-power mode, and the chip end realizes the wake-up by detecting the level or edge of the digital signal.

[0003] After entering the low-power mode, it is an important mechanism for the vehicle-mounted MCU chip to effectively recognize the wake-up signal and avoid being mistakenly triggered by the glitch and other interference signals. Because once the mistaken triggering occurs, the vehicle-mounted MCU chip will be unnecessarily woken up, losing the effect of the low-power mode. In an environment with less electromagnetic interference, the glitch on the digital interface signal is small, and the ordinary short-time filtering circuit (filtering range of about 10ns-200ns) can filter out the glitch, and it is not easy to be mistakenly woken up. However, in some environments with severe electromagnetic conditions, such as in a car or near a mobile phone base station, the glitch amplitude and time on the digital signal for waking up the chip will be more serious (the glitch amplitude can be greater than 50% of the input signal amplitude, and the time can be as long as hundreds of microseconds to tens of milliseconds).

[0004] One prior art uses a combination of delay circuits and logic gates to filter out glitches of several nanoseconds to several hundred nanoseconds in width, and because only the wake-up signal is used without using an additional clock source, the filtering and wake-up can be completed under the condition that the chip is in the low-power mode and the internal clock is completely turned off. However, its filtering capability is weak, and it can usually only filter out glitches of several hundred nanoseconds in width, so it cannot be applied to a severe electromagnetic interference environment.

[0005] Another prior art is to use an internal ring oscillator clock to sample and filter the wake-up signal, which can achieve strong filtering capability and avoid mistakenly waking up the chip. However, because the internal ring oscillator needs to be always on for real-time filtering processing when the chip is in the low-power mode, it cannot be applied to application scenarios with very strict requirements for current consumption in the low-power mode.

[0006] Therefore, how to balance the anti-interference capability and power consumption of the wake-up circuit has become one of the problems to be solved by those skilled in the art.

[0007] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely describing the technical scheme of the present application and facilitating the understanding of the skilled in the art. The above technical scheme cannot be considered as known to the skilled in the art only because it is described in the background of the present application. SUMMARY

[0008] In view of the above-mentioned defects of the prior art, the present application aims to provide a wake-up circuit, a chip and an electronic product, which can solve the problem that the anti-interference ability and power consumption of the wake-up circuit in the prior art cannot be considered.

[0009] To achieve the above object and other related objects, the present application provides a wake-up circuit, characterized in that the wake-up circuit comprises at least:

[0010] a primary wake-up module, a low-frequency clock generation module, a filtering module, a secondary wake-up module and a control module;

[0011] The primary wake-up module receives an input signal and generates a start signal when the input signal is valid.

[0012] The low-frequency clock generation module is connected to the output end of the primary wake-up module and generates a low-frequency clock signal when the start signal is valid.

[0013] The filtering module is connected to the output end of the low-frequency clock generation module, filters the input signal based on the low-frequency clock signal and outputs a filtered signal.

[0014] The secondary wake-up module is connected to the output ends of the low-frequency clock generation module and the filtering module, judges the filtered signal based on the low-frequency clock signal, generates a wake-up signal and generates a timeout signal to reset the filtering module and the secondary wake-up module when the wake-up is not completed within a preset time.

[0015] The control module is connected to the output end of the secondary wake-up module and generates a reset signal of the primary wake-up module when the wake-up is successful or the wake-up is timed out.

[0016] Optionally, the primary wake-up module comprises a filtering unit and a first D flip-flop; the input end of the filtering unit is connected to the input signal and filters the input signal; the data input end of the first D flip-flop receives a first level signal, the clock end is connected to the output end of the filtering unit, the reset end is connected to the reset signal and the output end outputs the start signal.

[0017] More optionally, the filtering unit comprises a delay circuit and a first AND gate; the delay circuit delays the input signal and outputs; the first input terminal of the first AND gate is connected to the output terminal of the delay circuit, the second input terminal is connected to the input signal, and the output terminal is connected to the first flip-flop.

[0018] Optionally, the low-frequency clock generation module is a low-frequency ring oscillator.

[0019] More optionally, the filtering module filters the input signal based on majority decision or successive decision.

[0020] More optionally, when the filtering module uses successive decision for filtering, the filtering module comprises N-stage D flip-flops and a second AND gate.

[0021] The D flip-flops are connected in series, the input terminal of the first-stage D flip-flop is connected to the input signal or the filtered signal of the input signal, and the clock terminals of the D flip-flops are connected to the low-frequency clock signal; N is a natural number greater than or equal to 2.

[0022] The input terminals of the second AND gate are connected to the output terminals of the D flip-flops, respectively, and when the output signals of the D flip-flops are all valid, it is determined that the input signal is valid, and the corresponding filtered signal is output.

[0023] Optionally, the secondary wake-up module comprises a first counting unit and a second counting unit.

[0024] The first counting unit receives the low-frequency clock signal and the filtered signal, counts the valid state of the filtered signal to obtain a first counting value, and outputs a valid wake-up signal when the first counting value is greater than or equal to a first set value.

[0025] The second counting unit receives the low-frequency clock signal, counts the working time of the secondary wake-up module to obtain a second counting value, and outputs a valid timeout signal when the second counting value reaches a second set value.

[0026] Among them, the first set value is less than the second set value.

[0027] More optionally, the first counting unit comprises a first counter, a first comparator, a first selector, and a second D flip-flop.

[0028] The first counter counts the valid state of the filtered signal based on the rising edge of the low-frequency clock signal.

[0029] The non-inverting input terminal of the first comparator is connected to the output terminal of the first counter, and the inverting input terminal is connected to the first set value.

[0030] The first input end of the first selector is connected with the output end of the first comparator, the second input end and the control end are connected with the output end of the second D flip-flop; wherein, the output signal of the first comparator is outputted when the wake-up signal is invalid, and the wake-up signal is locked as the valid state when the wake-up signal is valid;

[0031] The data input end of the second D flip-flop is connected with the output end of the first selector, the clock end is connected with the low-frequency clock signal, and the output end outputs the wake-up signal.

[0032] More optionally, the second counting unit comprises a second counter and a second comparator.

[0033] The second counter counts based on the falling edge of the low-frequency clock signal.

[0034] The non-inverting input end of the second comparator is connected with the output end of the second counter, the inverting input end is connected with the second set value, and the output end outputs the timeout signal.

[0035] Optionally, the control module comprises an OR gate and a second selector.

[0036] The input ends of the OR gate are connected with the wake-up signal and the timeout signal respectively.

[0037] The first input end of the second selector is connected with the output end of the OR gate, the second input end is connected with a second level signal, and the control end is connected with the inverse signal of the enable signal of the wake-up circuit; wherein, the first-level wake-up module is controlled to reset based on the output signal of the OR gate when the enable signal is valid, and the reset signal is locked as the valid state when the enable signal is invalid.

[0038] To achieve the above object and other related objects, the present application provides a chip, which comprises at least: a main circuit and the wake-up circuit.

[0039] The wake-up circuit provides a wake-up signal for the main circuit.

[0040] The main circuit is connected with the output end of the wake-up circuit, is woken up to work when the wake-up signal is valid, and the enable signal of the wake-up circuit is invalid after being woken up.

[0041] Optionally, the chip is a vehicle-mounted MCU chip.

[0042] To achieve the above object and other related objects, the present application further provides an electronic product, which comprises at least: the wake-up circuit.

[0043] As described above, the wake-up circuit, chip and electronic product of the present application have the following beneficial effects:

[0044] The wake-up circuit, chip and electronic product of the present application adopt a two-stage wake-up mechanism, which enhances the anti-interference ability to the input signal, avoids false wake-up caused by identification error, and further reduces power consumption; meanwhile, the wake-up circuit is turned off when the wake-up is successful or the wake-up is timed out, so that the wake-up circuit enters a low-power state, and the input signal is detected and identified again in the first stage, further reducing power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0045] Figure 1 A principle block diagram of the wake-up circuit of the present application is shown.

[0046] Figure 2 A structure schematic diagram of the wake-up circuit of the present application is shown.

[0047] Figure 3 A structure schematic diagram of the filter module of the present application is shown.

[0048] Figure 4 A structure schematic diagram of the chip of the present application is shown.

[0049] ELEMENT NUMBER EXPLANATION

[0050] 1 wake-up circuit

[0051] 11 first-stage wake-up module

[0052] 111 filter unit

[0053] 111a delay circuit

[0054] 111b first AND gate

[0055] 112 first D flip-flop

[0056] 12 low-frequency clock generation module

[0057] 13 filter module

[0058] 131 second AND gate

[0059] 132 first-stage D flip-flop

[0060] 133 second-stage D flip-flop

[0061] 134 third-stage D flip-flop

[0062] 14 second-stage wake-up module

[0063] 141 first counting unit

[0064] 141a first counter

[0065] 141b first comparator

[0066] 141c first selector

[0067] 141d Second D Flip-Flop

[0068] 142 Second Counting Unit

[0069] 142a Second Counter

[0070] 142b Second Comparator

[0071] 142c buffer

[0072] 14a Third Selector

[0073] 14b First Register

[0074] 14c First Adder

[0075] 14d second register

[0076] 14e Second Adder

[0077] 15 control modules

[0078] 151 or door

[0079] 152 Second Selector

[0080] 2 Main Circuit

[0081] 21 oscillators

[0082] 22 functional modules Detailed Implementation

[0083] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0084] Please see Figures 1-4 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0085] like Figure 1 As shown, the present invention provides a wake-up circuit 1, the wake-up circuit 1 comprising:

[0086] The system includes a primary wake-up module 11, a low-frequency clock generation module 12, a filtering module 13, a secondary wake-up module 14, and a control module 15.

[0087] As shown in Figure 1 , the primary wake-up module 11 receives an input signal INPUT and generates an activation signal ACT when the input signal INPUT is valid.

[0088] Specifically, the primary wake-up module 11 detects the level or edge of the input signal INPUT and determines that the input signal INPUT is valid when the level or edge of the input signal INPUT meets a preset condition. The preset condition can be set according to actual needs. For example, the input signal INPUT is determined to be valid when a high level of the input signal INPUT, a low level of the input signal INPUT, a rising edge of the input signal INPUT, or a falling edge of the input signal INPUT is detected. In this embodiment, the input signal INPUT is valid in a high level, and the primary wake-up module 11 detects the level of the input signal INPUT.

[0089] More specifically, as shown in Figure 2 , in this embodiment, the primary wake-up module 11 includes a filter unit 111 and a first D flip-flop 112. The input end of the filter unit 111 is connected to the input signal INPUT, and the input signal INPUT is filtered to filter out glitches in the input signal INPUT. The data input end D of the first D flip-flop 112 receives a first level signal, the clock end CK is connected to the output end of the filter unit 111, the reset end CLR is connected to the reset signal CLEAR, and the output end Q outputs the activation signal ACT. In this embodiment, the first level signal is set to a high level signal 1, the rising edge of the output signal of the filter unit 111 triggers the first D flip-flop 112 to output a high level signal, and the activation signal ACT jumps to a high level (valid). When the reset signal CLEAR is valid, the first D flip-flop 112 is reset, and the activation signal ACT jumps to a low level (invalid). In actual use, the level corresponding to the activation signal ACT being valid (for example, a low level 0) can also be configured as needed, which is not limited to this embodiment.

[0090] As an example, the filter unit 111 includes a delay circuit 111a and a first AND gate 111b; the delay circuit 111a delays the input signal INPUT and outputs; the first input terminal of the first AND gate 111b is connected to the output terminal of the delay circuit 111a, the second input terminal is connected to the input signal INPUT, and the output terminal is connected to the first flip-flop 111b; only when the input signal INPUT and its delay signal are both high, the first AND gate 111b outputs high; the effective filtering width of the filter unit 111 is the time of the signal passing through the delay circuit 111a. If there is a high level glitch on the input signal INPUT smaller than the time width of the delay circuit 111a, the high level signal passing through the delay circuit 111a has not reached the first input terminal of the first AND gate 111b, and the falling input signal INPUT has reached the second input terminal of the first AND gate 111b, the output clock of the first AND gate 111b always remains low (i.e. the glitch is filtered out).

[0091] As shown in Figure 1 , the low-frequency clock generation module 12 is connected to the output terminal of the first wake-up module 11, and generates a low-frequency clock signal CLK_S when the start signal ACT is valid.

[0092] Specifically, the enable terminal EN of the low-frequency clock generation module 12 is connected to the start signal ACT, and when the start signal ACT is valid, the low-frequency clock generation module 12 starts to work and generates a low-frequency clock signal CLK_S; when the start signal ACT is invalid, the low-frequency clock generation module 12 stops working. As an example, the frequency of the low-frequency clock signal CLK_S is set to 10KHz-100KHz, and the specific value is set according to the actual circuit needs, which is not described here. Any circuit structure that can provide a low-frequency clock signal is suitable for the low-frequency clock generation module 12 of the present application, and in this embodiment, the low-frequency clock generation module 12 is a low-frequency ring oscillator.

[0093] As shown in Figure 1 , the filter module 13 is connected to the output terminal of the low-frequency clock generation module 12, and filters the input signal INPUT based on the low-frequency clock signal CLK_S to output a filtered signal DIN_FLT.

[0094] Specifically, the filter module 13 is a digital filter, which performs digital filtering on the input signal INPUT, including but not limited to majority decision method and successive decision method, which will not be described one by one here; wherein the majority decision method samples the input signal multiple times, and the input signal is determined to be valid if the majority of the sampling results meet the requirements, otherwise it is determined to be invalid; the successive decision method samples the input signal multiple times, and the input signal is determined to be valid if the sampling results of the successive number of times meet the requirements, otherwise it is determined to be invalid.

[0095] More specifically, as shown in Figure 3 As an example, the filter module 13 includes N-stage D flip-flops and a second AND gate 131, N is a natural number greater than or equal to 2; in this embodiment, the filter module 13 makes a decision based on the sampling results of three consecutive times, that is, N = 3, which are respectively referred to as the first-stage D flip-flop 132, the second-stage D flip-flop 133, and the third-stage D flip-flop 134. The D flip-flops are connected in series (the data input end of the latter D flip-flop is connected to the output end of the former D flip-flop), the input end D of the first-stage D flip-flop 132 is connected to the input signal INPUT or the filtered signal of the input signal INPUT (in this example, the input signal INPUT is detected based on the output signal of the filtering unit 111), and the clock end CK of each D flip-flop is connected to the low-frequency clock signal CLK_S. The input ends of the second AND gate 131 are connected to the output ends of the D flip-flops, respectively, and the input signal INPUT is determined to be valid when the output signals of the D flip-flops are all valid, and a corresponding filtered signal is output. In this embodiment, the filtered signal DIN_FLT outputs a high level only when the outputs of the three D flip-flops are all high levels; when any one of the three D flip-flops is not a high level, the filtered signal DIN_FLT outputs a low level (i.e. the input signal is filtered out). Any circuit structure that can realize digital filtering is applicable to the present application, and is not limited to this embodiment.

[0096] As shown in Figure 1 The second-stage wake-up module 14 is connected to the output ends of the low-frequency clock generation module 12 and the filter module 13, and makes a decision on the filtered signal DIN_FLT based on the low-frequency clock signal CLK_S to generate a wake-up signal WKUP (the wake-up signal WKUP is valid when the filtered signal DIN_FLT meets the wake-up level or edge condition); and generates a timeout signal OT to reset the filter module 13 and the second-stage wake-up module 14 when the wake-up is not completed within the preset time.

[0097] Specifically, as shown in Figure 2As shown, in the embodiment, the secondary wake-up module 14 comprises a first counting unit 141 and a second counting unit 142. The first counting unit 141 receives the low-frequency clock signal CLK_S and the filtered signal DIN_FLT, counts the active state of the filtered signal DIN_FLT to obtain a first counting value, and outputs an active wake-up signal WKUP when the first counting value is greater than or equal to a first set value, and the wake-up signal WKUP is inactive (in the example, the wake-up signal WKUP is active in high level and inactive in low level) when the first counting value is less than the first set value. The second counting unit 142 receives the low-frequency clock signal CLK_S, counts the working time of the secondary wake-up module 14 to obtain a second counting value, and outputs an active timeout signal OT when the second counting value reaches a second set value, and the timeout signal OT is inactive (in the example, the timeout signal OT is active in high level and inactive in low level) when the second counting value is less than the second set value; wherein the first set value is less than the second set value, and the specific values are set according to the needs.

[0098] More specifically, as an example, the first counting unit 141 includes a first counter 141a, a first comparator 141b, a first selector 141c and a second D flip-flop 141d. The first counter 141a counts the active state of the filtered signal DIN_FLT based on the rising edge of the low-frequency clock signal CLK_S. In this embodiment, the first counter 141a includes a third selector 14a, a first register 14b and a first adder 14c; the first input end of the third selector 14a receives data 0, the second input end of the third selector 14a is connected to the output end of the first adder 14c, the control end is connected to the filtered signal DIN_FLT, and when the filtered signal DIN_FLT is invalid (low), the data output of the first input end is selected, and when the filtered signal DIN_FLT is active (high), the data output of the second input end is selected; the input end DIN of the first register 14b is connected to the output end of the third selector 14a, the clock end CLK receives the low-frequency clock signal CLK_S (rising edge triggering), and the data output by the third selector 14a is registered; the first input end of the first adder 14c is connected to the output end of the first register 14b, and the second input end is connected to data 1, which adds the data registered in the first register 14b to 1. The non-inverting input end of the first comparator 141b is connected to the output end of the first counter 141a, and the inverting input end is connected to the first set value, which is 8 in this embodiment. The first input end of the first selector 141c is connected to the output end of the first comparator 141b, the second input end is connected to the output end of the second D flip-flop 141d, and the control end is connected to the output end of the second D flip-flop 141d; wherein when the wake-up signal WKUP is invalid (low), the output signal of the first comparator 141b is output, and when the wake-up signal WKUP is active (high), the wake-up signal WKUP is locked in the active state. The data input end D of the second D flip-flop 141d is connected to the output end of the first selector 141c, the clock end CK is connected to the low-frequency clock signal CLK_S, and the output end outputs the wake-up signal WKUP; the set end SET of the second D flip-flop 141d is also connected to the inverse signal WKUP_ENB of the enable signal of the wake-up circuit 1, and when the enable signal is high and active (the wake-up circuit 1 is in the working state, and the main circuit has not been woken up), the inverse signal WKUP_ENB of the enable signal is low, the set end of the second D flip-flop 141d is invalid, and when the enable signal is low and invalid (the main circuit has been woken up), the inverse signal WKUP_ENB of the enable signal is high, the set end of the second D flip-flop 141d is active, and the wake-up signal WKUP is kept in the high and active state.The first counting unit 141 is responsible for identifying whether there are 8 continuous high level clock (CLK_S) periods on the filtered signal DIN_FLT: if the filtered signal DIN_FLT is always high, the first counter 141a accumulates 1 at the rising edge of each low frequency clock until the first counter 141a counts to 8, then the wake-up signal WKUP is valid, the main circuit is woken up to start working (the low frequency clock signal is stopped in the wake-up circuit, the main body of the wake-up circuit stops working), and the wake-up signal WKUP is self-locked; if the filtered signal DIN_FLT appears low level in the process, the first counter 141a starts counting from 0 again.

[0099] More specifically, as an example, the second counting unit 142 includes a second counter 142a and a second comparator 142b. The second counter 142a counts based on the falling edge of the low frequency clock signal CLK_S. In the embodiment, the second counter 142a includes a second register 14d and a second adder 14e; the input end DIN of the second register 14d is connected to the output end of the second adder 14e, the clock end CLK receives the low frequency clock signal CLK_S (falling edge trigger), and the data output by the second adder 14e is registered; the first input end of the second adder 14e is connected to the output end of the second register 14d, and the second input end is connected to data 1, which adds 1 to the data registered in the second register 14d. The non-inverting input end of the second comparator 142b is connected to the output end of the second counter 142a, the inverting input end is connected to the second set value, and the output end outputs the timeout signal OT; in the embodiment, the second set value is 15. As another implementation manner of the application, the second counting unit 142 further includes a buffer 142c connected to the output end of the second comparator 142b. The second counting unit 142 is used to limit the working time of the low frequency clock generation module 12, the filtering module 13 and the second level wake-up module 14; when the low frequency clock generation module 12 generates 16 clocks, i.e. the second counter 142a counts to 15, the second comparator 142b outputs the valid timeout signal OT, which is connected to the reset end of the filtering module 13, the first counting unit 141 and the second counting unit 142, so as to reset the filtering module 13, the first counting unit 141 and the second counting unit 142, and then start detecting the first level wake-up again.

[0100] It should be noted that any counting circuit structure capable of realizing wake-up detection and timeout detection is applicable to the first counting unit and the second counting unit of the application, which is not limited to the embodiment.

[0101] As shown in Figure 1 The control module 15 is connected to the output end of the secondary wake-up module 14, and generates the reset signal CLEAR of the primary wake-up module 11 when the wake-up is successful or the wake-up is timed out.

[0102] Specifically, the control module 15 receives the wake-up signal WKUP, the timeout signal OT and the enable signal (or the inverse signal WKUP_ENB of the enable signal). When the enable signal is invalid, the primary wake-up module 11 is reset, the start signal ACT is invalid, the low-frequency clock generation module 12 stops generating the low-frequency clock signal CLK_S, and the main body of the wake-up circuit 1 stops working. When the enable signal is valid, the wake-up circuit 1 works normally; and when the wake-up is timed out, the primary wake-up module 11 is reset.

[0103] More specifically, as an example, the control module 15 includes an OR gate 151 and a second selector 152. The input ends of the OR gate 151 are connected to the wake-up signal WKUP and the timeout signal OT respectively, and output a valid control signal for resetting when the wake-up signal WKUP or the timeout signal OT is valid. The first input end of the second selector 152 is connected to the output end of the OR gate 151, the second input end is connected to a second level signal, the control end is connected to the inverse signal WKUP_ENB of the enable signal, and the output is the reset signal CLEAR. In this embodiment, the second level signal is set to a high level signal 1, and in actual use, it can also be set to a low level signal 0 (the first level signal is irrelevant to the second level signal, both can be set to 1 and 0, or both can be set to 1 or 0). When the enable signal is valid (the inverse signal WKUP_ENB of the enable signal is low), the output signal of the OR gate 151 is used to control the reset of the primary wake-up module 11; when the enable signal is invalid (the inverse signal WKUP_ENB of the enable signal is high), the reset signal CLEAR is locked in the valid state.

[0104] It should be noted that the present application adopts a two-stage wake-up mechanism for the wake-up circuit, which can only be woken up by the two-stage wake-up mechanism, greatly improving the anti-interference ability; the primary wake-up module is reset when the wake-up is successful or the wake-up is timed out, so as to close the low-frequency clock generation module and the filter module, and make the wake-up circuit enter a low-power consumption state (avoiding that the internal low-frequency clock generation module is always on and cannot realize extremely low power consumption), thereby reducing power consumption.

[0105] As shown in Figure 4 The present application also provides a chip, which at least includes: a wake-up circuit 1 and a main circuit 2.

[0106] As shown in Figure 4As shown, the wake-up circuit 1 provides the wake-up signal WKUP to the main circuit 2. The structure and working principle of the wake-up circuit 1 are described above and will not be repeated here.

[0107] like Figure 4 As shown, the main circuit 2 is connected to the output terminal of the wake-up circuit 1. It is woken up and works when the wake-up signal WKUP is valid. After being woken up, the enable signal of the wake-up circuit 1 is invalidated.

[0108] Specifically, in this embodiment, the main circuit 2 includes an oscillator 21 and a functional module 22. The enable terminal of the oscillator 21 is connected to the wake-up signal WKUP. When the wake-up signal WKUP is valid, it generates a clock signal for the main circuit 2; when the wake-up signal WKUP is invalid, the main circuit 2 has no clock signal and is therefore in a non-operating state. The functional module 22 is connected to the output terminal of the oscillator 21, operates based on the clock signal provided by the oscillator 21, implements the main functions of the chip, and invalidates the enable signal of the wake-up circuit 1 after being woken up, thereby shutting down the main body of the wake-up signal 1 and achieving low power consumption.

[0109] Specifically, the chips include, but are not limited to, automotive MCU chips and battery management chips, which will not be described in detail here.

[0110] The present invention also provides an electronic product, which includes at least the wake-up circuit 1. Any electronic product that needs to achieve low power consumption is applicable to the present invention, and will not be described in detail here.

[0111] In summary, the present application provides a wake-up circuit, chip and electronic product, comprising: a first wake-up module, a low-frequency clock generation module, a filtering module, a second wake-up module and a control module; the first wake-up module receives an input signal and generates a start signal when the input signal is valid; the low-frequency clock generation module is connected to the output end of the first wake-up module and generates a low-frequency clock signal when the start signal is valid; the filtering module is connected to the output end of the low-frequency clock generation module, filters the input signal based on the low-frequency clock signal and outputs a filtered signal; the second wake-up module is connected to the output end of the low-frequency clock generation module and the filtering module, judges the filtered signal based on the low-frequency clock signal, generates a wake-up signal and generates a timeout signal to reset the filtering module and the second wake-up module when the wake-up is not completed within a preset time; and the control module is connected to the output end of the second wake-up module and generates a reset signal of the first wake-up module when the wake-up is successful or the wake-up is timed out. The wake-up circuit, chip and electronic product of the present application adopt a two-stage wake-up mechanism, enhance the anti-interference ability of the input signal, avoid false wake-up caused by identification error and reduce power consumption. At the same time, the wake-up circuit is closed when the wake-up is successful or the wake-up is timed out, so that the wake-up circuit enters a low-power state and the input signal is detected and identified again, further reducing power consumption. Therefore, the present application effectively overcomes the shortcomings of the prior art and has high industrial utilization value.

[0112] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought of the present application should be covered by the claims of the present application.

Claims

1. A wake-up circuit, characterized by, The wake-up circuit at least comprises: a primary wake-up module, a low-frequency clock generation module, a filtering module, a secondary wake-up module and a control module; the primary wake-up module receives an input signal and generates a start signal when the input signal is valid; the low-frequency clock generation module is connected to an output end of the primary wake-up module and generates a low-frequency clock signal when the start signal is valid; the filtering module is connected to an output end of the low-frequency clock generation module, filters the input signal based on the low-frequency clock signal and outputs a filtered signal; the secondary wake-up module is connected to output ends of the low-frequency clock generation module and the filtering module, judges the filtered signal based on the low-frequency clock signal, generates a wake-up signal and generates a timeout signal to reset the filtering module and the secondary wake-up module when the wake-up is not completed within a preset time; the control module is connected to an output end of the secondary wake-up module and generates a reset signal of the primary wake-up module when the wake-up is successful or the wake-up times out.

2. The wake-up circuit of claim 1, wherein: The primary wake-up module comprises a filtering unit and a first D flip-flop; an input end of the filtering unit is connected to the input signal and filters the input signal; a data input end of the first D flip-flop receives a first level signal, a clock end is connected to an output end of the filtering unit, a reset end is connected to the reset signal and an output end outputs the start signal.

3. The wake-up circuit of claim 2, wherein: The filtering unit comprises a delay circuit and a first AND gate; the delay circuit outputs after delaying the input signal; a first input end of the first AND gate is connected to an output end of the delay circuit, a second input end is connected to the input signal and an output end is connected to the first D flip-flop.

4. The wake-up circuit of claim 1, wherein: The filtering module uses a continuous judgment method for filtering and comprises N-stage D flip-flops and a second AND gate; the D flip-flops are connected in series; an input end of a first-stage D flip-flop is connected to the input signal or a filtered signal of the input signal; clock ends of the D flip-flops are all connected to the low-frequency clock signal; N is a natural number greater than or equal to 2; input ends of the second AND gate are respectively connected to output ends of the D flip-flops; when the output signals of the D flip-flops are all valid, it is judged that the input signal is valid and a corresponding filtered signal is output.

5. The wake-up circuit of claim 1, wherein: The secondary wake-up module comprises a first counting unit and a second counting unit; the first counting unit receives the low-frequency clock signal and the filtered signal, counts valid states of the filtered signal to obtain a first counting value and outputs a valid wake-up signal when the first counting value is greater than or equal to a first set value; the second counting unit receives the low-frequency clock signal, counts working time of the secondary wake-up module to obtain a second counting value and outputs a valid timeout signal when the second counting value reaches a second set value; wherein the first set value is less than the second set value.

6. The wake-up circuit of claim 5, wherein: The first counting unit comprises a first counter, a first comparator, a first selector and a second D flip-flop; the first counter counts valid states of the filtered signal based on rising edges of the low-frequency clock signal; The positive input terminal of the first comparator is connected to the output terminal of the first counter, and the negative input terminal is connected to the first set value; The first input terminal of the first selector is connected to the output terminal of the first comparator, the second input terminal and the control terminal are connected to the output terminal of the second D flip-flop; wherein, when the wake-up signal is invalid, the output signal of the first comparator is outputted, and when the wake-up signal is valid, the wake-up signal is locked in the valid state; The data input terminal of the second D flip-flop is connected to the output terminal of the first selector, the clock terminal is connected to the low-frequency clock signal, and the output terminal outputs the wake-up signal.

7. The wake-up circuit of claim 5, wherein: The second counting unit comprises a second counter and a second comparator; The second counter counts based on the falling edge of the low-frequency clock signal; The positive input terminal of the second comparator is connected to the output terminal of the second counter, the negative input terminal is connected to the second set value, and the output terminal outputs the timeout signal.

8. The wake-up circuit of claim 1, wherein: The control module comprises an OR gate and a second selector; The input terminals of the OR gate are respectively connected to the wake-up signal and the timeout signal; The first input terminal of the second selector is connected to the output terminal of the OR gate, the second input terminal is connected to a second level signal, and the control terminal is connected to the inverse signal of the enable signal of the wake-up circuit; wherein, when the enable signal is valid, the first-level wake-up module is controlled to be reset based on the output signal of the OR gate, and when the enable signal is invalid, the reset signal is locked in the valid state.

9. A chip, characterized by The chip at least comprises a main circuit and the wake-up circuit according to any one of claims 1-8; The wake-up circuit provides the wake-up signal for the main circuit; The main circuit is connected to the output terminal of the wake-up circuit, is woken up to work when the wake-up signal is valid, and is invalid after being woken up to enable the signal of the wake-up circuit.

10. An electronic product, characterized by comprising: The electronic product at least comprises the wake-up circuit according to any one of claims 1-8.

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