Band-gap reference circuit

Abstract

The invention relates to a band-gap reference circuit which comprises a bias circuit, a linear voltage stabilizing circuit, a state detection circuit and a reference voltage generating circuit, the bias circuit generates bias current according to an input power supply, and the state detection circuit detects the starting state of the reference voltage generating circuit. When the reference voltage generation circuit is not started, the linear voltage stabilizing circuit generates a first power supply voltage, the first power supply voltage supplies power to the reference voltage generation circuit, and after the reference voltage generation circuit is started, the linear voltage stabilizing circuit stops generating the first power supply voltage. And the second power supply voltage supplies power to the reference voltage generation circuit, so that the reference voltage generation circuit continuously generates the reference voltage. The band-gap reference circuit adopts the linear voltage stabilizing circuit to supply power to the reference voltage generating circuit, so that the fluctuation of the reference voltage is smaller, the anti-interference capability is stronger, and the stability is higher.

Description

Technical Field

[0001] This application relates to the field of reference voltages, and particularly to a bandgap reference circuit. Background Art

[0002] A bandgap reference circuit is a high-precision DC voltage reference source circuit widely used in integrated circuits, which is used to provide a reference voltage to other circuits or chips. However, the anti-interference ability of the bandgap reference circuit is weak, and the reference voltage is easily affected by the fluctuation of the input power supply, resulting in unstable reference voltage. Summary of the Invention

[0003] Embodiments of this application aim to provide a bandgap reference circuit, which can improve the anti-interference ability of the bandgap reference circuit and the stability of the reference voltage.

[0004] To solve the above technical problems, the embodiments of this application provide the following technical solutions:

[0005] Embodiments of this application provide a bandgap reference circuit, which includes a bias circuit, a linear voltage regulator circuit, a state detection circuit, and a reference voltage generation circuit;

[0006] The bias circuit is configured to generate a bias current according to the input power supply;

[0007] The state detection circuit is electrically connected to the linear voltage regulator circuit. The state detection circuit is configured to detect the startup state of the reference voltage generation circuit, and generate a first detection signal when the reference voltage generation circuit is not started, and generate a second detection signal after the reference voltage generation circuit is started;

[0008] The linear voltage regulator circuit is electrically connected to the state detection circuit and the reference voltage generation circuit respectively. The linear voltage regulator circuit is configured to generate a first supply voltage in response to the input of the bias current and the first detection signal;

[0009] The reference voltage generation circuit is configured to generate a reference voltage in response to the input of the first supply voltage, so that the linear voltage regulator circuit stops generating the first supply voltage and generates a second supply voltage in response to the input of the bias current, the second detection signal, and the reference voltage, and then enables the reference voltage generation circuit to continuously generate the reference voltage in response to the input of the second supply voltage.

[0010] In some embodiments, the linear voltage regulator circuit includes a first voltage regulation unit and a second voltage regulation unit;

[0011] The first voltage regulating unit is electrically connected to the state detection circuit, and the first voltage regulating unit, the second voltage regulating unit, and the power supply terminal of the reference voltage generating circuit are commonly connected to a first node. The first voltage regulating unit is configured to generate the first power supply voltage at the first node in response to the input of the bias current and the first detection signal, and is configured to stop generating the first power supply voltage in response to the input of the bias current and the second detection signal;

[0012] The second voltage regulating unit is also electrically connected to the output terminal of the reference voltage generating circuit. The second voltage regulating unit is configured to generate the second power supply voltage at the first node in response to the input of the reference voltage and the bias current.

[0013] In some embodiments, the first voltage regulating unit includes a first voltage generating unit, a first voltage following unit, and a first switching unit;

[0014] The first voltage generating unit is electrically connected to the input terminal of the voltage following unit. The first voltage generating unit is configured to generate a first voltage in response to the input of the bias current;

[0015] The output terminal of the first voltage following unit is electrically connected to the first end of the first switching unit. The first voltage following unit is configured to generate the first power supply voltage based on the first voltage;

[0016] The second end of the first switching unit is electrically connected to the first node. The control terminal of the first switching unit is electrically connected to the state detection circuit. The first switching unit is configured to connect the electrical connection between the output terminal of the first voltage following unit and the first node in response to the input of the first detection signal, so as to output the first power supply voltage at the first node. The first switching unit is further configured to disconnect the electrical connection between the output terminal of the first voltage following unit and the first node in response to the input of the second detection signal.

[0017] In some embodiments, the first voltage generating unit includes a first MOS transistor and a second MOS transistor, the first voltage following unit includes a third MOS transistor, and the first switching unit includes a fourth MOS transistor;

[0018] The drain of the first MOS transistor, the gate of the first MOS transistor, and the gate of the third MOS transistor are all used to access the bias current. The source of the first MOS transistor is respectively connected to the drain and the gate of the second MOS transistor. The source of the second MOS transistor is grounded. The drain of the third MOS transistor is used to access the input power supply. The source of the third MOS transistor is connected to the source of the fourth MOS transistor. The drain of the fourth MOS transistor is connected to the first node. The gate of the fourth MOS transistor is electrically connected to the state detection circuit.

[0019] In some embodiments, the second voltage regulation unit includes a second voltage generation unit and a second voltage follower unit;

[0020] The second voltage generation unit is respectively electrically connected to the output terminal of the reference voltage generation circuit and the input terminal of the second voltage follower unit. The second voltage generation unit is configured to generate a second voltage in response to the input of the bias current and the reference voltage;

[0021] The output terminal of the second voltage follower unit is electrically connected to the first node. The second voltage follower unit is configured to generate the second supply voltage based on the second voltage.

[0022] In some embodiments, the second voltage follower unit includes a fifth MOS transistor, and the second voltage generation unit includes a sixth MOS transistor;

[0023] The source of the fifth MOS transistor is electrically connected to the first node. The drain of the fifth MOS transistor is used to access the input power supply. The gate of the fifth MOS transistor and the source of the sixth MOS transistor are both used to access the bias current. The gate of the sixth MOS transistor is electrically connected to the output terminal of the reference voltage generation circuit. The drain of the sixth MOS transistor is grounded.

[0024] In some embodiments, the bandgap reference circuit further includes a first startup circuit, and the first startup circuit is respectively electrically connected to the output terminal of the reference voltage generation circuit and the state detection circuit;

[0025] The first startup circuit is configured to generate a startup current to start the reference voltage generation circuit in response to the input of the bias current, and is further configured to stop generating the startup current in response to the input of the reference voltage.

[0026] In some embodiments, the state detection circuit includes a first mirror unit, a second mirror unit, and a first inverter;

[0027] The input terminals of the first mirror unit, the second mirror unit, and the first inverter are commonly connected to a third node, and the output terminal of the first inverter is electrically connected to the linear voltage regulator circuit;

[0028] The first mirror unit is configured to mirror the startup current to raise the voltage of the third node, thereby causing the first inverter to output the first detection signal;

[0029] The second mirror unit is configured to mirror the bias current to lower the voltage of the third node, thereby causing the first inverter to output the second detection signal.

[0030] In some embodiments, the first mirror unit includes a seventh MOS transistor and an eighth MOS transistor, and the second mirror unit includes a first triode;

[0031] The drain of the seventh MOS transistor is respectively connected to the gate of the seventh MOS transistor, the gate of the eighth MOS transistor, and the first startup circuit. The sources of the seventh MOS transistor and the eighth MOS transistor are both used to connect to the input power supply. The drain of the eighth MOS transistor, the collector of the first triode, and the input terminal of the first inverter are commonly connected to the third node. The base of the first triode is electrically connected to the first startup circuit, and the emitter of the first triode is grounded.

[0032] In some embodiments, the first startup circuit includes a ninth MOS transistor, a tenth MOS transistor, and a second triode;

[0033] The drain of the ninth MOS transistor, the gate of the ninth MOS transistor, and the gate of the tenth MOS transistor are commonly connected to a fourth node and are used to connect to the bias current. The source of the ninth MOS transistor is respectively connected to the collector of the second triode, the base of the second triode, and the second mirror unit. The emitter of the second triode is grounded. The drain of the tenth MOS transistor is connected to the first mirror unit, and the emitter of the tenth MOS transistor is connected to the output terminal of the reference voltage generation circuit.

[0034] In some embodiments, the bandgap reference circuit further includes a second startup circuit;

[0035] The second startup circuit is respectively electrically connected to the bias circuit and the enable terminal of the reference voltage generation circuit. The second startup circuit is configured to respond to the input of the input power supply, send a startup signal to the bias circuit to start the bias circuit, and is further configured to respond to the input of the bias current, stop sending the startup signal, and generate an enable signal to drive the reference voltage generation circuit to operate.

[0036] In some embodiments, the second startup circuit includes an energy storage unit, a third mirror unit, a second switch unit, and a second inverter;

[0037] The control terminals of the energy storage unit, the third mirror unit, the second switch unit, and the input terminal of the second inverter are commonly connected to a fifth node. The first terminal of the second switch unit is connected to the control terminal of the bias circuit, and the second terminal of the second switch unit is grounded;

[0038] The energy storage unit is configured to store energy from the input power supply to raise the voltage of the fifth node, thereby causing the second switch unit to connect the electrical connection between the control terminal of the bias circuit and ground, and send the startup signal to the control terminal of the bias circuit;

[0039] The third mirror unit is configured to mirror the bias current to lower the voltage of the fifth node, thereby causing the second switch unit to disconnect the electrical connection between the control terminal of the bias circuit and ground, stop sending the startup signal, and cause the second inverter to output the enable signal.

[0040] In some embodiments, the energy storage unit includes an energy storage capacitor, the third mirror unit includes an eleventh MOS transistor, and the second switch unit includes a twelfth MOS transistor;

[0041] One end of the energy storage capacitor is used to connect to the energy storage power supply. The other end of the energy storage capacitor, the drain of the eleventh MOS transistor, and the gate of the twelfth MOS transistor are commonly connected to the fifth node. The source of the eleventh MOS transistor and the source of the twelfth MOS transistor are commonly grounded. The gate of the eleventh MOS transistor is connected to the bias circuit, and the drain of the twelfth MOS transistor is connected to the control terminal of the bias circuit.

[0042] In some embodiments, the reference voltage generation circuit includes a third triode, a fourth triode, a first resistor, a second resistor, a third resistor, a fourth resistor, and an operational amplifier;

[0043] The base of the third triode is respectively connected to the base of the fourth triode and the output terminal of the operational amplifier. The collector of the third triode and the collector of the fourth triode are used to access the first power supply voltage or the second power supply voltage. The emitter of the third triode is respectively connected to one end of the third resistor and the non-inverting input terminal of the operational amplifier. The emitter of the fourth triode is connected to one end of the first resistor. The other end of the first resistor is respectively connected to one end of the second resistor and the inverting input terminal of the operational amplifier. The other end of the third resistor and the other end of the second resistor are commonly connected to one end of the fourth resistor, and the fourth resistor is grounded.

[0044] In various embodiments of the present application, the bandgap reference circuit includes a bias circuit, a linear voltage regulator circuit, a state detection circuit, and a reference voltage generation circuit. Among them, the bias circuit generates a bias current according to the input power supply. The state detection circuit detects the startup state of the reference voltage generation circuit and generates a corresponding first detection signal or second detection signal. When the reference voltage generation circuit is not started, the linear voltage regulator circuit responds to the input of the bias current and the first detection signal to generate a first power supply voltage, and the first power supply voltage supplies power to the reference voltage generation circuit. After the reference voltage generation circuit is started, it responds to the input of the first power supply voltage to generate a reference voltage, and the reference voltage is fed back to the linear voltage regulator circuit, so that the linear voltage regulator circuit responds to the input of the bias current, the second detection signal, and the reference voltage, stops generating the first power supply voltage, and generates a second power supply voltage. The second power supply voltage supplies power to the reference voltage generation circuit, so that the reference voltage generation circuit responds to the input of the second power supply voltage and continuously generates a reference voltage. Therefore, the bandgap reference circuit uses a linear voltage regulator circuit to supply power to the reference voltage generation circuit, and the stable reference voltage drives the second power supply voltage generated by the linear voltage regulator circuit to be more stable, and further drives the reference voltage generated by the reference voltage generation circuit to be more stable until the entire circuit reaches a steady state. And because the power supply voltage of the reference voltage generation circuit is stable, the fluctuation of the reference voltage generated by it is small, the anti-interference ability is strong, and the stability is high. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, unless otherwise stated, and the drawings in the drawings do not constitute a proportional limitation.

[0046] Figure 1 is a schematic structural diagram of one of the bandgap reference circuits provided by the embodiments of the present application;

[0047] Figure 2 is a schematic structural diagram of one of the bandgap reference circuits provided by the embodiments of the present application;

[0048] Figure 3 It is a schematic structural diagram of one of the bandgap reference circuits provided by an embodiment of the present application;

[0049] Figure 4 It is a schematic structural diagram of one of the linear voltage regulator circuits provided by an embodiment of the present application;

[0050] Figure 5 It is a schematic structural diagram of one of the first voltage regulator unit and the second voltage regulator unit provided by an embodiment of the present application;

[0051] Figure 6 It is a schematic structural diagram of one of the state detection circuits provided by an embodiment of the present application;

[0052] Figure 7 It is a schematic structural diagram of one of the second startup circuits provided by an embodiment of the present application;

[0053] Figure 8 It is a schematic circuit diagram of one of the second startup circuit and the bias circuit provided by an embodiment of the present application;

[0054] Figure 9 It is a schematic circuit diagram of one of the first startup circuit and the state detection circuit provided by an embodiment of the present application;

[0055] Figure 10 It is a schematic circuit diagram of one of the linear voltage regulator circuits provided by an embodiment of the present application;

[0056] Figure 11 It is a schematic circuit diagram of one of the reference voltage generation circuits provided by an embodiment of the present application;

[0057] Figure 12 It is a schematic diagram of one of the DC simulation curves of the temperature drift of the reference voltage provided by an embodiment of the present application;

[0058] Figure 13 It is a schematic diagram of one of the AC simulation curves of the reference voltage rejection ratio provided by an embodiment of the present application. Detailed implementation manners

[0059] In order to make the objectives, technical solutions and advantages of the present application more clear and understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not configured to limit the present application.

[0060] Please refer to Figure 1 , Figure 1 It is a schematic structural diagram of a bandgap reference circuit provided by an embodiment of the present application, as shown in Figure 1As shown in the figure, the bandgap reference circuit 100 includes a bias circuit 10, a linear voltage regulator circuit 20, a status detection circuit 30, and a reference voltage generation circuit 40. Among them, the bias circuit 10 is electrically connected to the linear voltage regulator circuit 20 and the reference voltage generation circuit 40 respectively. The linear voltage regulator circuit 20 is also electrically connected to the power supply terminal VCC of the reference voltage generation circuit 40. The output terminal of the reference voltage generation circuit 40 is electrically connected to the linear voltage regulator circuit 20 and the status detection circuit 30 respectively, and the status detection circuit 30 is also electrically connected to the linear voltage regulator circuit 20.

[0061] The bias circuit 10 generates a bias current according to the input power supply VIN, and provides the bias current to the linear voltage regulator circuit 20 and the reference voltage generation circuit 40 respectively. The bias current provides appropriate bias for the linear voltage regulator circuit 20 and the reference voltage generation circuit 40 to maintain their normal working states.

[0062] When the reference voltage generation circuit 40 is not started, other circuits are needed to pull it out of the zero state. After the start-up is completed, it starts to continuously generate the reference voltage. Therefore, the status detection circuit 30 is used to detect the start-up status of the reference voltage generation circuit 40, generate a corresponding detection signal, and send the corresponding detection signal to the linear voltage regulator circuit 20, so that the linear voltage regulator circuit 20 provides different supply voltages to the reference voltage generation circuit 40. When the reference voltage generation circuit 40 is not started, the status detection circuit 30 generates a first detection signal. After the reference voltage generation circuit 40 is started, a second detection signal is generated.

[0063] When the reference voltage generation circuit 40 is not started, the status detection circuit 30 generates a first detection signal. The linear voltage regulator circuit 20 responds to the input of the bias current and the first detection, generates a first supply voltage, and supplies the first supply voltage to the reference voltage generation circuit 40, so that after the reference voltage generation circuit 40 is started, it responds to the input of the first supply voltage and the bias current and generates the reference voltage VBG.

[0064] The first supply voltage is generated based on the input power supply VIN. If the input power supply VIN fluctuates, it will drive the first supply voltage to fluctuate. Therefore, the first supply voltage is easily interfered with and has a large fluctuation, which in turn causes the reference voltage VBG generated by the reference voltage generation circuit 40 to also fluctuate and be unstable.

[0065] When the linear voltage regulator circuit 20 receives the reference voltage VBG and the second detection signal, it indicates that the reference voltage generation circuit 40 has completed the start-up. The linear voltage regulator circuit 20 responds to the input of the bias current, the second detection signal, and the reference voltage VBG, stops generating the first supply voltage, and generates a second supply voltage, thereby enabling the reference voltage generation circuit 40 to respond to the input of the second supply voltage and continuously generate the reference voltage VBG.

[0066] The linear voltage regulator circuit 20 generates a second supply voltage based on the reference voltage VBG, so that the second supply voltage is no longer affected by the fluctuations of the input power supply VIN, and is relatively stable. And the relatively stable second supply voltage continues to supply power to the reference voltage generation circuit 40, so that the reference voltage generation circuit 40 generates a more stable reference voltage VBG. The more stable reference voltage VBG continues to drive the second supply voltage generated by the linear voltage regulator circuit 20 to be more stable, and then the reference voltage VBG generated by the reference voltage generation circuit 40 is more stable until the loop reaches a steady state.

[0067] Therefore, since the linear voltage regulator circuit 20 provides a more stable supply voltage to the reference voltage generation circuit 40, the reference voltage VBG generated by the reference voltage generation circuit 40 is also more stable, not affected by the fluctuations of the input power supply VIN, improving the anti-interference ability of the bandgap reference circuit 100.

[0068] At the same time, in the related art, in order to improve the anti-interference ability of the bandgap reference circuit 100, generally the loop bandwidth of the bandgap reference circuit 100 is made high, and a high bandwidth means a large current, that is, high power consumption. And in the embodiment of the present application, the magnitude of the bias current affects the power consumption of the linear voltage regulator circuit 20, and the bias current is generally small, only a few milliamperes or even a few nanoamperes, making the power consumption of the linear voltage regulator circuit 20 also small.

[0069] Therefore, the embodiment of the present application uses the linear voltage regulator circuit 20 to provide a more stable supply voltage to the reference voltage generation circuit 40, so that the reference voltage generation circuit 40 generates a more stable reference voltage VBG, improving the anti-interference ability of the bandgap reference circuit 100. At the same time, the power consumption of the linear voltage regulator circuit 20 is also small, so that the bandgap reference circuit 100 has a low power consumption on the basis of high anti-interference ability.

[0070] In summary, the bandgap reference circuit uses a linear voltage regulator circuit to supply power to the reference voltage generation circuit, and the stable reference voltage drives the second supply voltage generated by the linear voltage regulator circuit to be more stable, and then drives the reference voltage generated by the reference voltage generation circuit to be more stable until the entire circuit reaches a steady state. And because the supply voltage of the reference voltage generation circuit is stable, the fluctuation of the reference voltage generated by it is small, the anti-interference ability is stronger, and the stability is higher.

[0071] Please refer to Figure 2 , Figure 2 which is a schematic structural diagram of a bandgap reference circuit provided by an embodiment of the present application. As Figure 2 shown, the bandgap reference circuit 100 further includes a first startup circuit 50, and the first startup circuit 50 is electrically connected to the output end of the reference voltage generation circuit 40 and the state detection circuit 30 respectively.

[0072] When just powered on, the reference voltage generation circuit 40 may be in a stable state with zero current, also known as the zero state, in which it is in an unstarted state and cannot generate a stable reference voltage VBG. To break the stable state of zero current or pull the reference voltage generation circuit 40 out of the zero state, in the embodiment of the present application, the first startup circuit 50 injects an initial current into the reference voltage generation circuit 40 at the moment of power-on, so that the reference voltage generation circuit 40 starts and enters the normal working state.

[0073] Specifically, at the moment of power-on, the bias circuit 10 provides a bias current to the first startup circuit 50, so that the first startup circuit 50 generates a startup current based on the bias current, and the startup current is injected into the reference voltage generation circuit 40 to start the reference voltage generation circuit 40 and start normal operation.

[0074] After the reference voltage generation circuit 40 is started, it generates the reference voltage VBG, and the reference voltage VBG acts on the first startup circuit 50, so that the first startup circuit 50 stops generating the startup current, avoiding interference with the normal operation of the reference generation circuit, and thus ensuring that the output of the reference voltage generation circuit 40 is not affected by the first startup circuit 50.

[0075] In the embodiment of the present application, the first startup circuit 50 provides a stable and reliable startup condition for the reference voltage generation circuit 40, ensuring that no matter in what circumstances, as long as the input power supply VIN is powered on, the reference voltage generation circuit 40 can smoothly enter the normal working state, thereby ensuring the stability and reliability of the entire system. At the same time, after the first startup circuit 50 completes the startup task, it stops generating the startup current, ensuring that the reference voltage generation circuit 40 can work normally and avoiding interference from the first startup circuit 50.

[0076] Please refer to Figure 3 , Figure 3 which is a schematic structural diagram of a bandgap reference circuit provided by the embodiment of the present application. As Figure 3 shown, the bandgap reference circuit 100 further includes a second startup circuit 60, and the second startup circuit 60 is electrically connected to the bias circuit 10 and the enable terminal of the reference voltage generation circuit 40 respectively.

[0077] The second startup circuit 60 is used to start the bias circuit 10 so that it can generate a bias current, thereby ensuring the normal operation of other circuits. Specifically, the second startup circuit 60 is electrically connected to the input power supply VIN. When the power supply is powered on, the second startup circuit 60 sends a startup signal to the bias circuit 10 based on the input power supply VIN to start the bias circuit 10, so that the bias circuit 10 can normally generate a bias current. After the bias current is generated, the second startup circuit 60 stops sending the startup signal to avoid affecting the normal operation of the bias circuit 10 and ensure the normal output of the bias current. At the same time, after the bias current is generated, the second startup circuit 60 also generates an enable signal based on the bias current to act on the enable terminal of the reference voltage generation circuit 40, thereby driving the reference voltage generation circuit 40 to work.

[0078] Therefore, in the embodiment of the present application, when powered on, the second startup circuit 60 is used to start the bias circuit 10 to normally generate a bias current. At the same time, after the bias circuit 10 is started up, the startup signal is stopped being sent to prevent affecting the normal operation of the bias circuit 10, and the reference voltage generation circuit 40 obtains the enable signal and enters the working state after the bias current is generated, reducing power consumption.

[0079] Please refer to Figure 4 , Figure 4 which is a schematic structural diagram of a linear voltage regulator circuit provided by an embodiment of the present application. As Figure 4 shown, the linear voltage regulator circuit 20 includes a first voltage regulator unit 21 and a second voltage regulator unit 22. Among them, the first voltage regulator unit 21 is electrically connected to the state detection circuit 30, and the first voltage regulator unit 21, the second voltage regulator unit 22, and the power supply terminal VCC terminal of the reference voltage generation circuit 40 are commonly connected to the first node A. The second voltage regulator unit 22 is also electrically connected to the output terminal of the reference voltage generation circuit 40.

[0080] The bias circuit 10 continuously provides bias currents for the first voltage regulator unit 21 and the second voltage regulator unit 22 respectively, so that the first voltage regulator unit 21 and the second voltage regulator unit 22 can work normally.

[0081] When the reference voltage generation circuit 40 is not started up, the state detection circuit 30 generates a first detection signal. The first voltage regulator unit 21 responds to the input of the first detection signal and generates a first supply voltage at the first node A.

[0082] After the reference voltage generation circuit 40 is started, the first power supply voltage supplies power to the reference voltage generation circuit 40 to make it work normally and generate the reference voltage VBG. Then, the reference voltage VBG acts on the second voltage stabilizing unit 22, causing the second voltage stabilizing unit 22 to respond to the input of the reference voltage VBG and generate the second power supply voltage at the first node A. At the same time, after the reference voltage generation circuit 40 is started, the state detection circuit 30 generates a second detection signal, and the first voltage stabilizing unit 21 responds to the input of the second detection signal and stops generating the first power supply voltage at the first node A.

[0083] The second power supply voltage is generated based on the reference voltage VBG, and it is not affected by the fluctuations of the input power supply VIN, making it more stable. Furthermore, this enables the reference voltage generation circuit 40 to generate a more stable reference voltage VBG, and the more stable reference voltage VBG drives the second stabilizing unit to generate a more stable second power supply voltage. This cycle continues until the loop reaches a steady state.

[0084] After the reference voltage generation circuit 40 is started, the second voltage stabilizing unit 22 continuously provides a more stable second power supply voltage to the reference voltage generation circuit 40, making the reference voltage VBG generated by the reference voltage generation circuit 40 more stable, and further enhancing the anti-interference ability of the entire circuit.

[0085] At the same time, the first voltage stabilizing unit 21 and the second voltage stabilizing unit 22 can work normally with only appropriate bias currents. The bias currents are relatively small, resulting in lower power consumption for the first voltage stabilizing unit 21 and the second voltage stabilizing unit 22, and thus lower power consumption for the entire circuit. Therefore, the bandgap reference circuit 100 has both high anti-interference ability and low power consumption.

[0086] Please refer to Figure 5 , Figure 5 which is a schematic structural diagram of a first voltage stabilizing unit and a second voltage stabilizing unit provided by an embodiment of the present application. As Figure 5 shown, the first voltage stabilizing unit 21 includes a first voltage generation unit 211, a first voltage follower unit 212, and a first switch unit 213. Among them, the input end of the first voltage generation unit 211 is electrically connected to the input end of the first voltage follower unit 212, the output end of the first voltage follower unit 212 is electrically connected to the first end of the first switch unit 213, the second end of the first switch unit 213 is electrically connected to the first node A, the control end of the first switch unit 213 is electrically connected to the state detection circuit 30, and the power supply end VCC of the first voltage follower unit 212 is electrically connected to the input power supply VIN.

[0087] The first voltage generating unit 211 generates a first voltage based on a bias current, such that the first voltage following unit 212 generates a first supply voltage based on the first voltage. When the reference voltage generating circuit 40 is not started, the state detection circuit 30 generates a first detection signal to control the first switching circuit to be in a conducting state, thereby connecting the output terminal of the first voltage following unit 212 and the first node A, so as to output the first supply voltage at the first node A.

[0088] After the reference voltage generating circuit 40 is started, the state detection circuit 30 generates a second detection signal to control the first switching circuit to be in a non-conducting state, thereby disconnecting the output terminal of the first voltage following unit 212 and the first node A, and stopping the output of the first supply voltage at the first node A.

[0089] In the embodiment of the present application, the first voltage generating unit 211 generates a first voltage, and can generate a suitable first voltage according to the power supply requirement of the reference voltage generating circuit 40. However, since the load current of the first voltage generating unit 211 is a bias current, and the bias current is generally a relatively small current, it cannot effectively carry the load. To improve the load-carrying capacity, the first voltage following unit 212 is provided in the present application. It can not only follow the first voltage, but also generate a larger load current based on the input power supply VIN, and can drive the load.

[0090] The embodiment of the present application also uses the first switching circuit to control the output of the first supply voltage, so as to stop the output of the first supply voltage in time after the reference voltage generating circuit 40 starts to generate the reference voltage VBG, prevent the influence of the first supply voltage on the second supply voltage, and enable the reference voltage generating circuit 40 to be completely powered by a more stable second supply voltage, thereby improving the anti-interference ability.

[0091] Please continue to refer to Figure 5 , the second voltage stabilizing unit 22 includes a second voltage generating unit 221 and a second voltage following unit 222. Among them, the second voltage generating unit 221 is electrically connected to the output terminal of the reference voltage generating circuit 40 and the input terminal of the second voltage following unit 222 respectively. The output terminal of the second voltage following unit 222 is electrically connected to the first node A, and the power supply terminal VCC of the second voltage following unit 222 is electrically connected to the input power supply VIN.

[0092] The bias circuit 10 also provides a bias current for the second voltage generating unit 221 to enable it to work normally. At the same time, after the reference voltage generating circuit 40 is started and it generates the reference voltage VBG, the second voltage generating unit 221 responds to the input of the reference voltage VBG to generate a second voltage, such that the second voltage following unit 222 generates a second supply voltage at the first node A based on the second voltage, so as to provide the second supply voltage for the reference voltage generating circuit 40.

[0093] In the embodiment of the present application, the reference voltage VBG controls the second voltage generating unit 221 to generate a second voltage, and further controls the generation of the second supply voltage, so that the second voltage generating unit 221, the second voltage following unit 222, and the reference voltage generating circuit 40 form a loop. When the loop reaches a steady state, both the second supply voltage and the reference voltage VBG reach stable voltages, and the anti-interference ability is relatively strong.

[0094] At the same time, since the load current of the second voltage generating unit 221 is a bias current, and the bias current is generally a relatively small current, it cannot effectively carry the load. To improve the load-carrying capacity, the present application provides a second voltage following unit 222, which can not only follow the second voltage, but also generate a larger load current based on the input power supply VIN and can drive the load.

[0095] Please refer to Figure 6 , Figure 6 which is a schematic structural diagram of a state detection circuit provided by an embodiment of the present application. In the embodiment of the present application, the bandgap reference circuit 100 includes a first startup circuit 50, a bias circuit 10, a linear voltage regulator circuit 20, a state detection circuit 30, and a reference voltage generating circuit 40. Among them, the state detection circuit 30 includes a first mirror unit 31, a second mirror unit 32, and a first inverter 33. The input ends of the first mirror unit 31, the second mirror unit 32, and the first inverter 33 are commonly connected to the third node C. The output end of the first inverter 33 is electrically connected to the linear voltage regulator circuit 20.

[0096] When the first startup circuit 50 generates a startup current to start the reference voltage generating circuit 40, the first mirror unit 31 mirrors the startup current and raises the voltage of the third node C based on the startup current, so that the third node C is in a high-level state, and then the first inverter 33 outputs a first detection signal, and the first detection signal is a low-level signal.

[0097] After the reference voltage generating circuit 40 finishes starting up, the startup current stops being generated. Then the second mirror unit 32 mirrors the bias current and pulls down the voltage of the third node C based on the mirrored bias current, so that the third node C is in a low-level state, and then the first inverter 33 outputs a second detection signal, and the second detection signal is a high-level signal.

[0098] To ensure that the reference voltage generation circuit 40 can start, a large starting current is used, which can ensure that the first mirror unit 31 can raise the voltage at the third node C. After the reference voltage generation circuit 40 starts up, since the bias current is less than the starting current, it can ensure that the second mirror unit 32 can lower the voltage at the third node C, so that when the reference voltage generation circuit 40 is in different states, the first inverter 33 can output different detection signals, and then control the linear voltage regulator circuit 20 to provide different supply voltages for the reference voltage generation circuit 40.

[0099] Please refer to Figure 7 , Figure 7 which is a schematic structural diagram of a second startup circuit provided by an embodiment of the present application. As Figure 7 shown, the second startup circuit 60 includes an energy storage unit 61, a third mirror unit 62, a second switch unit 63, and a second inverter 64. Among them, the control ends of the energy storage unit 61, the third mirror unit 62, and the second switch unit 63, and the input end of the second inverter 64 are commonly connected to the fifth node E. The first end of the second switch unit 63 is connected to the control end of the bias circuit 10, and the second end of the second switch unit 63 is grounded to AGND.

[0100] The energy storage unit 61 stores energy from the input power supply VIN to raise the voltage of the fifth node E, so that the voltage of the fifth node E is in a high level state, and then the second switch unit 63 is in a conducting state, connecting the control end of the bias circuit 10 and the ground AGND. The control end of the bias circuit 10 receives a startup signal, and the startup signal is a low level signal, thus starting the bias circuit 10 to generate a bias current.

[0101] After the bias circuit 10 starts up, the third mirror unit 62 mirrors the bias current and pulls down the voltage of the fifth node E based on the mirrored bias current, so that the voltage of the fifth node E is in a low level state, and then the second switch unit 63 is in a cutoff state, disconnecting the electrical connection between the bias circuit 10 and the ground AGND, and stopping sending the startup signal to the control end of the bias circuit 10.

[0102] The second inverter 64 generates an enable signal based on the pulled-down voltage of the fifth node E. When the voltage of the fifth node E is in a low level state, the second inverter 64 outputs an enable signal in a high level state, thereby driving the reference voltage generation circuit 40 to work normally.

[0103] In the embodiment of the present application, the energy storage unit 61 stores energy for the input power supply VIN, so that the voltage at the fifth node E is at a high level before the bias circuit 10 is started, thereby starting the bias circuit 10. During the startup process, no current startup is required, so that the power consumption of the second startup circuit 60 is relatively low, and further reduces the overall power consumption of the bandgap reference circuit 100.

[0104] Please refer to Figure 8 , Figure 8 which is a schematic circuit diagram of a second startup circuit and a bias circuit provided by an embodiment of the present application. As Figure 8 shown, the energy storage unit 61 includes an energy storage capacitor CB2, the third mirror unit 62 includes an eleventh MOS transistor M11, and the second switch unit 63 includes a twelfth MOS transistor M12. One end of the energy storage capacitor CB2 is used to connect to the input power supply VIN, and the other end of the energy storage capacitor CB2 is commonly connected to the fifth node E together with the drain of the eleventh MOS transistor M11 and the gate of the twelfth MOS transistor M12. The source of the eleventh MOS transistor M11 and the source of the twelfth MOS transistor M12 are commonly grounded to AGND. The gate of the eleventh MOS transistor M11 is connected to the bias circuit 10, and the drain of the second MOS transistor is connected to the control end of the bias circuit 10.

[0105] The bias circuit 10 includes a thirteenth MOS transistor M13, a fourteenth MOS transistor M14, a fifteenth MOS transistor M15, a sixteenth MOS transistor M16, and a bias resistor RB1. The source of the thirteenth MOS transistor M13 and the source of the fourteenth MOS transistor M14 are commonly connected to the input power supply VIN. The gate of the thirteenth MOS transistor M13, the drain of the thirteenth MOS transistor M13, and the gate of the fourteenth MOS transistor M14 are commonly connected to the fifth node E. The drain of the thirteenth MOS transistor M13 is also connected to the drain of the fifteenth MOS transistor M15. The gate of the fifteenth MOS transistor M15 is respectively connected to the gate of the sixteenth MOS transistor M16, the drain of the sixteenth MOS transistor M16, the drain of the fourteenth MOS transistor M14, and the gate of the eleventh MOS transistor M11. The source of the fifteenth MOS transistor M15 is connected to one end of the bias resistor RB1, and the other end of the bias resistor RB1 is grounded to AGND. The source of the sixteenth MOS transistor M16 is grounded to AGND.

[0106] When powered on, the energy storage capacitor CB2 stores energy from the input power supply VIN. Since the voltage across the energy storage capacitor CB2 cannot change abruptly, the voltage VS at the fifth node E is approximately equal to the voltage VIN of the input power supply VIN. The potential at the fifth node E is high, and the twelfth MOS transistor M12 conducts, connecting the gates of the thirteenth MOS transistor M13 and the fourteenth MOS transistor M14 to the ground AGND, that is, sending a low-level startup signal to the gates of the thirteenth MOS transistor M13 and the fourteenth MOS transistor M14, making the gate potentials of the thirteenth MOS transistor M13 and the fourteenth MOS transistor M14 become low, and the thirteenth MOS transistor M13 and the fourteenth MOS transistor M14 conduct, starting the entire bias circuit 10 and generating a bias current based on the input power supply VIN.

[0107] After the bias current is generated, the eleventh MOS transistor M11 mirrors the current of the sixteenth MOS transistor M16, thereby pulling down the potential at the fifth node E, turning off the twelfth MOS transistor M12, and disconnecting the electrical connection between the gates of the thirteenth MOS transistor M13 and the fourteenth MOS transistor M14 and the ground AGND, that is, stopping sending the startup signal to the gates of the thirteenth MOS transistor M13 and the fourteenth MOS transistor M14.

[0108] The input terminal of the second inverter INV2 is connected to the fifth node E. When the potential at the fifth node E is pulled down, the second inverter INV2 outputs a high-level enable signal, and this enable signal acts on the enable terminal of the reference voltage generation circuit 40 to drive the reference voltage generation circuit 40 to work.

[0109] Before the bias circuit 10 is started, the potential at the fifth node E is high, making the twelfth MOS transistor M12 conduct, and then starting the bias circuit 10 to generate a bias current. The embodiment of the present application realizes zero-current startup of the bias circuit 10, so the second startup circuit 60 has no current power consumption. And the bias current can be set as needed. In the embodiment of the present application, by selecting the models of the thirteenth MOS transistor M13 to the sixteenth MOS transistor M16 and the resistance value of the bias resistor RB1, a bias current of 5 nA is generated, and the entire bias circuit 10 only has a current power consumption of 10 nA, with relatively low power consumption.

[0110] Please refer to Figure 9 , Figure 9 which is a schematic circuit diagram of a first startup circuit and a state detection circuit provided by an embodiment of the present application. As Figure 9As shown, the first mirror unit 31 includes a seventh MOS transistor M7 and an eighth MOS transistor M8, and the second mirror unit 32 includes a first triode Q1. The drain of the seventh MOS transistor M7 is connected to the gate of the seventh MOS transistor M7, the gate of the eighth MOS transistor M8, and the first startup circuit 50 respectively. The source of the seventh MOS transistor M7 and the source of the eighth MOS transistor M8 are both used to connect to the input power supply VIN. The drain of the eighth MOS transistor M8, the collector of the first triode Q1, and the input terminal of the first inverter INV1 are commonly connected to the third node C. The base of the first triode Q1 is electrically connected to the first startup circuit 50, and the emitter of the first triode Q1 is grounded to AGND.

[0111] The first startup circuit 50 includes a ninth MOS transistor M9, a tenth MOS transistor M10, and a second triode Q2. The drain of the ninth MOS transistor M9, the gate of the ninth MOS transistor M9, and the gate of the tenth MOS transistor M10 are commonly connected to the fourth node D and are used to connect to a bias current. The source of the ninth MOS transistor M9 is connected to the collector of the second triode Q2, the base of the second triode Q2, and the second mirror unit 32 respectively. Specifically, the source of the ninth MOS transistor M9 is connected to the collector of the second triode Q2, the base of the second triode Q2, and the base of the first triode Q1 respectively. The emitter of the second triode Q2 is grounded to AGND. The drain of the tenth MOS transistor M10 is connected to the first mirror unit 31. Specifically, the drain of the tenth MOS transistor M10 is connected to the drain of the seventh MOS transistor M7. The emitter of the tenth MOS transistor M10 is connected to the output terminal of the reference voltage generation circuit 40.

[0112] The bias current of the first startup circuit 50 is current I7, which is generated by the bias circuit 10. The current I7 is applied to the ninth MOS transistor M9 and the second triode Q2 connected in diode configuration, generating a startup voltage VSY at the fourth node D. The width-to-length ratio of the tenth MOS transistor M10 is much larger than that of the ninth MOS transistor M9. When the reference voltage generation circuit 40 is not started, the reference voltage VBG is zero. The source voltage of the tenth MOS transistor M10 is zero, and its gate voltage is the startup voltage VSY. Then, the tenth MOS transistor M10 sinks current to its source, causing the source voltage of the tenth MOS transistor M10 to rise, that is, lifting the reference voltage VBG output by the reference voltage generation circuit 40, and further pulling the reference voltage generation circuit 40 out of the zero state to start the reference voltage generation circuit 40.

[0113] And due to the reduction of the gate-source voltage of the tenth MOS transistor M10, the tenth MOS transistor M10 is turned off. For example, if the current I7 is 5 nA, the startup voltage VSY is about 1.4 V, and the source voltage of the tenth MOS transistor M10 can be lifted to 1 V. Then, the gate-source voltage VGS of the tenth MOS transistor M10 is only 0.4 V, so the tenth MOS transistor M10 is turned off.

[0114] The status detection circuit 30 detects the startup status of the reference voltage generation circuit 40. Specifically, during the injection of the current I7 and the startup process of the reference voltage generation circuit 40, since the startup voltage VSY is relatively high, a large current will flow through the tenth MOS transistor M10, so a large current will flow through the seventh MOS transistor M7. The eighth MOS transistor M8 mirrors the current of the seventh MOS transistor M7, and a large current flows through the eighth MOS transistor M8, which raises the voltage of the third node C, causing the first inverter INV1 to output a first detection signal. The first detection signal is a low-level signal, that is, the signal VBG_OK is a low-level signal.

[0115] After the reference voltage generation circuit 40 finishes starting up, the tenth MOS transistor M10 is turned off, so the current of the eighth MOS transistor M8 is zero. Then the first triode Q1 mirrors the current of the second triode Q2. The current of the second triode Q2 is the current I7, and the current is relatively small, so the voltage generated on the first triode Q1 is relatively small, pulling down the voltage of the third node C, causing the first inverter INV1 to output a second detection signal. The second detection signal is a high-level signal, that is, the signal VBG_OK is a high-level signal.

[0116] In some embodiments, the status detection circuit 30 further includes a capacitor CS1. The capacitor CS1 is connected in parallel between the input power supply VIN and the input terminal of the first inverter INV1. When the reference voltage generation circuit 40 is not started, the capacitor CS1 stores energy from the input power supply VIN, raising the voltage of the third node C, thereby ensuring that the first inverter INV1 outputs a low-level first detection signal. After the reference voltage generation circuit 40 starts up, the first triode Q1 pulls down the voltage of the third node C, so that the first inverter INV1 outputs a high-level second detection signal.

[0117] The embodiment of the present application uses the capacitor CS1 to ensure that the first inverter INV1 generates a low-level first detection signal when the reference voltage generation circuit 40 is not started, providing a redundancy measure, thereby improving the reliability of the circuit operation.

[0118] If the current I7 is 5 nA, the current power consumption of the first startup circuit 50 is only 5 nA, and the power consumption is relatively low.

[0119] Please refer to Figure 10 , Figure 10 which is a schematic circuit diagram of a linear voltage regulator circuit provided by the embodiment of the present application. As Figure 10As shown in the figure, the first voltage generation unit 211 includes a first MOS transistor M1 and a second MOS transistor M2, the first voltage follower unit 212 includes a third MOS transistor M3, and the first switch unit 213 includes a fourth MOS transistor M4. The drain of the first MOS transistor M1, the gate of the first MOS transistor M1, and the gate of the third MOS transistor M3 are all used to access the bias current. The source of the first MOS transistor M1 is respectively connected to the drain and the gate of the second MOS transistor M2. The source of the second MOS transistor M2 is grounded to AGND. The drain of the third MOS transistor M3 is used to access the input power supply VIN. The source of the third MOS transistor M3 is connected to the source of the fourth MOS transistor M4. The drain of the fourth MOS transistor M4 is connected to the power supply terminal VCC of the reference voltage generation circuit 40 at the first node A. The gate of the fourth MOS transistor M4 is electrically connected to the state detection circuit 30.

[0120] The second voltage follower unit 222 includes a fifth MOS transistor M5, and the second voltage generation unit 221 includes a sixth MOS transistor M6. The source of the fifth MOS transistor M5 is electrically connected to the first node A. The drain of the fifth MOS transistor M5 is used to access the input power supply VIN. The gate of the fifth MOS transistor M5 and the source of the sixth MOS transistor M6 are both used to access the bias current. The gate of the sixth MOS transistor M6 is electrically connected to the output terminal of the reference voltage generation circuit 40. The drain of the sixth MOS transistor M6 is grounded to AGND.

[0121] The bias current of the first voltage stabilizing unit 21 is current I1, and the bias current of the second voltage stabilizing unit 22 is current I2. Both current I1 and current I2 are generated by the bias circuit 10.

[0122] Current I1 flows through the first MOS transistor M1 and the second MOS transistor M2. The first MOS transistor M1 and the second MOS transistor M2 are connected in diode configuration. Then, the gate voltage of the first MOS transistor M1, that is, the first voltage VX = VGS1 + VGS2. The third MOS transistor M3 generates the first supply voltage VCC1 based on the first voltage. At this time, the reference voltage generation circuit 40 is not started. The gate of the fourth MOS transistor M4 is a first detection signal with a low level. Then, the fourth MOS transistor M4 is turned on, and the voltage of the first node A is set to the first supply voltage VCC1 through the fourth MOS transistor M4.

[0123] The first supply voltage VCC1 is generated based on the input power supply VIN. It is easily affected by process, voltage, and temperature, with large fluctuations, large deviations, and poor stability. Therefore, using the first supply voltage VCC1 to supply power to the reference voltage generation circuit 40 will also make the reference voltage VBG unstable. In order to obtain a more stable reference voltage VBG, the second voltage stabilizing unit 22 generates a second supply voltage to supply power to the reference voltage generation circuit 40.

[0124] The first supply voltage VCC1 serves as the supply voltage for the reference voltage generation circuit 40. After the reference voltage generation circuit 40 is started, a reference voltage VBG is generated. And when the gate of the fourth MOS transistor M4 receives a high-level second detection signal, the fourth MOS transistor M4 is turned off, and the output of the first supply voltage VCC1 stops. At the same time, the reference voltage VBG acts on the gate of the sixth MOS transistor M6, then the second voltage VY = VBG + VGS M6 , then the second supply voltage is generated at the first node A point through the source of the fifth MOS transistor M5:

[0125] VCC2 = VY - VGS M5 = VBG + VGS M6 - VGS M5 (1)

[0126] wherein, VCC2 is the second supply voltage, VBG is the reference voltage VBG, VGS M6 is the gate-source voltage of the sixth MOS transistor M6, and VGS M5 is the gate-source voltage of the fifth MOS transistor M5.

[0127] Therefore, the second supply voltage VCC2 is not affected by the input power supply VIN, and is only related to the reference voltage VBG. The reference voltage VBG is relatively stable, which makes the second supply voltage VCC2 more stable. The second supply voltage VCC2 supplies power to the reference voltage generation circuit 40, which makes the reference voltage generation circuit 40 generate a more stable reference voltage VBG. The loop circulates like this until it reaches a steady state.

[0128] In the embodiment of the present application, when the reference voltage generation circuit 40 is not started, a first supply voltage is provided to it so that the reference voltage generation circuit 40 generates a reference voltage VBG. And after the reference voltage generation circuit 40 is started, a more stable second supply voltage is generated based on the reference voltage VBG, and the more stable second supply voltage is supplied to the reference voltage generation circuit 40, so that the reference voltage generation circuit 40 generates a more stable reference voltage VBG. The supply voltage of the reference voltage generation circuit 40 is more stable, so it is less affected by power fluctuations and has stronger anti-interference ability.

[0129] Moreover, both the current I1 and the current I2 are bias currents, and the currents are small, so the current power consumption of the first voltage stabilizing unit 21 and the second voltage stabilizing unit 22 are both small.

[0130] The values of the first supply voltage VCC1 and the second supply voltage VCC2 can be set as needed. For example, if the current I1 is 5 nA and the current I2 is 5 nA, then the first voltage VX is approximately 1.8 V and is easily susceptible to interference. The first supply voltage is approximately 1.4 V and has a large fluctuation. After the reference voltage generation circuit 40 is started, if the reference voltage VBG is 1.2 V, then the second voltage VY is a relatively accurate 1.8 V, the second supply voltage is approximately 1.4 V and has a small fluctuation. The entire linear voltage regulator circuit 20 consumes only 10 nA of current.

[0131] Please refer to Figure 11 , Figure 11 which is a schematic diagram of the circuit structure of a reference voltage generation circuit provided by an embodiment of the present application. As Figure 11 shown, the reference voltage generation circuit 40 includes a third triode Q3, a fourth triode Q4, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and an operational amplifier U1.

[0132] The base of the third triode Q3 is respectively connected to the base of the fourth triode Q4 and the output terminal of the operational amplifier U1. The collector of the third triode Q3 and the collector of the fourth triode Q4 are connected to the supply terminal VCC of the reference voltage generation circuit. The emitter of the third triode Q3 is respectively connected to one end of the third resistor R3 and the non-inverting input terminal of the operational amplifier U1. The emitter of the fourth triode Q4 is connected to one end of the first resistor R1. The other end of the first resistor R1 is respectively connected to one end of the second resistor R2 and the inverting input terminal of the operational amplifier U1. The other ends of the third resistor R3 and the second resistor R2 are commonly connected to one end of the fourth resistor R4, and the fourth resistor R4 is grounded to AGND.

[0133] The voltage VP at the non-inverting input terminal of the operational amplifier U1 is equal to the voltage VN at its inverting input terminal. Then, the current IR1 flowing through the first resistor R1 is calculated by the following formula:

[0134] IR1 = (VBE2 - VBE3) / R1 (2)

[0135] where IR1 is the current of the first resistor R1, VBE2 is the base-emitter voltage difference of the third triode Q3, and VBE3 is the base-emitter voltage difference of the fourth triode Q4.

[0136] The currents flowing through the first resistor R1, the second resistor R2, and the third resistor R3 are equal and are all IR1. Then, the current flowing through the fourth resistor R4 is 2*IR1. The reference voltage VBG is:

[0137] VBG = IR1*(2*r4 + r3) + VBE2 (3)

[0138] Among them, VBG is the reference voltage VBG, r4 is the resistance value of the fourth resistor R4, r3 is the resistance value of the third resistor R3, and VBE2 is the base-emitter voltage difference of the third triode Q3.

[0139] By designing the resistance values of the first resistor R1, the second resistor R2, and the third resistor R3, different reference voltages VBG can be obtained. If the resistance value of the first resistor R1 is 2.7 MΩ, the resistance value of the second resistor R2 is equal to that of the third resistor R3 which is 18 MΩ, the resistance value of the fourth resistor R4 is 10 MΩ, and the bias current is 5 nA, then the reference voltage VBG can be obtained as 1.204 V through formulas (2) and (3).

[0140] In the embodiment of the present application, the third triode Q3 and the fourth triode Q4 are NPN triodes, and the third triode Q3 and the fourth triode Q4 are directly connected to the first power supply voltage or the second power supply voltage, that is, directly connected to the power supply VCC terminal, far from the ground AGND, which can effectively isolate the interference of the chip substrate noise and obtain good anti-ground AGND interference ability. And the collectors of the third triode Q3 and the fourth triode Q4 are directly connected to the power supply VCC terminal. Then, at high temperatures, the nA-level leakage current from the collector to the substrate will not cause a large offset of the reference voltage VBG, which improves the temperature drift characteristic of the bandgap reference. The embodiment of the present application uses the linear voltage regulator circuit 20 to provide a clean VCC power supply for the reference voltage generation circuit 40, greatly reducing the influence of the noise of the input power supply VINVIN on the reference voltage VBG.

[0141] If the bias current provided by the bias circuit 10 for the operational amplifier U1 is 5 nA, then the operational amplifier U1 only has a current consumption of 35 nA, and the current IR1 flowing through the first resistor R1 only has 20 nA, and the current consumption is also small.

[0142] Please refer to Figure 12 , Figure 12 which is a schematic diagram of a DC simulation curve of the temperature drift of the reference voltage provided by the embodiment of the present application. As Figure 12 shown, the abscissa is the temperature, and the ordinate is the reference voltage. Based on the bias current of 5 nA for simulation, the curve L1 in the figure is the DC simulation curve of the temperature drift of the reference voltage. The coordinates of point F are (-24.8 °C, 1.20477 V), and the coordinates of point G are (127.2 °C, 1.204003 V). The difference dx between the abscissas of point G and point F is about 152.0 °C, and the difference dy between the ordinates is about 766.685796 μV. Then dy / dx is 5.0439855 μV / °C, that is, in the temperature range of [-25 °C, 125 °C], the maximum change of the reference voltage is about 0.76 mV, and the temperature drift is about 4.22 ppm, and the temperature drift is small.

[0143] Please refer to Figure 13 ,Figure 13 It is a schematic diagram of the AC simulation curve of the reference voltage rejection ratio provided by an embodiment of the present application. As Figure 13 shown, the abscissa is the frequency of the input power supply, with the unit of Hz, and the ordinate is the power supply rejection ratio (PSRR), with the unit of dB. The curve L2 in the figure is the AC simulation curve of the reference voltage rejection ratio. The coordinates of point M1 are (6.91831 kHz, -42.6049 dB), and the coordinates of point M2 are (1.02678 kHz, -69.971 dB). A power supply rejection effect greater than 42.6 dB can be achieved within the full frequency range, and the DC power supply rejection ratio is greater than 80 dB. The reference voltage generation circuit has a strong ability to suppress the change of the input power supply voltage, the output voltage is relatively stable, and the anti-interference ability of the reference voltage generation circuit is enhanced.

[0144] In summary, the bandgap reference circuit uses a linear voltage regulator circuit to supply power to the reference voltage generation circuit, and the stable reference voltage drives the second supply voltage generated by the linear voltage regulator circuit to be more stable, thereby driving the reference voltage generated by the reference voltage generation circuit to be more stable until the entire circuit reaches a steady state. Since the supply voltage of the reference voltage generation circuit is stable, the fluctuation of the reference voltage generated by it is small, the anti-interference ability is stronger, and the stability is higher.

[0145] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; under the idea of the present application, the technical features in the above embodiments or different embodiments can also be combined, and the steps can be implemented in any order, and there are many other changes in different aspects of the present application as described above. For the sake of brevity, they are not provided in detail; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A bandgap reference circuit, characterized in that: The bandgap reference circuit includes a bias circuit, a linear voltage stabilization circuit, a state detection circuit and a reference voltage generation circuit; The bias circuit is configured to generate a bias current based on an input power supply; The state detection circuit is electrically connected to the linear voltage stabilization circuit, and the state detection circuit is configured to detect the startup state of the reference voltage generation circuit, and generate a first detection signal when the reference voltage generation circuit is not started, and generate a second detection signal after the reference voltage generation circuit is started; The linear voltage stabilization circuit is electrically connected to the state detection circuit and the reference voltage generation circuit respectively, and the linear voltage stabilization circuit is configured to generate a first supply voltage in response to input of the bias current and the first detection signal; The reference voltage generating circuit is configured to generate a reference voltage in response to the input of the first power supply voltage, so that the linear voltage regulator circuit stops generating the first power supply voltage and generates a second power supply voltage in response to the bias current, the second detection signal and the input of the reference voltage, and then the reference voltage generating circuit continues to generate the reference voltage in response to the input of the second power supply voltage.

2. The bandgap reference circuit according to claim 1, characterized in that: The linear voltage stabilization circuit comprises a first voltage stabilization unit and a second voltage stabilization unit; The first voltage stabilizing unit is electrically connected to the state detection circuit, and the first voltage stabilizing unit, the second voltage stabilizing unit and the power supply end of the reference voltage generating circuit are commonly connected to a first node, the first voltage stabilizing unit is configured to generate the first supply voltage at the first node in response to the input of the bias current and the first detection signal, and is configured to stop generating the first supply voltage in response to the input of the bias current and the second detection signal; The second voltage stabilizing unit is also electrically connected to the output terminal of the reference voltage generating circuit, and the second voltage stabilizing unit is configured to generate the second supply voltage at the first node in response to input of the reference voltage and the bias current.

3. The bandgap reference circuit according to claim 2, characterized in that: The first voltage stabilizing unit includes a first voltage generating unit, a first voltage following unit and a first switching unit; The first voltage generating unit is electrically connected to the input terminal of the voltage follower unit, and the first voltage generating unit is configured to generate a first voltage in response to the input of the bias current; The output end of the first voltage follower unit is electrically connected to the first end of the first switch unit, and the first voltage follower unit is configured to generate the first supply voltage based on the first voltage; The second end of the first switch unit is electrically connected to the first node, the control end of the first switch unit is electrically connected to the state detection circuit, the first switch unit is configured to respond to the input of the first detection signal, connect the electrical connection between the output end of the first voltage follower unit and the first node to output the first supply voltage at the first node, and the first switch unit is also configured to respond to the input of the second detection signal, disconnect the electrical connection between the output end of the first voltage follower unit and the first node.

4. The bandgap reference circuit according to claim 3, characterized in that: The first voltage generating unit includes a first MOS transistor and a second MOS transistor, the first voltage following unit includes a third MOS transistor, and the first switch unit includes a fourth MOS transistor; The drain of the first MOS tube, the gate of the first MOS tube and the gate of the third MOS tube are all used to access the bias current, the source of the first MOS tube is respectively connected to the drain of the second MOS tube and the gate of the second MOS tube, the source of the second MOS tube is grounded, the drain of the third MOS tube is used to access the input power supply, the source of the third MOS tube is connected to the source of the fourth MOS tube, the drain of the fourth MOS tube is connected to the first node, and the gate of the fourth MOS tube is electrically connected to the state detection circuit.

5. The bandgap reference circuit according to claim 3, characterized in that: The second voltage stabilizing unit includes a second voltage generating unit and a second voltage following unit; The second voltage generating unit is electrically connected to the output terminal of the reference voltage generating circuit and the input terminal of the second voltage following unit respectively, and the second voltage generating unit is configured to generate a second voltage in response to the input of the bias current and the reference voltage; An output terminal of the second voltage follower unit is electrically connected to the first node, and the second voltage follower unit is configured to generate the second supply voltage based on the second voltage.

6. The bandgap reference circuit according to claim 5, characterized in that: The second voltage following unit includes a fifth MOS transistor, and the second voltage generating unit includes a sixth MOS transistor; The source of the fifth MOS tube is electrically connected to the first node, the drain of the fifth MOS tube is used to access the input power supply, the gate of the fifth MOS tube and the source of the sixth MOS tube are both used to access the bias current, the gate of the sixth MOS tube is electrically connected to the output end of the reference voltage generating circuit, and the drain of the sixth MOS tube is grounded.

7. The bandgap reference circuit according to claim 1, characterized in that: The bandgap reference circuit further includes a first startup circuit, which is electrically connected to the output end of the reference voltage generating circuit and the state detection circuit respectively; The first startup circuit is configured to generate a startup current to start the reference voltage generation circuit in response to the input of the bias current, and is further configured to stop generating the startup current in response to the input of the reference voltage.

8. The bandgap reference circuit according to claim 7, characterized in that: The state detection circuit includes a first mirror unit, a second mirror unit and a first inverter; The first mirror unit, the second mirror unit and the input end of the first inverter are commonly connected to a third node, and the output end of the first inverter is electrically connected to the linear voltage stabilization circuit; The first mirror unit is configured to mirror the startup current to raise the voltage of the third node, thereby causing the first inverter to output the first detection signal; The second mirror unit is configured to mirror the bias current to pull down the voltage of the third node, thereby causing the first inverter to output the second detection signal.

9. The bandgap reference circuit according to claim 8, characterized in that: The first mirror unit includes a seventh MOS tube and an eighth MOS tube, and the second mirror unit includes a first triode; The drain of the seventh MOS tube is respectively connected to the gate of the seventh MOS tube, the gate of the eighth MOS tube and the first startup circuit, the source of the seventh MOS tube and the source of the eighth MOS tube are both used to access the input power supply, the drain of the eighth MOS tube, the collector of the first transistor and the input end of the first inverter are commonly connected to the third node, the base of the first transistor is electrically connected to the first startup circuit, and the emitter of the first transistor is grounded.

10. The bandgap reference circuit according to claim 8, characterized in that: The first startup circuit includes a ninth MOS transistor, a tenth MOS transistor and a second triode; The drain of the ninth MOS tube, the gate of the ninth MOS tube and the gate of the tenth MOS tube are commonly connected to a fourth node and are used to access the bias current, the source of the ninth MOS tube is respectively connected to the collector of the second triode, the base of the second triode and the second mirror unit, the emitter of the second triode is grounded, the drain of the tenth MOS tube is connected to the first mirror unit, and the emitter of the tenth MOS tube is connected to the output end of the reference voltage generating circuit.

11. The bandgap reference circuit according to claim 1, characterized in that: The bandgap reference circuit also includes a second startup circuit; The second startup circuit is electrically connected to the enable terminals of the bias circuit and the reference voltage generating circuit, respectively. The second startup circuit is configured to respond to the input of the input power supply, send a startup signal to the bias circuit to start the bias circuit, and is also configured to respond to the input of the bias current, stop sending the startup signal, and generate an enable signal to drive the reference voltage generating circuit to work.

12. The bandgap reference circuit according to claim 11, characterized in that: The second startup circuit includes an energy storage unit, a third mirror unit, a second switch unit and a second inverter; The energy storage unit, the third mirror unit, the control end of the second switch unit and the input end of the second inverter are commonly connected to a fifth node, the first end of the second switch unit is connected to the control end of the bias circuit, and the second end of the second switch unit is grounded; The energy storage unit is configured to store energy for the input power supply to raise the voltage of the fifth node, thereby enabling the second switch unit to connect the electrical connection between the control terminal of the bias circuit and the ground to send the start signal to the control terminal of the bias circuit; The third mirror unit is configured to mirror the bias current to lower the voltage of the fifth node, thereby causing the second switch unit to disconnect the electrical connection between the control end of the bias circuit and the ground, stop sending the start signal, and cause the second inverter to output the enable signal.

13. The bandgap reference circuit according to claim 12, characterized in that: The energy storage unit includes an energy storage capacitor, the third mirror unit includes an eleventh MOS tube, and the second switch unit includes a twelfth MOS tube; One end of the energy storage capacitor is used to connect to the energy storage power supply, the other end of the energy storage capacitor and the drain of the eleventh MOS tube and the gate of the twelfth MOS tube are commonly connected to the fifth node, the source of the eleventh MOS tube and the source of the twelfth MOS tube are commonly grounded, the gate of the eleventh MOS tube is connected to the bias circuit, and the drain of the twelfth MOS tube is connected to the control end of the bias circuit.

14. The bandgap reference circuit according to any one of claims 1 to 13, characterized in that: The reference voltage generating circuit comprises a third triode, a fourth triode, a first resistor, a second resistor, a third resistor, a fourth resistor and an operational amplifier; The base of the third transistor is respectively connected to the base of the fourth transistor and the output end of the operational amplifier, the collector of the third transistor and the collector of the fourth transistor are used to access the first power supply voltage or the second power supply voltage, the emitter of the third transistor is respectively connected to one end of the third resistor and the in-phase input end of the operational amplifier, the emitter of the fourth transistor is connected to one end of the first resistor, the other end of the first resistor is respectively connected to one end of the second resistor and the inverting input end of the operational amplifier, the other end of the third resistor and the other end of the second resistor are commonly connected to one end of the fourth resistor, and the fourth resistor is grounded.

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