Board-level and wafer-level combined packaging manufacturing method

Abstract

The invention discloses a board-level and wafer-level combined packaging manufacturing method, and the method comprises the steps: directly embedding a whole-board wafer into a board-level substrate with a manufactured cavity, fixing the whole-board wafer through plastic packaging, leading out a metal connection position of the wafer through a metal atom injection mode, and carrying out the layer adding and module structure manufacturing. According to the method, the wafer is matched with the board level, so that the output efficiency of the packaging module is improved, the defect occurrence rate of the product in the packaging and cutting process is reduced, and the yield of the final packaging whole and the product reliability are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging, and particularly to a manufacturing method for a combined board-level and wafer-level packaging. Background Art

[0002] Existing flip-chip wafer packaging is small-strip unit packaging or single-chip packaging. The substrate needs to be cut into small-strip units or single chips in advance, and then the small-strip unit substrate or single-chip substrate is packaged with the wafer. The packaging efficiency is low, and waste will be generated during the cutting into small-strip units or single-chip substrates and wafers, affecting the cost. When a single wafer is mounted, due to the mounting accuracy and the thickness of the wafer, the wafer will be scrapped during the mounting process.

[0003] At the same time, in the existing substrate Via / PTH manufacturing technology, relying on laser / mechanical processing and then electroplating to achieve copper in the holes, enabling the upper and lower layer RDLs to be connected. In the existing technology Via / PTH manufacturing, using the laser / mechanical processing method, it is completely limited by the equipment capabilities. When the hole diameter size exceeds the equipment capabilities, the product cannot be processed.

[0004] The existing wafer packaging process is relatively complex. First, the wafer is fixed to the substrate, and a dielectric layer is formed on the wafer to achieve the fixation of the wafer. Then, via holes are formed through the method of pattern transfer etching. After the inner walls of the via holes are processed, metal conduction pillars are formed in the via holes for leading out the wafer connection positions, and then upper-layer wiring can be carried out. When manufacturing multi-layer chips, the above processes need to be repeated multiple times. Then, the product is fixed by heating and pressing through a lamination process. Finally, plastic encapsulation is performed on the top layer to achieve the encapsulation effect. This process is not only relatively complex, but also because the conduction between the dielectric layer and each wiring layer and between the wiring layer and the wafer is made through metal pillars, the deformations generated by the materials of the metal pillars and the dielectric layer under pressure are different. After the wafer is installed first and then the wiring layer is manufactured, it is easy to cause the situation of the offset of both ends of the metal pillars through the lamination method, affecting the yield of the finished product. Summary of the Invention

[0005] The main purpose of the present invention is to provide a manufacturing method for a combined board-level and wafer-level packaging.

[0006] To achieve the above purpose, the technical solution adopted by the present invention is as follows: A manufacturing method for a combined board-level and wafer-level packaging, the method includes directly embedding a whole-board wafer on a board-level substrate with a cavity already made, and fixing it through plastic encapsulation. Then, the metal connection positions of the wafer are led out by means of metal atom injection, and then build-up and module structure manufacturing are carried out. After completion, the whole board is cut into single-unit packaged wafer combinations or strip-level wafer combinations.

[0007] Further, the specific steps of the method include: S1. Select the overall carrier board, form a wafer embedding cavity on the carrier board, embed the whole wafer into the embedding cavity, and fix it by encapsulation process; S2. Conduct through at the metal connection positions of the wafers by means of atomic implantation, fabricate a metal wiring layer on the conduction surface, and encapsulate again; S3. Repeat step S2 for build-up manufacturing until the entire board structure is completely fabricated. After the topmost wiring layer is fabricated, no encapsulation is required, and then perform required cutting to form the required encapsulated units.

[0008] Further, the method of metal atom implantation is specifically to implant conductive metal atoms at corresponding positions, fill the macromolecular gaps of the materials at corresponding positions with metal atoms through the kinetic energy of high-speed implanted atoms, and the high-density metal atoms can achieve up-and-down conduction.

[0009] Further, the embedding direction of the wafer can be selected according to requirements, and the effect of conduction without drilling holes on the substrate can be achieved by means of atomic implantation.

[0010] Further, a masking layer needs to be laid on the implantation surface before metal atom implantation.

[0011] Further, the compactness of the masking layer manufacturing material is higher than that of the metal atom implantation layer material.

[0012] Further, the step of atomic implantation can be operated multiple times to meet sufficient conduction effect.

[0013] Further, the method may further include directly embedding the whole wafer on a board-level substrate with a pre-fabricated cavity, then using an additive process to lead out the metal connection positions of the chips, and after completion, using an encapsulation method to fabricate the substrate dielectric layer. After the build-up and module structure fabrication are completed, the whole board is cut into a single-unit encapsulated wafer combination or a strip-level wafer combination; The specific steps include: a. Select the overall carrier board, form a wafer embedding cavity on the carrier board, flip-chip embed the wafer into the embedding cavity, and form a pattern transfer layer on the embedding cavity surface of the carrier board using a photosensitive material; b. Use the pattern transfer method to form the required pattern on the upper surface of the photosensitive material, fabricate the first metal layer, prepare the first copper pillar layer on the metal layer, and then encapsulate by the encapsulation process; c. Perform surface treatment on the upper surface of the encapsulation layer in S5 by mechanical grinding or physical etching; d. Fabricate the second metal layer on the upper surface of the encapsulation layer, and fabricate a copper pillar layer on the upper surface of the second metal layer; e. After the second copper pillar layer is fabricated, a second encapsulation is performed, and surface treatment is carried out on the upper surface of the secondary encapsulation layer by mechanical grinding or physical etching; f. A third metal layer is fabricated on the upper surface of the encapsulation layer, the back of the carrier substrate is thinned, and then cutting is performed to form the package.

[0014] Furthermore, in step a, it is necessary to apply fan-out or fan-in technology on the surface of the wafer or the wafer already embedded in the substrate to fabricate the substrate metal layer or the metal layer required for the wafer.

[0015] Even further, the encapsulation method of the dielectric layer is a compression molding method.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The present invention uses the entire board substrate before cutting. The wafers do not need to be individually pasted. The entire board of wafers is placed on a large-sized substrate for encapsulation and the fabrication of the metal layer. After the metal layer is completed, cutting is performed, solving the problem of yield loss caused by multiple cuttings in the prior art and the slow efficiency of small-sized packaging. 2. Conductive metal atoms are implanted at the positions corresponding to the holes in the substrate. By the high-speed implantation of atomic kinetic energy, the gaps between the large molecules of the material are filled with metal atoms. The high-density metal atoms can achieve vertical conduction, achieving the functions of existing board-level PTH or Via; the implantation is at the atomic level, which can meet the requirements of any small-sized specifications at the board level. At the same time, conduction is achieved through the method of atomic injection, and the encapsulation process is combined to achieve the effect of rapid encapsulation and conduction. Moreover, since the method of metal atom injection does not overly affect the overall structure of the dielectric layer, the problem of conduction structure deviation is reduced during the processing of the entire board.

[0017] This technology directly skips the existing traditional wire bonding, flip-chip packaging, and separate cutting processes. What is directly used is all at the board level, and it is formed in one processing step, improving both the manufacturing process and the transportation time. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic flow chart of Embodiment 1 of the present invention; Figure 2 It is a schematic flow chart of Embodiment 2 of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] The following elaborates on the preferred embodiments of the present invention in conjunction with the attached drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making the scope of protection of the present invention more clearly defined. Embodiment 1

[0020] Refer to Figure 1As shown in the figure, a method for manufacturing a board-level and wafer-level combined package includes directly embedding a whole wafer on a board-level substrate with a pre-fabricated cavity, fixing it by encapsulation, then leading out the metal connection positions of the wafer by metal atom injection, and then performing build-up and module structure manufacturing. After completion, the whole board is cut into individual unit encapsulated wafer combinations or strip-level wafer combinations.

[0021] The specific steps include: S1, Select an overall carrier board, form a wafer embedding cavity on the carrier board, embed the whole wafer into the embedding cavity, and fix it by encapsulation process. S2, Conduct through at the metal connection positions of the wafer by atom injection, and fabricate a metal wiring layer on the conducting surface, and then perform encapsulation again. S3, Repeat step S2 for build-up manufacturing until the whole board structure is completely fabricated. After the topmost wiring layer is fabricated, no encapsulation is required, and then cutting is performed according to requirements to form the required encapsulated units.

[0022] The specific method of metal atom injection is to implant conducting metal atoms at corresponding positions, and fill the macromolecular gaps of the materials at corresponding positions with metal atoms through the kinetic energy of high-speed implanted atoms. The high-density metal atoms can achieve up-and-down conduction.

[0023] The embedding direction of the wafer can be selected according to requirements, and the effect of conduction without drilling holes on the substrate can be achieved by atom injection.

[0024] A masking layer needs to be laid on the injection surface before metal atom injection.

[0025] The compactness of the masking layer manufacturing material is higher than that of the metal atom injection layer material.

[0026] In step S2, atom injection can be performed multiple times to achieve sufficient conduction effect. Embodiment 2

[0027] See Figure 2 As shown in the figure, a method for manufacturing a board-level and wafer-level combined package may also include directly embedding a whole wafer on a board-level substrate with a pre-fabricated cavity, and then using the additive process to lead out the metal connection positions of the chip. After completion, the dielectric layer of the substrate is fabricated by encapsulation. After build-up and module structure manufacturing, the whole board is cut into individual unit encapsulated wafer combinations or strip-level wafer combinations. The specific steps include: a, Select an overall carrier board, form a wafer embedding cavity on the carrier board, flip-chip embed the wafer into the embedding cavity, and form a pattern transfer layer on the embedding cavity surface of the carrier board using photosensitive materials. b. Use the graphic transfer method to form the required pattern on the upper surface of the photosensitive material, fabricate the first metal layer, prepare the first copper pillar layer on the metal layer, and then perform encapsulation through the encapsulation process; c. Perform surface treatment on the upper surface of the encapsulation layer of S5 by mechanical grinding or physical etching; d. Fabricate the second metal layer on the upper surface of the encapsulation layer and fabricate the copper pillar layer on the upper surface of the second metal layer; e. After the second copper pillar layer is fabricated, perform secondary encapsulation and perform surface treatment on the upper surface of the secondary encapsulation layer by mechanical grinding or physical etching; f. Fabricate the third metal layer on the upper surface of the encapsulation layer, perform back thinning on the carrier board, and then perform cutting to form the package.

[0028] In the step a, the fan-out or fan-in technology is applied on the wafer surface or the wafer already embedded in the substrate to fabricate the substrate metal layer or the required metal layer of the wafer.

[0029] The encapsulation method of the dielectric layer is the compression molding method.

[0030] The above is only the preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. Any equivalent modification or change made by those of ordinary skill in the art according to the disclosure of the present invention shall be included in the protection scope recorded in the claims.

Claims

1. A method for manufacturing a board-level and wafer-level combined package, characterized in that: The method includes directly embedding a whole-board wafer on a board-level substrate with a cavity already made, fixing it by plastic sealing, then leading out the metal connection position of the wafer by metal atom injection, and then adding layers and making a module structure, and after completion, cutting the whole board into a packaged wafer assembly or a strip-level wafer assembly of a single unit; The method specifically comprises the following steps: S1, selecting an integral carrier board, forming a wafer embedding cavity on the carrier board, embedding the entire wafer into the embedding cavity, and fixing the wafer by plastic sealing process; S2, conduction is performed at the metal connection position of the wafer by atomic implantation, and a metal wiring layer is made on the conduction surface, and then plastic sealing is performed again; S3, repeat step S2 to add layers until the entire board structure is completed. After the top wiring layer is completed, no packaging is required, and then the required cutting is performed to form the required packaging units.

2. The method for manufacturing a board-level and wafer-level combined package according to claim 1, characterized in that: The metal atom injection method is specifically to implant conductive metal atoms at corresponding positions, and fill the macromolecular gaps of the material at the corresponding positions with metal atoms through the kinetic energy of high-speed implanted atoms. High-density metal atoms can achieve upper and lower conduction.

3. The method for manufacturing a board-level and wafer-level combined package according to claim 1, characterized in that: The embedding direction of the wafer can be selected according to the requirements, and the effect of conducting without drilling holes on the substrate can be achieved by atomic implantation.

4. The method for manufacturing a board-level and wafer-level combined package according to claim 1, characterized in that: Before the metal atoms are injected, a mask layer needs to be laid on the injection surface.

5. The method for manufacturing a board-level and wafer-level combined package according to claim 4, characterized in that: The density of the material used to make the masking layer is higher than that of the material used to inject the metal atoms into the layer.

6. The method for manufacturing a board-level and wafer-level combined package according to claim 1, characterized in that: The atomic implantation in step S2 may be performed multiple times to achieve a sufficient conduction effect.

7. The method for manufacturing a board-level and wafer-level combined package according to claim 1, characterized in that: The method may also include directly embedding the wafer of the whole board on the board-level substrate in which the cavity has been made, and then using the additive process to lead out the metal connection position of the chip, and after completion, using the plastic packaging method to realize the production of the substrate dielectric layer, completing the layer increase, and the module structure production, and after completion, cutting the whole board into a single unit package wafer combination or a strip-level wafer combination; The specific steps include: a. Select an integral carrier board, form a wafer embedding cavity on the carrier board, embed the wafer in the embedding cavity by flip-chipping, and form a pattern transfer layer on the embedding cavity surface of the carrier board using a photosensitive material; b. Using a pattern transfer method to form a desired pattern on the upper surface of the photosensitive material, and making a first metal layer, preparing a first copper column layer on the metal layer, and then performing plastic sealing through a plastic sealing process; c. Surface treatment is performed on the upper surface of the plastic sealing layer of S5 by mechanical grinding or physical etching; d. forming a second metal layer on the upper surface of the plastic packaging layer, and forming a copper column layer on the upper surface of the second metal layer; e. After the second copper pillar layer is manufactured, a second plastic encapsulation is performed, and a surface treatment is performed on the upper surface of the second plastic encapsulation layer by mechanical grinding or physical etching; f. Make a third metal layer on the upper surface of the plastic packaging layer, thin the back of the carrier board, and then cut it to form a package.

8. The method for manufacturing a board-level and wafer-level combined package according to claim 7, characterized in that: In the step a, a substrate metal layer or a metal layer required by the wafer is manufactured by applying a fan-out or fan-in technology on the surface of the wafer or on a wafer already embedded on the substrate.

9. The method for manufacturing a board-level and wafer-level combined package according to claim 7, characterized in that: The dielectric layer is sealed by compression molding.

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