Preparation method of strained SGOI substrate structure

Abstract

The invention discloses a preparation method of a strained SGOI substrate structure, which belongs to the technical field of semiconductors, and comprises the following steps: preparing a first wafer and a second wafer; generating a germanium-silicon layer on the surface of the first wafer; performing thermal oxidation treatment on the surface of the second wafer to form an oxide layer on the surface of the second wafer; performing a hydrogen ion implantation process on the first wafer to enable the first wafer to form a weakening layer in the germanium-silicon layer; combining the surface of the germanium-silicon layer of the first wafer with the surface of the oxide layer of the second wafer through low-temperature bonding; stripping along the weakening layer, and forming a top layer germanium-silicon film on the second wafer on the remaining part; recrystallizing the top germanium-silicon thin film through thermal annealing treatment; and etching the top germanium-silicon thin film to the required thickness through wet etching. According to the invention, the contact interface between the germanium-silicon and the oxide is improved; the thickness of the top germanium-silicon thin film is controllable, the required ultrathin thickness can be achieved, and the uniformity of the thin film is good; the surface is relatively smooth, the surface defects are few, and relatively good single crystal property is maintained.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor design and manufacturing, and particularly relates to a method for preparing a strained SGOI substrate structure. Background Art

[0002] As the Bulk CMOS technology node reaches below 28 nm, during the continuous miniaturization of the feature size of MOSFET transistors, although their operating speed is getting faster and faster, off-state leakage, increasing power consumption density, mobility degradation, short channel effects (SCE), hot carrier effects, etc. are becoming more and more significant. Therefore, based on the silicon material itself, improving the performance of current mainstream silicon CMOS devices by the method of proportional scaling is subject to more and more physical and technological limitations. In order to continue to maintain the development speed of Moore's Law, new materials, new structures, and new properties compatible with the silicon process must be developed. Therefore, the manufacturing process and device structure require innovative technologies to achieve further development, such as SOI technology, strained engineering, shallow junction engineering, low contact resistance and multilayer interconnect technology, etc. The traditional planar MOSFET structure is no longer applicable. Among potential technologies, a channel structure composed of high carrier mobility materials such as heterostructure materials, especially silicon-based germanium-silicon materials, can introduce strained engineering and bandgap engineering into the mature silicon process. This is one of the effective technologies and becomes a solution for advanced chips. For example, directly bonding germanium-silicon to a silicon wafer with a silicon dioxide insulating layer to form a strained SGOI structure (Strained SiGe on Insulator), which is a silicon-based germanium-silicon material with high hole mobility and has excellent application development prospects.

[0003] However, the disadvantages of the existing technology are that if a germanium-silicon material layer is directly formed on the insulating oxide layer in the strained SGOI technology, due to the relatively poor contact interface between the germanium-silicon material and the insulating oxide, especially the high interface state density, it will cause serious scattering and leakage, thereby affecting the device performance. In the matching with the substrate, a large number of defects will be generated, such as surface roughness (RMS), defect density, and dislocation density (TD), etc. In particular, dislocations will further reduce the degree of strain, thereby reducing the mobility of carriers. In addition, Ge in SiGe is prone to diffusion during the heat treatment process, reducing the degree of strain. When Ge diffuses to the oxide interface, the surface defect concentration will increase greatly, thereby reducing the performance and reliability of the MOS transistor. Summary of the Invention

[0004] Based on the technical problems existing in the prior art, the present invention provides a method for preparing a strained SGOI substrate structure, which solves the problems in the existing preparation methods, such as the poor contact interface between the germanium-silicon material and the insulating oxide, the large dislocation density, the ultra-thin thickness requirement of the top germanium-silicon thin film which is difficult to prepare and control, the uneven film thickness at the wafer edge, and the large number of defects, etc., thereby achieving beneficial technical effects such as improving the performance and reliability of semiconductor devices.

[0005] According to the technical solution of the present invention, a method for preparing a strained SGOI substrate structure is provided, which is characterized by including the following steps:

[0006] Step S1, prepare a first wafer and a second wafer, both of which are bare wafer substrates;

[0007] Step S2, form a germanium-silicon layer on the surface of the first wafer;

[0008] Step S3, perform a thermal oxidation treatment on the surface of the second wafer to form an oxide layer on the surface of the second wafer;

[0009] Step S4, perform a hydrogen ion implantation process on the first wafer to form a weakened layer in the germanium-silicon layer of the first wafer;

[0010] Step S5, after cleaning the surfaces of the first wafer and the second wafer, bond the surface of the germanium-silicon layer of the first wafer to the surface of the oxide layer of the second wafer through low-temperature bonding;

[0011] Step S6, strip the first wafer and part of the germanium-silicon layer along the weakened layer, and the remaining part forms a top germanium-silicon thin film on the second wafer;

[0012] Step S7, perform a thermal annealing treatment to recrystallize the top germanium-silicon thin film;

[0013] Step S8, etch the top germanium-silicon thin film to the required thickness through a wet etching process.

[0014] In some embodiments, in step S4, the implantation energy of the hydrogen ion implantation process is 50 keV to 200 keV, and / or the implantation dose is 1×10^16 atoms / cm² to 1×10^18 atoms / cm².

[0015] In some embodiments, in step S4, the temperature of the hydrogen ion implantation process is ≤60 °C.

[0016] In some embodiments, in step S5, the temperature of the low-temperature bonding is ≤200 °C.

[0017] In some embodiments, in step S7, the thermal annealing treatment is a high-temperature thermal annealing treatment, and the temperature of the thermal annealing treatment is ≥500°C.

[0018] In some embodiments, in step S7, the temperature of the thermal annealing treatment is ≤700°C.

[0019] In some embodiments, after step S8, the top germanium-silicon thin film reaches the required ultra-thin thickness, and the ultra-thin thickness is ≤20 nm.

[0020] Compared with the prior art, the beneficial technical effects of the present invention are as follows:

[0021] The preparation method of the strained SGOI substrate structure of the present invention realizes a semiconductor structure with an ultra-thin germanium-silicon thin film on the top layer, a flat surface, and few defects through an innovative process flow; among them, a low-temperature bonding process is adopted to improve the contact interface between germanium-silicon and the oxide, ensuring a flat interface. At the same time, the low-temperature process avoids the problem that germanium in germanium-silicon diffuses significantly and affects the device performance; a hydrogen ion implantation process is used to form a flat and easily peelable weakening layer; wet etching is used to thin the top germanium-silicon thin film. The wet etching rate is slow in germanium-silicon materials, so the thickness is controllable and can reach the required ultra-thin thickness, and the film uniformity is good; at the same time, the surface is relatively flat, the surface defects are few, and good single-crystallinity is maintained. Description of the Drawings

[0022] Figure 1 is a flowchart of the preparation method of the strained SGOI substrate structure provided by the present invention.

[0023] Explanation of the reference numerals in the drawings:

[0024] A, the first wafer; B, the second wafer; 1, germanium-silicon layer; 2, oxide layer; 3, weakening layer; 4, top germanium-silicon thin film. Detailed Embodiments

[0025] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below in conjunction with the drawings in the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present invention without creative efforts shall fall within the protection scope of the present invention.

[0026] In addition, it should be noted that for the convenience of description, only parts related to the relevant invention are shown in the drawings. Without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other. Without conflict, the order of the steps in the present invention can be adjusted, and the step numbers do not limit that the present invention must be strictly carried out in the order of the serial numbers.

[0027] It should be noted that concepts such as "first" and "second" mentioned in the present invention are only used to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependent relationships.

[0028] It should be noted that the modifications of "one" and "multiple" mentioned in the present invention are illustrative rather than restrictive. Those skilled in the art should understand that unless otherwise clearly specified in the context, it should be understood as "one or more".

[0029] The present invention provides a method for preparing a strained SGOI substrate structure. Without changing the sandwich structure of the SGOI substrate structure, the preparation method is redesigned. A typical preparation method of the present invention includes: preparing two bare wafer substrates A and B; depositing a germanium-silicon thin film (SiGe Deposition) on the surface of wafer A and performing a thermal oxidation treatment on the surface of wafer B; performing a hydrogen ion implantation process on wafer A; first cleaning the surfaces of wafer A and wafer B, and then performing a low-temperature bonding (Bonding); stripping wafer A to form a top germanium-silicon thin film, and then annealing the top germanium-silicon thin film at a high temperature to perform re-crystallization (Re-crystallization); using a wet etching (WET Etch) process to etch the top germanium-silicon to an ultra-thin film thickness. The main purpose of the present invention is to solve problems such as poor contact interfaces between germanium-silicon materials and insulating oxides, large dislocation densities, difficulty in preparing and controlling the ultra-thin thickness of the top germanium-silicon thin film, uneven film thickness at the wafer edge (Wafer Edge) and many defects in the existing preparation methods, so as to achieve beneficial technical effects such as improving the performance and reliability of semiconductor devices.

[0030] Please refer to Figure 1 , a method for preparing a strained SGOI substrate structure of the present invention includes the following steps.

[0031] Step S1, preparing a first wafer A and a second wafer B, both the first wafer A and the second wafer B are bare wafer substrates.

[0032] Step S2, generating a germanium-silicon layer 1 (SiGe) on the surface of the first wafer A; specifically, depositing a germanium-silicon thin film (SiGe Deposition) on the surface of the first wafer A to generate a high-quality and low-defect germanium-silicon layer 1.

[0033] Step S3, performing a thermal oxidation treatment on the surface of the second wafer B to form an oxide layer 2 on the surface of the second wafer B, and the oxide layer 2 is specifically a high-quality and low-defect silicon dioxide insulating oxide layer.

[0034] Step S4: Perform a hydrogen ion implantation process on the first wafer A to form a weakened layer 3 within the germanium-silicon layer 1 of the first wafer A. Preferably, the implantation energy of the hydrogen ion implantation process is 50 keV to 200 keV, and / or the implantation dose is 1×10^16 atoms / cm² to 1×10^18 atoms / cm². The temperature of the hydrogen ion implantation process is preferably ≤60°C. Hydrogen ions are relatively small. When they are implanted into the germanium-silicon layer 1 to a certain depth position, a structure similar to bubbles is formed, which is the weakened layer of the structure. Since this layer is a weak link, it can be peeled off along the precise position of this layer in the subsequent steps to initially obtain the top layer structure of SGOI. Among them, hydrogen ion implantation is preferably at a high dose. Compared with low-dose implantation, high-dose implantation can make the weakened layer 2 smoother, that is, make the surface generated after peeling smoother. The depth of hydrogen ion implantation, that is, the depth position of the weakened layer 2, is directly related to the implantation energy, and the required parameters are obtained through design calculations. Using room temperature or preferably low-temperature ion implantation process can avoid the ion diffusion during ion implantation, control the carbon ions to be uniformly implanted into a certain position in the substrate, with precise position and narrow distribution range, that is, form an implanted layer with precise position and smoothness, namely the weakened layer 2. At the same time, in the case of using lower temperature implantation, a lower dose implantation can be selected to further avoid lattice damage and reduce defects.

[0035] Step S5: After surface cleaning the first wafer A and the second wafer B, bond the surface of the germanium-silicon layer 1 of the first wafer A to the surface of the oxide layer 2 of the second wafer B through low-temperature bonding. In the embodiment, when bonding, the first wafer A is flipped and inverted on the upper surface of the second wafer B. Preferably, the temperature of the low-temperature bonding is, for example, ≤200°C.

[0036] Step S6: Peel off the first wafer A and part of the germanium-silicon layer 1 along the weakened layer 3, and the remaining part forms the top germanium-silicon thin film 4 on the second wafer B.

[0037] Step S7: Recrystallize the top germanium-silicon thin film 4 through thermal annealing treatment. Among them, preferably, the thermal annealing treatment is high-temperature thermal annealing treatment, and the temperature of the thermal annealing treatment is, for example, ≥500°C. More preferably, the temperature of the thermal annealing treatment is ≤700°C, and further, for example, 500°C to 700°C. In this way, it can be avoided that germanium in the germanium-silicon reduces the strain degree due to the diffusion during the heat treatment process and affects the device performance.

[0038] Step S8, the top germanium-silicon thin film 4 is etched to a desired thickness by wet etching treatment. Thus, a strained SGOI substrate structure is obtained, and the strained SGOI substrate structure is a substrate (formed by the second wafer B), an oxide layer 2, and a top germanium-silicon thin film 4 stacked in sequence. Preferably, after step S8, the top germanium-silicon thin film 4 reaches a desired ultra-thin thickness, and the ultra-thin thickness is ≤20 nm. In the prior art, when thinning the top structure, chemical mechanical polishing is generally used, which has the problem of difficult control of the layer thickness, and there is an easy large (e.g., exceeding 10%) thickness drop at the crystal edge, and surface scratches will also occur. For the relatively thick top germanium-silicon thin film at present, the influence of the defects on the performance is not very significant. However, for the ultra-thin top germanium-silicon thin film such as nanoscale required in advanced processes, the above defects will significantly affect the performance. The present invention adopts a wet etching process, which can make the film uniformity consistent, achieve a thickness drop of less than 2%, and have no surface defects.

[0039] In summary, the preparation method of the strained SGOI substrate structure of the present invention realizes a semiconductor structure with an ultra-thin germanium-silicon film on the top layer, a flat surface and few defects through an innovative process flow. Among them, a low-temperature bonding process is adopted to improve the contact interface between germanium-silicon and the oxide, ensuring a flat interface. At the same time, the low-temperature process avoids the obvious diffusion of germanium in germanium-silicon and the problem of affecting device performance. The hydrogen ion implantation process is used to form a flat and easily peelable weakening layer. Wet etching is used to thin the top germanium-silicon film. The wet etching rate is slow in germanium-silicon materials, so the thickness is controllable and can reach the required ultra-thin thickness, and the film uniformity is good. At the same time, the surface is relatively flat, the surface defects are few, and good single crystal properties are maintained. In addition, for the transistor prepared by the strained SGOI technology, the germanium-silicon film defines the source-drain junction depth and depletion region, which can improve short-channel effects such as DIBL (Drain Induced Barrier Lowering), further improve the sub-threshold characteristics of the device, and reduce the static power consumption of the circuit. Introducing strain into the channel of MOS devices can increase the mobility of carriers. In addition, the strained SGOI transistor does not require channel doping, which can avoid effects such as RDF (Random Dopants Fluctuation) and the reduction of carrier mobility, and maintain a stable threshold voltage (threshold voltage, Vth). Different from the 3D transistor structure adopted by the FinFET process, the strained SGOI is a planar process technology, which can effectively reduce the process difficulty. Compared with the traditional Bulk Silicon technology, the strained SGOI can provide better transistor electrostatic characteristics, and the buried oxide can reduce the parasitic capacitance between the source and the drain. In addition, this technology can effectively limit the electron flow between the source and the drain, greatly reducing the leakage current performance of the device. In addition to through the gate, the strained SGOI can also control the transistor behavior through the bottom substrate of the device to achieve the back bias control function.

[0040] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing a strained SGOI substrate structure, characterized in that: The steps include: Step S1, preparing a first wafer (A) and a second wafer (B), wherein the first wafer (A) and the second wafer (B) are both wafer substrate bare chips; Step S2, forming a silicon germanium layer (1) on the surface of the first wafer (A); Step S3, performing thermal oxidation treatment on the surface of the second wafer (B) to form an oxide layer (2) on the surface of the second wafer (B); Step S4, performing a hydrogen ion implantation process on the first wafer (A) so as to form a weakened layer (3) in the germanium silicon layer (1) of the first wafer (A); Step S5, after cleaning the surfaces of the first wafer (A) and the second wafer (B), the surface of the germanium silicon layer (1) of the first wafer (A) is bonded to the surface of the oxide layer (2) of the second wafer (B) by low temperature bonding; Step S6, peeling off the first wafer (A) and part of the germanium silicon layer (1) along the weakened layer (3), and the remaining part forms a top germanium silicon film (4) on the second wafer (B); Step S7, recrystallizing the top silicon-germanium film (4) by thermal annealing; Step S8, etching the top silicon-germanium film (4) to a desired thickness by wet etching.

2. The method for preparing a strained SGOI substrate structure according to claim 1, characterized in that: In step S4, the implantation energy of the hydrogen ion implantation process is 50 keV to 200 keV, and / or the implantation dose is 1×1016 atoms / cm2 to 1×1018 atoms / cm2.

3. The method for preparing a strained SGOI substrate structure according to claim 1, characterized in that: In step S4, the temperature of the hydrogen ion implantation process is ≤ 60°C.

4. The method for preparing a strained SGOI substrate structure according to claim 1, characterized in that: In step S5, the temperature of low temperature bonding is ≤200°C.

5. The method for preparing a strained SGOI substrate structure according to claim 1, characterized in that: In step S7, the thermal annealing treatment is a high temperature thermal annealing treatment, and the temperature of the thermal annealing treatment is ≥500°C.

6. The method for preparing a strained SGOI substrate structure according to claim 1, characterized in that: In step S7, the temperature of the thermal annealing treatment is ≤ 700°C.

7. The method for preparing a strained SGOI substrate structure according to claim 1, characterized in that: After step S8, the top germanium silicon film (4) reaches the required ultra-thin thickness, which is ≤20 nm.

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