High-voltage self-starting circuit

Abstract

The invention belongs to the technical field of analog circuit power management, and particularly relates to a high-voltage self-starting circuit. High input voltage of the bus is reduced and divided through voltage division of the high-voltage resistor, most of the voltage on the bus is distributed on the high-voltage MOS device, pre-power rail voltage capable of being processed in a chip is achieved through the voltage stabilization effect of the Zener tube, and due to the fact that the open-loop starting speed is high enough, the high-voltage MOS device can be started rapidly. And meanwhile, after the reference signal is established, the high-voltage LDO is powered to generate an internal available stable voltage so as to realize power supply of a high-performance module of the chip. Meanwhile, in order to meet the requirement for high efficiency, the output stable voltage of the self-starting LDO can be directly supplied with power from the outside to reduce static power consumption.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog circuit power management, and particularly relates to a circuit that can start and generate an internal stable voltage under a high input bus voltage. Background Art

[0002] In an electronic power system, switched-mode power supplies are widely used due to their high efficiency, stability, and strong load-carrying capacity. Among them, isolated converters are widely used in industrial power supplies, automobiles, and other fields due to their electrical isolation, low common-mode noise, and support for multi-voltage-level conversion. Isolated converters are commonly used to process the high-voltage DC bus voltage after AC rectification. Compared with traditional non-isolated converters, their advantage is that when a power transistor burns out or other faults occur on the high-voltage side of the primary side, the high-voltage input circuit is short-circuited. At this time, due to the isolation characteristics of the transformer, no high-voltage and large-current events will occur on the secondary side, protecting the safety of secondary-side devices and subsequent loads.

[0003] To ensure the safety isolation characteristics, the control chip is generally placed on the primary side to control the duty cycle of the power transistor to achieve stable output. To meet the scenario of high input voltage, and at the same time, due to the fact that the function implementation of high-performance modules in the current process depends on the low mismatch and few parasitics of low-voltage transistors, a high-voltage self-starting circuit that can convert the high-voltage input bus into a stable power supply rail that can be used inside the chip is required. At the same time, to effectively meet the high-efficiency requirements, after the system initialization and startup are completed, the stable output voltage on the secondary side is directly used to supply power to this chip through the auxiliary winding to reduce the static power consumption. Therefore, the present invention also has the function of external direct power supply. Therefore, it is of great significance to research and develop a high-voltage self-starting circuit. Summary of the Invention

[0004] The purpose of the present invention is to propose a high-voltage self-starting circuit to meet the requirements of safe and high-efficiency power supply inside the chip under the high input bus voltage of an isolated converter.

[0005] To achieve the above purpose, the technical solution of the present invention is as follows:

[0006] A high-voltage self-starting circuit includes a bus bucking circuit and a self-starting LDO circuit; wherein, the bus bucking circuit is used to reduce the high voltage on the bus to a rough pre-power supply rail signal available inside the chip, supply power to the subsequent reference module and the self-starting LDO, and generate a stable voltage signal. Specifically:

[0007] The bus voltage reduction circuit includes a first high-voltage resistor HR1, a second high-voltage resistor HR2, a first high-voltage NMOS transistor HN1, a second high-voltage NMOS transistor HN2, N series-connected Zener diodes, a second Zener diode Z2, and a third Zener diode Z3. Define the bus input power supply voltage as VIN. One end of the first high-voltage resistor HR1 and the drain of the first high-voltage NMOS transistor HN1 are connected to the power supply VIN. The gate of the first high-voltage NMOS transistor HN1 is connected to the other end of the first high-voltage resistor HR1, one end of the second high-voltage resistor HR2, and the negative terminal of the second Zener diode Z2. The source of the first high-voltage NMOS transistor HN1 is connected to the positive terminal of the second Zener diode Z2 and the drain of the second high-voltage NMOS transistor HN2. The gate of the second high-voltage NMOS transistor HN2 is connected to the other end of the second high-voltage resistor HR2, the negative terminals of the N series-connected Zener diodes, and the negative terminal of the third Zener diode Z3. The source of the second high-voltage NMOS transistor HN2 is connected to the positive terminal of the third Zener diode Z3 and the rough pre-power supply rail VPRE. The positive terminals of the N series-connected Zener diodes are grounded;

[0008] The self-starting LDO circuit includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first NPN transistor Q1, a second NPN transistor Q2, a third NPN transistor Q3, a fourth NPN transistor Q4, a first capacitor C1, a first high-voltage PMOS transistor HP1, a second high-voltage PMOS transistor HP2, a third high-voltage PMOS transistor HP3, a fourth high-voltage PMOS transistor HP4, a fifth high-voltage PMOS transistor HP5, a sixth high-voltage PMOS transistor HP6, a seventh high-voltage PMOS transistor HP7, a third high-voltage NMOS transistor HN3, a fourth high-voltage NMOS transistor HN4, a fifth high-voltage NMOS transistor HN5, a sixth high-voltage NMOS transistor HN6, a seventh high-voltage NMOS transistor HN7, an eighth high-voltage NMOS transistor HN8, a fourth Zener diode Z4, a fifth Zener diode Z5, a first reference current source IBIAS1, and a second reference current source IBIAS2; the drain of the third high-voltage NMOS transistor HN3 is connected to the source of the first high-voltage NMOS transistor HN1, the positive terminal of the second Zener diode Z2, and the drain of the second high-voltage NMOS transistor HN2; the gate of the third high-voltage NMOS transistor HN3 is connected to the negative terminal of the fourth Zener diode Z4, the drain of the second high-voltage PMOS transistor HP2, the source of the first high-voltage PMOS transistor HP1, and the drain of the fourth high-voltage NMOS transistor HN4; the source of the third high-voltage NMOS transistor HN3 is connected to the positive terminal of the fourth Zener diode Z4, the negative terminal of the fifth Zener diode Z5, the source of the fourth high-voltage NMOS transistor HN4, the source of the fifth high-voltage NMOS transistor HN5, the drain of the eighth high-voltage NMOS transistor HN8, the drain of the first high-voltage PMOS transistor HP1, one end of the first resistor R1, one end of the sixth resistor R6, the source of the fourth high-voltage PMOS transistor HP4, the source of the fifth high-voltage PMOS transistor HP5, and one end of the first capacitor C1 is connected to VCC; the gate of the fourth high-voltage NMOS transistor HN4 is connected to the gate of the fifth high-voltage NMOS transistor HN5, the drain of the fifth high-voltage NMOS transistor HN5, and the drain of the third high-voltage PMOS transistor HP3; the gate of the third high-voltage PMOS transistor HP3 is connected to the gate of the second high-voltage PMOS transistor HP2, and the source of the third high-voltage PMOS transistor HP3 is connected to the source of the second high-voltage PMOS transistor HP2, the source of the sixth high-voltage PMOS transistor HP6, and the source of the seventh high-voltage PMOS transistor HP7 is connected to VPRE; the gate of the first high-voltage PMOS transistor HP1 is connected to the positive terminal of the fifth Zener diode Z5, the drain of the sixth high-voltage PMOS transistor HP6, and the drain of the sixth high-voltage NMOS transistor HN6; the gate of the sixth high-voltage PMOS transistor HP6 is connected to the gate of the seventh high-voltage PMOS transistor HP7, the drain of the seventh high-voltage PMOS transistor HP7, and the drain of the seventh high-voltage NMOS transistor HN7; the gate of the seventh high-voltage NMOS transistor HN7 is connected to the reference voltage VBIAS, and its source is connected to the source of the sixth high-voltage NMOS transistor HN6 and the input terminal of the second reference current source IBIAS2;The gate of the sixth high-voltage NMOS transistor HN6 is connected to the other end of the first capacitor C1, one end of the second resistor R2, and one end of the third resistor R3; the gate of the eighth high-voltage NMOS transistor HN8 is connected to the self-starting LDO enable signal Disable; the base of the first NPN transistor Q1 is connected to the other end of the first resistor R1 and the other end of the second resistor R2, the emitter of the first NPN transistor Q1 is connected to one end of the fourth resistor R4, and the collector of the first NPN transistor Q1 is connected to the gate of the fourth high-voltage PMOS transistor HP4, the gate of the fifth high-voltage PMOS transistor HP5, and the drain of the fifth high-voltage PMOS transistor HP5; the drain of the fourth high-voltage PMOS transistor HP4 is connected to the collector of the third NPN transistor Q3 and the base of the fourth NPN transistor Q4; the base of the third NPN transistor Q3 is connected to the base of the second NPN transistor Q2, the collector of the second NPN transistor Q2, and the other end of the fourth resistor R4, and the emitter of the third NPN transistor Q3 is connected to one end of the fifth resistor R5; the source of the eighth high-voltage NMOS transistor HN8 is connected to the input terminal of the first reference current source IBIAS1; the collector of the fourth NPN transistor Q4 is connected to the other end of the sixth resistor R6, the negative terminal of the fifth Zener diode Z5 is connected to VCC_READY, and the emitter of the fourth NPN transistor Q4 is connected to the output terminal of the first reference current source IBIAS1, the output terminal of the second reference current source IBIAS2, the positive terminal of the fifth Zener diode Z5, the other end of the third resistor R3, the other end of the fifth resistor R5, and the emitter of the second NPN transistor Q2 is grounded.

[0009] The advantages of the present invention are as follows: the high input voltage of the bus is step-down and voltage-divided through the voltage division of the high-voltage resistor, and most of the voltage on the bus is distributed on the high-voltage MOS devices. At the same time, the pre-power supply rail voltage that can be processed inside the chip is realized through the voltage stabilization function of the Zener diode. Since it is an open-loop start, the start speed is fast enough. After the reference signal is established, an internal available stable voltage is generated for the power supply of the high-voltage LDO to realize the power supply of the high-performance module of the chip. At the same time, to meet the high-efficiency requirement, the output stable voltage of the self-starting LDO of the present invention can be directly supplied by an external power supply to reduce the static power consumption. Brief Description of the Drawings

[0010] Figure 1 It is a schematic diagram of the high-voltage self-starting circuit structure;

[0011] Figure 2 It is a schematic diagram of the power-on sequence of the high-voltage self-starting circuit.

[0012] Note: The transistors with names starting with HP are HV PMOS (High Voltage P-channel Metal-Oxide-Semiconductor) transistors; the transistors with names starting with HN are HV NMOS (High Voltage N-channel Metal-Oxide-Semiconductor) transistors; the transistors with names starting with Q are NPN bipolar transistors; the devices with names starting with HR are high-voltage resistors; the devices with names starting with R are resistors; the devices with names starting with C are capacitors; the devices with names starting with Z are Zener diodes; the devices with names starting with IBIAS are reference current sources. Detailed Implementation Manner

[0013] The technical solution of the present invention will be analyzed and described in detail below with reference to the accompanying drawings:

[0014] As Figure 1 Shown in the partial circuit of the bus voltage reduction in the schematic diagram of the high-voltage self-starting circuit structure. The working principle is that when the VIN input bus voltage is a high voltage, under the voltage division of the resistors HR1 and HR2 and the voltage regulation of the series array of Z1-ZN Zener diodes, the gate of HN2 will be stabilized at the breakdown voltage of N Zener diodes. At the same time, the high voltage on the bus is all dropped on the high-voltage resistor and the high-voltage transistors HN1 and HN2. Generally, to ensure safety, the breakdown voltages of HN1 and HN2 need to meet the highest voltage requirement of VIN. The selection of the high-voltage resistor needs to be calculated according to the rated current, rated voltage parameters of the corresponding Zener diode and the selected series number N, so that the Zener diode works in the normal reverse breakdown region. For the thin gate oxide process, the high-voltage transistor can only withstand voltage through the drift region between the drain and source, and the breakdown voltage between the gate and source is still the same as that of the low-voltage transistor. Therefore, the Zener diodes Z2 and Z3 are used to prevent the gate-source breakdown of the high-voltage transistors HN1 and HN2. At this time, the pre-power supply rail voltage value can be obtained as the breakdown voltage of N Zener diodes minus the gate-source voltage of HN2. N can be determined according to the specific voltage value required inside to ensure the universality of the present invention.

[0015] As Figure 1The self - starting LDO section shown is powered by the pre - power rail VPRE after the bus voltage is stepped down as described above. The main function of this section is to step down the rough pre - power rail VPRE again to obtain a stable signal that can be used on - chip. This section mainly consists of an error amplifier EA, a buffer stage HP1, an LDO composed of an output power transistor HN3, and a band - gap comparator. The input stage of the error amplifier is a five - transistor operational amplifier structure with a high - voltage PMOS as the active load. When the input bus is powered on, VPRE starts to be established, and at the same time, the internal reference and the power - on enable power supply rise. Signals such as VBIAS, Vb, IBIAS1, IBIAS2, Disable, etc. are gradually established. When a fault occurs, such as the input bus voltage being lower than the set undervoltage point, at this time, the system Disable is 1, which will control the switch transistor HN8 to turn on, and the reference current source IBIAS1 injects into this module. IBIAS1 directly pulls down the VCC potential to ensure that the LDO does not start and avoid errors. At this time, due to the action of EA, the gate of HP1 will approach the voltage of VPRE. To avoid the gate - source breakdown of HP1, through the forward conduction of the Zener diode Z5, the gate charge is discharged so that its potential will not be too high. During normal operation, the Disable signal is 0, turning off the switch transistor HN8. At this time, only the I2 branch of the reference current source works. The function of I2 is to provide the tail current source for the input stage of EA. The function of Vb is to provide a fixed - current pull - up ability for the gate of the power transistor through the current mirror composed of HP2 and HP3, where the size of HP2 is larger than that of HP3. The principle of the self - starting LDO to output a stable voltage is that the feedback voltage obtained by the voltage division of VCC through resistors R1, R2, and R3 is compared with the reference voltage signal VBIAS at the other end of EA. Through the loop, VFB is stabilized at the reference voltage, and the output voltage VCC can be stabilized at

[0016]

[0017] To ensure a stable output voltage, the loop stability of this self - starting LDO is analyzed. The LDO of the present invention has a positive feedback loop composed of HN6, HP1, and a feedback resistor, and a negative feedback loop composed of HN6, HP1, HN3, and a feedback resistor. The gain of the positive feedback loop is very low and can be ignored. By breaking the loop at the gate of the feedback node HN6, the loop gain of the present invention can be obtained as

[0018]

[0019] In the above formula, g mN6 、g mP1 、g mN3 respectively represent the transconductances of the input transistor HN6 of EA, the buffer stage HP1, and the power stage HN3, r oN6 、r oP6 respectively represent the output resistances of HN6 and HP6, C p1 、Cp2 , C gsN3 , C L respectively represent the parasitic capacitance of the HP1 gate, the equivalent parasitic capacitance of the EA output, the gate-source parasitic capacitance and the output capacitance of HN3. Generally speaking, in the present invention, a zero point is introduced through the feedforward action of capacitor C1 to ensure the stability of the loop. The loop characteristics of the present invention can be further designed through the loop expression. Considering the relatively low-frequency output pole p1 = -g mN3 / C L , the output pole of EA p2 = -1 / (r oN6 ||r oP6 ), the zero point z1 = -1 / C1(R1 + R2) introduced by the compensation capacitor C1 and the pole p3 = -1 / C1((R1 + R2)||R3) introduced. In the most extreme case, when the output capacitance is the smallest and the load is the heaviest, and all three poles and one zero point are within the band, when the VCC and the reference voltage VREF are determined, the sum of the values of R1, R2, and R3 is constant, and the sum of R1 and R2 is greater than R3. To achieve better compensation, the values of R1 and R2 can be appropriately increased to make the first zero point z1 and the third pole p3 move away from each other, increasing the phase lead ability of the zero point. At the same time, the load of the EA output stage can be increased to move the second pole p2 to a higher frequency, weakening its phase lag ability, to ensure the stability of the loop. The input bus of the present invention directly provides current for the self-starting LDO through HN1 to ensure that its current capacity is sufficient. At the same time, there is a rough current limit in this LDO. When the load reaches a certain limit, the zener diode Z4 between the gate and source of HN3 will break down to ensure that its gate-source voltage will not increase and its current capacity will not increase further. The loop of the LDO is broken, and VCC begins to gradually decrease to limit the current.

[0020] As Figure 2 shown in the power-on sequence schematic diagram of the high-voltage self-starting circuit, the pre-power supply rail VPRE can be established quickly after the bus is powered on, driving the establishment of the internal reference to provide signals for subsequent modules. At the same time, VCC slowly starts to rise to establish power supply for subsequent key modules. In actual applications, to meet the high-efficiency requirements, the VCC of the present invention can be directly powered by an external auxiliary winding. At this time, the externally provided VCC voltage may be higher or lower than the VCC voltage determined by the internal loop. Due to the action of EA, the gate-source voltage difference of HP1 is extremely large. Through the forward conduction and reverse voltage regulation of the zener diode Z5, it is ensured that the gate potential of HP1 and the VCC potential will not differ too much, ensuring that the gate-source of HP1 will not break down. At this time, the HN3 transistor is turned off to reduce power consumption.

[0021] Since power supply to the subsequent critical modules can only be provided after determining whether the LDO has been established, it is difficult to judge when the power rail is not established at this time. At the same time, there is an independent situation when VCC is directly supplied by an external power source. The present invention uses a bandgap comparator with VCC directly as the power rail to determine whether the LDO has been established. The principle is to achieve the determination by comparing the sampled voltage obtained by dividing the voltage of VCC with a resistor with the built-in reference signal. When VCC is not established and is relatively low, the current flowing through R4 is relatively low. The current mirror formed by HP5 and HP4 provides a relatively small pull-up current for the base of Q4, while its pull-down current is a fixed PTAT current determined by the bandgap structure composed of Q2, Q3, and R5. At this time, the larger pull-down current makes VCC_READY a high potential that follows the rise of VCC, indicating that VCC is not established properly. The function of Z5 is to limit the high potential of VCC_READY from being too high to avoid exceeding the withstand voltage of the subsequent low-voltage logic gates. When VCC continues to rise, the current flowing through R4 increases, the pull-up current of the base of Q4 becomes larger and the voltage rises, causing VCC_READY to turn low. At this time, it represents that VCC has been established. Assuming that the power supply for the subsequent logic gates is VDD, the flip point can be considered as VDD / 2, and the flip point of VCC is calculated through the balance of the pull-up current and the pull-down current.

[0022]

[0023] In the above formula, β represents the current gain of Q4, V BE is the base-emitter voltage of Q1 and Q2, V T represents the thermal voltage, N represents the area ratio of Q2 and Q3, and can be approximately obtained according to the selected resistors and current gain

[0024]

[0025] The right side of the equal sign is the addition of the PTAT and CTAT voltages. By reasonably designing the ratio of the resistances of R4 and R5, the reference voltage can be obtained, which has very high temperature stability. Then, by allocating the corresponding ratios of R1, R2, and R3, the desired VCC flip point can be achieved. The present invention thus obtains the determination of the self-starting LDO ready signal.

[0026] In summary, the present invention realizes a high-voltage self-starting circuit structure, which can achieve a structure that is suitable for internal step-down and voltage regulation under the high input bus voltage of an isolated converter, and has the function of automatically judging whether the voltage is ready. This structure can also be directly powered by an external auxiliary winding to reduce power consumption and improve efficiency.

[0027] Those of ordinary skill in the art can make various specific deformations and combinations that do not deviate from the essence of the present invention based on these technical revelations disclosed in the present invention, and these deformations and combinations are still within the protection scope of the present invention.

Claims

1. A high voltage self-starting circuit, characterized in that: It includes a bus voltage reduction circuit and a self-starting LDO circuit; wherein the bus voltage reduction circuit is used to reduce the high voltage on the bus to a rough pre-power rail signal available in the chip, to power the subsequent reference module and the self-starting LDO, and to generate a stable voltage signal, specifically: The busbar step-down circuit comprises a first high-voltage resistor HR1, a second high-voltage resistor HR2, a first high-voltage NMOS tube HN1, a second high-voltage NMOS tube HN2, N series-connected Zener tubes, a second Zener tube Z2, and a third Zener tube Z3; the busbar input power supply voltage is defined as VIN, one end of the first high-voltage resistor HR1 and the drain of the first high-voltage NMOS tube HN1 are connected to the power supply VIN, the gate of the first high-voltage NMOS tube HN1 is connected to the other end of the first high-voltage resistor HR1, one end of the second high-voltage resistor HR2, and the negative end of the second Zener tube Z2, the source of the first high-voltage NMOS tube HN1 is connected to the positive end of the second Zener tube Z2 and the drain of the second high-voltage NMOS tube HN2; the gate of the second high-voltage NMOS tube HN2 is connected to the other end of the second high-voltage resistor HR2, the negative ends of the N series-connected Zener tubes, and the negative end of the third Zener tube Z3, the source of the second high-voltage NMOS tube HN2 is connected to the positive end of the third Zener tube Z3 and the rough pre-power rail VPRE; the positive ends of the N series-connected Zener tubes are grounded; The self-starting LDO circuit includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first NPN transistor Q1, a second NPN transistor Q2, a third NPN transistor Q3, a fourth NPN transistor Q4, a first capacitor C1, a first high-voltage PMOS transistor HP1, a second high-voltage PMOS transistor HP2, a third high-voltage PMOS transistor HP3, a fourth high-voltage PMOS transistor HP4, a fifth high-voltage PMOS transistor HP5, a sixth high-voltage PMOS transistor HP6, a seventh high-voltage PMOS transistor HP7, a third high-voltage NMOS transistor HN3, a fourth high-voltage NMOS transistor HN4, a fifth high-voltage NMOS transistor HN5, and a sixth high-voltage NMOS transistor HP7. The drain of the third high-voltage NMOS tube HN3 is connected to the source of the first high-voltage NMOS tube HN1, the positive terminal of the second Zener tube Z2, and the drain of the second high-voltage NMOS tube HN2; the gate of the third high-voltage NMOS tube HN3 is connected to the negative terminal of the fourth Zener tube Z4, the drain of the second high-voltage PMOS tube HP2, the source of the first high-voltage PMOS tube HP1, and the drain of the fourth high-voltage NMOS tube HN4; the source of the third high-voltage NMOS tube HN3 is connected to the positive terminal of the fourth Zener tube Z4, the drain of the second high-voltage PMOS tube HP2, the source of the first high-voltage PMOS tube HP1, and the drain of the fourth high-voltage NMOS tube HN4; the source of the third high-voltage NMOS tube HN3 is connected to the positive terminal of the fourth Zener tube Z4, the fifth Zener tube Z5 The negative end of the fourth high-voltage NMOS tube HN4, the source of the fifth high-voltage NMOS tube HN5, the drain of the eighth high-voltage NMOS tube HN8, the drain of the first high-voltage PMOS tube HP1, one end of the first resistor R1, one end of the sixth resistor R6, the source of the fourth high-voltage PMOS tube HP4, the source of the fifth high-voltage PMOS tube HP5, and one end of the first capacitor C1 are connected to VCC; the gate of the fourth high-voltage NMOS tube HN4 is connected to the gate of the fifth high-voltage NMOS tube HN5, the drain of the fifth high-voltage NMOS tube HN5, and the drain of the third high-voltage PMOS tube HP3; the gate of the third high-voltage PMOS tube HP3 is connected to the gate of the second high-voltage PMOS tube HP2, and the gate of the third high-voltage PMOS tube HP3 is connected to the gate of the The source electrode is connected to the source electrode of the second high-voltage PMOS tube HP2, the source electrode of the sixth high-voltage PMOS tube HP6, and the source electrode of the seventh high-voltage PMOS tube HP7, and is connected to VPRE; the gate electrode of the first high-voltage PMOS tube HP1 is connected to the positive terminal of the fifth Zener tube Z5, the drain electrode of the sixth high-voltage PMOS tube HP6, and the drain electrode of the sixth high-voltage NMOS tube HN6; the gate electrode of the sixth high-voltage PMOS tube HP6 is connected to the gate electrode of the seventh high-voltage PMOS tube HP7, the drain electrode of the seventh high-voltage PMOS tube HP7, and the drain electrode of the seventh high-voltage NMOS tube HN7; the gate electrode of the seventh high-voltage NMOS tube HN7 is connected to the reference voltage VBIAS, and the source electrode thereof is connected to the source electrode of the sixth high-voltage NMOS tube HN6 and the input terminal of the second reference current source IBIAS2;The gate of the sixth high-voltage NMOS transistor HN6 is connected to the other end of the first capacitor C1, one end of the second resistor R2, and one end of the third resistor R3; the gate of the eighth high-voltage NMOS transistor HN8 is connected to the self-starting LDO enable signal Disable; the base of the first NPN transistor Q1 is connected to the other end of the first resistor R1 and the other end of the second resistor R2, the emitter of the first NPN transistor Q1 is connected to one end of the fourth resistor R4, the collector of the first NPN transistor Q1 is connected to the gate of the fourth high-voltage PMOS transistor HP4, the gate of the fifth high-voltage PMOS transistor HP5, and the drain of the fifth high-voltage PMOS transistor HP5; the drain of the fourth high-voltage PMOS transistor HP4 is connected to the collector of the third NPN transistor Q3 and the base of the fourth NPN transistor Q4; the third NPN The base of transistor Q3 is connected to the base of the second NPN transistor Q2, the collector of the second NPN transistor Q2, and the other end of the fourth resistor R4, and the emitter of the third NPN transistor Q3 is connected to one end of the fifth resistor R5; the source of the eighth high-voltage NMOS transistor HN8 is connected to the input end of the first reference current source IBIAS1; the collector of the fourth NPN transistor Q4 is connected to the other end of the sixth resistor R6, the negative end of the fifth Zener transistor Z5 is connected to VCC_READY, and the emitter of the fourth NPN transistor Q4 is connected to the output end of the first reference current source IBIAS1, the output end of the second reference current source IBIAS2, the positive end of the fifth Zener transistor Z5, the other end of the third resistor R3, the other end of the fifth resistor R5, and the emitter of the second NPN transistor Q2 are grounded. ;

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