Pixel circuit and image sensor

Abstract

A pixel circuit and an image sensor are provided. The pixel circuit includes a photodiode configured to operate in a photovoltaic mode and to accumulate a charge corresponding to an amount of incident light, a reset transistor configured to reset the photodiode accumulated charge, and a peak hold circuit configured to hold an output corresponding to the photodiode accumulated charge, the peak hold circuit including a peak hold transistor connected to an output terminal of the photodiode, a switch transistor configured to turn on / off the peak hold transistor output, and a hold capacitor configured to hold the switch transistor output. The peak hold transistor operates in a state where there is no carrier charge or only one carrier charge on a channel.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to a pixel circuit and an image sensor each including a photodiode configured to operate in a photovoltaic mode and accumulate a charge corresponding to an amount of incident light, and a peak hold circuit. BACKGROUND

[0002] A photodiode for an image sensor generally operates in a logarithmic region and a linear region. In the logarithmic region, the photodiode operates with forward bias and shows a logarithmic response to incident light; in the linear region, the photodiode operates with reverse bias and partial forward bias, and shows a linear response to incident light.

[0003] One example discloses a pixel circuit using such a photodiode. The pixel circuit includes a peak hold circuit that holds a peak of an output of the photodiode, thereby eliminating flicker caused by an LED light source.

[0004] As described above, when the peak hold circuit is provided, the peak hold transistor performs a floating gate operation. Thus, noise increases due to positive feedback. SUMMARY

[0005] According to the pixel circuit of the present disclosure, a photodiode is configured to operate in a photovoltaic mode and accumulate a charge corresponding to an amount of incident light; a reset transistor is configured to reset the accumulated charge of the photodiode; and a peak hold circuit is configured to hold an output corresponding to the accumulated charge of the photodiode, the peak hold circuit including a peak hold transistor connected to an output terminal of the photodiode, a switch transistor configured to turn on / off an output of the peak hold transistor, and a holding capacitor configured to hold an output of the switch transistor. The peak hold transistor operates in a state in which there is no carrier charge or only one carrier charge on a channel.

[0006] An image sensor according to the present disclosure includes a plurality of pixels, a plurality of analog-digital converters, and a horizontal scanning circuit. Each of the pixels includes (1) a photodiode configured to operate in a photovoltaic mode and to accumulate electric charges corresponding to an amount of incident light, (2) a reset transistor configured to reset the accumulated electric charges of the photodiode, (3) a peak hold circuit configured to hold an output corresponding to the accumulated electric charges of the photodiode, the peak hold circuit including (i) a peak hold transistor connected to an output terminal of the photodiode, (ii) a switch transistor configured to turn on / off an output of the peak hold transistor, and (iii) a hold capacitor configured to hold the output of the switch transistor, and (4) a source follower circuit configured to output, as a signal voltage, a voltage held in the hold capacitor of the peak hold circuit. The peak hold transistor operates in a state in which no electric charges or only one electric charge exists on a channel. The plurality of analog-digital converters convert respective signal voltages output by the source follower circuits of the plurality of pixels into digital signals. The horizontal scanning circuit serially outputs the digital signals.

[0007] According to the pixel circuit and the image sensor of the present disclosure, by limiting movement of electric charges in the peak hold transistor, positive feedback noise can be suppressed. BRIEF DESCRIPTION OF DRAWINGS

[0008] Embodiments of the present disclosure will be described based on the following diagrams, in which:

[0009] Figure 1 is a diagram illustrating a configuration of a pixel circuit as a premise of the present disclosure;

[0010] Figure 2 is a diagram illustrating capacitances around a peak hold transistor PH;

[0011] Figure 3A is a diagram illustrating a potential state of the peak hold transistor PH in a strong inversion state;

[0012] Figure 3B is a diagram illustrating a potential state of the peak hold transistor PH in a weak inversion state;

[0013] Figure 4 is a diagram illustrating a relationship between frequency and noise power;

[0014] Figure 5 is a diagram illustrating a state in which no electric charges (no electrons) exist in a channel region;

[0015] Figure 6 is a circuit diagram in a case where electric charges (holes) are injected from a drain of a p-channel peak hold transistor PH to operate a peak hold circuit, in which an amount of the injected holes is limited by a Tvct transistor;

[0016] Figure 7 is a timing chart illustrating Figure 6 circuit operation;

[0017] Figure 8 is a chart illustrating a two-dimensional arrangement of pixels of an image sensor according to one embodiment;

[0018] Figure 9 is a timing chart illustrating Figure 8 sensor operation;

[0019] Figure 10 is a chart illustrating a configuration in the case where a plurality of pixels are provided in Figure 6 and illustrates two pixels;

[0020] Figure 11 is a chart illustrating another configuration of a pixel circuit;

[0021] Figure 12 is a chart illustrating still another configuration of a pixel circuit;

[0022] Figure 13 is a chart illustrating a configuration in the case where a plurality of pixels are provided in Figure 12 and illustrates two pixels; and

[0023] Figure 14 is a chart illustrating a relationship between a signal current of an output PDout of a photodiode PD, an output PHout of a peak holding circuit, and a signal-to-noise ratio S / N.

[0024] BRIEF DESCRIPTION OF DRAWINGS

[0025] 40: output line

[0026] 200: image sensor

[0027] 210: pixel array

[0028] 212: vertical scanning circuit

[0029] 214: analog-digital converter 216: horizontal scanning circuit

[0030] B: reset power supply

[0031] bias: bias transistor

[0032] Cpd: capacitance

[0033] Csig: holding capacitance

[0034] Cox: gate capacitance

[0035] e: electron mobility fc, fcph, fcpd: cut-off frequency H: level

[0036] Isig: Logarithm (Log)

[0037] Injection: Injection power source

[0038] k: Boltzmann constant

[0039] L: Gate length

[0040] load: Load transistor MOSFET: Transistor

[0041] N: Noise

[0042] P: Pixel

[0043] PD: Photodiode PDout, PHout: Output PH: Peak holding transistor RESET: Reset potential

[0044] RST: Reset transistor

[0045] SEL: Selection transistor

[0046] SF: Source follower transistor

[0047] S / N: Signal-to-noise ratio

[0048] SWsig: Switching transistor

[0049] T: Absolute temperature

[0050] Ton / off: Switching transistor

[0051] Tvct: Voltage control transistor

[0052] t0, t1, t2: Time

[0053] Vg: Gate voltage

[0054] Vpd: Output voltage

[0055] Vt: Threshold voltage DETAILED DESCRIPTION

[0056] Embodiments of the present disclosure are described below with reference to the accompanying drawings. The following embodiments do not limit the present disclosure, and configurations obtained by selectively combining a plurality of described embodiments are also included in the present disclosure.

[0057] Configuration of pixel circuit

[0058] Figure 1 is a diagram illustrating a configuration of a pixel circuit as a premise of the present disclosure.

[0059] The photodiode PD accumulates electric charges (electrons in this case) based on incident light. The cathode of the photodiode PD serves as an output terminal, and the anode is connected to a power source (e.g., ground). Thus, the output voltage Vpd of the photodiode PD is an output signal.

[0060] One end (drain) of the reset transistor RST is connected to the cathode of the photodiode PD, and the other end (source) of the reset transistor RST is connected to a power source (e.g., ground) through a reset power source B. In this example, the reset transistor RST is an n-channel transistor.

[0061] The cathode of the photodiode PD is connected to the gate of the peak hold transistor PH. The peak hold transistor PH is a p-channel transistor. The drain of the peak hold transistor PH is connected to a power source (e.g., ground). The peak hold circuit includes the peak hold transistor PH and a hold capacitor Csig. In this example, the peak hold circuit further includes a bias transistor bias, a load transistor load, and a switch transistor SWsig. Figure 1

[0062] The source of the switch transistor SWsig is connected to the source of the peak hold transistor PH. One end of the hold capacitor Csig is connected to the drain of the switch transistor SWsig. The other end of the hold capacitor Csig is connected to a power source (e.g., ground). The switch transistor SWsig is a p-channel transistor.

[0063] The drain of the switch transistor SWsig is connected to the gate of the source follower transistor SF. The drain of the source follower transistor SF is connected to a power source, and the source is connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to the output line 40.

[0064] The source of the peak hold transistor PH is also connected to a power source through the bias transistor and the load transistor. The bias transistor and the load transistor are p-channel transistors.

[0065] The gate voltage of the load transistor load is set to a direct current voltage that causes the peak hold transistor PH to perform a source follower operation. To inject holes into the hold capacitor Csig, a negative pulse is applied to the bias transistor bias.

[0066] A row selection signal is supplied to the gate of the selection transistor SEL. When the row selection signal becomes an H level, a signal corresponding to the gate voltage of the readout source follower transistor SF is output to the output line 40.

[0067] After the reset transistor RST is turned on to reset the photodiode PD, the bias transistor and the switch transistor SWsig are turned on to inject electric charges (holes) into the hold capacitor Csig.

[0068] ​Thereafter, the bias transistor is turned off to discharge the excess charge through the peak holding transistor PH. As a result, the holding capacitor Csig is placed in a reset state. In this state, a signal supplied from the peak holding transistor PH is accumulated in the holding capacitor Csig through the switching transistor SWsig during one frame period. As described above, the output voltage corresponding to the accumulated charge of the photodiode PD is supplied to the gate of the peak holding transistor PH. Therefore, the charge corresponding to the amount of incident light of the photodiode PD during one frame period is accumulated in the holding capacitor Csig.

[0069] Further, when the switching transistor SWsig is turned off and the selection transistor SEL is turned on, a voltage signal corresponding to the charge accumulated in the holding capacitor Csig is read out to the output line 40.

[0070] In this example, the gate of the peak holding transistor PH is connected only to the output terminal of the photodiode. Therefore, the gate of the peak holding transistor PH is in a floating state, and the peak holding transistor PH performs a floating gate operation. Therefore, noise increases due to positive feedback.

[0071] Note that, in the present embodiment, the MOSFET is configured to function as a transistor.

[0072] Figure 2 The capacitances around the peak holding transistor PH are illustrated. In this example, an n-type channel in which the carrier of the peak holding transistor PH is an electron is described. In the case of a p-type channel, the carrier is a hole, and the polarity of the potentials in the figure is reversed.

[0073] As illustrated, the capacitance Cpd of the photodiode PD is connected to the gate of the peak holding transistor PH, and the holding capacitor Csig is connected to the source. Further, the peak holding transistor PH includes a gate capacitance Cox.

[0074] Figure 3A And Figure 3B is a graph illustrating the potential state of the peak holding transistor PH. Figure 3A illustrates the potential in a strong inversion state, Figure 3B illustrates the potential in a weak inversion state. In the figure, the potential is negative on the upper side and positive on the lower side.

[0075] As illustrated, in the strong inversion state in which the gate voltage Vg exceeds the threshold voltage Vt, the potential on the holding capacitor Csig side is further shifted to the negative side, and the charge (electrons) flows to the power supply over the potential barrier of the gate. In contrast, in the weak inversion state in which the gate voltage Vg does not exceed the threshold voltage Vt, the potential of the holding capacitor Csig is lower than the potential barrier of the gate, and a small amount of charge (electrons) randomly flows to the power supply over the potential barrier of the gate.

[0076] Noise characteristics of a peak hold circuit including a peak hold transistor PH and a hold capacitor Csig are described. Noise in the case where a gate voltage is fixed and a noise band is limited is expressed as N. Further, a Boltzmann constant is expressed as k, and an absolute temperature is expressed as T.

[0077] Strong inversion state

[0078] In the strong inversion state, in a limited band (in-phase) where the noise is limited to be less than or equal to a cutoff frequency fc, the noise N is expressed as follows,

[0079] (1 + A) * N,

[0080] where A = (2 / 3) * Cox / Cpd.

[0081] Further, in a full band where a frequency is not limited, the noise N is expressed as follows,

[0082] (1 + A) 1 / 2 * [(2 / 3) * kT / Csig] 1 / 2 .

[0083] Weak inversion state

[0084] In the weak inversion state, in a limited band (in-phase) where the noise is limited to be less than or equal to a cutoff frequency fc, the noise N is expressed as follows,

[0085] (1 + A) * N,

[0086] where A = (1 / 2) * Cox / Cpd.

[0087] Therefore, the noise is amplified by (1 + A) times by the peak hold circuit.

[0088] Further, in a full band where a frequency is not limited, the noise is expressed as follows,

[0089] (1 + A) 1 / 2 * [(1 / 2) * kT / Csig] 1 / 2 .

[0090] In a limited band (a frequency band is limited to be less than or equal to a cutoff frequency fc), the noise is amplified by (1 + A) times by the peak hold circuit. This is because the peak hold circuit performs an in-phase operation to cause positive feedback. In contrast, at a frequency greater than or equal to the cutoff frequency fc, positive feedback does not occur since the phase is rotated by 90 degrees. Therefore, in a full band, the noise is amplified by (1 + A) 1 / 2 times. Note that, as described above, the value "A" is different between the strong inversion state and the weak inversion state.

[0091] Figure 4is a graph illustrating the relationship between frequency and noise power. As shown in the graph, the noise increases at frequencies less than or equal to the cutoff frequency fc. The noise decreases at frequencies greater than or equal to the cutoff frequency.

[0092] Note that whether the peak hold circuit performs a limited band operation or a full band operation is determined by the circuit and signal processing of the subsequent stage.

[0093] As described above, when the peak hold circuit including the peak hold transistor PH and the hold capacitor Csig is set, the noise increases due to positive feedback.

[0094] Embodiment 1

[0095] According to the noise analysis, in a case where only one carrier charge (hereinafter referred to as charge) exists on the channel of the peak hold transistor PH, or in a case where no charge exists on the channel of the peak hold transistor PH, the noise does not increase due to positive feedback.

[0096] Figure 5 A state in which no charge (no electron) exists in the channel region is illustrated.

[0097] The current in a case where only one electron exists in the channel region is estimated. When one electron flows through the gate channel, the current is expressed as follows,

[0098] I = kT * (e / L 2 ).

[0099] where k is the Boltzmann constant, T is the absolute temperature, e is the mobility of the electron, and L is the gate length of the peak hold transistor PH (MOSFET in this case).

[0100] When L = 1 μm and e = 0.02 m 2 / V / s are assumed, the current value is about 10 nA. Therefore, it can be considered that the peak hold circuit operates in a state where only one electron exists when the current (1 nA) is one order of magnitude lower than this value.

[0101] Note that, by microfabrication technology in recent years, the L value can be reduced to less than or equal to 0.01 μm, and the mobility e of the electron can be increased to about 0.15 m 2 / V / s. Therefore, even at a current of 1 nA or more, the peak hold circuit can sufficiently operate with only one electron. This charge-limited mode is called a single carrier transfer mode.

[0102] Therefore, when the peak hold circuit operates at a level of about 1 nA, the peak hold circuit performs operation in the single carrier transfer mode, and the noise does not increase due to positive feedback.

[0103] In this state, the noise N = N in the limited bandwidth (in-phase) holds, and the noise N = ((1 / 2) * kT / Csig) in the full bandwidth holds 1 / 2 holds.

[0104] In the present embodiment, the number of charges (electrons) present in the channel of the peak holding transistor PH is set to one or less. This makes it possible to suppress the occurrence of noise due to positive feedback. In the case where the number of charges is limited as described above, the peak holding transistor PH performs full bandwidth operation due to the small current value.

[0105] As described above, in the present embodiment, the peak holding transistor PH of the circuit is limited Figure 1 the drain current of the drain output of the peak holding transistor PH of the circuit, so that the peak holding circuit performs operation in the single carrier transfer mode. This makes it possible to prevent an increase in noise due to positive feedback.

[0106] Embodiment 2

[0107] Figure 6 is a circuit diagram in the case where charges (holes) are injected from the drain of the p-channel peak holding transistor PH to operate the peak holding circuit. Figure 7 is a timing chart illustrating Figure 6 operation of the circuit.

[0108] In the present example, the drain of the p-channel peak holding transistor PH is connected to the injection power source Injection through the voltage control transistor Tvct. The source of the peak holding transistor PH is connected to the holding capacitor Csig and the gate of the source follower transistor SF through the switching transistor SWsig.

[0109] The reset transistor RST is turned on to reset the output of the photodiode PD. Next, the injection power source Injection is set to the H level for a short time to supply holes to the holding capacitor Csig through the peak holding transistor PH and the switching transistor SWsig.

[0110] After the signal integration period corresponding to one frame, the gate of the switching transistor SWsig is set to the H level (off for a p-channel transistor), and the selection transistor SEL is set to the H level (on). As a result, the signal voltage held in the holding capacitor Csig is output to the output line 40 through the source follower transistor SF and the selection transistor SEL.

[0111] At this time, if the drain voltage of the peak holding transistor PH becomes too high, the drain current increases. In the present embodiment, a voltage control transistor Tvct is provided between the injection power supply and the drain of the peak holding transistor PH. Further, the voltage control transistor Tvct performs control so that the drain voltage of the peak holding transistor PH does not become too high. This makes it possible to reduce the amount of charge injected to the peak holding transistor PH and achieve operation in the single carrier transfer mode.

[0112] Configuration of image sensor

[0113] Figure 8 is a diagram illustrating an image sensor 200 in which pixels according to any embodiment are two-dimensionally arranged. The pixel array 210 includes pixels P arranged in m columns * n rows (m * n) as described above, i.e., m pixels in the horizontal direction and n pixels in the vertical direction. A vertical scanning circuit (V-Scan) 212 sequentially selects the rows of pixels in the vertical direction. The pixels of each column are connected to a respective analog-to-digital converter (ADC) 214 through a respective vertical direction read line. A horizontal scanning circuit (H-Scan) 216 is connected to the analog-to-digital converters (ADCs) 214, and the image signals of the respective pixels are sequentially output from the horizontal scanning circuit (H-Scan) 216.

[0114] Figure 9 is a timing chart illustrating the operation of the image sensor in Figure 8 Figure 7 The timing chart of the injection power supply Injection and SWsig shown in

[0115] In the (k-1)th row, the reset transistor RST is turned on to reset the photodiode PD. The reset is performed for each vertical period (= 1 frame period). Further, the exposure starts after the reset once. In addition, the signal is read out shortly before the next reset. As described above, the selection transistor SEL is turned on, and the signal accumulated in the holding capacitor Csig is read out to the output line 40. This control is performed in response to a signal from the vertical scanning circuit (V-scan) 212. The read-out signal is supplied to the analog-to-digital converter (ADC) 214 and converted into a digital signal. This operation is performed simultaneously on the m pixels on one horizontal line. Thereafter, the horizontal scanning circuit (H-scan) 216 sequentially outputs the digital signals of the m pixels.

[0116] Next, by shifting the horizontal period by 1H, the same operation is performed in the kth row. By repeating this operation n times, the signals of all the m * n pixels can be read out.

[0117] Embodiment 3

[0118] Figure 10 is a diagram illustrating the operation of the image sensor in Figure 6 ​A diagram showing the configuration for multiple pixels, with an illustration of two pixels.

[0119] As shown in the figure, the drains of the peak holding transistors PH for multiple pixels in a row are connected to a voltage-controlled transistor Tvct. Therefore, a voltage-controlled transistor Tvct can control the drain voltages of the peak holding transistors PH for multiple pixels.

[0120] Note that the number of pixels controlled by a voltage-controlled transistor Tvct is optional; for example, all pixels in a row can be controlled by a single voltage-controlled transistor Tvct.

[0121] Example 4

[0122] Figure 11 This is a diagram illustrating the configuration according to Example 4. Basic configuration and... Figure 6 The same applies in the example. However, in this example, the gate of the voltage-controlled transistor Tvct is connected to the output of the photodiode PD. Therefore, the gate voltage of the voltage-controlled transistor Tvct, along with the gate voltage of the peak-hold transistor PH, varies with the output of the photodiode PD. This allows the effects of voltage variations in the output of the photodiode PD to be eliminated.

[0123] Example 5

[0124] Figure 12 This is a diagram illustrating the configuration according to Example 5. In this example, holes are injected from the source side of the peak holding transistor PH.

[0125] The source of the peak holding transistor PH is connected to the power supply via the switching transistor Ton / off and the voltage control transistor Tvct.

[0126] In this circuit, after holes are injected into the holding capacitor Csig via the peak-holding transistor PH and the switching transistor SWsig, the switching transistor Ton / off is turned on, and the source voltage of the peak-holding transistor PH is controlled by the voltage-controlled transistor Tvct. In other words, by controlling the source voltage of the peak-holding transistor PH to a predetermined value, the amount of charge on the channel is reduced to one or less, resulting in operation in a single-carrier transfer mode.

[0127] Example 6

[0128] Figure 13 This means that in Figure 12 The diagram provides a configuration for multiple pixels, illustrating two pixels. As shown, the source of the peak holding transistor PH for multiple pixels is connected to a voltage-controlled transistor Tvct. Therefore, the source voltage of the peak holding transistor PH for multiple pixels can be controlled by a single voltage-controlled transistor Tvct.

[0129] Other effects

[0130] Figure 14 is a graph showing the relationship between the output PDout of the photodiode PD, the signal current of the output PHout of the peak hold circuit, and the signal-to-noise ratio S / N.

[0131] The thermal noise of the photodiode PD depends on the signal current and has a wide noise bandwidth. According to the prior art (Yang Ni. New Imaging Technologies, France, "QLOG-Logarithmic CMOS Pixel with Single Electron Detection Capability" Proceedings of the 2017 International Image Sensor Workshop, Hiroshima, Japan, 30 May-2 June 2017), the signal-to-noise ratio of the photodiode PD has a constant value in the logarithmic region (as shown by the solid line in Figure 14 ). According to the prior art, the signal-to-noise ratio is 29 dB in the case where the capacitance Cpd of the photodiode PD is 1 fF, which is not a good value.

[0132] In the case where the peak hold circuit operates in the single-carrier transfer mode as in the present embodiment, the operating bandwidth is narrowed. Therefore, the noise is reduced by band limitation, and the signal-to-noise ratio is improved when the signal is acquired by the peak hold circuit (as shown by the dashed line in Figure 14 ).

[0133] Therefore, according to the present embodiment, a clear image can be obtained in a region where the signal current is large.

[0134] In the graph, "fcph" is the cut-off frequency of the peak hold circuit, and "fcpd" is the cut-off frequency of the photodiode PD.

Claims

1. A pixel circuit comprising: a photodiode configured to operate in a photovoltaic mode and to accumulate a charge corresponding to an amount of incident light; a reset transistor configured to reset the accumulated charge of the photodiode; and a peak hold circuit configured to hold an output corresponding to the accumulated charge of the photodiode, the peak hold circuit including a peak hold transistor connected to an output of the photodiode, a switch transistor configured to turn on / off an output of the peak hold transistor, and a hold capacitor configured to hold an output of the switch transistor, wherein the peak hold transistor operates in a state where there is no or only one carrier charge on a channel of the peak hold circuit, and 2. The pixel circuit according to claim 1, wherein the peak holding transistor operates at a drain current less than or equal to kT μe / L 2 where k is the Boltzmann constant, T is the absolute temperature, μe is the mobility of the electron, and L is the gate length of the peak holding transistor. the peak hold transistor is a p-channel transistor and includes a drain connected to a voltage control transistor, and an injection of charge is controlled by adjusting a drain voltage of the peak hold transistor.

3. The pixel circuit according to claim 1, wherein the peak hold transistor is a p-channel transistor and includes a source connected to a voltage control transistor, and an injection of charge is controlled by adjusting a source voltage of the peak hold transistor.

4. The pixel circuit according to claim 2, wherein the voltage control transistor includes one end connected to an injection power supply for supplying charge for resetting the hold capacitor, and the other end connected to a drain of the peak hold transistor, and charge from the injection power supply is supplied to the hold capacitor through the voltage control transistor and the peak hold transistor.

5. The pixel circuit according to claim 3, wherein a vertical scanning circuit; the voltage control transistor includes one end connected to a predetermined negative power supply, and the other end connected to a source of the peak hold transistor, and the peak hold transistor is source-follower driven to supply charge from a gate of the peak hold transistor to the hold capacitor.

6. An image sensor comprising: a plurality of pixels; a plurality of analog-to-digital converters; and a horizontal scanning circuit, wherein each of the pixels includes a photodiode configured to operate in a photovoltaic mode and to accumulate a charge corresponding to an amount of incident light, a reset transistor configured to reset the accumulated charge of the photodiode, and a peak hold circuit configured to hold an output corresponding to the accumulated charge of the photodiode, wherein the peak hold circuit includes a peak hold transistor connected to an output of the photodiode, a switch transistor configured to turn on / off an output of the peak hold transistor, a hold capacitor configured to hold an output of the switch transistor, and a source follower circuit configured to output a voltage held in the hold capacitor of the peak hold circuit as a signal voltage, the analog-to-digital converters convert the signal voltage output from the source follower circuit of the plurality of pixels into a digital signal, and the horizontal scanning circuit serially outputs the digital signal. the peak holding transistor operates under the condition that drain current is less than or equal to kT μe / L 2 where k is the Boltzmann constant, T is the absolute temperature, μe is the mobility of the electron, and L is the gate length of the peak holding transistor.

7. A pixel circuit comprising: ​ ​ A photodiode configured to operate in a photovoltaic mode and accumulate a charge corresponding to an amount of incident light; A reset transistor configured to reset the accumulated charge of the photodiode; and A peak holding circuit configured to hold an output corresponding to the accumulated charge of the photodiode, the peak holding circuit including a peak holding transistor connected to an output terminal of the photodiode, a switch transistor configured to turn on / off the output of the peak holding transistor, and a holding capacitor configured to hold the output of the switch transistor, wherein the peak holding transistor operates in a state where there is no carrier charge or only one carrier charge on a channel of the peak holding circuit, wherein the peak holding transistor is a p-channel transistor and includes a drain connected to a voltage control transistor, and an injection of a charge is controlled by adjusting a drain voltage of the peak holding transistor, wherein the voltage control transistor includes one end connected to an injection power source for supplying a charge for resetting the holding capacitor, and the other end connected to the drain of the peak holding transistor, and the charge from the injection power source is supplied to the holding capacitor through the voltage control transistor and the peak holding transistor.

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