Printed circuit board and method for manufacturing printed circuit board

Abstract

The invention provides a printed circuit board and a manufacturing method of the printed circuit board. The printed circuit board includes a first insulating layer and a plurality of first metal patterns disposed on the first insulating layer, where the first insulating layer has at least one recess disposed between the plurality of first metal patterns, and each of the plurality of first metal patterns includes: a first seed metal layer disposed on the first seed metal layer; the first electrode is arranged on the first insulating layer; the second seed metal layer is arranged on the first seed metal layer; and a first metal pattern layer disposed on the second seed metal layer.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2023-0181532, filed with the Korean Intellectual Property Office on December 14, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a printed circuit board and a method of manufacturing the printed circuit board. Background Art

[0003] One of the current development directions in the semiconductor industry is to increase the driving speed by closely arranging multiple chips in a single package. In this regard, in order to overcome the fine wiring limitations of packages made of organic materials, a technology using an interposer made of an inorganic material as a redistribution layer for inter-chip connection has been developed. However, in the case of an interposer made of such an inorganic material, since it is necessary to form other components in addition to the components required for interconnection, its process may be slightly complicated, and its cost may increase due to unnecessary area expansion. Summary of the Invention

[0004] One aspect of the present disclosure is to provide a printed circuit board and a method of manufacturing the printed circuit board that can form a microcircuit pattern in a desired region without side effects such as undercut.

[0005] One aspect of the present disclosure is to provide a printed circuit board and a method of manufacturing the printed circuit board that can improve the adhesion between insulating layers.

[0006] As one of several solutions proposed by the present disclosure, a first seed metal layer and a second seed metal layer are formed on an insulating layer, and based on this, a metal pattern layer is formed. Then, the second seed metal layer exposed between the metal pattern layers is removed by wet etching, and the first seed metal layer is removed by dry etching to form a microcircuit pattern. In addition, if necessary, by this dry etching, recesses can be formed in the regions of the insulating layer located between the metal pattern layers, and surface roughness can be formed on the bottom surfaces of the recesses.

[0007] For example, a printed circuit board according to an exemplary embodiment may include: a first insulating layer; and a plurality of first metal patterns disposed on the first insulating layer, and the first insulating layer may include at least one recess, the at least one recess may be disposed between the plurality of first metal patterns, and each of the plurality of first metal patterns may include: a first seed metal layer disposed on the first insulating layer; a second seed metal layer disposed on the first seed metal layer; and a first metal pattern layer disposed on the second seed metal layer.

[0008] For example, a method of manufacturing a printed circuit board according to an exemplary embodiment may include: forming a first seed metal layer on an insulating layer; forming a second seed metal layer on the first seed metal layer; forming a first metal pattern layer on the second seed metal layer; removing at least a part of the second seed metal layer exposed from the first metal pattern layer; and removing at least a part of the first seed metal layer exposed from the first metal pattern layer and the second seed metal layer, wherein the step of removing the at least a part of the first seed metal layer includes removing at least a part of the insulating layer to form at least one recess.

[0009] One of the various effects of the present disclosure is to provide a printed circuit board capable of forming a microcircuit pattern in a desired region without side effects such as undercut and a method of manufacturing the same.

[0010] Another effect of the present disclosure is to provide a printed circuit board capable of improving the adhesion between insulating layers and a method of manufacturing the same. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 is a block diagram schematically showing an example of an electronic device system; Figure 2 is a perspective view schematically showing an example of an electronic device; Figure 3 is a cross-sectional view schematically showing an example of a printed circuit board; Figures 4A to 4H is schematically showing the manufacturing Figure 3 in an example of a process cross-sectional view of a printed circuit board; Figure 5A , Figure 6A , Figure 7A and Figure 8A are cross-sectional images schematically showing a dry etching process of a first seed metal layer captured by an electron microscope, and Figure 5B , Figure 6B , Figure 7B and Figure 8B are respectively Figure 5A , Figure 6A , Figure 7A and Figure 8A top view images of the cross-sectional images in; Figure 9 is an image captured by an electron microscope schematically showing the shape of an interconnect after dry etching of a first seed metal layer and the shape of a recess formed in an insulating layer; and Figure 10 It is a cross-sectional view schematically showing another example of a printed circuit board. Detailed implementation

[0012] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. In the drawings, for clarity of description, the shapes and sizes of elements may be exaggerated or reduced.

[0013] Electronic device Figure 1 It is a block diagram schematically showing an example of an electronic device system.

[0014] Referring to Figure 1 , in the electronic device 1000, a main board 1010 is accommodated. Physical connections and / or electrical connections are made to the main board 1010 for chip-related components 1020, network-related components 1030, other components 1040, and the like. These components are also connected to other electronic components to be described below through various signal lines 1090.

[0015] The chip-related components 1020 may include: memory chips, such as volatile memories (e.g., dynamic random access memory (DRAM)), non-volatile memories (e.g., read-only memory (ROM), flash memory), etc.; application processor chips, such as central processors (e.g., central processing unit (CPU)), graphics processors (e.g., graphics processing unit (GPU)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADC), application-specific integrated circuits (ASIC), etc. However, the chip-related components 1020 are not limited thereto, and may also include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of packages including the above-mentioned chips.

[0016] The network-related components 1030 may include components that are compatible with or operate according to protocols such as: Wi-Fi (such as the Institute of Electrical and Electronics Engineers (IEEE) 802.11 series), Worldwide Interoperability for Microwave Access (WiMAX) (such as the IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed Packet Access Plus (HSPA+), High Speed Downlink Packet Access Plus (HSDPA+), High Speed Uplink Packet Access Plus (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, 3rd generation mobile communication technology (3G) protocols, 4th generation mobile communication technology (4G) protocols, and 5th generation mobile communication technology (5G) protocols, as well as any other wireless standards or protocols and wired standards or protocols specified after the above-mentioned protocols. However, the network-related components 1030 are not limited thereto, and may also include components that are compatible with or operate according to any one of multiple other wireless standards or protocols and wired standards or protocols. In addition, the network-related components 1030 may be combined with the above-mentioned chip-related components 1020.

[0017] The other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, Low Temperature Co-fired Ceramic (LTCC) components, Electromagnetic Interference (EMI) filters, Multi-Layer Ceramic Capacitors (MLCCs), etc. However, the other components 1040 are not limited thereto, and may also include passive components in the form of chip components for various other purposes. In addition, the other components 1040 may be combined with each other together with the chip-related components 1020 and / or the network-related components 1030.

[0018] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that are physically connected and / or electrically connected to the main board 1010 or not physically connected and / or not electrically connected to the main board 1010. These other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, and a battery 1080. However, these other electronic components are not limited thereto, but may include an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a Compact Disc (CD) drive, a Digital Versatile Disc (DVD) drive, etc. In addition, depending on the type of the electronic device 1000, the electronic device 1000 may also include other electronic components for various purposes.

[0019] The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automotive component. However, the electronic device 1000 is not limited thereto, and may be any other electronic device capable of processing data.

[0020] Figure 2 is a perspective view schematically showing an example of an electronic device.

[0021] Referring to Figure 2 , the electronic device may be, for example, the smart phone 1100. The main board 1110 may be accommodated in the smart phone 1100, and various components 1120 may be physically and / or electrically connected to the main board 1110. In addition, other electronic components (such as the camera module 1130 and / or the speaker 1140) that are physically and / or electrically connected to the main board 1110 or not physically and / or not electrically connected to the main board 1110 may be accommodated in the smart phone 1100. Some of the components 1120 may be the above-described chip-related components. For example, the component package 1121, but the present disclosure is not limited thereto. The component package 1121 may be in the form of a printed circuit board on which electronic components (including active components and / or passive components) are surface-mounted. Alternatively, the component package 1121 may be in the form of a printed circuit board in which electronic components (including active components and / or passive components) are embedded. On the other hand, the electronic device does not have to be limited to the smart phone 1100, and may be other electronic devices as described above.

[0022] Printed circuit board Figure 3 is a cross-sectional view schematically showing an example of a printed circuit board.

[0023] Referring to Figure 3 , according to an exemplary embodiment, the printed circuit board 500A may include an insulating layer 110 and a plurality of metal patterns 120 disposed on an upper surface of the insulating layer 110. The insulating layer 110 may have at least one recess R. The recess R may be disposed between the plurality of metal patterns 120. Each of the plurality of metal patterns 120 may include: a first seed metal layer 121 disposed on the insulating layer 110; a second seed metal layer 122 disposed on the first seed metal layer 121; and a metal pattern layer 123 disposed on the second seed metal layer 122. On the upper surface of the insulating layer 110, the metal pattern layer 123 may be thicker than each of the first seed metal layer 121 and the second seed metal layer 122.

[0024] In addition, during the manufacturing process of a microcircuit board, the process for forming a multi-layer microcircuit pattern may have the following sequence. First, titanium (Ti) and copper (Cu) may be sequentially disposed (e.g., deposited) on an insulating layer as a seed metal layer. Next, copper (Cu) plating may be performed using a photoresist. Next, the photoresist may be removed, and then the seed metal layer in the unnecessary portion may be sequentially removed. By repeating this process, a multi-layer microcircuit pattern may be formed. In this case, wet etching may be used as a method for etching the titanium (Ti) layer (one of the seed metal layers), but due to the isotropic nature of wet etching, etching in the longitudinal direction and etching in the lateral direction (collectively referred to as undercut) occur simultaneously, such that the width of the titanium (Ti) layer in the interconnect line may become narrower. When the width of the interconnect line is wide due to design, this undercut may not be a serious problem, but in the case of a microcircuit pattern, the line width of the interconnect line is very narrow. Therefore, when undercut occurs, the line width may be reduced to 1 / 2 or less of the line width of the interconnect line, such that the titanium (Ti) layer may be lost or may remain very small, resulting in peeling.

[0025] On the other hand, as in the following process, in the printed circuit board 500A according to the exemplary embodiment, the first seed metal layer 121 may be removed by dry etching after wet etching is performed on the second seed metal layer 122. Compared with wet etching, dry etching may have anisotropic characteristics, and thus undercut in the first seed metal layer 121 may be prevented. For example, even when a plurality of metal patterns 120 include a plurality of microcircuit patterns in which L (line width) is 5 μm or less and / or S (spacing) is 5 μm or less, or L (line width) is 2 μm or less and / or S (spacing) is 2 μm or less, the above problem may not occur. This may prevent defective peeling of fine interconnect lines in advance, thereby improving quality defects (such as short circuits, open circuits, and signal noise) that may be caused by the separation of interconnect lines. In addition, a microcircuit board having a minimum area may be provided, thereby replacing a large-area interposer. Therefore, its cost may also be saved.

[0026] On the other hand, when performing such dry etching, a recess R may be formed in the region of the insulating layer 110 where the first seed metal layer 121 has been removed. For example, the recess R may penetrate a part of the first insulating layer 110 in the thickness direction from the region between the plurality of metal patterns 120 on the upper surface of the insulating layer 110. Accordingly, a stepped portion may exist between the region of the upper surface of the insulating layer 110 where the plurality of metal patterns 120 are provided and the region of the upper surface of the insulating layer 110 where the recess R is provided. If necessary, surface roughness may be formed on the region of the upper surface of the insulating layer 110 where the recess R is provided by dry etching. For example, the surface roughness of the region of the upper surface of the insulating layer 110 where the recess R is provided may be greater than the surface roughness of the region of the upper surface of the insulating layer 110 where the plurality of metal patterns 120 are provided. In this case, when the printed circuit board 500A is applied to a multilayer board and an additional insulating layer is formed on the insulating layer 110, the contact area between the insulating layers may be increased to improve adhesion. The surface roughness may be measured using a surface profilometer or a laser scanner. Even if not described in the present disclosure, other methods and / or tools understood by those of ordinary skill in the art may be used.

[0027] Hereinafter, components of the printed circuit board 500A according to an exemplary embodiment will be described in more detail with reference to the drawings.

[0028] The insulating layer 110 may include an organic insulating material. The organic insulating material may include a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide), or a material prepared by impregnating an inorganic filler, an organic filler, and / or glass fiber (e.g., a glass fabric such as glass cloth) in the resin. For example, the organic insulating material may be a non-photosensitive insulating material such as an Ajinomoto build-up film (ABF) or a prepreg (PPG), or may be a photosensitive insulating material such as a photosensitive dielectric (PID), but the present disclosure is not limited thereto. If necessary, the insulating layer 110 may include an inorganic insulating material including SiO2 and Si3N4.

[0029] The metal pattern 120 may include a metal. Examples of the metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or their alloys. The metal pattern 120 may perform various functions according to the design. For example, the metal pattern 120 may include a signal pattern, a power pattern, a ground pattern, etc. Preferably, the metal pattern 120 may include a signal pattern, but the present disclosure is not limited thereto. Each of these patterns may have various forms such as a line, a plane, and a pad.

[0030] The first seed metal layer 121 can increase the adhesion between the insulating layer 110 and the metal pattern 120. The first seed metal layer 121 can include titanium (Ti). For example, the first seed metal layer 121 can include pure titanium (pure Ti). Pure titanium (pure Ti) can mean including only titanium (Ti) (e.g., including 100% titanium (Ti)), rather than including an alloy or oxide containing titanium (Ti). For example, the first seed metal layer 121 can be formed by a deposition process such as a sputtering process, and thus, materials such as titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), etc. can be used as its material, but considering dry etching, most preferably, titanium (Ti) can be used. However, the present disclosure is not limited thereto, and the first seed metal layer 121 can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or their alloys.

[0031] The second seed metal layer 122 can be provided for an electroplating (or electrodepositing) conductive region. The second seed metal layer 122 can be formed by a deposition process such as a sputtering process, and considering the adhesion, conductivity, cost, etc. to the metal pattern layer 123, the second seed metal layer 122 can include copper (Cu), for example, it can include pure copper (Cu). Pure copper (Cu) can mean including only copper (Cu) (e.g., including 100% copper (Cu)), rather than including an alloy or oxide containing copper (Cu). However, the present disclosure is not limited thereto, and the second seed metal layer 122 can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or their alloys. The second seed metal layer 122 can be thicker than the first seed metal layer 121.

[0032] The metal pattern layer 123 can substantially provide the function of the metal pattern 120. The metal pattern layer 123 can be formed by a plating process such as an electroplating (or electrodepositing) process, and considering conductivity, cost, etc., the metal pattern layer 123 can include copper (Cu), for example, it can include pure copper (Cu). In addition, pure Cu can mean including only copper (Cu) (e.g., including 100% copper (Cu)), rather than including an alloy or oxide containing copper (Cu). However, the present disclosure is not limited thereto, and the metal pattern layer 123 can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or their alloys. The metal pattern layer 123 can be thicker than the first seed metal layer 121 and the second seed metal layer 122.

[0033] The bottom surface (e.g., the fourth surface) and the wall surface (e.g., the fifth surface) of the recess R may be substantially angled. As used herein, unless otherwise specified, the term "substantially" may provide an industry-accepted tolerance for the correlation between corresponding terms and / or items, such as a tolerance of ±1%, ±5% or ±10% of the actual value, or other suitable tolerances. As used herein, "substantially angled" means that the bottom surface and the wall surface together form an angle within the range of 30° to 150°.

[0034] For example, the recess R may have a substantially constant depth. For example, the difference between the maximum value and the minimum value among the measured depths may be less than 5% (e.g., the percentage of the difference between the maximum depth value and the minimum depth value relative to the minimum depth value, the maximum depth value, or the average depth value). For example, when surface roughness is not considered, each of the bottom surface and the wall surface of the recess R may be substantially flat. For example, the wall surface of the recess R may be substantially perpendicular to the bottom surface or may have an inclination close to vertical. For example, since the recess R may be formed in a process of removing a pure metal layer such as titanium (Ti) by dry etching, the recess R may have a substantially vertical shape rather than a rounded shape. The recess R may be recessed downward with respect to the surface of the insulating layer 110 that contacts the first seed metal layer 121. Therefore, the recess R may have a larger area, which can more effectively improve the adhesion between the above-mentioned insulating layers. The depth of the recess R may be greater than the thickness of the first seed metal layer 121 (the thickness of the seed metal layer is exaggerated in the drawings). In addition, the depth of the recess R may vary according to the pattern design (such as due to the loading effect (RIE lag) during Ti dry etching).

[0035] Figures 4A to 4H schematically shows the manufacturing Figure 3 in the process cross-sectional view of an example of a printed circuit board.

[0036] Referring to Figure 4A , the insulating layer 110 can be prepared. The insulating layer 110 may include an organic insulating material or an inorganic insulating material as described above.

[0037] Referring to Figure 4B , the first seed metal layer 121 can be formed on the insulating layer 110. As described above, a material such as titanium (Ti) can be used to form the first seed metal layer 121 by a deposition process such as a sputtering process.

[0038] Referring to Figure 4C , the second seed metal layer 122 can be formed on the first seed metal layer 121. As described above, a material such as copper (Cu) can be used to form the second seed metal layer 122 by a deposition process such as a sputtering process.

[0039] Referring to Figure 4D, a resist layer 150 having a plurality of openings h may be formed on the second seed metal layer 122. The resist layer 150 may include a photosensitive insulating material. The plurality of openings h may be formed by a photolithography process. Each of the plurality of openings h may expose at least a portion of the second seed metal layer 122.

[0040] Referring to Figure 4E , a metal pattern layer 123 may be formed in each of the plurality of openings h. For example, at least a portion of each of the plurality of openings h may be filled with copper (Cu) by a plating process such as electroplating (or electroless plating).

[0041] Referring to Figure 4F , the resist layer 150 may be removed. The resist layer 150 may be removed by a physical method or a chemical method. For example, a stripping solution or the like may be used to remove the resist layer 150, but the present disclosure is not limited thereto.

[0042] Referring to Figure 4G , at least a portion of the second seed metal layer 122 exposed from the metal pattern layer 123 may be removed. For example, at least a portion of the exposed second seed metal layer 122 may be removed by wet etching. At least a portion of the exposed second seed metal layer 122 may be removed such that at least a portion of the first seed metal layer 121 may be exposed from the second seed metal layer 122 and the metal pattern layer 123.

[0043] Referring to Figure 4H , at least a portion of the first seed metal layer 121 exposed from the metal pattern layer 123 and the second seed metal layer 122 may be removed. For example, at least a portion of the exposed first seed metal layer 121 may be removed by dry etching. At least a portion of the exposed first seed metal layer 121 may be removed such that at least a portion of the insulating layer 110 may be exposed from the first seed metal layer 121, the second seed metal layer 122, and the metal pattern layer 123. Further, during the dry etching process, at least a portion of the exposed insulating layer 110 may be removed to form at least one recess R. If necessary, surface roughness may be formed on a portion of the upper surface of the insulating layer 110 where the recess R is formed (e.g., the bottom surface of the recess R).

[0044] Through a series of processes, a printed circuit board 500A according to an exemplary embodiment may be manufactured. Other descriptions may be substantially the same as those in the printed circuit board 500A according to the above exemplary embodiment, and repeated descriptions thereof will be omitted.

[0045] Figure 5A , Figure 6A , Figure 7A and Figure 8A are chronological cross-sectional images schematically showing a dry etching process of the first seed metal layer captured by an electron microscope, and Figure 5B ,Figure 6B , Figure 7B and Figure 8B are respectively Figure 5A , Figure 6A , Figure 7A and Figure 8A the top-down images of the cross-sectional images in

[0046] Referring to the attached drawings, for example, in Figure 5A , Figure 5B , Figure 6A and Figure 6B it can be confirmed that in the dry etching of a titanium (Ti) layer with a thickness of approximately 50 nm, the insulating layer located on the lower surface of the titanium (Ti) layer can maintain its shape when the etching time has elapsed for about 30 seconds (for example, referring to Figure 5A and Figure 5B ), and can also maintain its shape when the etching time has elapsed for about 60 seconds (for example, referring to Figure 6A and Figure 6B ). On the other hand, for example, in Figure 7A , Figure 7B , Figure 8A and Figure 8B it can be confirmed that when the etching time has elapsed for about 90 seconds (for example, referring to Figure 7A and Figure 7B ), the insulating layer can be partially etched, and when the etching time has elapsed for about 120 seconds (for example, referring to Figure 8A and Figure 8B ), the insulating layer can be etched more, thus forming a concave portion including a stepped portion. For example, in addition to an etching gas for physical reaction (such as argon), a mixed gas obtained by mixing a fluorine-based gas (CF4, CHF3, SF6, etc.) or a chlorine-based gas (Cl2, BCl3, etc.) as an etching gas for chemical reaction can be used to etch an organic insulating layer, thereby generating an etching step difference, which can also be similarly applied to an inorganic insulating layer. For example, in an etching process for removing a specific material, in order to respond to a change in the etching rate caused by a change in the etchant or spatial dispersion occurring in the plate, an additional etching time can be added based on the required etching time, and in the case of dry etching, since dry etching has anisotropic characteristics, the etching can be performed in the downward direction, thereby forming the above-mentioned concave portion, for example, a recessed stepped portion.

[0047] Figure 9 is an image captured by an electron microscope schematically showing the interconnect shape after dry etching of the first seed metal layer and the shape of the concave portion formed in the insulating layer.

[0048] Referring to Figure 9, it can be seen that when the titanium (Ti) layer, which is the first seed metal layer, is removed by dry etching, undercut may not occur in the titanium (Ti) layer, and recesses can be formed in the insulating layer. In addition, it can be seen that surface roughness can be formed on the surface of the insulating layer in which the recesses are formed. Therefore, it can be seen that sufficient width can be ensured in the lower part of the interconnect line, and the above-described technical effects can be achieved accordingly. In addition, it can be seen that the adhesion between the insulating layers can be improved.

[0049] Figure 10 is a cross-sectional view schematically showing another example of a printed circuit board.

[0050] Referring to Figure 10 , according to another exemplary embodiment, a printed circuit board 500B may include: a first insulating layer 110; a plurality of first metal patterns 120 disposed on an upper surface (i.e., a first surface) of the first insulating layer 110; a plurality of second metal patterns 220 disposed below the first insulating layer 110 (e.g., disposed on a lower surface (i.e., a second surface) of the first insulating layer 110 or in a lower surface of the first insulating layer 110); at least one first via pattern 130 filling at least one via hole V that penetrates a region between an upper surface and a lower surface of the first insulating layer 110 and between at least a part of the plurality of first metal patterns 120 and at least a part of the plurality of second metal patterns 220; a second insulating layer 210 disposed on the upper surface of the first insulating layer 110 and covering at least a part of each of the plurality of first metal patterns 120; a plurality of third metal patterns 320 disposed on an upper surface (i.e., a third surface) of the second insulating layer 210; and at least one second via pattern 330 penetrating a region between an upper surface and a lower surface of the second insulating layer 210 and between at least a part of each of the plurality of first metal patterns 120 and at least a part of each of the plurality of third metal patterns 320.

[0051] In addition, each of the plurality of first metal patterns 120 may include: a first seed metal layer 121 disposed on the first insulating layer 110; a second seed metal layer 122 disposed on the first seed metal layer 121; and a first metal pattern layer 123 disposed on the second seed metal layer 122. The first via pattern 130 may include: a third seed metal layer 131 disposed on the wall surface of the via hole V and at least a part of the plurality of second metal patterns 220; a fourth seed metal layer 132 disposed on the third seed metal layer 131; and a second metal pattern layer 133 disposed on the fourth seed metal layer 132 and filling a part of the via hole V. In addition, the third seed metal layer 131 may be in contact with one of the plurality of second metal patterns 220. In addition, the third seed metal layer 131, the fourth seed metal layer 132, and the second metal pattern layer 133 may be sequentially stacked on one of the plurality of second metal patterns 220. In addition, another of the plurality of second metal patterns 220 may be stacked on two adjacent ones of the plurality of first metal patterns 120. The first seed metal layer 121 and the third seed metal layer 131 may be the same layer formed together (e.g., by a deposition process or the like), the second seed metal layer 122 and the fourth seed metal layer 132 may be the same layer formed together (e.g., by a deposition process or the like), and the first metal pattern layer 123 and the second metal pattern layer 133 may be the same layer formed together (e.g., by a plating process or the like). For example, the same layer may include the same metal and may be integrated with each other without a boundary.

[0052] As described above, the printed circuit board 500B according to another exemplary embodiment may be a multi-layer circuit board, and the inner layer of the multi-layer circuit board may include the insulating layer 110, the plurality of metal patterns 120, and the recess R of the printed circuit board 500A according to the above exemplary embodiment. For example, the structure of the printed circuit board 500A according to the above exemplary embodiment may be applied as an inner layer of a multi-layer circuit board such as the printed circuit board 500B according to another exemplary embodiment. However, the present disclosure is not limited thereto, and the structure of the printed circuit board 500A may be applied as an outer layer of the multi-layer circuit board, or may be applied as both the inner layer and the outer layer. On the other hand, the printed circuit board 500B according to another exemplary embodiment may be formed with more layers, and may include, for example, a larger number of insulating layers, metal pattern layers, and via pattern layers. In addition, the structure of the printed circuit board 500A according to the above exemplary embodiment may be freely applied as the inner layer and the outer layer according to the design. In addition, if necessary, the structure of the printed circuit board 500A according to the above exemplary embodiment may be partially introduced only in the portions where the interconnections need to be connected. The printed circuit board 500B according to another exemplary embodiment of the multi-layer circuit board structure may be used as a flip chip board (FCB), a ball grid array (BGA) board, an interposer, a package board, an interconnect bridge board, etc. However, the present disclosure is not limited thereto, and the printed circuit board 500B according to another exemplary embodiment may be applied to various other types of boards.

[0053] Hereinafter, the components of the printed circuit board 500B according to another exemplary embodiment will be described in more detail with reference to the drawings.

[0054] Each of the first insulating layer 110 and the second insulating layer 210 may include an organic insulating material. The organic insulating material may include a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as a polyimide), or a material prepared by impregnating an inorganic filler, an organic filler, and / or glass fiber (for example, a glass fabric such as a glass cloth) in the resin. For example, the organic insulating material may be a non-photosensitive insulating material such as an Ajinomoto build-up film (ABF) or a prepreg (PPG), or may be a photosensitive insulating material such as a photosensitive dielectric (PID), but the present disclosure is not limited thereto. If necessary, each of the first insulating layer 110 and the second insulating layer 210 may include an inorganic insulating material including SiO2 and Si3N4. The first insulating layer 110 and the second insulating layer 210 may include the same insulating material, and if necessary, the first insulating layer 110 and the second insulating layer 210 may be integrated with each other without a boundary. However, the present disclosure is not limited thereto, and the first insulating layer 110 and the second insulating layer 210 may include different insulating materials and may have a distinct boundary.

[0055] Each of the first metal pattern 120, the second metal pattern 220, and the third metal pattern 320 may include a metal. Examples of the metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or their alloys. Each of the first metal pattern 120, the second metal pattern 220, and the third metal pattern 320 may perform various functions according to the design. For example, each of the first metal pattern 120, the second metal pattern 220, and the third metal pattern 320 may include a signal pattern, a power pattern, and a ground pattern. Each of these patterns may have various forms such as a line, a plane, and a pad. Each of the second metal pattern 220 and the third metal pattern 320 may be formed by a plating process using a semi-additive process (SAP), a modified semi-additive process (MSAP), a through-hole (TT) method, etc., and each of the second metal pattern 220 and the third metal pattern 320 may include, for example, an electroless plating layer and an electrolytic plating layer, but the present disclosure is not limited thereto. If necessary, each of the second metal pattern 220 and the third metal pattern 320 may include a sputtering layer instead of an electroless plating layer, or may include both a sputtering layer and an electroless plating layer.

[0056] The plurality of first metal patterns 120 may be circuit patterns finer than each of the plurality of second metal patterns 220 and the plurality of third metal patterns 320. For example, the line width and the gap of the line pattern in the plurality of first metal patterns 120 may be smaller than the line width and the gap of the line pattern in the plurality of second metal patterns 220, and may be smaller than the line width and the gap of the line pattern in the plurality of third metal patterns 320. In addition, the pitch of the pad pattern in the plurality of first metal patterns 120 may be smaller than the pitch of the pad pattern in the plurality of second metal patterns 220, and may be smaller than the pitch of the pad pattern in the plurality of third metal patterns 320. For example, compared with the patterns included in each of the plurality of second metal patterns 220 and the plurality of third metal patterns 320, the plurality of first metal patterns 120 may include patterns with a higher density.

[0057] Each of the first via pattern 130 and the second via pattern 330 may include a metal. Examples of the metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or their alloys. Each of the first via pattern 130 and the second via pattern 330 may include a filled via filling a via hole, and may include a conformal via disposed along a wall surface of the via hole. Each of the first via pattern 130 and the second via pattern 330 may perform various functions according to a design. For example, each of the first via pattern 130 and the second via pattern 330 may include a ground via, a power via, and a signal via. In a cross section, each of the first via pattern 130 and the second via pattern 330 may have a shape tapered in the same direction. For example, in respective cross sections, a width of an upper end of each of the first via pattern 130 and the second via pattern 330 may be larger than a width of a lower end of each of the first via pattern 130 and the second via pattern 330. The second via pattern 330 may be formed by a plating process using a semi-additive process (SAP), a modified semi-additive process (MSAP), a through-hole (TT) method, etc., and the second via pattern 330 may include, for example, an electroless plating layer and an electrolytic plating layer, but the present disclosure is not limited thereto, and each of the first via pattern 130 and the second via pattern 330 may include a sputtering layer instead of an electroless plating layer, or may include both a sputtering layer and an electroless plating layer.

[0058] The first seed metal layer 121 and the third seed metal layer 131 may increase adhesion between the first insulating layer 110 and the first metal pattern 120 and adhesion between the first insulating layer 110 and the first via pattern 130, respectively. The first seed metal layer 121 and the third seed metal layer 131 may include the same metal, for example, titanium (Ti). For example, the first seed metal layer 121 and the third seed metal layer 131 may include pure titanium (pure Ti). Pure titanium (pure Ti) may mean including only titanium (Ti) (e.g., including 100% of titanium (Ti)), rather than including an alloy or an oxide containing titanium (Ti). For example, the first seed metal layer 121 and the third seed metal layer 131 may be formed together by a deposition process such as a sputtering process, and may use titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), etc. as its material, but considering dry etching, most preferably, titanium (Ti) may be used. However, the present disclosure is not limited thereto, and the first seed metal layer 121 and the third seed metal layer 131 may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or their alloys.

[0059] The second seed metal layer 122 and the fourth seed metal layer 132 may be provided for conductive regions for electroplating (or electrodeposition). The second seed metal layer 122 and the fourth seed metal layer 132 may be formed together by a deposition process such as a sputtering process, and in consideration of adhesion, conductivity, cost, etc. to metal pattern layers (such as the first metal pattern layer 123 and the second metal pattern layer 133), the second seed metal layer 122 and the fourth seed metal layer 132 may include copper (Cu). For example, the second seed metal layer 122 and the fourth seed metal layer 132 may include pure copper (Cu). Pure copper (Cu) may mean including only copper (Cu) (e.g., including 100% copper (Cu)), rather than including an alloy or oxide containing copper (Cu). However, the present disclosure is not limited thereto, and the second seed metal layer 122 and the fourth seed metal layer 132 may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or their alloys. The thickness of the second seed metal layer 122 may be greater than the thickness of the first seed metal layer 121. Similarly, the thickness of the fourth seed metal layer 132 may be greater than the thickness of the third seed metal layer 131.

[0060] The first metal pattern layer 123 and the second metal pattern layer 133 may substantially provide the functions of the metal pattern 120 and the first via pattern 130. The first metal pattern layer 123 and the second metal pattern layer 133 may be formed together by a plating process such as an electroplating (or electrodeposition) process, and in consideration of conductivity, cost, etc., the first metal pattern layer 123 and the second metal pattern layer 133 may include the same metal, for example, may include copper (Cu). For example, the first metal pattern layer 123 and the second metal pattern layer 133 may include pure copper (Cu). In addition, pure Cu may mean including only copper (Cu) (e.g., including 100% copper (Cu)), rather than including an alloy or oxide containing copper (Cu). However, the present disclosure is not limited thereto, and the first metal pattern layer 123 and the second metal pattern layer 133 may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or their alloys. The thickness of the first metal pattern layer 123 may be greater than the thickness of each of the first seed metal layer 121 and the second seed metal layer 122. The thickness of the second metal pattern layer 133 may be greater than the thickness of each of the third seed metal layer 131 and the fourth seed metal layer 132.

[0061] The bottom surface and the wall surface of the recess R may be substantially angled. For example, the recess R may have a substantially constant depth. For example, when surface roughness is not taken into account, each of the bottom surface and the wall surface of the recess R may be substantially flat. For example, the wall surface of the recess R may be substantially perpendicular to the bottom surface or may have an inclination close to vertical. For example, since the recess R may be formed in a process of removing a pure metal layer such as titanium (Ti) by dry etching, the recess R may have a substantially vertical shape rather than a rounded shape or the like, so that the recess R may have a larger area, thereby effectively improving the adhesion between the first insulating layer 110 and the second insulating layer 210. The depth of the recess R may be larger than the thickness of the first seed metal layer 121 (the thickness of the seed metal layer is exaggerated in the drawing).

[0062] The via hole V may be formed in the first insulating layer 110 before forming the first seed metal layer 121. For example, depending on the material of the first insulating layer 110, the via hole V may be formed using various methods such as mechanical drilling, laser processing, or chemical etching. The via hole V may be formed to penetrate the first insulating layer 110. When the first seed metal layer 121 is formed after forming the via hole V, the third seed metal layer 131 may be formed in the via hole V. In addition, when the second seed metal layer 122 is formed, the fourth seed metal layer 132 may be formed in the via hole V. In addition, when the first metal pattern layer 123 is formed, the second metal pattern layer 133 may be formed inside the via hole V.

[0063] Since other descriptions may be substantially the same as those described in the method of manufacturing the printed circuit board 500A according to the above exemplary embodiment and the printed circuit board 500A according to the exemplary embodiment, the repeated descriptions thereof will be omitted.

[0064] In the present disclosure, the expression "cover" may include the case of covering a part and the case of covering the whole, and may also include the cases of direct covering and indirect covering. In addition, the expression "fill" may include not only the case of complete filling but also the case of partial filling, or may include the case of substantially filling. For example, the expression "fill" may include the case where there are some pores or voids. In addition, the expression "surround" may include not only the case of complete surrounding but also the case of partial surrounding, or may include the case of substantially surrounding. In addition, the expression "adjacent" means that elements are disposed next to each other on substantially the same layer, and is not limited to the case where the elements are in contact with each other. In addition, exposure may include not only complete exposure but also partial exposure, and exposure may mean that an element is exposed from the corresponding component in which the element is buried.

[0065] In the present disclosure, "substantially" can be determined by including process errors or positional deviations that occur during the manufacturing process and errors during measurement. For example, substantially coplanar can include not only the case where components are present on exactly the same plane, but also the case where components are present on approximately the same plane.

[0066] In the present disclosure, the meaning of a cross-section can refer to the cross-sectional shape when an object is vertically cut or the shape when the object is observed from a side view perspective. In addition, the meaning of a plane can refer to the shape when an object is horizontally cut or the planar shape when the object is observed from a top view or bottom view perspective.

[0067] In the present disclosure, the lower side, lower part, and lower surface are used to represent the downward direction with respect to the cross-section of the drawing, and the upper side, upper part, and upper surface are used to represent the direction opposite to this downward direction. However, the above directions are defined for ease of explanation, and the scope of the claims is not particularly limited by the description of such directions, and the concepts of upper and lower can change at any time.

[0068] In the present disclosure, the meaning of "connected" includes not only direct connection but also the concept of indirect connection through an adhesive layer or the like. In addition, the meaning of "electrically connected" includes the concepts of both physical connection and non-physical connection. In addition, expressions such as "first" and "second" are used to distinguish one component from another component, and do not limit the order and / or importance of the components. In some cases, without departing from the scope of the claims, the first component can be referred to as the second component, or similarly, the second component can be referred to as the first component.

[0069] In the present disclosure, thickness, width, length, depth, line width, gap, pitch, angle, L (line width) / S (spacing), etc. can be measured using a scanning electron microscope or an optical microscope based on the cross-section obtained by polishing or cutting a printed circuit board. Even if not described in the present disclosure, other methods and / or tools understood by those of ordinary skill in the art can be used. The cross-section can be a vertical cross-section or a horizontal cross-section, and their respective values can be measured based on the required cross-section. For example, the width of the upper part and / or lower part of a via can be measured in a cross-section cut along the central axis of the via. In this case, when these values are not constant, these values can be determined as the values obtained by averaging the values measured at five arbitrary points. In addition, the minimum value can be determined as the minimum value measured on the corresponding layer or region.

[0070] The expression "exemplary embodiment" used in the present disclosure does not mean the same embodiment, but is provided to explain different unique features. However, the exemplary embodiments presented above do not preclude the combination with the features of other exemplary embodiments for implementation. For example, unless there is an interpretation contrary to or inconsistent with the matters in other exemplary embodiments, even if the matters described in a specific exemplary embodiment are not described in other exemplary embodiments, they can be understood as interpretations related to other exemplary embodiments.

[0071] The terms used in the present disclosure are only for describing exemplary embodiments and are not intended to limit the present disclosure. In this case, unless they are clearly stated otherwise in the context, the singular meaning includes the plural meaning.

[0072] Although the exemplary embodiments have been shown and described above, it will be readily understood by those skilled in the art that modifications and variations can be made without departing from the scope of the present disclosure defined by the appended claims.

Claims

1. A printed circuit board, comprising: a first insulating layer; as well as A plurality of first metal patterns are arranged on the first insulating layer, wherein the first insulating layer comprises at least one recess, The at least one recess is disposed between the plurality of first metal patterns, and Each of the plurality of first metal patterns includes: a first seed metal layer disposed on the first insulating layer; a second seed metal layer disposed on the first seed metal layer; and a first metal pattern layer disposed on the second seed metal layer.

2. The printed circuit board according to claim 1, in, The first seed metal layer includes Ti, The second seed metal layer includes Cu, and The first metal pattern layer includes Cu.

3. The printed circuit board according to claim 1, in, The plurality of first metal patterns are disposed on a first surface of the first insulating layer, and The first metal pattern layer is thicker than each of the first seed metal layer and the second seed metal layer.

4. The printed circuit board according to claim 3, in, The first insulating layer has a step portion between a first region of the first surface of the first insulating layer where the plurality of first metal patterns are disposed and a second region of the first surface of the first insulating layer where the at least one recess is disposed.

5. The printed circuit board according to claim 3, in, A surface roughness of a region of the first surface of the first insulating layer where the at least one recess is disposed is greater than a surface roughness of a region of the first surface of the first insulating layer where the plurality of first metal patterns are disposed.

6. The printed circuit board according to claim 3, in, The at least one recess penetrates a portion of the first insulating layer from a region of the first surface of the first insulating layer between the plurality of first metal patterns in a thickness direction.

7. The printed circuit board according to claim 3, further comprising: A plurality of second metal patterns are disposed on a second surface of the first insulating layer opposite to the first surface or in the second surface of the first insulating layer; at least one via pattern filling at least one via hole penetrating the first insulating layer in a region between the first surface and the second surface, wherein the region of the first insulating layer is between at least a portion of the plurality of first metal patterns and at least a portion of the plurality of second metal patterns, Wherein, the at least one via pattern comprises: a third seed metal layer disposed on a wall surface of the via hole and at least a portion of the plurality of second metal patterns; a fourth seed metal layer, disposed on the third seed metal layer; and A second metal pattern layer is disposed on the fourth seed metal layer and fills a portion of the via hole.

8. The printed circuit board according to claim 7, wherein: One of the plurality of second metal patterns contacts the third seed metal layer.

9. The printed circuit board according to claim 8, wherein: The third seed metal layer, the fourth seed metal layer, and the second metal pattern layer are sequentially stacked on the one second metal pattern.

10. The printed circuit board according to claim 7, wherein: Another second metal pattern among the plurality of second metal patterns overlaps adjacent two first metal patterns among the plurality of first metal patterns.

11. The printed circuit board according to claim 7, wherein: The first seed metal layer and the third seed metal layer are integrated with each other, the second seed metal layer and the fourth seed metal layer are integrated with each other, and the first metal pattern layer and the second metal pattern layer are integrated with each other.

12. The printed circuit board according to claim 3, further comprising: a second insulating layer disposed on the first surface of the first insulating layer and covering at least a portion of each of the plurality of first metal patterns; as well as A plurality of third metal patterns are disposed on the third surface of the second insulating layer.

13. The printed circuit board according to claim 1, wherein: The at least one recess has a bottom surface and a wall surface that are angled with each other.

14. The printed circuit board according to claim 13, wherein: The at least one recess has a constant depth.

15. The printed circuit board according to claim 1, wherein The plurality of first metal patterns include a plurality of micro circuit patterns having a line width of 5 μm or less and / or an interval of 5 μm or less.

16. A method for manufacturing a printed circuit board, comprising: forming a first seed metal layer on the insulating layer; forming a second seed metal layer on the first seed metal layer; forming a first metal pattern layer on the second seed metal layer; removing at least a portion of the second seed metal layer exposed from the first metal pattern layer; as well as removing at least a portion of the first seed metal layer exposed from the first metal pattern layer and the second seed metal layer, The step of removing the at least a portion of the first seed metal layer includes removing at least a portion of the insulating layer to form at least one recess.

17. The method for manufacturing a printed circuit board according to claim 16, in, The step of forming the first seed metal layer includes depositing Ti to form the first seed metal layer, The step of forming the second seed metal layer includes depositing Cu to form the second seed metal layer, and The step of forming the first metal pattern layer includes forming a resist layer having a plurality of openings on the second seed metal layer, filling the plurality of openings with Cu by plating, and then removing the resist layer to form the first metal pattern layer.

18. The method for manufacturing a printed circuit board according to claim 16, in, In the step of removing the at least a portion of the second seed metal layer, the at least a portion of the second seed metal layer is removed by wet etching, In the step of removing the at least a portion of the first seed metal layer, the at least a portion of the first seed metal layer is removed by dry etching, and The at least one recess is formed by the dry etching.

19. The method for manufacturing a printed circuit board according to claim 16, in, The step of removing at least a portion of the first seed metal layer makes the surface roughness of the insulating layer in a region where the at least one recess is formed greater than the surface roughness of the insulating layer in a region where the first metal pattern layer is formed.

20. The method for manufacturing a printed circuit board according to claim 16, further comprising: Before the step of forming the first seed metal layer, a via hole is formed penetrating the insulating layer, and A third seed metal layer, a fourth seed metal layer, and a second metal pattern layer are formed in the via hole, wherein the fourth seed metal layer is formed on the third seed metal layer and the second metal pattern layer is formed on the fourth seed metal layer.

21. The method for manufacturing a printed circuit board according to claim 20, wherein: The first seed metal layer and the third seed metal layer are the same layer formed together, the second seed metal layer and the fourth seed metal layer are the same layer formed together, and the first metal pattern layer and the second metal pattern layer are the same layer formed together.

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