Semiconductor unit structure

Abstract

The invention provides a semiconductor unit structure comprising a semiconductor substrate having an original semiconductor surface, the original semiconductor surface having a first set of active regions and a second set of active regions; the shallow trench isolation region surrounds the first group of active regions and the second group of active regions, and the group of PMOS transistors are arranged in the first group of active regions; the group of NMOS transistors are arranged in the second group of active regions; the VDD contact line is electrically connected to the group of PMOS transistors; the VSS contact line is electrically connected to the group of NMOS transistors; wherein the bottom surfaces of the source and drain regions of the PMOS and NMOS transistors are isolated from the semiconductor substrate by local insulating regions, the plurality of local insulating regions being located below the original semiconductor surface.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure, and more particularly to a static random-access memory (SRAM) cell or logic standard cell structure having a smaller component area and a higher current on / off ratio (I-on / I-off). Background Art

[0002] Improvements in integrated circuit performance and cost have been largely achieved by the process scaling technology of Moore's law. However, as the process size is scaled down to 28 nanometers (nm) (or lower), the variation in transistor performance in semiconductor manufacturing has become a major challenge. In particular, in order to implement a semiconductor cell structure with a larger capacity (e.g., an SRAM cell structure or other components), it has become increasingly difficult to scale down the semiconductor cell structure proportionally to increase the component storage density, reduce its operating voltage (VDD) to reduce standby power consumption, and at the same time increase its process yield.

[0003] SRAM components are one of the commonly used memory components. SRAM components typically include an SRAM cell array and peripheral circuits, and the peripheral circuits include a row address decoder, a column address decoder, and an input / output circuit, etc. The SRAM cell array contains multiple SRAM cells, and each SRAM cell contains a static latch, which has two cross-coupled inverters. Thus, as long as the SRAM cell has a sufficient voltage supply, i.e., a high voltage VDD and a low voltage VSS, it does not need to retain the stored information by periodic update like a dynamic random-access memory (DRAM). The high voltage VDD and the low voltage VSS are also connected to the peripheral circuits (decoder, I / O circuit) of the SRAM. In addition, the high voltage VDD usually corresponds to the stored logic "1" in the SRAM cell, and the low voltage VSS corresponds to the stored logic "0" in the SRAM cell.

[0004] Figure 1Shows an SRAM cell structure, namely a six-transistor (6-T) SRAM cell. It consists of two sets of cross-coupled inverters (one set of PMOS pull-up transistors PU-1 and PU-2 and one set of NMOS pull-down transistors PD-1 and PD-2) and two access transistors (NMOS transmission gate transistors PG-1 and PG-2). The high-level voltage VDD is connected to the PMOS pull-up transistors PU-1 and PU-2, and the low-level voltage VSS is connected to the NMOS pull-down transistors PD-1 and PD-2. When the word line (WL) is enabled (i.e., a particular row in the array is selected), the access transistors are turned on, and the storage nodes Node-1 / Node-2 are connected to the vertically running bit lines (BL and BL Bar).

[0005] Figure 2 Is a "stick diagram" showing the layout and connection between the six transistors of the SRAM cell structure. The stick diagram typically only includes the active regions (vertical red lines) and the gate lines (horizontal blue lines). Of course, there are also many contacts, which are directly connected to the six transistors on one hand and to the word line W, bit lines BL and BL Bar, high-level voltage VDD, low-level voltage VSS, etc. on the other hand.

[0006] However, even when the process dimension (the so-called "minimum feature size", "λ" or "F") is scaled down to 28 nm or lower, due to the interference between the contact structure sizes among the metal wire layouts such as the word line WL, bit lines BL and BL Bar, high-level voltage VDD and low-level voltage VSS, etc., the total area of the SRAM cell (represented by λ 2 or F 2 indicates) still increases significantly when the minimum feature size is reduced, as shown in Figure 3 shown. Therefore, how to redesign the SRAM cell so that when the minimum feature size is reduced, the total area of the SRAM cell represented by λ 2 can be maintained within an acceptable range has become a challenge. Summary of the Invention

[0007] An object of the present invention is to provide a semiconductor cell structure, which includes a semiconductor substrate having an original semiconductor surface, a shallow trench isolation (STI) region, a group of PMOS transistors, a group of NMOS transistors, a VDD contact line, and a VSS contact line. Among them, the semiconductor substrate includes a first group of active regions and a second group of active regions. The shallow trench isolation region surrounds the first group of active regions and the second group of active regions. This group of PMOS transistors are respectively disposed in the first group of active regions. Each PMOS transistor includes a source region, a drain region, a gate structure, a PMOS body region, and a channel region located in the PMOS body region. This group of NMOS transistors are respectively disposed in the second group of active regions. Each NMOS transistor includes a source region, a drain region, a gate structure, an NMOS body region, and a channel region located in the NMOS body region. The VDD contact line is electrically connected to this group of PMOS transistors. The VSS contact line is electrically connected to this group of NMOS transistors. The bottom surface of the source region of each PMOS transistor is isolated from the semiconductor substrate by a first local insulation region, and the bottom surface of the drain region of each PMOS transistor is isolated from the semiconductor substrate by a second local insulation region. And the first local insulation region and the second local insulation region are disposed below the original semiconductor surface; the bottom surface of the source region of each NMOS transistor is isolated from the semiconductor substrate by a third local insulation region, and the bottom surface of the drain region of each NMOS transistor is isolated from the semiconductor substrate by a fourth local insulation region, and the third local insulation region and the fourth local insulation region are disposed below the original semiconductor surface.

[0008] According to an embodiment of the present specification, each PMOS body region or each NMOS body region is completely isolated from the semiconductor substrate by a local isolation region.

[0009] According to an embodiment of the present specification, the top surface of the shallow trench isolation region is higher than the original semiconductor surface, and the shallow trench isolation region surrounds the first, second, third, and / or fourth local insulation regions.

[0010] According to an embodiment of the present specification, each local insulation region in the first, second, third, and / or fourth local insulation regions includes an L-shaped insulation region located in a recess below the original semiconductor surface.

[0011] According to an embodiment of the present specification, the source region of the first NMOS transistor is in electrical contact with the channel region of the first NMOS transistor. The source region of the first NMOS transistor is located in the recess and includes an epitaxial lightly doped drain (LDD) region laterally extending from the channel region of the first NMOS transistor and an epitaxial heavily doped region laterally extending from the epitaxial lightly doped drain region.

[0012] According to an embodiment of the present specification, a metal region is disposed within the shallow trench isolation region and the gate structure of the first NMOS transistor, and the metal region contacts the top surface and the most lateral sidewalls of the source region of the first NMOS transistor.

[0013] According to an embodiment of the present specification, a VDD contact line or a VSS contact line is disposed below the original semiconductor surface.

[0014] According to an embodiment of the present specification, the VDD contact line is electrically connected to the first PMOS transistor in this group of PMOS transistors through a contact plug disposed in one of the first group of active regions, and the sidewall of the contact plug directly contacts the sidewall of the VDD contact line. Alternatively, the VSS contact line is electrically connected to the first NMOS transistor in this group of NMOS transistors through a contact plug disposed in one of the second group of active regions, and the sidewall of the contact plug directly contacts the sidewall of the VSS contact line.

[0015] According to an embodiment of the present specification, this semiconductor cell structure further includes a heat dissipation layer disposed within the shallow trench isolation region and below the original semiconductor surface, wherein the thermal conductivity of the heat dissipation layer is higher than that of silicon (Si).

[0016] According to an embodiment of the present specification, the heat dissipation layer surrounds the first group of active regions and / or the second group of active regions.

[0017] According to an embodiment of the present specification, the heat dissipation layer extends from a position close to the first group of active regions or the second group of active regions to another position close to the edge of the semiconductor substrate.

[0018] According to an embodiment of the present specification, the first PMOS transistor in this group of PMOS transistors or the first NMOS transistor in this group of NMOS transistors includes a protruding semiconductor structure having at least one trench therein. This protruding semiconductor structure includes a group of thin semiconductor bodies separated from each other, and there is no shallow trench isolation region between any two adjacent thin semiconductor bodies.

[0019] According to an embodiment of the present specification, the gate electrode pitch between two NMOS transistors in this group of NMOS transistors is determined by the width of a dielectric layer inserted therein.

[0020] According to an embodiment of the present specification, this semiconductor cell structure is a SRAM cell, and this SRAM cell further includes: a word line electrically connected to this group of NMOS transistors; a bit line and a complementary bit line electrically connected to this group of NMOS transistors; wherein, when the process node λ is 16 nm, the cell area of the SRAM cell is between 105 and 216λ 2 ; or when the process node λ is 10 nm, the cell area of the SRAM cell is between 166 and 299λ 2Between. Or when the process node λ is 7 nm, the cell area of the SRAM cell is between 271 and 451λ 2 Between; or when the process node λ is 5 nm, the cell area of the SRAM cell is between 432 and 657λ 2 Between; or when the process node λ is 3 nm, the cell area of the SRAM cell is between 1005 and 1588λ 2 Between.

[0021] Another object of the present invention is to provide a semiconductor cell structure, which includes a semiconductor substrate having an original semiconductor surface, shallow trench isolation regions, a group of transistors, VDD contact lines, and / or VSS contact lines. Among them, the semiconductor substrate includes a group of active regions. The shallow trench isolation regions surround this group of active regions. This group of transistors is disposed within this group of active regions. Each transistor includes a first epitaxial region, a second epitaxial region, and a gate structure located between the first epitaxial region and the second epitaxial region. The VDD contact lines and the VSS contact lines are electrically connected to this group of transistors. Among them, this group of transistors includes a first transistor and a second transistor adjacent to each other. The first epitaxial region of the first transistor extends along a first direction. The first epitaxial region of the second transistor extends along the first direction. The first epitaxial region of the first transistor has a first end face, and the first epitaxial region of the second transistor has a second end face facing the first end face. The first end face is parallel or substantially parallel to the second end face.

[0022] According to an embodiment of the present specification, both the first end face and the second end face are perpendicular or substantially perpendicular to the original semiconductor surface.

[0023] According to an embodiment of the present specification, the top surface of the shallow trench isolation region is higher than the original semiconductor surface and surrounds three sides of the first epitaxial region of the first transistor and three sides of the first epitaxial region of the second transistor. Description of the Drawings

[0024] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention is provided in conjunction with the accompanying drawings, where:

[0025] Figure 1 is a schematic diagram showing a conventional 6T SRAM cell according to the prior art;

[0026] Figure 2 is shown corresponding to Figure 1 The layout and connection "bar graph" of the 6T SRAM cell shown, where the active region corresponds to a vertical line and the gate line corresponds to a horizontal line;

[0027] Figure 3 is the total area λ of the SRAM cell shown at different process dimensions λ (or F) according to the prior art process2 (or denoted by F 2 );

[0028] Figure 4 is a structural cross-sectional view showing the latching distance between NMOS transistors and PMOS transistors in a conventional 6T SRAM cell;

[0029] Figure 5(a) is a top view of the structure of a miniaturized metal oxide semiconductor field effect transistor (mMOSFET) used for an SRAM cell structure according to an embodiment of the present specification;

[0030] Figures 5(b) to 5(g) are structural cross-sectional views showing a series of manufacturing processes for forming the mMOSFET shown in Figure 5(a);

[0031] Figure 5(h) is a top view of the structure of the mMOSFET shown in Figure 5(g);

[0032] Figure 6(a) is a top view of a combined structure of PMOS transistors and NMOS transistors used in an SRAM cell structure according to an embodiment of the present invention;

[0033] Figure 6(b) is a structural cross-sectional view of the PMOS transistor shown along the tangent 1 (X-axis) of Figure 6(a);

[0034] Figure 6(c) is a structural cross-sectional view of the NMOS transistor shown along the tangent 2 (X-axis) of Figure 6(a);

[0035] Figure 6(d) is a structural cross-sectional view of the PMOS transistor and the NMOS transistor shown along the tangent 3 (Y-axis) of Figure 6(a);

[0036] Figure 6(e) is a structural cross-sectional view showing a known complementary metal oxide semiconductor (CMOS) transistor combining PMOS transistors and NMOS transistors;

[0037] Figure 6(f) is a top view of another combined structure of PMOS transistors and NMOS transistors used in an SRAM cell structure according to another embodiment of the present specification;

[0038] Figure 6(g) is a schematic cross-sectional view of the combined structure shown along the tangent (X-axis) of Figure 6(f);

[0039] Figures 7(a) to 7(d) are schematic cross-sectional views of a series of process structures for forming an NMOS transistor in an SRAM cell structure according to an embodiment of the present specification;

[0040] Figure 7(e) is a perspective view of the NMOS transistor structure shown in Figure 7(d);

[0041] Figure 8 is a perspective view of a fin field-effect transistor (FinFET) for an SRAM cell structure according to an embodiment of the present specification;

[0042] In Figure 9A , (a) is a top view of a temporary structure after forming a shallow trench isolation region; (b) is a cross-sectional view of the structure shown along the tangent Y-cut shown in (a); (c) is a cross-sectional view of the structure shown along the tangent X-cut shown in (a);

[0043] In Figure 9B , (a) is a top view of a process structure after forming a SOD material and a photoresist layer; (b) is a cross-sectional view of the structure shown along the tangent Y-cut shown in (a); (c) is a cross-sectional view of the structure shown along the tangent X-cut shown in (a);

[0044] In Figure 9C , (a) is a top view of a process structure after forming a narrow trench; (b) is a cross-sectional view of the structure shown along the tangent Y-cut shown in (a); (c) is a cross-sectional view of the structure shown along the tangent X-cut shown in (a);

[0045] In Figure 9D , (a) is a top view of a process structure after forming a silicon oxynitride carbon (SiOCN) material; (b) is a cross-sectional view of the structure shown along the tangent Y-cut shown in (a); (c) is a cross-sectional view of the structure shown along the tangent X-cut shown in (a);

[0046] In Figure 9E , (a) is a top view of a process structure after forming a silicon nitride (SiN) layer and a high density plasma (HDP) silicon oxide layer 914; (b) is a cross-sectional view of the structure shown along the tangent Y shown in (a); (c) is a cross-sectional view of the structure shown along the tangent X-cut shown in (a);

[0047] Figure 9Fis a CMOS perspective view showing a structure having an embedded underground bit line (UGBL), where the UGBL is defined by all insulators and is connected to the drain region by self-aligned vertical interconnects;

[0048] In Figure 10A , (a) is a top view of the process structure after forming the recess; (b) is a cross-sectional view of the structure taken along the X-axis direction parallel to that shown in (a); (c) is a cross-sectional view of the structure taken along the Y-axis direction parallel to that shown in (a);

[0049] In Figure 10B , (a) is a top view of the process structure after forming the silicon nitride cover layer; (b) is a cross-sectional view of the structure taken along the X-axis direction parallel to that shown in (a); (c) is a cross-sectional view of the structure taken along the Y-axis direction parallel to that shown in (a);

[0050] In Figure 10C , (a) is a top view of the process structure after the shallow trench isolation region is etched downward; (b) is a cross-sectional view of the structure taken along the X-axis direction parallel to that shown in (a); (c) is a cross-sectional view of the structure taken along the Y-axis direction parallel to that shown in (a);

[0051] In Figure 10D , (a) is a top view of the process structure after forming the conductive center pillar; (b) is a cross-sectional view of the structure taken along the X-axis direction parallel to that shown in (a); (c) is a cross-sectional view of the structure taken along the Y-axis direction parallel to that shown in (a);

[0052] In Figure 10E , (a) is a top view of the process structure after forming the silicon oxide spacer and the silicon nitride spacer; (b) is a cross-sectional view of the structure taken along the X-axis direction parallel to that shown in (a);

[0053] In Figure 10F , (a) is a top view of the process structure after etching away a part of the silicon oxide layer to expose the silicon sidewalls; (b) is a cross-sectional view of the structure taken along the X-axis direction parallel to that shown in (a);

[0054] In Figure 10G , (a) is a top view of a structure of a vertical thin body field-effect transistor (VTBFET) for an SRAM cell according to an embodiment of the present specification; (b) is a cross-sectional view of the vertical thin body field-effect transistor taken along the X-axis direction parallel to that shown in (a);

[0055] Figures 11A(1) to Figure 11HAccording to an embodiment of the present specification, a series of process structure cross-sectional diagrams for forming a FinFET in an SRAM cell are shown;

[0056] Figures 12A to 12F shows the use of Figure 8 the shown FinFET to form a layout bar chart in a series of processes for forming a novel 6T SRAM structure;

[0057] Figures 13A to 13H is a layout bar chart in a series of processes for forming a novel 6T SRAM structure using the NMOS transistor shown in FIG. 7(e);

[0058] Figures 14A to 14D is a layout bar chart in a series of processes for forming a novel inverter unit using the FinFET and NMOS transistor provided in the above embodiment; and

[0059] Figures 15A to 15E According to another embodiment of the present specification, a layout bar chart in a series of processes for forming another novel inverter unit is shown.

[0060] Reference numerals:

[0061] 40: 6T SRAM cell structure

[0062] 44N: NMOS transistor

[0063] 44P: PMOS transistor

[0064] 500: mMOSFET

[0065] 501: p-type substrate

[0066] 502: Shallow trench isolation region

[0067] 503: Spin-on dielectric layer

[0068] 505A: Shallow trench isolation silicon oxide

[0069] 505B: Silicon oxide layer

[0070] 505O: Opening

[0071] 506D: Drain region

[0072] 506S: Source region

[0073] 507: Spacer

[0074] 508: Spacer

[0075] 509G: Contact hole opening

[0076] 509S: Contact Hole Opening

[0077] 509D: Contact Hole Opening

[0078] 510: Gate Structure

[0079] 510N: Silicon Nitride Layer

[0080] 510E: Gate Extension Region

[0081] 511: Intrinsic Silicon Electrode

[0082] 512: Spin-on Dielectric Material Layer

[0083] 513: First Metal Layer

[0084] 514: Spacer

[0085] 5021: Dielectric Insulator

[0086] 61: NMOS Transistor

[0087] 62: PMOS Transistor

[0088] 63: Gate Structure

[0089] 64: Spacer

[0090] 65: Source Region

[0091] 66: Drain Region

[0092] 68: Local Isolation Region

[0093] 601: Silicon Substrate

[0094] 611E: Edge Surface

[0095] 621E: Edge Surface

[0096] 631: Gate Dielectric Layer

[0097] 632: Gate Conductive Layer

[0098] 633: Dielectric Capping Layer

[0099] 641: Silicon Oxide Layer

[0100] 642: Silicon Nitride Layer Composite

[0101] 651: Lightly Doped Drain Region

[0102] 652: P+ Heavily Doped Region

[0103] 653: Tungsten Plug

[0104] 681: Oxide-3V Layer

[0105] 682: Oxide-3B layer

[0106] 683: Silicon nitride layer

[0107] 691: STI-1 layer

[0108] 692: STI-2 layer

[0109] 700: NMOS transistor

[0110] 701: Semiconductor substrate

[0111] 701A: Trench

[0112] 701B: Trench

[0113] 701S: Semiconductor surface

[0114] 701W1: Partial silicon sidewall

[0115] 701W2: Partial silicon sidewall

[0116] 702: Shallow and deep trench isolation structure

[0117] 702A: Silicon oxide layer

[0118] 702B: Silicon oxide layer

[0119] 703: Dielectric insulator

[0120] 704: Gate structure

[0121] 704A: Gate layer

[0122] 704B: Silicon nitride layer

[0123] 705A: Spacer

[0124] 705B: Spacer

[0125] 706: n-type lightly doped drain region

[0126] 707A: First recess

[0127] 707B: Second recess

[0128] 708A: First protective isolation layer

[0129] 708B: Second protective isolation layer

[0130] 709: Metal layer

[0131] 710A: First semiconductor region

[0132] 710B: Second semiconductor region

[0133] 710E1: Edge surface

[0134] 710E2: Edge surface

[0135] 710E3: Edge surface

[0136] 710E4: Edge surface

[0137] 711A: First metal-containing region

[0138] 711B: Second metal-containing region

[0139] 653 Metal material

[0140] 800: Fin field-effect / fully-depleted gate transistor

[0141] 801: Semiconductor substrate

[0142] 801F: Superlattice structure

[0143] 804: Gate structure

[0144] 808: Protection isolation layer

[0145] 810A: n-type lightly doped drain region

[0146] 810B: n-type lightly doped semiconductor region

[0147] 811A: Heavily doped semiconductor region

[0148] 811B: Heavily doped semiconductor region

[0149] 900: Semiconductor circuit

[0150] 901: Semiconductor substrate

[0151] 901A: Active region

[0152] 902: Pad silicon oxide layer

[0153] 903: Pad silicon nitride layer

[0154] 904: Shallow trench isolation region

[0155] 905: Silicon oxide

[0156] 906: Spin-on dielectric material

[0157] 907: Photoresist layer

[0158] 908: Narrow trench

[0159] 910: Silicon carbonitride

[0160] 911 Titanium nitride layer

[0161] 912: Tungsten layer

[0162] 913: Lower internal connection

[0163] 916: Vertical internal connection

[0164] 915: Drain region

[0165] 925: Source region

[0166] 1000: Vertical thin body field effect transistor

[0167] 1001: Semiconductor substrate

[0168] 1001A: Active region

[0169] 1001R: Vertical thin body

[0170] 1001F: Vertical thin body

[0171] 1002: Pad silicon oxide layer

[0172] 1003: Silicon oxide spacer

[0173] 1004: Pad nitride layer

[0174] 1005: Nitride spacer

[0175] 1006: Shallow trench isolation region

[0176] 1007: Thin nitride layer

[0177] 1008: Lithography photoresist mask

[0178] 1009: Recess

[0179] 1010: Spacer

[0180] 1011: Recess

[0181] 1012: Central pillar

[0182] 1013: Nitride capping layer

[0183] 1014: Trench

[0184] 1015: Gate dielectric material

[0185] 1016: Gate conductive material

[0186] 1016P: Conductive central pillar

[0187] 1017A: Nitride layer

[0188] 1017B: Hard mask silicon oxide layer

[0189] 1018A: Silicon oxide spacer

[0190] 1018B: Silicon nitride spacer

[0191] 1019: Shallow trench

[0192] 1020: Silicon oxide layer

[0193] 1020V: Silicon oxide layer on the vertical sidewall of the shallow trench

[0194] 1020L: Silicon oxide layer above the bottom of the shallow trench

[0195] 1021: Silicon nitride layer

[0196] 1022: Metal layer

[0197] 1022A: Tungsten layer

[0198] 1022B: Titanium nitride layer

[0199] 1023S: Lightly doped drain region

[0200] 1023D: Lightly doped drain region

[0201] 1024S: Heavily doped source region

[0202] 1024B: Heavily doped drain region

[0203] 1025: Metal contact structure

[0204] 1025A: Titanium nitride layer

[0205] 1025B: Tungsten layer

[0206] 1026: Landing pad

[0207] 1100: Transistor structure

[0208] 1101: Semiconductor substrate

[0209] 1101T: Trench

[0210] 1101F1: Fin structure

[0211] 1101F2: Fin structure

[0212] 1102: Gate opening

[0213] 1103: Epitaxial semiconductor material 1104: Gate structure

[0214] 1104O: Gate dielectric layer

[0215] 1104S: Gate electrode

[0216] 1105: Gate structure

[0217] 1105S: Gate electrode

[0218] 1105O: Gate dielectric layer

[0219] 1107: Spacer

[0220] 1107A: Silicon oxide spacer 1107B: Silicon nitride spacer 1110B: Pad silicon nitride layer

[0221] 1108: Shallow trench isolation region

[0222] 1109: Dielectric capping layer

[0223] 1110A: Pad silicon oxide layer

[0224] 1106: Inserted dielectric layer

[0225] 1113: Local isolation region

[0226] 1123: Local isolation region

[0227] 1111A: Lightly doped drain region 1111: Source region

[0228] 1111B: N+ semiconductor region 1111C: Landing pad 1112A: Lightly doped drain region (1112: Drain region

[0229] 1112B: N+ semiconductor region 1112C: Landing pad

[0230] T111: MOS transistor

[0231] T112: MOS transistor

[0232] HSS: Original horizontal surface

[0233] OHS: Original horizontal surface

[0234] C-S(L:): Opening length

[0235] C-S(W): Opening width

[0236] C-D(L:): Opening length

[0237] C-D(W): Opening width

[0238] S(L): Length

[0239] S(W): Width

[0240] G(L): Length

[0241] G(W): Width

[0242] VDD: High voltage

[0243] VSS: Low voltage

[0244] PU-1: Pull-up transistor

[0245] PU-2: Pull-up transistor

[0246] PU: Pull-up transistor

[0247] PD-1: Pull-down transistor

[0248] PD-2: Pull-down transistor

[0249] Node-1: Storage node

[0250] Node-2: Storage node

[0251] PG: Transmission gate transistor

[0252] PG-1: Transmission gate transistor

[0253] PG-2: Transmission gate transistor

[0254] W: Word line

[0255] BL: Bit line

[0256] BL Bar: Bit line

[0257] TG1-TG3: True gate

[0258] DSG: Virtual shield gate TEC: Vertical boundary

[0259] Xn: Edge distance

[0260] Xp: Edge distance

[0261] Y-cut: Tangent line

[0262] X-cut: Tangent line

[0263] ①, ②, ③, ④, ⑤, ⑥, ⑦, ⑧: Length

[0264] d, e, f, g: Length

[0265] C11A1: Tangent line

[0266] C11A2: Tangent line

[0267] C11B1: Tangent line

[0268] C11B2: Tangent line

[0269] C11C1: Tangent line

[0270] C11C2: Tangent line

[0271] C11BD1: Tangent line

[0272] C11BE1: Tangent line

[0273] C11BF1: Tangent line

[0274] C11G1: Tangent line

[0275] C11G2: Tangent line

[0276] D4: Distance

[0277] P: Gate electrode spacing Detailed implementation manners

[0278] This specification provides an SRAM cell structure with a relatively small component area and a high current on-off ratio (I-on / I-off). Through the detailed description of the following preferred exemplary embodiments, the above and other aspects of this specification can be better understood. The following will be described in conjunction with the accompanying drawings:

[0279] Only several embodiments of this specification are publicly disclosed in conjunction with the accompanying drawings below. However, the structures and contents disclosed in the embodiments are only for illustration and explanation. The protection scope of this invention specification is not limited to the contents of the disclosed embodiments. It should be noted that the specification does not illustrate all possible embodiments. Any person with ordinary knowledge in the technical field to which this invention pertains can make appropriate modifications or changes based on the content of the following disclosed specification to meet actual needs. However, such modifications or changes do not depart from the spirit scope of this invention. The scope of this invention still extends to other implementation manners not publicly disclosed in the specification.

[0280] The present invention discloses a new SRAM cell structure, including a set of PMOS transistors and a set of NMOS transistors disposed in a bulk semiconductor substrate (e.g., an SRAM cell structure with six-transistor CMOS formed in a bulk wafer substrate). The PMOS / NMOS transistors have selective localized underground insulator layers (e.g., a silicon oxide layer) for isolating the diffusion regions (including source and drain regions) and / or the body regions (i.e., the semiconductor body regions under the transistor channels) of the PMOS / NMOS transistors. In addition, in one embodiment, the body region of the PMOS transistor is isolated from the body substrate through a local isolation region, but the body region of the NMOS transistor is not isolated from the body substrate (or vice versa). The embodiments disclosed below are several designs of NMOS / PMOS transistors for forming an SRAM cell structure, which can reduce the cell area of the SRAM cell structure, thereby improving performance and significantly reducing power consumption. It is applicable to stand-alone SRAM components and embedded SRAM components used in logic or system-on-chip (SOC) designs.

[0281] Example 1 (NuCMOS transistor - minimum size and raised shallow trench isolation)

[0282] This embodiment discloses an mMOSFET 500 for an SRAM cell structure, which is particularly suitable for a 6T SRAM cell structure. The stacked isolation region formed by the self-alignment technology can precisely control the size of the component. At the same time, with the help of the local isolation region under the source / drain regions of the transistor, the distance from the n+ region of the NMOS transistor to the p+ region of the PMOS transistor between two adjacent transistor components is reduced, and the latch-up problem can still be avoided without increasing the size of the SRAM cell structure.

[0283] Figure 4 It is a schematic cross-sectional view showing the structures of the NMOS transistor 44N and the PMOS transistor 44P in the conventional 6T SRAM cell structure 40. In the conventional 6T SRAM cell structure 40, at least one NMOS transistor 44N and one PMOS transistor 44P are respectively located in some adjacent regions of the p substrate 401 and the n-type well region. These regions are adjacent to each other, forming a parasitic junction structure called an n+ / p / n / p+ parasitic bipolar component, whose profile starts from the n+ region of the NMOS transistor 44N, goes to the p-type well region, then to the adjacent n-type well region, and further reaches the p+ region of the PMOS transistor 44P (as Figure 4As shown). The n+ / p junction or p+ / n junction generates significant noise, and an abnormally large current flows abnormally through the n+ / p / n / p+ junction, which may shut down some operations of the CMOS circuit and cause overall chip failure. This abnormal phenomenon called latch-up is harmful to the operation of CMOS transistors and must be avoided. One way to increase the immunity of CMOS transistors to this weakness of latch-up is to increase the distance from the n+ region to the p+ region. However, increasing the distance from the n+ region to the p+ region to avoid the latch-up problem will increase the size of the SRAM cell structure 40.

[0284] Figure 5(a) is a top view of the structure of an mMOSFET 500 for an SRAM cell structure according to an embodiment of the present specification. As shown in Figure 5(a), the mMOSFET 500 includes: (1) a gate structure 510 having a length G(L), a width G(W), and a gate extension region 510E located outside the transistor and above the shallow trench isolation region 502; (2) a source region 506S located on the left side of the gate structure 510, having a length S(L) and a width S(W). Wherein, the length S(L) is the linear dimension from the edge of the gate structure 510 to the edge of the shallow trench isolation region 502; (3) a drain region 506D located on the right side of the gate structure 510, having a length D(L) and a width D(W). Wherein, the length D(L) is the linear dimension from the edge of the gate structure 510 to the edge of the shallow trench isolation region 502; (4) a contact hole 509S formed by self-alignment technology at the center of the source region 506S, and its opening length and opening width are respectively marked as C-S(L) and C-S(W); and (5) a contact hole 509D formed by the same self-alignment technology at the center of the drain 506D, and its opening length and opening width are respectively marked as C-D(L) and C-D(W). The length G(L), the length D(L), and the length S(L) can be precisely controlled and reduced to the minimum feature size λ. In addition, the opening length and width marked as C-S(L) and C-S(W) or the opening length and width marked as D-S(L) and D-S(W) can also be scaled down to less than λ, such as 0.6λ to 0.8λ.

[0285] Figures 5(b) to 5(g) are schematic cross-sectional views of a series of process structures for forming the mMOSFET 500 shown in Figure 5(a). First, by removing a portion of the silicon material outside the active region, the original or horizontal semiconductor surface (HSS) of a portion of the silicon substrate is exposed to define the active region of the mMOSFET 500. And a dielectric insulator 5021 is formed. Then, a gate layer and a silicon nitride layer 510N are deposited over the horizontal semiconductor surface HSS, and a plurality of true gates TG1-TG3 and a plurality of dummy shield gates DSG of the mMOSFET 500 are formed by etching the gate layer and the silicon nitride layer 510N. Among them, each dummy shield gate DSG is disposed between two adjacent true gates TG1-TG3 at a default linear distance. As shown in Figure 5(b), the length of the true gates TG1-TG3 can be scaled down to λ, the length of the dummy shield gate DSG is also scaled down to λ, and the distance between the edge of the dummy shield gate DSG and the edge of the adjacent true gate TG1-TG3 is also λ. In another embodiment, the aforementioned distance can be adjusted or enlarged according to manufacturing tolerances.

[0286] Then, a spin-on dielectric (SOD) 503 is deposited to fill the gap between any two adjacent ones of the dummy shield gates DSG and the true gates TG1-TG3, and then the spin-on dielectric 503 is etched back. An elaborate gate mask layer 504 is formed by photolithography masking technology. After that, the dummy shield gate DSG, a portion of the silicon nitride layer 510N above the dummy shield gate DSG, a portion of the dielectric insulator 5021 corresponding to the dummy shield gate DSG, and a portion of the p-type substrate 501 corresponding to the dummy shield gate DSG are removed by anisotropic etching technology. A plurality of openings 505O extending from the original horizontal semiconductor surface HSS into the p-type substrate 501 are formed (as shown in Figure 5(c)).

[0287] After that, the gate mask layer 504 is removed, the spin-on dielectric 503 is etched, and a plurality of shallow trench isolation silicon oxides 505A are deposited in the plurality of openings 505O and then etched back. Then, a silicon oxide layer is deposited and etched back; silicon oxide spacer walls 507 are formed on the sidewalls of the true gates TG1-TG3; lightly doped drains LDD are formed in the p-type substrate 501; a silicon nitride layer is deposited and etched back to form silicon nitride spacer walls 508; a portion of the dielectric insulator 5021 not covered by the true gates TG1-TG3, the silicon oxide spacer walls 507, and the silicon nitride spacer walls 508 is removed to expose a portion of the original horizontal semiconductor surface HSS.

[0288] In addition, an intrinsic silicon electrode 511 is grown on the exposed part of the original horizontal semiconductor surface HSS by using selective epitaxial growth (SEG) technology. The CVD-STI-silicon oxide layer 505B is redeposited and etched back. It should be noted that the combination of the silicon oxide layer 505B and the shallow trench isolation silicon oxide 505A can be part of the shallow trench isolation region 502 surrounding the transistor with the real gate TG1. The top of the shallow trench isolation region 502 is higher than the original horizontal semiconductor surface HSS and can be higher than the real gate TG1. In addition, in this step, the shallow trench isolation region 502 surrounds three sides of the intrinsic silicon electrode 511. Then, the intrinsic silicon electrode 511 is removed, and the original horizontal semiconductor surface HSS is exposed again to form the source region (n+ source) 506S and the drain region (n+ drain) 506D of the mMOSFET 505 (for example, by etching the original horizontal semiconductor surface HSS to expose the side (1,1,0) of the semiconductor substrate and selectively growing the source region / drain region). Therefore, the source region / drain region is also surrounded by the shallow trench isolation region 502. Since the source region (n+ source) 506S and the drain region (n+ drain) 506D are formed between the real gates TG1-TG3 of the shallow trench isolation region 502 and the CVD-STI-silicon oxide layer 505B, and since their positions were originally occupied by the dummy shield gate DSG, the length and width of the source region (n+ source) 506S (or the drain region (n+ drain) 506D) can be scaled down to λ. Due to the presence of the additional spacer 508, the opening of the source region (n+ source) 506S (or the drain region (n+ drain) 506D) can be less than λ, for example, 0.8λ. If a silicon oxide spacer 507 is additionally formed (as shown in Fig. 5(e)), such an opening can be made even smaller.

[0289] In addition, the new SRAM cell structure enables the in-line connection in the first metal layer (Metal-1) to be directly connected to the gate structure 510, the source region 506S, and / or the drain region 506D through a self-aligned miniaturized contact structure, without the need to use a traditional contact-hole-opening mask and / or a Metal-0 conversion layer to connect the in-line layer in the first metal layer (Metal-1). After the source region / drain region is formed, a spin-on dielectric material layer 512 is redeposited to fill the vacancy in the substrate 501 that was previously occupied by the intrinsic silicon electrode 511, and this vacancy includes the opening of the source region (n+ source) 506S (or the drain region (n+ source) 506S). Then, chemical mechanical polishing (CMP) is used to planarize the surface (as shown in Fig. 5(f)).

[0290] In addition, a pre-designed photomask is used to form a patterned photoresist layer (not shown) having a plurality of stripe patterns (instead of the conventional two-dimensional contact opening pattern) separated from each other by a certain interval length GROC(L) along the X-axis, so as to expose the portion of the gate extension region 510E extending along the Y-axis to the outside. The most aggressive design rule is that the length GROC(L)=λ. Then, an anisotropic etching technique is used to remove the silicon nitride covering layer located within and exposed to the gate extension region 510E, so as to expose the conductive metal gate layer of the true gate TG1.

[0291] After that, the spin-on dielectric layer 512 is removed, so that the openings at the tops of the source region 506S and the drain region 506D are exposed again. Then, a silicon oxide layer with a preset thickness is deposited, and then an anisotropic etching technique is used to form spacer walls 514 on the openings of the source region 506D and the drain region 506D and the four sidewalls of the exposed gate extension region 510E. Therefore, contact hole openings 509G, 509S, and 509D are naturally formed in the exposed gate extension region 510E, source region 506S, and drain region 506D, respectively.

[0292] Finally, a first metal layer (Metal-1) 513 is formed, which has a preset thickness to fill the aforementioned contact hole openings 509G, 509S, and 509D and produce a smooth planar surface following the chip surface topography. Then, a photolithography mask technique is used to establish all the internal connections between these contact hole openings 509G, 509S, and 509D respectively, so as to implement the necessary internal connection network of the first metal layer (Metal-1). The process of forming the mMOSFET 500 (as shown in Figure 5(g)) is completed.

[0293] Figure 5(h) is a top view of the structure of the mMOSFET shown in Figure 5(g). The vertical length CRMG(L) of the contact hole opening 509G located in the exposed gate extension region 510E is less than the length GROC(L), which can be λ.

[0294] Since the first metal layer (Metal-1) 513 has completed its tasks of filling and connecting the contact plugs between the gate region and the source / drain regions, as well as the internal connection function of directly connecting all the transistors. Therefore, there is no need to use the expensive and strictly controlled traditional contact hole opening photomask and perform the subsequent very difficult contact hole drilling technique. Especially after further miniaturizing the horizontal geometry, it is a very difficult challenge to perform this (contact hole drilling) process for billions of transistors. In addition, it eliminates the need to fabricate metal plugs in the contact hole openings and perform chemical mechanical polishing on them, and realizes the process of the metal plug column through complex integration process steps (for example, constructing the Metal-0 structure that is absolutely required for some cutting-edge technologies).

[0295] Example 2 (NuCMOS transistor - using local isolation and the vertical edges of the source / drain regions to shorten the latch distance, and using metal-semiconductor junctions to reduce resistance)

[0296] This embodiment discloses a new SRAM cell structure, in which the n+ regions and p+ regions of the source regions and drain regions in the NMOS transistors and PMOS transistors are completely isolated by insulators respectively. Such insulators can not only increase the immunity to latch-up problems, but also increase the isolation distance of the junctions used to isolate the NMOS transistors and PMOS transistors in the silicon substrate, so as to reduce the surface distance between the junctions (such as 3λ), and further reduce the size of the SRAM cell structure. A new SRAM cell structure is briefly introduced below, in which the n+ regions and p+ regions of the source regions and drain regions of the NMOS transistors and PMOS transistors are completely isolated by insulators respectively.

[0297] FIG. 6(a) is a top view of a combined structure of a PMOS transistor 62 and an NMOS transistor 61 used in an SRAM cell structure according to an embodiment of the present invention. FIG. 6(b) is a cross-sectional view of the PMOS transistor 62 shown along the tangent line 1 (X-axis) of FIG. 6(a); FIG. 6(c) is a cross-sectional view of the NMOS transistor 61 shown along the tangent line 2 (X-axis) of FIG. 6(a); FIG. 6(d) is a cross-sectional view of the PMOS transistor 62 and the NMOS transistor 61 shown along the tangent line 3 (Y-axis) of FIG. 6(a).

[0298] A gate structure 63 including a gate dielectric layer 631 and a gate conductive layer 632 (e.g., gate metal) is formed above a horizontal or native surface of a semiconductor substrate (e.g., a silicon substrate, or a semiconductor substrate having a plurality of silicon / silicon germanium (Si / SiGe) multiple superlattice structures and applied to a gate all around (GAA) transistor, the horizontal or native surface of which will be the top of the multiple superlattice structure). A dielectric capping layer 633 (e.g., a composite of a silicon oxide layer and a silicon nitride layer) is located above the gate conductive layer 632. Additionally, a spacer 64 including a composite of a silicon oxide layer 641 and a silicon nitride layer 642 can be used on the sidewalls of the gate structure 63. Trenches are formed in the semiconductor substrate and are located below the horizontal or native surface of the semiconductor substrate. Then, a local isolation region 68 (e.g., silicon nitride or other high-k dielectric material) is located in one trench and below the source region, while another local isolation region 68 is located in another trench and below the drain region. Such a local isolation region 68 is located below the native horizontal semiconductor surface HSS of the silicon substrate 601 and can be referred to as a localized isolation into silicon substrate (LISS) 68 in the silicon substrate. The local isolation region 68 in the silicon substrate can be a composite of a thick silicon nitride layer or a dielectric layer. For example, the local isolation region (or LISS) 68 can include an L-shaped composite local isolation region having a silicon oxide layer (referred to as Oxide-3V layer 681) covering at least a part of the sidewalls of the trench and another silicon oxide layer (referred to as Oxide-3B layer 682) covering at least a part of the bottom wall of the trench. Among them, the Oxide-3V layer 681 and the Oxide-3B layer 682 can be formed by a thermal oxidation process, so that the edge of the Oxide-3V layer 681 is well controlled. For example, it is aligned with the edge of the gate conductive layer 632. The composite local isolation region 68 further includes a silicon nitride layer 683 (referred to as Nitride-3) located above the Oxide-3B layer 682 and in contact with the Oxide-3V layer 681. It should be noted that as long as the Oxide-3V layer 681 remains intact and precisely controlled, the silicon nitride layer 683 or Nitride-3 can be replaced by any suitable insulating material. Then, a part of the Oxide-3V layer 681 above the top of the silicon nitride layer 683 is etched away to expose the surface with the (110) lattice direction of the silicon substrate. Then, all or at least a part of the source region 65 and the drain region 66 are respectively positioned in the corresponding trenches. The source (or drain region) in the PMOS transistor 62 can include a P+ region selectively grown from the (110) lattice surface or other appropriate doped profile regions (e.g., a region where the doping concentration gradually or stepwise changes from the P- region of the lightly doped drain to the P+ region).It should be noted that, by means of the edge of the Oxide-3V layer 681, the edge of the lightly doped drain region can be well controlled and aligned with the edge of the gate conductive region 632. Therefore, the present invention can reduce the Gate-induced-drain-leakage current (GIDL). In addition, the shallow trench isolation region may include a composite shallow trench isolation region 69, which includes an STI-1 layer 691 and an STI-2 layer 692, wherein the STI-1 layer 691 and the STI-2 layer 692 may be made of thick silicon oxide materials respectively using different processes. As described above, the shallow trench isolation region can be raised to a level higher than the original level semiconductor surface HSS of the semiconductor substrate and as high as the top of the gate structure 63 to surround or confine the source region / drain region grown between the gate structures.

[0299] In addition, the source region 65 (or the drain region 66) may include a composite source region 65 and / or drain region 66. For example, in the PMOS transistor 62, the composite source region 65 (or drain region 66) located in the trench includes at least a lightly doped drain region 651 and a P+ heavily doped region 652. It should be noted that the lightly doped drain region 651 is adjacent to an exposed silicon surface having a uniform (110) lattice direction. Compared with the edge of the gate structure, the exposed silicon surface has a vertically bounded edge with an appropriately concave thickness, which is labeled as TEC (i.e., the thickness of the transistor body that has been etched away, which can be clearly defined as the sharp edge of the effective channel length). The exposed silicon surface is substantially aligned with the gate structure. And the exposed silicon surface can be the end face of the transistor channel.

[0300] As described above, the lightly doped drain region 651 and the P+ heavily doped region 652 can be formed by selectively epitaxial growth technology (or other suitable technologies, such as atomic layer deposition (ALD) or selective atomic layer deposition growth (SALD)) to grow silicon from the exposed TEC region. Among them, the TEC region can be used as a seed layer to form a well-organized new silicon with a (110) lattice direction across the entire local isolation region (or LISS) 68. And the local isolation region (or LISS) 68 has no seeding effect on changing the newly formed (110) crystal structure of the composite source region 65 or drain region 66. This newly formed crystal (including the lightly doped drain region 651 and the P+ heavily doped region 652) can be called TEC-Si. In an embodiment of the present specification, the TEC region is aligned or substantially aligned with the edge of the gate structure 63; the length of the lightly doped drain region 651 can be adjusted; and the side wall of the lightly doped drain region 651 relative to the TEC region can be aligned with the side wall of the spacer 64.

[0301] Similarly, the TEC-Si of the composite source / drain region of the NMOS transistor 61 (including the lightly doped drain region 651 and the P+ heavily doped region 652) is shown in Fig. 6(c). The composite source / drain region may also include some tungsten (or other suitable metal materials) plugs 653, forming a horizontal connection with the TEC-Si part to constitute a complete source / drain region. After the active channel current reaches the tungsten plug 653 (or other metal materials) through the lightly doped drain region 651 and the P+ heavily doped region 652, it will flow to the metal interconnect (e.g., the first metal layer (Metal-1)). Since the tungsten plug 653 can be directly connected to the first metal layer (Metal-1) through a good metal-metal ohmic contact, its resistance is much lower than that of the traditional silicon-metal contact. As mentioned before, since the shallow trench isolation region can be raised to a level higher than the original surface (silicon) of the semiconductor substrate HSS and extended to the top of the gate structure 63 to surround or limit the growth of the source / drain region on three sides. As shown in Fig. 5(g), self-aligned contact holes are formed above the selectively grown source / drain region. Therefore, the tungsten plug 653 or other composite metal materials (Meta+W) can be deposited in the self-aligned contact holes and contact the top of the source / drain region that grows and extends to the shallow trench isolation region 69, or contact the top and the most lateral sidewalls of the source / drain region that does not grow and extend to the shallow trench isolation region 69. Thereby, the contact resistance can be reduced.

[0302] In addition, as shown in Fig. 6(a) and Fig. 6(d), the epitaxially grown source region (drain region) extending along the X-axis of the PMOS transistor 62 has an edge surface 621E; the epitaxially grown source region (drain region) extending along the X-axis of the NMOS transistor 61 has an edge surface 611E; and the edge surface 621E faces the edge surface 611E and is parallel or substantially parallel to the edge surface 611E. Both the edge surface 611E and the edge surface 621E can be perpendicular or substantially perpendicular to the original horizontal surface of the substrate.

[0303] As shown in FIG. 6(d), there is a composite local isolation region (or LISS) 68 between the bottom of the P+ source / drain region of the PMOS transistor 62 and the N-type well region of n-type electrical conductivity. There is also another composite local isolation region (or LISS) 68 between the bottom of the N+ source / drain region of the NMOS transistor 61 and the P-type well region of p-type electrical conductivity or the substrate 601. The obvious advantage is that in the CMOS transistor structure of the present invention, the bottoms of the n+ region and the p+ region are completely isolated by an insulator. That is to say, from the bottom of the p+ region of the PMOS transistor 62 to the bottom of the N+ region of the NMOS transistor 61, possible latch-up paths are completely blocked by the local isolation region (or LISS) 68. Therefore, the latch-up distance between the PMOS transistor and the NMOS transistor can be reduced.

[0304] On the other hand, in the conventional CMOS transistor structure, the n+ region and the p+ region are not completely isolated by an insulator, as shown in FIG. 6(e). The possible latch-up path starts from the n+ / p junction between the n+ region and the P-type well region, passes through the p-well / n-well junction between the P-type well region and the N-type well region, and extends to the n / p+ junction between the N-type well region and the p+ region. Its path length includes lengths d, e, f, and g. Therefore, from the perspective of component layout, the guard band distance (Xn+Xp) between the NMOS transistor and the PMOS transistor of the present invention (as shown in FIG. 6(d)) can be smaller than the guard band distance in the conventional design (as shown in FIG. 6(e)). For example, the guard band distance (Xn+Xp) can be about 2λ to 4λ, for example, 3λ.

[0305] Another combined structure of the novel PMOS transistor 62 and the novel NMOS transistor 61 is a top view of the structure shown in Fig. 6(f). Fig. 6(g) is a schematic cross-sectional view of the combined structure of the novel PMOS transistor 62 and the novel NMOS transistor 61 shown along the tangent line (X-axis) of Fig. 6(f). As shown in Fig. 6(g), starting from the n+ / p junction between the n+ region and the p-well region, passing through the p-well / n-well junction between the p-well region (or p-type substrate) and the N-well region, and extending to the n / p+ junction between the n-well region and the p+ region, the path is longer. The possible latch-up path starts from the LDD-n / p junction between the n-type lightly doped drain region and the p-well region, passes through the p-well / n-well between the p-well region and the n-well region, and extends to the n / LDD-p junction between the n-well region and the p-type lightly doped drain region. Its path length includes length ①, length ② (the length of the bottom wall of a local isolation region LISS), length ③, length ④, length ⑤, length ⑥, length ⑦ (the length of the bottom wall of another local isolation region LISS), and length ⑧ shown in Fig. 6(g). On the other hand, in the traditional CMOS transistor structure combining PMOS and NMOS transistors, as shown in Fig. 6(e), the possible latch-up path starts from the n+ / p junction between the n+ region and the P-well region, passes through the p-well / n-well junction between the p-well region and the n-well region, and extends to the n / p+ junction between the n-well region and the p+ region. Its path length includes length d, length e, length f, and length g. The possible latch-up path shown in Fig. 6(g) is longer than the possible latch-up path shown in Fig. 6(e). Therefore, from the perspective of component layout, the reserved edge distance (Xn+Xp) between the NMOS transistor and the PMOS transistor shown in Fig. 6(g) can be smaller than the reserved edge distance shown in Fig. 6(e). For example, the reserved edge distance (Xn+Xp) can be about 2λ to 4λ, for example, it is 3λ.

[0306] Another embodiment of forming the NMOS transistor 700 includes the following steps: First, by using a photolithography mask technology, a part of the silicon material of the semiconductor substrate 701 is removed to form trenches 701A and 701B, thereby defining an active region pattern having a semiconductor surface 701S. Then, a silicon oxide layer 702A is deposited to completely fill the trenches 701A and 701B, and then an etching-back process is performed so that the remaining silicon oxide layer 702A is located below the semiconductor surface 701S of the active region. Then, a dielectric insulator 703 is formed to cover the semiconductor surface 701S and the remaining silicon oxide layer 702A. A gate structure 704 including a gate layer 704A and a silicon nitride layer 704B is formed above the dielectric insulator 703 in the active region of the semiconductor substrate 701.

[0307] Then, a silicon oxide layer 702B with a sufficient thickness is deposited to fill the vacancies above the trenches 701A and 701B, and the silicon oxide layer 702B is planarized to the top of the semiconductor surface 701S or the top of the dielectric insulator 703 using chemical mechanical polishing (CMP) and / or etching-back techniques (or as described above, the top of the silicon oxide layer 702B can be higher than the semiconductor surface 701S or as high as the top of the gate structure 704). The silicon oxide layers 702A and 702B and a part of the dielectric insulator 703 formed in the trenches 701A and 701B together form a trench isolation layer 702, also known as a shallow and deep trench isolation structure (or simply referred to as "deep oxide isolation (DOI)") (as shown in Figure 7(a)).

[0308] A silicon oxide spacer wall 705A is formed to cover the sidewalls of the gate structure 704. Then, a lightly doped region is formed in the p-type substrate 701, and rapid thermal annealing (RTA) is performed on the lightly doped region to form an n-type lightly doped drain region (NLDD) 706. A nitride spacer wall 705B is formed to cover the silicon oxide spacer wall 705A and the n-type lightly doped drain region 706.

[0309] The silicon oxide spacer wall 705A, the silicon nitride spacer wall 705B, and the shallow and deep trench isolation structure (trench isolation layer) 702 can act as a mask, and a part of the dielectric insulator 703 not covered by the mask is removed to expose the semiconductor surface 701S. Then, anisotropic etching techniques can be used to etch downward from the semiconductor surface 701S to expose the silicon material, thereby forming a first recess 707A and a second recess 707B.

[0310] Silicon oxide layers are grown in the first recess 707A and the second recess 707B respectively to form a first protective isolation layer 708A and a second protective isolation layer 708B respectively. A metal layer (such as tungsten) 709 is deposited into the first recess 707A and the second recess 707B respectively. Additionally, the metal layer 709 located in the first recess 707A and the second recess 707B is etched to a preset height using anisotropic etching techniques, so that the top of the metal layer 709 is lower than the semiconductor surface 701S. Then, using the etched metal layer 709 as a blocking substrate, the parts of the first protective isolation layer 708A and the second protective isolation layer 708B that are higher than the etched metal layer 709 are removed, so that a part of the silicon sidewall 701W1 of the first recess 707A and a part of the silicon sidewall 701W2 of the second recess 707B can be exposed, as shown in Figure 7(b).

[0311] Using the silicon sidewalls 701W1 with the first recess 707A exposed and the silicon sidewalls 701W2 with the second recess 707B exposed as seed materials (where the exposed silicon sidewalls 701W1 and 701W2 are located below the semiconductor surface 701S), by using selective epitaxial growth (SEG) technology (or atomic layer deposition (ALD) growth technology), from the exposed silicon sidewalls 701W1 and 701W2, the sidewalls of the n+-in-situ-doped first semiconductor region 710A and the n+-in-situ-doped second semiconductor region 710B are grown laterally respectively, so as to form an n+ semiconductor junction between the first semiconductor region 710A and the p-type substrate 701, and form an n+ semiconductor junction between the second semiconductor region 710B and the p-type substrate 701. In addition, as described above, the grown silicon is surrounded by a shallow trench isolation structure.

[0312] Since the laterally grown silicon electrodes of the present invention, that is, the first semiconductor region 710A and the second semiconductor region 710B, are formed based on the exposed sidewalls of the silicon of the p-type substrate of the NMOS transistor (or the n-type substrate of the PMOS transistor). The most advanced tri-gate transistors, fin field-effect transistors (FinFETs), gate-all-around (GAA) transistors or other fin structure type transistors, and other technologies, such as any strain-related materials or processes that can enhance the mobility and speed of the transistors, can be applied to the present invention to grow the drain region and the source region. Then, a metal silicide layer can be formed on the top region of the electrode of the transistor to make the top region of the electrode have a better ohmic contact interface, and so on.

[0313] The metal layer 709 formed in the first recess 707A and the second recess 707B can be selectively removed. Then, a composite metal material (CMM) layer is deposited into the first recess 707A and the second recess 707B to contact the bottom surfaces and the most lateral sidewalls of the first semiconductor region 710A and the second semiconductor region 710B. For example, in one embodiment, the composite metal material may include a metal silicide material covering the first semiconductor region 710A / second semiconductor region 710B, a titanium nitride (TiN) buffer layer (a type of core metal column (CMC)) covering the metal silicide material, and a tungsten layer filled in the first recess / second recess. The titanium nitride (TiN) buffer layer is deposited into the first recess 707A and the second recess 707B to provide a good interface for the metal silicide layers respectively located on the sidewalls of the first semiconductor region 710A and the second semiconductor region 710B, facilitating subsequent deposition of the tungsten layer into the first recess 707A and the second recess 707B. The composite metal material (CMM) can be the first metal-containing region 711A and the second metal-containing region 711B, where the titanium nitride (TiN) buffer layer contacts the metal silicide layer and the core metal column (CMC). Additionally, the composite metal material (CMM) not only fills the first recess 707A and the second recess 707B, but also fills all the voids above the first recess 707A and the second recess 707B, and uses an anisotropic etching technique to remove the excess composite metal material (CMM) until the height of the composite metal material (CMM) reaches the top of the semiconductor surface 701S, or even higher than the semiconductor surface 701S, to cover the top surfaces of the first semiconductor region 710A and the second semiconductor region 710B.

[0314] As shown in FIG. 7(c), one sidewall of the first metal-containing region 711A contacts the lateral sidewall of the first semiconductor region 710A, and the other three sidewalls of the first metal-containing region 711A are isolated by the shallow trench isolation structure 702 / first protective isolation layer 708A. The bottom of the first metal-containing region 711A is also isolated by the first protective isolation layer 708A. Similarly, one sidewall of the second metal-containing region 711B contacts the lateral sidewall of the second semiconductor region 710B, and the other three sidewalls of the second metal-containing region 711B are also isolated by the shallow trench isolation structure 702 / second protective isolation layer 708B. The bottom of the second metal-containing region 711B is also isolated by the second protective isolation layer 708B.

[0315] In addition, taking the first metal-containing region 711A and the first protective isolation layer 708A shown in FIGS. 7(b) and 7(c) as an example, the first protective isolation layer 708A includes a horizontal protective isolation portion 708A1 and a vertical protective isolation portion 708A2. The vertical protective isolation portion 708A2 contacts the sidewall of the first metal-containing region 711A and the bottom of the first semiconductor region 710A; and the horizontal protective isolation portion 708A2 contacts the bottom of the first metal-containing region 711A. Therefore, the first metal-containing region 711A can be prevented from directly contacting the p-type substrate 701 by means of the first protective isolation layer 708A. In addition, since the top of the shallow trench isolation structure 702 reaches the semiconductor surface 701S or the top of the gate structure 704, the shallow trench isolation structure 702 can isolate the NMOS transistor 700 from adjacent transistors.

[0316] Furthermore, taking the first metal-containing region 711A, the first semiconductor region 710A, and the n-type lightly doped drain region (NLDD) 706 shown in FIG. 7(c) as an example, the vertical length of the first semiconductor region 711A in contact with the n-type lightly doped drain region 706 can be adjusted by weighing the design parameters required by the NMOS transistor 700. These parameters can be, for example, the width of the gate layer 704A, the magnitude of the target allowable leakage current, which includes drain Induced Barrier Lowering (DIBL), the drain-to-source sub-channel conduction current that will deteriorate the short-channel effect to a certain extent, and the drain (source) / substrate junction leakage, etc. The top of the first metal-containing region 710A can be designed to have a metal landing pad (MLP) function for receiving the internal connection in the first metal layer (Metal-1), and greatly reduce the boundary edge of the opening connecting the first semiconductor region 710A. This allows the design rule between the first metal layer (Metal-1) and the first semiconductor region 710A to be more tightened.

[0317] After the selective epitaxial growth of the semiconductor material and the formation of the composite metal material (CMM) layer are completed, FIG. 7(d) shows a top view of the NMOS transistor 700 shown in FIG. 7(c). As shown in FIGS. 7(c) and 7(d), the laterally grown n+ silicon (i.e., the first semiconductor region 710A) and the composite metal material layer (i.e., the first metal-containing region 711A) are formed in a rectangular first recess (not shown), and the laterally grown n+ silicon (i.e., the second semiconductor region 710B) and the composite metal material layer (i.e., the second metal-containing region 711B) are formed in a second recess (not shown). The laterally grown n+ silicon and the composite metal material layer are surrounded by a shallow trench isolation silicon oxide layer (i.e., the shallow and deep trench isolation structure 702 including the silicon oxide layers 702A and 702B), and the laterally grown n+ silicon 710B has at least two edge surfaces 710E1 and 710E2 that are perpendicular or substantially perpendicular to the original surface of the substrate. The laterally grown n+ silicon 710A has at least two edge surfaces 710E3 and 710E4 that are perpendicular or substantially perpendicular to the original surface of the substrate. The same applies to the first metal-containing region 711A and the second metal-containing region 711B.

[0318] The above steps can be applied to a semiconductor manufacturing process for producing fin field-effect transistors at a process node of 12 nanometers (or less). For example, the active region of the NMOS transistor 700 can be a fin structure or a gate-all-around (GAA) transistor. According to an embodiment of the present specification, the 6T SRAM cell structure includes a plurality of transistors having the same structure as the NMOS transistor 700, separated from each other by the shallow and deep trench isolation structure 702, and covered by the same gate structure 704; and the source regions / drain regions of each transistor form a plurality of finger structures or gate-all-around (GAA) structures.

[0319] FIG. 7(e) is a perspective view of the NMOS transistor structure 700 shown in FIG. 7(d). Since the left side portion (including the first semiconductor region 710A and the first metal-containing region 711A) and the right side portion (including the second semiconductor region 710B and the second metal-containing region 711B) of each finger structure or gate-all-around (GAA) structure are formed in a rectangular recess (the first recess 707A and the second recess 707B) surrounded by the shallow and deep trench isolation structure 702 and having three sidewalls, and these recesses limit the lateral growth of the n+ silicon and the CMM. Therefore, the left side portion and the right side portion of each finger structure or gate-all-around (GAA) structure are rectangular in shape. At the same time, the bottom of each rectangular recess is covered by the first protective isolation layer 708A or the second protective isolation layer 708B.

[0320] Example 3 (OPCMOS transistor with diamond-shaped source / drain (S / D) and no raised shallow trench isolation (STI)) Figure 8

[0321] This embodiment discloses a fin field-effect / wrapped gate (GAA) transistor 800 for an SRAM cell structure, particularly for a 6T SRAM cell structure. In this embodiment, the structure of the fin field-effect / wrapped gate (GAA) transistor 800 is similar to the structure of the NMOS transistor 700 shown in FIGS. 7, 7(e), and 7(d), except that the left and right sides (or source / drain regions) of the fin field-effect / wrapped gate (GAA) transistor are not formed in a recess having three sidewalls surrounded by shallow trench isolation silicon oxide.

[0322] For example, in Example 4 (Compound shallow trench isolation for signal distribution or heat dissipation of underground the fin field-effect / wrapped gate (GAA) transistor 800 has a plurality of fin structures or superlattice structures 801F defined by shallow trench isolation regions (not shown) in a semiconductor substrate 801, and source / drain regions grown in situ from the lateral sidewalls of the fin structures or superlattice structures 801F by selective epitaxial growth (SEG) technology (or atomic layer deposition (ALD) growth technology). These fin structures or superlattice structures are separated from each other and are covered by a gate structure 804 (including a gate dielectric layer and a gate electrode (not shown)). In this embodiment, each end of the fin structure or superlattice structure 801F can provide a seed region for selectively growing a lightly doped drain region (LDD) and a highly doped region. For example, the left side of each fin structure or superlattice structure respectively includes a lightly doped semiconductor region (e.g., a silicon epitaxial n-type lightly doped drain region (NLDD) for an NMOS transistor) 810A grown laterally from the edge of each fin structure or superlattice structure 810F, and a heavily doped semiconductor region (e.g., a silicon epitaxial N+ region for an NMOS transistor) 811A grown from the lateral edge of each n-type lightly doped semiconductor region 810A. The right side of each fin structure or superlattice structure 810F also respectively includes an n-type lightly doped semiconductor region 810B grown laterally from the other edge of each fin structure or superlattice structure 801F, and a heavily doped semiconductor region 811B grown from the lateral edge of each n-type lightly doped semiconductor region 810B. At the same time, as described above, the bottom of each finger structure is covered by a protective isolation layer 808.

[0323] Since the two n+ semiconductor regions 811A and 811B formed by selective epitaxial growth technology in the fin field-effect / cladded gate (GAA) transistor 800 are not restricted by the shallow trench isolation silicon oxide region, these two heavily doped (epitaxial) semiconductor regions 811A and 811B can gradually expand to form mushroom shapes (or diamond shapes) respectively. Therefore, in one embodiment, the width of each fin structure / superlattice structure 801F is 6 nanometers, and the width of the shallow trench isolation region (not shown) located between two independent fin structures / superlattice structures can be 25 nanometers. The width of the shallow trench isolation region between a conventional fin field-effect transistor and another identical fin field-effect transistor is also 25 nanometers. Therefore, the pitch between two fin field-effect / cladded gate (GAA) transistors 800 is 62 nanometers. This fin field-effect / cladded gate (GAA) transistor 800 with NMOS and PMOS transistors can be called an OPCMOS transistor, which applies the technologies described in Embodiment 1 and Embodiment 2 but does not have a raised shallow trench isolation region (and / or metal-semiconductor junction). On the other hand, if the fin field-effect / cladded gate (GAA) transistor 800 applies all the technologies described in Embodiment 1 and Embodiment 2 (including the raised shallow trench isolation region), it can be called a NuCMOS transistor.

[0324] interconnection lines (UGI)) Figure 9A

[0325] In addition, in a conventional SRAM cell structure, metal lines for high-level voltage VDD and low-level voltage VSS (or ground) are distributed above the original silicon surface of a silicon substrate. If there is not enough space between the metal lines, such distribution will interfere with metal lines used as word lines (WL), bit lines (BL and BL Bar), or other internal connection lines. The present invention discloses a novel SRAM cell structure, in which metal lines connecting high-level voltage VDD and / or low-level voltage VSS and / or bit lines (BL and BL Bar) can be distributed below the original (silicon) surface of a silicon-based substrate. Therefore, even if the size of the SRAM cell is reduced, interference between the size of the contact structure, the layout of metal lines connecting word lines (WL), bit lines (BL and BL Bar), high-level voltage VDD, low-level voltage VSS, etc. can be avoided. For example, as shown in FIG. 6(g), in the drain region of PMOS transistor 62, a tungsten plug 653 or other metal material is directly electrically connected to the n-type well region; and the n-type well region is directly electrically connected to high-level voltage VDD. On the other hand, in the source region of NMOS transistor 61, a tungsten plug 653 or other metal material is directly electrically connected to the p-type well region or P-type substrate; and the p-type well region or P-type substrate is directly... Therefore, the novel SRAM cell structure can omit openings originally used to electrically connect the source / drain region to the second metal layer or the third metal layer as connection lines for high-level voltage VDD or ground in the source / drain region.

[0326] This embodiment discloses a semiconductor circuit 900 including an asymmetric spacer and an underlying internal connection line (e.g., an underground bit line (UGBL) or other conductive line), wherein the asymmetric spacer extends along the sidewalls of the active regions, and the underlying internal connection line is located between the asymmetric spacers, below the original horizontal (silicon) surface HSS, and inside the shallow trench isolation region surrounding the active regions. Another alternative process for forming such an asymmetric spacer and an underlying internal connection line is described below.

[0327] First, a pad silicon oxide layer 902 and a pad silicon nitride layer 903 are sequentially deposited on a semiconductor substrate 901, a part of the semiconductor substrate 901 is removed, a silicon oxide layer is deposited and etched back to form a shallow trench isolation region 904, thereby defining a plurality of active regions 901A (e.g., a plurality of fin structures). Figure 9B FIG. (a) is a top view showing the temporary structure after forming the shallow trench isolation region 904. (b) is a cross-sectional view of the structure shown along the tangent Y-cut shown in (a); (c) is a cross-sectional view of the structure shown along the tangent X-cut shown in (a).

[0328] Thereafter, a thermal oxide layer 905 is grown along the sidewalls of the active region 901A that are exposed to the outside. Then, a spin-on dielectric (SOD) material 906 is deposited to fill the gaps between the active regions 901A, and then the spin-on dielectric (SOD) material 906 is planarized by a chemical mechanical process. Then, a photoresist layer 907 is formed and patterned to cover a part (e.g., 1 / 2) of the active region 901A and expose a part of the spin-on dielectric (SOD) material 906. In Figure 9C , (a) is a top view of the process structure showing after the SOD material and the photoresist layer are formed; (b) is a cross-sectional view of the structure taken along the tangent Y-cut shown in (a); (c) is a cross-sectional view of the structure taken along the tangent X-cut shown in (a).

[0329] Then, a part of the spin-on dielectric (SOD) material 906 that is not covered by the photoresist layer 907 and a part of the thermal silicon oxide 905 located under the spin-on dielectric (SOD) material that is not covered by the photoresist layer 907 are removed to form a narrow trench 908. It should be noted that after removing a part of the spin-on dielectric (SOD) material 906 that is not covered by the photoresist layer 907 and a part of the thermal silicon oxide 905 located under the spin-on dielectric (SOD) material 906 that is not covered by the photoresist layer 907, the narrow trench 908 exposes the sidewalls of the active region 901A to the outside. In Figure 9D , (a) is a top view of the process structure showing after the narrow trench 908 is formed; (b) is a cross-sectional view of the structure taken along the tangent Y-cut shown in (a); (c) is a cross-sectional view of the structure taken along the tangent X-cut shown in (a).

[0330] After removing the patterned photoresist 907, silicon oxycarbide nitride (SiOCN) 910 is deposited into the narrow trench 908 and planarized. Thereby, an asymmetric spacer (e.g., a silicon oxide 905 spacer and a silicon oxycarbide nitride 910 spacer) containing different materials is formed in the shallow trench isolation region 904. In another view, this asymmetric spacer also covers the two sidewalls of the active region 901A respectively. In Figure 9E , (a) is a top view of the process structure showing after the silicon oxycarbide nitride (SiOCN) material 910 is formed; (b) is a cross-sectional view of the structure taken along the tangent Y-cut shown in (a); (c) is a cross-sectional view of the structure taken along the tangent X-cut shown in (a).

[0331] Then, the spin-on dielectric (SOD) material 906 is removed, and a titanium nitride (TiN) layer 911 and a tungsten layer 912 are deposited between the silicon oxide 905 spacer walls and the silicon carbonitride spacer walls 910. Then, the titanium nitride (TiN) layer 911 and the tungsten layer 912 are etched back to form the underlying interconnect. Then, a silicon nitride layer 913 and a high-density plasma (HDP) silicon oxide layer 914 are formed to cover the underlying interconnect. In Figure 9F , (a) is a top view of the process structure after the formation of the silicon nitride layer 913 and the high-density plasma (HDP) silicon oxide layer 914; (b) is a cross-sectional view of the structure taken along the tangent line Y shown in (a); (c) is a cross-sectional view of the structure taken along the tangent line X-cut shown in (a). Then, the underlying interconnect is formed and embedded in or surrounded by a composite shallow trench isolation region including at least the shallow trench isolation region 904 and the high-density plasma (HDP) silicon oxide layer 914. The underlying interconnect (UGI) may be part of the composite shallow trench isolation region.

[0332] In some embodiments of the present specification, the UIG will be applied to the access transistor of the 6T SRAM cell structure. For example, Example 5 (4CFET) is a three-dimensional perspective view of the circuit structure 900 (whose structure is similar to the NMOS transistor 700 shown in FIG. 7(e)), which can be applied to the 6T SRAM cell and has an underlying interconnect (UGI) 913 embedded in and surrounded by all insulators, and is electrically connected to the drain region 915 (or the source region 925) through a self-aligned vertical interconnect 916. The sidewalls of the vertical interconnect 916 are connected to the sidewalls of the underlying interconnect 913. By using such an underlying interconnect UGI and electrically connecting it to the drain region and / or the source region of the access transistor, the size of the 6T SRAM cell structure can be reduced.

[0333] In addition, when the underlying interconnect is not used for signal / power distribution, this underlying interconnect can also be used for heat dissipation purposes. In particular, since the shallow trench isolation region 904 or the composite shallow trench isolation region not only surrounds the transistor but also extends to the edge portion of the chip, the underlying interconnect embedded in the composite shallow trench isolation region can also surround the transistor and extend to the edge portion of the chip. Therefore, the heat generated by the transistor can be dissipated to the chip edge through the underlying interconnect and then connected to the heat sink from the chip edge. At this time, the material of the underlying interconnect can be metal, silicon carbide (SiC), polysilicon, aluminum nitride (AlN), boron nitride (BN), or other materials with a higher thermal conductivity than silicon dioxide (SiO2) or silicon.

[0334] Figure 10A

[0335] This embodiment discloses a vertical thin-body field-effect transistor (VTBFET) that has a low standby current, a low gate-induced drain leakage current, and a low short channel effect (SCE), and forms a solid fence wall to clamp the active region of the vertical thin-body field-effect transistor or the narrow protruding structure of the vertical thin-body field-effect transistor. The vertical thin-body field-effect transistor can be applied to an SRAM cell structure, especially for a 6T SRAM cell structure.

[0336] The manufacturing method of a vertical thin-body field-effect transistor (taking an NMOS transistor as an example) 1000 includes the following steps: sequentially form a pad oxide layer 1002 and a pad nitride layer 1004 above the original semiconductor surface or the original horizontal surface OHS of the p-type well region of a p-type semiconductor substrate 1001. Remove a part of the pad oxide layer 1002, a part of the pad nitride layer 1004, and a part of the semiconductor substrate 1001 by an anisotropic etching technique to define the active region 1001A (such as a fin structure) of the vertical thin-body field-effect transistor 1000.

[0337] Deposit a silicon oxide spacer wall 1003 and a silicon nitride spacer wall 1005 at the edge of the active region 1001A, and etch back the silicon oxide spacer wall 1003 and the silicon nitride spacer wall 1005 by an anisotropic etching technique to form a solid gate wall to clamp the active region 1001A, so as to protect the fin structure from collapsing during the formation of the source / drain region or the gate region of the vertical thin-body field-effect transistor.

[0338] Next, deposit a thick silicon oxide layer to completely fill the trench around the active region 1001A, and use chemical mechanical polishing technology to remove the excess silicon oxide layer to form a shallow trench isolation region 1006. Wherein, the top surface of the shallow trench isolation region 1006 is flush with the top surface of the pad nitride layer 1004. Similarly, the shallow trench isolation region 1006 also surrounds or clamps the active region 1001A or the narrow protruding structure, especially the side wall of the protruding structure, so as to protect the fin structure from collapsing during the formation of the source / drain region or the gate region of the vertical thin-body field-effect transistor.

[0339] Deposit a thin nitride silicon 1007 above the pad nitride layer 1004 and the shallow trench isolation region 1006, deposit a patterned photolithography photoresist mask 1008 for defining the gate region above the thin nitride layer 1007, and form a recess 1009 corresponding to the gate region by removing a part of the thin nitride layer 1007 and a part of the pad nitride layer 1004. At Figure 10BAmong them, (a) is a top view of the process structure after forming the recess 1009; (b) is a cross-sectional view of the structure shown along the X-axis direction parallel to that shown in (a); (c) is a cross-sectional view of the structure shown along the Y-axis direction parallel to that shown in (a).

[0340] After removing the patterned photolithography resist mask 1008, the gate region of the vertical thin-body field-effect transistor can be defined along the smooth edges of the thin silicon nitride layer 1007 and the pad silicon nitride layer 1004, and the region related to the conductive central pole in the active region 1001A can be defined. Then, etch-back is performed to form SiCOH spacer walls 1010 on the four edges within the region related to the central pole to protect the underlying original silicon region, making it a silicon surround ring (or silicon-on-surround ring) to be constructed on the central pole in the future, and it is called SRS-CP.

[0341] By using the SiCOH spacer walls 1010 and the thin silicon nitride layer 1007 as etch masks, a part of the pad oxide layer 1002 and a part of the semiconductor material corresponding to the region related to the central pole in the active region 1001A are removed to expose the silicon region, and a recess (or trench) 1011 is formed in the active region 1001A. A dielectric layer is deposited to fill the recess 1011 and form the central pole 1012, or it is called the central silicon oxide column or column pole (CP). Then, a silicon nitride layer 1013 is deposited, and etch-back is performed to form a silicon nitride capping layer 1013 above the central pole 1012. Please refer to Figure 10B , in Figure 10C Among them, (a) is a top view of the process structure after forming the silicon nitride capping layer 1013; (b) is a cross-sectional view of the structure shown along the X-axis direction parallel to that shown in (a); (c) is a cross-sectional view of the structure shown along the Y-axis direction parallel to that shown in (a).

[0342] Etch-back is performed on the shallow trench isolation region 1006 located in the defined gate region and exposed to the outside to establish a protruding semiconductor structure in the defined gate region. In one embodiment, the protruding height is the same as or substantially the same as the height of the central pole 1012. Among them, the height of the central pole 1012 is measured from the original horizontal surface (OHS) of the active region 1001A until the bottom of the central pole 1013 (as Figure 10C(as shown in (c)). Etch the silicon nitride overlay 1013 and the SiCOH spacer 1010 in the region related to the central pillar, the thin silicon nitride layer 1007, and the silicon nitride spacer 1005 covering the protruding structure (active region 1001A) located within the defined gate region. Thus, the previously defined region related to the central pillar is exposed again. Next, etch the pad oxide layer 1002 and the silicon oxide spacer 1003 covering the protruding structure in the region related to the central pillar by another etching process. A certain amount of the shallow trench isolation region 1006 outside the gate region can also be etched, and the top surface of the shallow trench isolation region 1006 is lower than the top surface of the pad silicon nitride layer 1004.

[0343] Therefore, two outer sides of the single-crystalline silicon of the protruding structure (active region 1001A) are exposed. There is a surrounding silicon ring on the central pillar (SRS-CP) 1012. Then, remove the central pillar 1012 and expose the trench 1014. In the protruding structure (active region 1001A), there are two vertical thin (silicon) bodies 1001R and 1001F for conducting current during the on-state of the vertical thin-body field-effect transistor 1000. There is a shallow trench isolation region between the two vertical thin (silicon) bodies. The vertical thin (silicon) body 1001R has an outer sidewall and an inner sidewall adjacent to the trench 1014, and the same is true for the vertical thin (silicon) body 1001F. The inner sidewall of the vertical thin (silicon) body 1001R faces the inner sidewall of the vertical thin (silicon) body 1001F within the trench 1014. In Figure 10D , (a) is a top view of the process structure after the shallow trench isolation region 1006 is etched downward; (b) is a cross-sectional view of the structure shown along the X-axis direction parallel to that shown in (a); (c) is a cross-sectional view of the structure shown along the Y-axis direction parallel to that shown in (a).

[0344] Then, form a gate dielectric material (e.g., a high-K dielectric material or silicon oxide) 1015 in the gate region. Deposit a gate conductive material 1016 (e.g., polysilicon, or a metal such as tungsten on a titanium nitride layer, or other metals with an appropriate work function) in the gate region, and then remove a part of the gate conductive material by an etch-back process. The part of the gate conductive material remaining in the trench 1014 can be referred to as the "conductive central pillar" 1016P, and the conductive central pillar 1016P is surrounded by the gate dielectric material 1015 in the trench 1014. In Figure 10E , (a) is a top view of the process structure after forming the conductive central pillar 1016P; (b) is a cross-sectional view of the structure shown along the X-axis direction parallel to that shown in (a); (c) is a cross-sectional view of the structure shown along the Y-axis direction parallel to that shown in (a).

[0345] A capping layer 1017 composed of a silicon nitride layer 1017A and a hard mask silicon oxide layer 1017B is formed on the top surface of the gate material 1016 corresponding to the gate region. Then, a portion of the pad silicon nitride layer 1004 and the pad silicon oxide layer 1002 are etched away to expose the original horizontal surface OHS of the (active region 1001A). Then, silicon oxide spacer walls 1018A and silicon nitride spacer walls 1018B are formed on the edges of the gate material 1016 and the capping layer 1017. In Figure 10F , (a) is a top view of the process structure after the formation of the silicon oxide spacer walls 1018A and the silicon nitride spacer walls 1018B; (b) is a cross-sectional view of the structure shown along the X-axis direction parallel to that shown in (a).

[0346] Then, some of the exposed silicon regions in the active region 1001A are etched away to form shallow trenches 1019 for the source and drain regions of the vertical thin film field effect transistor 1000. A silicon oxide layer 1020 is grown using a thermal oxidation process (including a silicon oxide layer 1020V that penetrates the vertical sidewalls of the shallow trenches 1019 and a silicon oxide layer 1020L located above the bottom of the shallow trenches 1019; wherein the shallow trenches 1019 are defined in the bulk body of the vertical thin film field effect transistor 1000, and this bulk body has a sharp (110) lattice direction). Based on this thermal oxidation process, the thickness of the silicon oxide layer 1020 can be very precisely controlled by precisely controlling the thermal oxidation temperature, time, and growth rate. In one embodiment, the edge of the silicon oxide layer 1020V can be aligned or substantially aligned with the edge of the gate structure.

[0347] A silicon nitride layer 1021 is formed on the top surface of the 3B-silicon oxide layer 1020 by chemical vapor deposition (CVD). Then, a metal layer 1022 including a tungsten layer 1022A and a titanium nitride (TiN) layer 1022B is deposited on the top surface of the silicon nitride layer 1021. Then, using the top surface of the titanium nitride layer 1022B as a reference body, a portion of the silicon oxide layer 1020V is etched away to expose the silicon sidewall 1001V of the active region 1001A (having a (110) lattice direction) from the shallow trenches 1019. In Figure 10G , (a) is a top view of the process structure after etching away a portion of the silicon oxide layer 1020V to expose the silicon sidewall 1001V; (b) is a cross-sectional view of the structure shown along the X-axis direction parallel to that shown in (a).

[0348] By selective epitaxial growth (SEG) technology, using the exposed silicon sidewall 1001V as a substrate, lightly doped drain regions 1023S and 1023D (e.g., the n-region of an NMOS transistor) are formed. Then, using the lateral sidewalls of the lightly doped drain regions 1023S and 1023D as a substrate, another selective growth process is used to form heavily doped source region 1024S and heavily doped drain region 1024B (e.g., the n+ region of an NMOS transistor). It should be noted that using the above method, it is not necessary to use ion implantation technology to form all the n-type lightly doped drain regions 1023S and 1023D, n+ heavily doped source region 1024S and heavily doped drain region 1024B of the vertical thin-film field-effect transistor 1000, and no additional high-temperature thermal annealing step is required to remove the damage caused by intense ion bombardment during the formation of the n+ heavily doped source region 1024S and heavily doped drain region 1024B.

[0349] Finally, a titanium nitride layer 1025A and a tungsten layer 1025B are deposited and then etched back to form a metal contact structure 1025 for the n+ heavily doped source region 1024S and heavily doped drain region 1024B. A landing pad 1026 is formed above the metal contact structure 1025 to correspondingly reduce the contact resistance. Since the shallow trench isolation region 1006 is higher than the horizontal semiconductor surface HSS, the titanium nitride layer 1025A and the tungsten layer 1025B are confined between the gate structure and the shallow trench isolation region 1006 (also between the landing pads 1026), so it is not necessary to use other masks to define the contact holes for the source / drain regions, thus completing the self-alignment process. In another embodiment, the metal contact structure 1025 and the landing pad 1026 can be formed simultaneously. Please refer to Figure 10G , in Example 6 (New Poly-cut process) , (a) is a top view of the structure of a vertical thin-film field-effect transistor 1000 used in an SRAM cell according to an embodiment of the present specification; (b) is a cross-sectional view of the structure of the vertical thin-film field-effect transistor 1000 taken along the X-axis direction parallel to that shown in (a).

[0350] A conductive center pillar 1016P is present between the vertical thin bodies 1001R and 1001F (such as fin structures) of the active region 1001A. By using an appropriate gate metal material to adjust the work function of the conductive center pillar 1016P and / or the gate conductive material, the current density in the on-state of the vertical thin body field effect transistor 1000 can be 7 times that of a conventional fin field effect transistor (not shown), and the on-current (I-on) of the vertical thin body field effect transistor 1000 of the present invention is approximately 2 times that of a conventional fin field effect transistor. It is worth noting that due to the design of the vertical thin bodies 1001R and 1001F, the novel vertical thin body field effect transistor 1000 has multiple current conduction channels. On the other hand, the current density in the off-state of a conventional fin field effect transistor is 17 times that of the vertical thin body field effect transistor 1000. The off-current (I-off) of a conventional fin field effect transistor is 34 times that of the vertical thin body field effect transistor 1000. Therefore, compared with a conventional fin field effect transistor, the vertical thin body field effect transistor 1000 of the present invention can effectively increase the current on-off ratio (I-on / I-off) by approximately 68 times.

[0351] Figure 11H

[0352] This embodiment discloses a new polysilicon cutting process for a transistor structure 1100, which has two MOS transistors T111 and T112 formed on the bases of two adjacent fin (or GAA) structures 1101F1 and 1101F2 respectively, especially used in a 6T SRAM cell structure. An exemplary manufacturing method of the transistor structure 1100 is as follows:

[0353] Define a plurality of fin structures 1101F1 and 1101F2 in a semiconductor substrate 1101, and each of the fin structures 1101F1 and 1101F2 is surrounded by fin spacer walls 1107. Please refer to FIGS. 11A(1) to 11A(3). FIG. 11A(1) is a top view of the structure after defining the fin structures 1101F1 and 1101F2 in the semiconductor substrate 1101. FIG. 11A(2) is a cross-sectional view of the structure shown along the cutting line C11A1 of FIG. 11A(1). FIG. 11A(3) is a cross-sectional view of the structure shown along the cutting line C11A2 of FIG. 11A(1). The fin structures 1101F1 and 1101F2 are defined by sub-steps S711 - S715, which are detailed as follows:

[0354] An etching process is performed using a patterned pad dielectric layer 1110 (including a patterned pad silicon oxide layer 1110A and a patterned pad silicon nitride layer 1110B) as an etching mask to remove a portion of the silicon material in the semiconductor substrate 1101, thereby forming trenches 1101T and defining a plurality of fin structures 1101F1 and 1101F2 in the semiconductor substrate 1101. In some embodiments, the distance between two adjacent fin structures 1101F1 and 1101F2 can be about 30 nanometers to 50 nanometers. The thickness of each fin structure 1101F1 and 1101F2 is approximately between 3 nanometers and 10 nanometers, for example, 5 nanometers.

[0355] A shallow trench isolation region 1108 is formed to surround the fin structures 1101F1 and 1101F2. In some embodiments of the present specification, a silicon oxide material is deposited to completely fill the trenches 1101T, and then an etch-back is performed so that the silicon oxide material remaining in the trenches 1101T can be used as the shallow trench isolation region 1108 surrounding the plurality of fin structures 1101F1 and 1101F2. Another etch-back process is performed to remove a portion of the shallow trench isolation region 1108, thereby exposing the sidewalls of the fin structures 1101F1 and 1101F2.

[0356] Next, a thermal oxidation process is performed to form silicon oxide spacer walls 1107A on the sidewalls of the fin structures 1101F1 and 1101F2; then a silicon nitride deposition process is performed to form silicon nitride spacer walls 1107B on the silicon oxide spacer walls 1107A (as shown in FIGS. 11A(2) and 11A(3)).

[0357] Thereafter, a gate opening 1102 is defined in a dielectric capping layer 1109 covering the fin structures 1101F1 and 1101F2 and the shallow trench isolation region 1108. Wherein, at least a portion of the sidewalls of each fin structure 1101F1 and 1101F2 is exposed from a corresponding gate opening 1102. Please refer to FIGS. 11B(1) to 11B(3). FIG. 11B(1) is a top view showing the structure after forming the dielectric capping layer 1109 to cover the fin structures 1101F1 and 1101F2; FIG. 11B(2) is a cross-sectional view of the structure taken along the tangent C11B1 of FIG. 11B(1); FIG. 11B(3) is a cross-sectional view of the structure taken along the tangent C11B2 of FIG. 11B(1). In this embodiment, after the silicon oxide deposition process for forming the dielectric capping layer 1109, a planarization process is performed; the dielectric capping layer 1109 includes silicon dioxide (SiO2).

[0358] Then, a patterning process is performed to remove a portion of the dielectric capping layer 1109 to define the gate opening 1102, exposing the silicon nitride spacer wall 1107B from the gate opening 1102. Then, another etching process is used to remove the silicon nitride spacer wall 1107B and the silicon oxide spacer wall 1107A respectively, so that each fin structure 1101F1 and 1101F2 is partially exposed from the gate opening 1102. Please refer to FIGS. 11C(1) to 11C(3). FIG. 11C(1) is a top view showing that the fin structures 1101F1 and 1101F2 are partially exposed from the gate opening 1102; FIG. 11C(2) is a cross-sectional view of the structure taken along the tangent line C11C1 of FIG. 11C(1); FIG. 11C(3) is a cross-sectional view of the structure taken along the tangent line C11C2 of FIG. 11C(1).

[0359] An epitaxial semiconductor material 1103 (serving as a sacrificial spacer wall) is formed on the exposed portions based on the fin structures 1101F1 and 1101F2. Please refer to FIGS. 11D(1) and 11D(2). FIG. 11D(1) is a top view showing the structure after the epitaxial semiconductor material 1103 is formed. FIG. 11D(2) is a cross-sectional view of the structure taken along the tangent line C11D1 of FIG. 11D(1). In some embodiments of the present specification, through a selective epitaxy process, an epitaxial semiconductor material 1103 (such as silicon, silicon germanium, germanium, etc.) is formed on the exposed portions of the fin structures 1101F1 and 1101F2. In some other embodiments of the present specification, other semiconductor epitaxial materials (such as gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), etc.) can be grown on the exposed portions of the fin structures 1101F1 and 1101F2. The thickness of the epitaxial semiconductor material 1103 is about 5 nanometers to 12 nanometers, for example, 7 nanometers to 8 nanometers.

[0360] Next, the gate opening 1102 is deepened to expose the semiconductor substrate 1101. Please refer to FIGS. 11E(1) and 11E(2). FIG. 11E(1) is a top view showing the structure after the gate opening 1102 is deepened to expose the semiconductor substrate 1101. FIG. 11E(2) is a cross-sectional view of the structure taken along the tangent line C11E1 of FIG. 11E(1). In some embodiments of the present specification, an etching process is performed to remove a portion of the shallow trench isolation region 1108 exposed from the gate opening 1102 and a portion of the semiconductor substrate 1101 located below the removed portion of the shallow trench isolation region 1108.

[0361] Thereafter, an interposed dielectric layer 1106 is inserted and filled in the gate opening 1102 to surround the epitaxial semiconductor material 1103 and the remaining shallow trench isolation region 1108. Please refer to FIGS. 11F(1) and 11F(2). FIG. 11F(1) is a top view of the structure showing the gate opening 1102 filled with the interposed dielectric layer 1106. FIG. 11F(2) is a cross-sectional view of the structure taken along the tangent line C11F1 of FIG. 11F(1). In some embodiments of the present specification, the material forming the interposed dielectric layer 1106 may be different from the material forming the dielectric capping layer 1109. In this embodiment, the interposed dielectric layer 1106 may be formed by a low-k dielectric material (e.g., SiCOH) deposition process. The bottom of the interposed dielectric layer 1106 (SiCOH) is lower than the bottom of the shallow trench isolation region 1108. Since the dielectric constant of the interposed dielectric layer 1106 (SiCOH) is lower than that of the shallow trench isolation region 1108, the coupling effect (as shown in FIGS. 11G(1) to 11G(3)) between the two gate structures 1104 and 1105 (formed later) can be improved. Then, the interposed dielectric layer 1106 may be etched back to expose the patterned pad silicon nitride layer 1110B from the partially filled gate opening 1102. In addition, as shown in FIG. 11F(2), the distance D4 between the two epitaxial semiconductor materials 1103 (or sacrificial spacer walls) is about 15 nm to 30 nm, for example, it can be 20 nm. The distance D4 may be equal to or substantially equal to the "gate cut" or "polysilicon cut" pitch between the two gate structures of two adjacent transistors.

[0362] Then, the epitaxial semiconductor material 1103 is removed to form a void; and the silicon nitride spacer wall 1107B and the silicon oxide spacer wall 407A are removed to expose the fin structures 1101F1 and 1101F2. Then, gate structures 1104 and 1105 are respectively formed on the fin structures 1101F1 and 1101F2. Please refer to FIGS. 11G(1) to 11G(3). FIG. 11G(1) is a top view of the structure showing the gate structures 1104 and 1105 formed; FIG. 11G(2) is a cross-sectional view of the structure taken along the tangent line C11G1 of FIG. 11G(1); FIG. 11G(3) is a cross-sectional view of the structure taken along the tangent line C11G2 of FIG. 11G(1).

[0363] To form the gate structures 1104 and 1105, gate dielectric layers 1104O and 1105O are formed to cover the tops and sidewalls of the fin structures 1101F1 and 1101F2, respectively. In some embodiments of the present specification, the gate dielectric layers 1104O and 1105O are formed via a silicon oxide deposition process. Then, gate electrodes 1104S and 1105S are formed to cover the gate dielectric layers 1104O and 1105O, respectively. In some embodiments of the present specification, the gate electrodes 1104S and 1105S are formed of polysilicon or metal. In this way, the voids formed after removing the epitaxial semiconductor material 1103 are filled with the gate dielectric layers 1104O and 1105O and the gate electrodes 1104S and 1105S.

[0364] Subsequently, as described in the previous embodiments, local isolation regions 1113 and 1123 are formed in the semiconductor substrate 1101. A source region 1111 including a lightly doped drain region (e.g., an N-semiconductor region) 1111A, an N+ semiconductor region 1111B, and a landing pad 1111C, and a drain region 1112 including a lightly doped drain region (e.g., an N-semiconductor region) 1112A, an N+ semiconductor region 1112B, and a landing pad 1112C are formed over the local isolation region 1113 and are in electrical contact with the fin (or GAA) structure 1101F1. A source region 1121 including a lightly doped drain region (e.g., an N-semiconductor region) 1121A, an N+ semiconductor region 1121B, and a landing pad 1121C, and a drain region 1122 including a lightly doped drain region (e.g., an N-semiconductor region) 1122A, an N+ semiconductor region 1122B, and a landing pad 1122C are formed over the local isolation 1123 and are in electrical contact with the fin (or GAA) structure 1101F2. Thereby, two adjacent NMOS transistors T111 and T112 with a certain gate electrode pitch P between them can be formed. Wherein, the gate electrode pitch P can be equal to the distance D4. And the distance D4 is defined by a part of the inserted dielectric layer 1106 located between the two fin structures 1101F1 and 1101F2 (as Figures 12A to 12F shown).

[0365] Since the distance D4 can be precisely controlled by depositing and etching back the inserted dielectric layer 1106, making it much smaller than the gate electrode pitch P between two adjacent MOS transistors defined by the photolithography etching process in the conventional photolithography process specifications. Therefore, the gate electrode pitch P between the two adjacent NMOS transistors T111 and T112 can be significantly scaled down. Therefore, the gate electrode pitch (or referred to as "gate cut" or "polysilicon cut" pitch) of the present invention is determined by the width of the inserted dielectric layer, rather than by the photomask used in the conventional SRAM cell structure.

[0366] The transistors provided in the above Embodiments 1 to 6 can be used to form a 6T SRAM cell structure. For example, Figures 13A to 13H is a process layout diagram showing a conventional 6T SRAM cell structure formed based on the N3 (3-nanometer) technology node. Figure 12F is a process layout diagram showing a novel 6T SRAM cell structure formed based on the NuCMOS structure.

[0367] However, the advantages and applications of Embodiments 1 to 6 are not limited thereto. The transistors and related technologies provided in the above Embodiments 1 to 6 can be applied alone or in combination to form a novel SRAM cell structure. Several actual SRAM cell structures formed by the transistors and their combinations provided in the above embodiments and their test results are listed in Tables 1 and 2. They are formed based on different technologies or process nodes (λ, also known as the minimum feature length) from λ = 16 nm (N16) to λ = 3 nm (N3). The definitions of the M1 rule, polycrystalline cutting rule, gate length, gate pitch, and NN / NP / PP pitch described herein are Figures 14A to 14D defined in detail. The SRAM cell area can be represented by λ 2 as shown.

[0368]

[0369]

[0370] As shown in Table 1, due to the better drain-induced barrier lowering (DIBL) of the vertical fin shape, the gate length and gate pitch of the fin field-effect / clad gate (GAA) transistor 800 (OpCMOS technology) and the NMOS transistor 700 (NuCMOS technology) can be reduced by 35% to 11% compared with the conventional 6T SRAM cell structure; the NN pitch (the distance between two adjacent NMOS transistors) can be reduced by 21% because they have self-aligned source / drain regions and landing pads. Additionally, compared with the SRAM cell structure applying the fin field-effect / clad gate (GAA) transistor 800 (OpCMOS technology), the SRAM cell structure applying the NMOS transistor 700 (NuCMOS technology) can reduce the cell area by 36% to 22%. This is because the diamond-shaped source / drain regions of the fin field-effect / clad gate (GAA) transistor 800 are larger than the rectangular source / drain regions of the NMOS transistor 700.

[0371] Although the SRAM cell structure adopting the "NuCMOS + UGI" technology does not have an obvious area reduction, due to the application of UGI, the SRAM cell structure can be more flexible electrically, such as in terms of power and / or heat dissipation.

[0372] In Table 2, as shown in the column of "NuCMOS+poly cut", the poly cutting rules of the fin field-effect transistor structure 1100 (Example 6) in the SRAM cell structure formed using the N16 (16 nm) to N3 (3 nm) technology nodes can be reduced to 15 nm respectively. In addition, when using the N16 (16 nm) to N3 (3 nm) technology nodes, the NP pitch (the distance between adjacent PMOS and NMOS transistors) and the NN pitch (the distance between two adjacent NMOS transistors) can be scaled down to between 70 nm and 37 nm. In addition, compared with the SRAM cell structure applying the "NuCMOS" technology in Table 1, the SRAM cell structure applying the "NuCMOS+poly cut" technology can additionally reduce the cell area.

[0373] Please refer to Table 2 again. Since the ultra-thin vertical fin shape (~2 nm) of the vertical thin-body field-effect transistor 1000 ("4CFET in NuCMOS" field) is used to form the SRAM cell structure, the gate lengths of the N16 to N3 technology nodes can be shortened to 27 nm and 10 nm respectively. Since the gate length is 10 nm, the NP pitch and the NN pitch can be scaled down to a range between 78 nm and 45 nm (for different technology nodes). In addition, compared with the traditional SRAM cell structure, the cell area of the SRAM cell structure adopting the "4CFET in NuCMOS" technology can be reduced by 55% to 39%.

[0374] It should be noted that the present invention can be applied to form other semiconductor cell structures, such as logic standard cells. For example, Figures 15A to 15E is a layout bar chart showing a series of processes for forming a new inverter cell using the "4CFET in NuCMOS" technology provided by the above embodiments; ​ is a layout bar chart showing a series of processes for forming another new inverter cell using the "4CFET in NuCMOS+UGI" technology provided by the above embodiments. Table 3 reveals the cell areas of several new inverter cell structures (Examples 8 to 10) formed based on the "4CFET in NuCMOS" technology.

[0375] Table 3

[0376]

[0377] Compared with the traditional inverter cell structure, by applying the "4CFET in NuCMOS" technology of the present invention, the cell area of the new inverter cell structure (Examples 8-11 with different technology nodes and CPP) can be significantly reduced. For the new inverter cell structure (Examples 8 and 9) adopted in the N5 technology node, the cell area can be reduced by 44% to 47% compared with the traditional inverter cell structure. For the new inverter cell structure (Examples 10 and 11) adopted in the N3 technology node, the cell area can be reduced by 55% to 47% compared with the traditional inverter cell structure.

[0378] Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the claims.

Claims

1. A semiconductor unit structure, comprising: A semiconductor substrate having an original semiconductor surface and including a first set of active regions and a second set of active regions; a shallow trench isolation region surrounding the first group of active regions and the second group of active regions; A group of PMOS transistors are respectively disposed in the first group of active regions, and each of the group of PMOS transistors includes a source region, a drain region, a gate structure, a PMOS body region and a channel region located in the PMOS body region; A group of NMOS transistors are respectively disposed in the second group of active regions, and each of the group of NMOS transistors includes a source region, a drain region, a gate structure, an NMOS body region and a channel region located in the NMOS body region; a VDD contact line electrically connected to the group of PMOS transistors; and a VSS contact line electrically connected to the group of NMOS transistors; in, A bottom surface of the source region of each of the group of PMOS transistors is isolated from the semiconductor substrate by a first local insulating region, and a bottom surface of the drain region of each of the group of PMOS transistors is isolated from the semiconductor substrate by a second local insulating region; and the first local insulating region and the second local insulating region are arranged below the original semiconductor surface; a bottom surface of the source region of each of the group of NMOS transistors is isolated from the semiconductor substrate by a third local insulating region; a bottom surface of the drain region of each of the group of NMOS transistors is isolated from the semiconductor substrate by a fourth local insulating region, and the third local insulating region and the fourth local insulating region are arranged below the original semiconductor surface.

2. The semiconductor unit structure according to claim 1, characterized in that: The PMOS body region or the NMOS body region is completely isolated from the semiconductor substrate by a local isolation body.

3. The semiconductor unit structure according to claim 1, characterized in that: A top surface of the shallow trench isolation region is higher than the original semiconductor surface, and the shallow trench isolation region surrounds the first local insulating region, the second local insulating region, the third local insulating region and / or the fourth local insulating region.

4. The semiconductor unit structure according to claim 3, characterized in that: Each of the first local insulating region, the second local insulating region, the third local insulating region, and the fourth local insulating region includes an L-shaped insulating region in a recess below the original semiconductor surface.

5. The semiconductor unit structure according to claim 4, characterized in that: The source region of a first NMOS transistor of the first group of NMOS transistors is electrically in contact with the channel region of the first NMOS transistor. The source region of the first NMOS transistor is located in the recess and includes an epitaxial lightly doped drain region extending laterally from the channel region of the first NMOS transistor and an epitaxial heavily doped region extending laterally from the epitaxial lightly doped drain region.

6. The semiconductor unit structure according to claim 5, characterized in that: A metal region is disposed in the shallow trench isolation region and the gate structure of the first NMOS transistor, and the metal region contacts a top surface and a most lateral sidewall of the source region of the first NMOS transistor.

7. The semiconductor unit structure according to claim 1, wherein: The VDD contact line or the VSS contact line is disposed below the original semiconductor surface.

8. The semiconductor unit structure according to claim 7, characterized in that: The VDD contact line is electrically connected to a first PMOS transistor in the group of PMOS transistors through a contact plug disposed in one of the first group of active regions, and a side wall of the contact plug directly contacts a side wall of the VDD contact line; Alternatively, the VSS contact line is electrically connected to a first NMOS transistor in the group of NMOS transistors through a contact plug disposed in one of the second group of active regions, and a sidewall of the contact plug directly contacts a sidewall of the VSS contact line.

9. The semiconductor unit structure according to claim 1, wherein: The invention further comprises a heat dissipation layer, which is arranged in the shallow trench isolation region and below the original semiconductor surface, wherein a thermal conductivity of the heat dissipation layer is higher than a thermal conductivity of silicon (Si).

10. The semiconductor unit structure according to claim 9, characterized in that: The heat dissipation layer surrounds the first group of active areas and / or the second group of active areas.

11. The semiconductor unit structure according to claim 10, characterized in that: The heat dissipation layer extends from a position close to the first group of active regions or the second group of active regions to another position close to the edge of the semiconductor substrate.

12. The semiconductor unit structure according to claim 1, wherein: A first PMOS transistor in the group of PMOS transistors or a first NMOS transistor in the group of NMOS transistors includes a protruding semiconductor structure having at least one trench therein, the protruding semiconductor structure includes a group of semiconductor thin bodies separated from each other, and there is no shallow trench isolation region between any two adjacent ones in the group of semiconductor thin bodies.

13. The semiconductor unit structure according to claim 10, characterized in that: A gate electrode spacing between two NMOS transistors in the group of NMOS transistors is determined by a width of a dielectric layer inserted therebetween.

14. The semiconductor unit structure according to claim 1, wherein: The semiconductor unit structure is a SRAM unit, and the SRAM unit further includes: a word line electrically connected to the set of NMOS transistors; and A bit line and a complementary bit line are electrically connected to the set of NMOS transistors; When a process node λ is 16nm, a unit area of ​​the SRAM unit is between 105 and 216λ. 2 or when the process node λ is 10nm, the cell area of ​​the SRAM cell is between 166 and 299λ 2 or when the process node λ is 7nm, the cell area of ​​the SRAM cell is between 271 and 451λ 2 or when the process node λ is 5nm, the cell area of ​​the SRAM cell is between 432 and 657λ 2 or when the process node λ is 3nm, the cell area of ​​the SRAM cell is between 1005 and 1588λ 2 between.

15. A semiconductor unit structure comprising: A semiconductor substrate having an original semiconductor surface and including a set of active regions; a shallow trench isolation region surrounding the group of active regions; a group of transistors disposed in the group of active regions, each of the group of transistors comprising a first epitaxial region, a second epitaxial region, and a gate structure located between the first epitaxial region and the second epitaxial region; and A VDD contact line and / or a VSS contact line are electrically connected to the group of transistors; in, The group of transistors includes a first transistor and a second transistor adjacent to each other; a first epitaxial region of the first transistor extends along a first direction; a first epitaxial region of the second transistor extends along the first direction; the first epitaxial region of the first transistor has a first end face, and the first epitaxial region of the second transistor has a second end face facing the first end face; the first end face is parallel or substantially parallel to the second end face.

16. The semiconductor unit structure according to claim 15, characterized in that: The first end surface and the second end surface are both perpendicular or substantially perpendicular to the original semiconductor surface.

17. The semiconductor unit structure according to claim 15, characterized in that: A top surface of the shallow trench isolation region is higher than the original semiconductor surface and surrounds three sides of the first epitaxial region of the first transistor and three sides of the first epitaxial region of the second transistor.

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