Manufacturing method of self-aligned high-voltage CMOS (complementary metal oxide semiconductor) device
By adding the overlap region between the gate and the light doped leakage in a high-voltage CMOS device and using a self-alignment process for light doped leakage ion implantation, the y-fluctuation problem caused by the non-self-alignment LDD process in the prior art is solved, and the breakdown voltage is increased and the leakage is reduced.
Patent Information
- Application Number
- CN202510379384.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-28
- Publication Date
- 2025-06-17
AI Technical Summary
In the prior art, the non-self-aligned LDD high-voltage CMOS devices have large fluctuations in y due to the process, which limits the breakdown voltage and reduces the stability of the device.
By adding the overlap region of the gate and light doped drain in a high-voltage CMOS device, a self-alignment process is used to control the morphology and inclination angle of the mask layer, light doped drain ion implantation with an inclination angle is performed to form a heavy doped region of the second conductive type.
The breakdown voltage of the device is increased, the leakage is reduced, the stability of the device is enhanced, and the fluctuation of y is reduced.
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Figure CN120166764A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a manufacturing method of a self-aligned high-voltage CMOS device. Background Art
[0002] In order to integrate more gate circuits per unit area, the process technology is becoming more and more advanced. One feature of advanced processes is that the gate material (such as polysilicon) is getting thinner. The thickness of the gate material limits the maximum energy of the self-aligned implantation of LDD (lightly doped drain) in high-voltage CMOS (such as 5V CMOS), and limits the width of the overlap region (such as Figure 1 the y dimension shown), thus limiting the breakdown voltage (BV). Increasing the overlap region between the LDD and the gate is beneficial to improving the breakdown voltage and reducing leakage.
[0003] Please refer to Figure 1 , which shows a structure of an NMOS device in the prior art, where each reference numeral is: 100 - substrate, 101 - Shallow Trench Isolation (STI), 102 - high-voltage P-type well implantation, 103 - high-voltage N-type lightly doped drain (LDD) implantation, 104 - high-voltage gate insulating dielectric layer, 105 - gate material layer, 107 - first sidewall dielectric layer, 108 - second sidewall dielectric layer, 109 - N-type heavily doped implantation; 202
[0004] —P-type well implantation, 204 - gate insulating dielectric layer, 206 - N-type LDD implantation (or N-type LDD + P-type halo / pocket implantation for ultra-shallow junctions).
[0005] Therefore, a high-voltage CMOS device with non-self-aligned LDD (i.e., moving the LDD implantation before the formation of the gate) has been developed, so that the implantation energy of the LDD is no longer limited by the thickness of the gate material, and at the same time, y is not limited by the thickness of the gate material. However, due to the non-self-aligned process, the fluctuation of y is relatively large.
[0006] To solve the above problems, a new manufacturing method of a self-aligned high-voltage CMOS device needs to be proposed. Summary of the Invention
[0007] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a manufacturing method for a self-aligned high-voltage CMOS device, which is used to solve the problem that in the prior art, a non-self-aligned LDD (i.e., moving the LDD implantation before the gate formation) high-voltage CMOS device is developed, so that the implantation energy of the LDD is no longer limited by the thickness of the gate material, and at the same time y is also not limited by the thickness of the gate material, but due to the non-self-aligned process, the fluctuation of y is relatively large.
[0008] To achieve the above object and other related objects, the present invention provides a manufacturing method for a self-aligned high-voltage CMOS device, including:
[0009] Step 1: Provide a substrate, form shallow trench isolation on the substrate to define the active regions of high-voltage CMOS and other CMOS, and form a first well region of the first conductivity type on the active region of the high-voltage CMOS and a second well region of the first conductivity type on the active region of the other CMOS by ion implantation;
[0010] Step 2: Form a first gate dielectric layer on the active region of the high-voltage CMOS and a second gate dielectric layer on the active region of the other CMOS, and form a gate polysilicon layer covering the first and second gate dielectric layers;
[0011] Step 3: Pattern the gate polysilicon layer and the first and second gate dielectric layers thereunder to form the first and second gate structures of the high-voltage CMOS and the other CMOS respectively, form a mask layer covering the other CMOS region and located on the first gate structure. From the cross-sectional structure, the mask layer located on the first gate structure is in a trapezoidal shape with a narrow top and a wide bottom, and its bottom inclination angle is θ. Use the mask layer and the first gate structure as masks to perform lightly doped drain ion implantation with an inclination angle to form a first lightly doped drain of the high-voltage CMOS. The first lightly doped drain is of the second conductivity type, so that the overlapping region between the first gate structure and the first lightly doped drain is increased;
[0012] Step 4: Remove the mask layer, form a first sidewall on the sidewalls of the first and second gate structures, form a photoresist layer covering the first and second gate structures, open the photoresist layer on the other CMOS region by lithography, and form a second lightly doped drain of the other CMOS by ion implantation;
[0013] Step 5: Remove the photoresist layer and form a second sidewall on the first sidewall on the sidewalls of the first and second gate structures;
[0014] Step 6: Selectively form a heavily doped region of the second conductivity type on the first lightly doped drain and the second lightly doped drain.
[0015] Preferably, the substrate in Step 1 is a silicon substrate.
[0016] Preferably, the first conductivity type is P-type and the second conductivity type is N-type.
[0017] Preferably, the first conductivity type is N-type and the second conductivity type is P-type.
[0018] Preferably, the second gate dielectric layer in step two is an oxide layer formed by thermal oxidation, chemical vapor deposition or atomic layer deposition.
[0019] Preferably, the first and second gate structures are formed by photolithography and dry etching in step three.
[0020] Preferably, the mask layer in step three is a patterned photoresist layer.
[0021] Preferably, the mask layer in step three is a patterned hard mask layer.
[0022] Preferably, the bottom tilt angle θ in step three is greater than or equal to 30° and less than 90°.
[0023] Preferably, the implantation angle of the tilted lightly doped drain ion implantation in step three is 15 - 45°.
[0024] Preferably, the second lightly doped drain is formed by lightly doped drain implantation in step six.
[0025] Preferably, in step six, it is formed by lightly doped drain implantation of the second conductivity type of ultra-shallow junction and halo and pocket implantation of the first conductivity type.
[0026] As described above, the manufacturing method of the self-aligned high-voltage CMOS device of the present invention has the following beneficial effects:
[0027] By increasing the size of the overlapping region between the gate and the lightly doped drain of the high-voltage CMOS device, the present invention improves the breakdown voltage of the device and reduces the leakage current. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 Schematic diagram of the NMOS device structure shown as the prior art;
[0029] Figure 2 Schematic diagram of the process flow of the present invention;
[0030] Figure 3 Schematic diagram of forming the first and second well regions of the present invention;
[0031] Figure 4 Schematic diagram of forming the first and second gate dielectric layers and gate polysilicon layers of the present invention;
[0032] Figure 5 Schematic diagram showing the formation of a mask layer according to the present invention;
[0033] Figure 6 Schematic diagram showing the formation of a second lightly doped drain of other CMOS according to the present invention;
[0034] Figure 7 Schematic diagram showing the formation of a second sidewall according to the present invention;
[0035] Figure 8 Schematic diagram showing the formation of a heavily doped region according to the present invention;
[0036] Figure 9 Schematic diagram showing the impact ionization of a device according to the present invention;
[0037] Figure 10 Schematic diagram showing the simulation of the breakdown voltage curve of a device according to the present invention. Detailed implementation manners
[0038] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0039] Please refer to Figure 2 , the present invention provides a manufacturing method for a self-aligned high-voltage CMOS device, including:
[0040] Step 1: Provide a substrate 100, form a shallow trench isolation 101 on the substrate 100 to define the active regions of high-voltage CMOS and other CMOS, and use ion implantation to form a first well region 102 of a first conductivity type on the active region of high-voltage CMOS and a second well region 202 of the first conductivity type on the active region of other CMOS, forming a structure as shown in Figure 3 ;
[0041] In some embodiments, the substrate 100 in Step 1 is a silicon substrate.
[0042] In some embodiments, the first conductivity type is P-type and the second conductivity type is N-type, or the first conductivity type is N-type and the second conductivity type is P-type.
[0043] Step 2: Form a first gate dielectric layer 104 on the active region of high-voltage CMOS and a second gate dielectric layer 204 on the active region of other CMOS, form a gate polysilicon layer 105 covering the first and second gate dielectric layers, forming a structure as shown in Figure 4 ;
[0044] In some embodiments, the second gate dielectric layer 204 in step two is an oxide layer formed by thermal oxidation, chemical vapor deposition, or atomic layer deposition. The first and second gate dielectric layers may first form the first gate dielectric layer 104, and then use photolithography and etching methods to retain it on the active region of the high-voltage CMOS. After that, the second gate dielectric layer 204 is formed, and then use photolithography and etching methods to retain it on the active region of other CMOSs.
[0045] Step three: Pattern the gate polysilicon layer 105 and the first and second gate dielectric layers thereunder to form the first and second gate structures of the high-voltage CMOS and other CMOSs respectively. A mask layer 501 covering the other CMOS region and located on the first gate structure is formed. Observed from the cross-sectional structure, the mask layer 501 located on the first gate structure has a trapezoidal morphology that is narrow at the top and wide at the bottom, and the bottom tilt angle is θ. Using the mask layer 501 and the first gate structure as masks, perform lightly doped drain ion implantation with an inclined angle to form the first lightly doped drain 103 of the high-voltage CMOS. The first lightly doped drain 103 is of the second conductivity type, so that the overlapping region between the first gate structure and the first lightly doped drain 103 is increased, forming a structure as Figure 5 shown;
[0046] In some embodiments, in step three, the first and second gate structures are formed by using photolithography and dry etching methods.
[0047] In some embodiments, the mask layer 501 in step three is a patterned photoresist layer. The photoresist layer has a trapezoidal morphology that is narrow at the top and wide at the bottom, and the bottom tilt angle is θ, which can be formed by controlling photolithography parameters.
[0048] In some embodiments, the mask layer 501 in step three is a patterned hard mask layer. Its material can be a hard mask material such as a nitride layer or an oxide layer. The hard mask layer has a trapezoidal morphology that is narrow at the top and wide at the bottom, and the bottom tilt angle is θ, which can be formed by controlling etching parameters.
[0049] In some embodiments, the bottom tilt angle θ in step three is greater than or equal to 30° and less than 90°, for example, 45°.
[0050] In some embodiments, the implantation angle of the lightly doped drain ion implantation with an inclined angle in step three is 15 to 45°.
[0051] Step 4. Remove the mask layer 501. If the material of the mask layer 501 is a photoresist layer, it can be removed by ashing process or wet cleaning method. If the material of the mask layer 501 is a hard mask material such as a nitride layer or an oxide layer, it can be removed by wet etching method, forming the first spacer 107 on the sidewalls of the first and second gate structures. The first spacer 107 can be formed by deposition and re-etching methods, forming a photoresist layer covering the first and second gate structures, lithographically opening the photoresist layer on other CMOS regions, and forming the second lightly doped drain 206 of other CMOS by ion implantation, forming a structure as shown in Figure 6 shown;
[0052] Step 5. Remove the photoresist layer 502, and form a second spacer 108 on the first spacer 107 on the sidewalls of the first and second gate structures. The second spacer 108 can be formed by deposition and re-etching methods, forming a structure as shown in Figure 7 shown;
[0053] Step 6. Selectively form a heavily doped region 109 of the second conductive type on the first lightly doped drain 103 and the second lightly doped drain 206, forming a structure as shown in Figure 8 shown.
[0054] In some embodiments, the second lightly doped drain 206 is formed by lightly doped drain implantation in Step 6.
[0055] In some embodiments, it is formed by ultra-shallow junction second conductive type lightly doped drain implantation and first conductive type halo and pocket implantation in Step 6.
[0056] Please refer to Figure 9 , which shows the impact ionization diagram of the device obtained by the present invention. When θ is 45°, the y value at the channel surface increases by 100%.
[0057] Please refer to Figure 9 , which shows the breakdown voltage simulation curve diagram of the device obtained by the present invention. The breakdown voltage increases by about 1V, and the leakage current decreases by about one order of magnitude.
[0058] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, number, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.
[0059] In summary, the present invention increases the size of the overlapping region between the gate and the lightly doped drain of the high-voltage CMOS device, improves the breakdown voltage of the device, and reduces the leakage current. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.
[0060] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.
Claims
1. A method for manufacturing a self-aligned high-voltage CMOS device, characterized in that: At least: Step 1, providing a substrate, forming shallow trench isolation on the substrate to define active areas of the high-voltage CMOS and other CMOS, forming a first well region of a first conductivity type on the active area of the high-voltage CMOS, and forming a second well region of the first conductivity type on the active area of the other CMOS by ion implantation; Step 2: forming a first gate dielectric layer on the active area of the high voltage CMOS, forming a second gate dielectric layer on the active area of the other CMOS, and forming a gate polysilicon layer covering the first and second gate dielectric layers; Step 3: patterning the gate polysilicon layer and the first and second gate dielectric layers thereunder to form first and second gate structures of high-voltage CMOS and other CMOS respectively, forming a mask layer covering other CMOS regions and located on the first gate structure, wherein from the cross-sectional structure, the mask layer located on the first gate structure is a trapezoidal morphology that is narrow at the top and wide at the bottom, and the bottom inclination angle is θ, and using the mask layer and the first gate structure as masks to perform lightly doped drain ion implantation with an inclination angle to form a first lightly doped drain of the high-voltage CMOS, wherein the first lightly doped drain is of the second conductivity type, so that the overlapping area between the first gate structure and the first lightly doped drain is increased; Step 4: removing the mask layer, forming a first sidewall spacer located on the sidewalls of the first and second gate structures, forming a photoresist layer covering the first and second gate structures, photolithographically opening the photoresist layer on other CMOS regions, and forming a second lightly doped drain of other CMOS by ion implantation; Step 5, removing the photoresist layer, and forming a second sidewall on the first sidewall of the first and second gate structure sidewalls; Step six: selectively forming a heavily doped region of the second conductivity type on the first lightly doped drain and the second lightly doped drain.
2. The method for manufacturing a self-aligned high voltage CMOS device according to claim 1, characterized in that: The substrate in step one is a silicon substrate.
3. The method for manufacturing a self-aligned high voltage CMOS device according to claim 1, characterized in that: The first conductivity type is P type, and the second conductivity type is N type.
4. The method for manufacturing a self-aligned high voltage CMOS device according to claim 1, characterized in that: The first conductivity type is N type, and the second conductivity type is P type.
5. The method for manufacturing a self-aligned high voltage CMOS device according to claim 1, characterized in that: The second gate dielectric layer in step 2 is an oxide layer formed by thermal oxidation, chemical vapor deposition or atomic layer deposition.
6. The method for manufacturing a self-aligned high voltage CMOS device according to claim 1, characterized in that: In step three, the first and second gate structures are formed by photolithography and dry etching.
7. The method for manufacturing a self-aligned high voltage CMOS device according to claim 1, characterized in that: The mask layer in step three is a patterned photoresist layer.
8. The method for manufacturing a self-aligned high voltage CMOS device according to claim 1, characterized in that: The mask layer in step three is a patterned hard mask layer.
9. The method for manufacturing a self-aligned high voltage CMOS device according to claim 1, characterized in that: The bottom inclination angle θ in step three is greater than or equal to 30° and less than 90°.
10. The method for manufacturing a self-aligned high voltage CMOS device according to claim 1, characterized in that: The implantation angle of the lightly doped drain ion implantation with an inclined angle in step three is 15-45°.
11. The method for manufacturing a self-aligned high voltage CMOS device according to claim 1, characterized in that: In step six, the second lightly doped drain is formed by a lightly doped drain implantation method.
12. The method for manufacturing a self-aligned high voltage CMOS device according to claim 1, characterized in that: In step six, the ultra-shallow junction is formed by lightly doped drain injection of the second conductivity type and halo and pocket injection of the first conductivity type.