Using the least reliable bit energy function in bit flipping decoder to bypass iteration

Abstract

A bit flip decoder receives a codeword stored in a memory device. The bit flip decoder determines a plurality of energy function values for the codeword and a least reliable one of the energy function values for the codeword. In response to the bit flip decoder determining that the least reliable energy function value fails to satisfy a bit flip criterion for a current iteration, the bit flip decoder increments an iteration count. The incrementing of the iteration count bypasses a comparison of the plurality of energy function values to the bit flip criterion for the current iteration.

Description

Technical Field

[0001] This disclosure generally relates to error correction in memory devices, and more specifically, to bit-flip decoders using the least reliable bit energy function value to bypass one or more decoding iterations. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Attached Figure Description

[0003] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are for explanation and understanding only.

[0004] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0005] Figure 2 This is a flowchart of an example method, according to some embodiments of the present disclosure, of using the least unreliable bit energy function value to provide bit flipping to bypass one or more decoding iterations.

[0006] Figure 3 A block diagram illustrating an exemplary table containing the maximum energy function value and bit-flipping threshold for iteration of a bit-flipping decoder, according to some embodiments.

[0007] Figure 4 This is a flowchart of another instance method, according to some embodiments of the present disclosure, of using the least unreliable bit energy function value to provide bit flipping to bypass one or more decoding iterations.

[0008] Figure 5 This is a block diagram of an example computer system in which embodiments of this disclosure may be operated. Detailed Implementation

[0009] This disclosure relates to a bit-flip decoder using the least reliable bit energy function value to bypass one or more decoding iterations in a memory subsystem. The memory subsystem may be a storage device, a memory module, or a hybrid of a storage device and a memory module. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0010] Memory devices can be non-volatile memory devices. A non-volatile memory device is a package of one or more dies. One example of a non-volatile memory device is a NAND flash memory device. Other examples of non-volatile memory devices are described below. Figure 1 The following description is provided. A die within a package can be assigned one or more channels for communication with the memory subsystem controller. Each die can consist of one or more planes. Planes can be divided into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND memory devices), each plane consists of a set of physical blocks, which are groups of memory cells used to store data. A cell is an electronic circuit that stores information.

[0011] Depending on the cell type, a cell can store one or more binary information bits and has various logical states related to the number of bits stored. Logical states can be represented by binary values ​​such as "0" and "1" or combinations of such values. Various types of cells exist, such as single-level cells (SLC), multi-level cells (MLC), three-level cells (TLC), and four-level cells (QLC). For example, an SLC can store one information bit and has two logical states.

[0012] Low-density parity-check (LDPC) codes are commonly used for error correction in memory subsystems. LDPC codes are a class of efficient linear block codes that incorporate single-parity (SPC) codes. LDPC codes offer high error correction capabilities and performance approaching Shannon channel capacity. LDPC decoders utilize a "belief propagation" algorithm, which is an iterative exchange of reliability information based on, for example, "belief levels." The Minimum Sum Algorithm (MSA) (a simplified version of the belief propagation algorithm) can be used to decode LDPC codes. MSA-based decoders use relatively high energy per bit (e.g., per picojoule) to decode codewords and are therefore less suitable for energy-efficient applications, such as mobile applications.

[0013] Bit-flipping (BF) decoders have been introduced to address this issue. Compared to MSA-based decoders, BF decoders use less energy per bit at the cost of lower error correction capability. In each decoding iteration, the BF decoder evaluates each bit and flips the least reliable bit to correct errors. The least reliable bit is identified by comparing a threshold to the energy function value of each bit. The bit-flipping threshold can be determined, for example, based on a heuristic process and / or optimized using machine learning algorithms. Furthermore, the bit-flipping threshold can vary between decoding iterations. For a given iteration, comparing the energy function of each bit to the bit-flipping threshold may not result in any bit flips. In other words, while one or more bits may be erroneous, no bit is eligible for flipping using the bit-flipping threshold of the current iteration. These "flip-free iterations" lead to longer decoding times and lower decoder throughput.

[0014] This disclosure addresses the aforementioned and other drawbacks by utilizing the least reliable bit energy function value of the codeword and bypassing one or more iterations of the bit-flip decoding process when the least reliable bit energy function value does not satisfy a bit-flip threshold. The bit-flip decoder can, for example, iterate using a bit-flip threshold satisfied by the least reliable bit energy function value, resulting in the decoder flipping one or more bits in the codeword. Therefore, the bit-flip decoder can improve latency and reduce power consumption during the decoding process.

[0015] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0016] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0017] The computing system 100 may be, for example, a desktop computer, a laptop computer, a web server, a mobile device, a vehicle (such as an airplane, drone, train, car or other means of transport), a device with Internet of Things (IoT) capabilities, an embedded computer (such as an embedded computer contained in a vehicle, industrial equipment or networked commercial device), or a computing device containing memory and processing devices.

[0018] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediary component), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0019] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and to read data from the memory subsystem 110.

[0020] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include (but are not limited to) Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect Fast (PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Double Data Rate (DDR) memory bus, Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM slot interfaces supporting Double Data Rate (DDR)), Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can further utilize NVM Fast (NVMe) interface access components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data and other signals between the memory subsystem 110 and the host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0021] Memory devices 130 / 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (such as memory device 140) may be (but are not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0022] Examples of non-volatile memory devices (such as memory device 130) include NAND flash memory and in-situ write memory, such as a three-dimensional crosspoint (“3D crosspoint”) memory device that is an array of crosspoints of non-volatile memory cells. The crosspoint array of non-volatile memory can perform bit storage based on changes in volume resistance combined with a stackable cross-gate format data access array. Therefore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-situ write operations, where non-volatile memory cells can be programmed without prior erasing of the non-volatile memory cells. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0023] Although a non-volatile memory device, such as a NAND-type memory (e.g., 2D NAND, 3D NAND) and a 3D cross-point array of non-volatile memory cells, is described, the memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), selectable memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0024] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations (e.g., in response to commands scheduled on the command bus by the controller 115). The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-coded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0025] The memory subsystem controller 115 may include a processing means 117 (processor) configured to execute instructions stored in local memory 119. In the illustrative example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines for controlling the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0026] In some embodiments, local memory 119 may include memory registers for storing memory pointers, fetch data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although already... Figure 1 The instance memory subsystem 110 is described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem 110).

[0027] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to memory devices 130 and / or 140. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling operations, discard item collection operations, error detection and error correction code (ECC) operations, encryption operations, caching operations, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access memory devices 130 and / or 140 and translate responses associated with memory devices 130 and / or 140 into information for the host system 120.

[0028] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive and decode addresses from the memory subsystem controller 115 to access the memory device 130.

[0029] In some embodiments, memory device 130 includes a local media controller 135, which operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a native memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0030] The memory subsystem 110 includes an error corrector 113 (e.g., an encoder and / or decoder) capable of encoding and decoding data stored in the memory device. In some embodiments, the controller 115 includes at least a portion of the error corrector 113. For example, the controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the error corrector 113 is part of the host system 120, an application, or an operating system.

[0031] Encoding data using error correction codes (ECC) allows for the correction of erroneous data bits as data is retrieved from a memory device. For example, error corrector 113 may encode data received from host system 120 and store the data and parity bits as codewords in memory device 130. Error corrector 113 may further decode the data stored in memory device 130 to identify and correct erroneous bits in the data, and then transmit the corrected data to host system 120. Although described as a single component capable of performing data encoding and decoding, error corrector 113 may be / comprise a separate component. In some embodiments, error corrector 113 encodes data according to low-density parity check (LDPC) codes.

[0032] Error corrector 113 uses a BF decoder to decode codewords stored in memory device 130. For example, error corrector 113 receives codewords stored in memory device 130. Error corrector 113 performs error correction on the codeword in a set of iterations, for example by flipping bits using the bit energy function value in one or more iterations. The energy function value of the codeword bit is an indicator of the reliability of the codeword bit. In some embodiments, the energy function value of the codeword bit is determined based on the number of parity violations per codeword bit and channel information. Channel information is determined based on the current state of the bit (e.g., after one or more iterations of the BF decoder) and the state of the bit read from the memory device (also called a hard bit). As described below, error corrector 113 implements an enhanced BF decoder that can use the least reliable bit energy function value to perform bit-flipping decoding to efficiently bypass one or more decoding iterations. Further details regarding the operation of error corrector 113 are described below.

[0033] Figure 2 This is a flowchart of an example method 200, according to some embodiments of the present disclosure, of using the least reliable bit energy function value to provide bit flips to bypass one or more decoding iterations. Method 200 may be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 200 is performed by… Figure 1 Error corrector 113 is executed. Although shown in a specific sequence or order, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0034] At operation 205, the processing device receives a codeword from the memory device. In some embodiments, the codeword is received from the host system 120 during a read operation. The codeword may contain a combination of data bits and parity bits. For example, each of the data bits and parity bits is a hard bit generated by reading a memory cell to determine the state of the memory cell (e.g., "0" or "1"). Additionally, each data bit may be verified by multiple parity bits.

[0035] In one embodiment, the processing device optionally receives soft information about codewords. In addition to the bits of the codewords, the soft information may also include bits received from a memory device. In some embodiments, the memory device is operable to determine soft information for a hard read. In other embodiments, the memory device does not generate and transmit soft information to the processing device. In some embodiments, the memory device generates soft information for some, but not all, of the codewords it transmits and transmits the soft information to the processing device. The soft information may indicate confidence about hard data bits. For example, the soft information may indicate a high confidence level about hard data bits, and the hard data bits may be referred to as strong bits. Alternatively, the soft information may indicate a low confidence level about hard data bits, and the hard data bits may be referred to as weak bits.

[0036] In some embodiments, soft information indicates a specific voltage to which a memory cell is charged (where the memory cell is the memory cell from which hard data bits are read). In these embodiments, hard data bits are less reliable (i.e., weak bits) when their associated soft information indicates that the memory cell is charged to a specific voltage near the boundary between two states; and hard data bits are more reliable (i.e., strong bits) when their associated soft information indicates that the memory cell is charged to a specific voltage near the center of the voltage range corresponding to the state ("0" or "1").

[0037] In some embodiments, for each hard data bit of a codeword, the soft information includes at most one soft bit. The soft bit of a hard data bit indicates whether the hard data bit is strong or weak. For example, a soft bit can be "0" when its associated hard data bit is weak and "1" when its associated hard data bit is strong. In some embodiments, the number of bits of the soft information of a codeword is strictly less than the number of bits of the codeword. For example, the processing device can receive an index of a strong bit in the codeword. Alternatively, the processing device can receive an index of a weak bit in the codeword to reduce the amount of information transmitted from the memory device 130 to the error corrector 113. In some embodiments, for each hard data bit of a codeword, the soft information includes more than one soft bit. For example, when the soft information includes two soft bits, this results in four reliability levels for the bit, such as very weak, weak, strong, and very strong.

[0038] At operation 210, the processing device determines the energy function value of the bits of the codeword. The energy function of the codeword bits is an indication of the reliability information of the bits. Error corrector 113 may determine the energy function value of the bits of the codeword based on the number of unsatisfied parity checks of the bits and the channel information of the bits. In some embodiments, a higher number of unsatisfied parity checks of a bit indicates a less reliable bit and results in a higher energy function value for the bit. Similarly, a lower number of unsatisfied parity checks of a bit (a higher number of satisfied parity checks) indicates a more reliable bit and results in a lower energy function value for the bit. The channel information is determined based on the current state of the bit compared to the state of the bit when it is read from the memory device. For example, the channel information of a bit may be defined as the XOR of the current state of the bit (which may have been flipped during one or more decoding iterations) with the bit read from the memory device. In this example, the channel information has a value of "1" when there is a mismatch and a value of "0" when the current state of the bit matches the state when the bit is read. When the current state of the bit matches the state when the bit is read from the memory device, the bit is considered more reliable. In the unrestricted instance, the energy function can be determined according to equation (1):

[0039] e (bit) = Number of parity violations (bits) + Channel information (bits) (1)

[0040] The bit energy function value is lower when the current state of the bit matches the hard bit, compared to when the current state of the bit does not match the hard bit received from the memory device. In one embodiment, the error corrector 113 determines the energy function value by retrieving the bit energy function value of the codeword from a lookup table based on the number of parity violations of the bit and the channel information of the bit.

[0041] Additionally, the error corrector 113 can use soft information to determine the energy function. Continuing with the above example values ​​where "1" is the soft value for a strong bit and "0" is the soft value for a weak bit, the energy function can be, for example, by subtracting the soft value from the number of parity violations plus the channel information.

[0042] Similarly, in the above examples, higher e(bit) values ​​indicate less reliable bits and lower e(bit) values ​​indicate more reliable bits. In other embodiments, a high energy function value for a bit indicates a more reliable bit and a low energy function value for a bit indicates a less reliable bit. In this embodiment, the energy function can be determined, for example, by adding the number of parity checks that have been satisfied to a negative number of the channel information value. In some embodiments, the error corrector 113 uses a scalar value and / or a weighted value plus parity and channel information to determine the energy function value. For example, different rows, columns, or other dissimilar locations within the memory can be determined as more reliable or less reliable. Therefore, the error corrector 113 can scale or weight the energy function values ​​of bits in these locations.

[0043] In addition to determining the energy function value of each bit, the processing device also flips those bits that satisfy the bit-flipping criterion of the bit-flipping decoder's iteration. For example, error corrector 113 evaluates each bit of the codeword by comparing its energy function value with the bit-flipping criterion of the current iteration to determine whether to flip the bit. When the energy function value of a bit in the codeword does not satisfy the bit-flipping criterion, error corrector 113 does not flip the bit. When the energy function value of a bit in the codeword satisfies the bit-flipping criterion, error corrector 113 flips the bit. The bit-flipping criterion may also be referred to herein as a bit-flipping or energy function value threshold. When the energy function value of a bit satisfies the threshold, error corrector 113 determines to flip the bit. For example, error corrector 113 may flip a bit when the bit's energy function value is greater than or equal to the threshold and not flip a bit when the bit's energy function value is less than the threshold.

[0044] At operation 215, the processing apparatus iteratively determines the energy function value of the least reliable bit in the codeword for the initial decoder. For example, when a higher energy function value indicates a less reliable bit, error corrector 113 determines the maximum value of the energy function value of the codeword. In one embodiment, error corrector 113 uses a first energy function value as an initial maximum value, compares each determined current energy function value with the maximum value, and updates the maximum value when a current energy function value exceeds the maximum value (e.g., when the energy function value is determined in operation 210).

[0045] When the processing device flips a bit in operation 210, it updates the energy function value of the codeword. For example, flipping one or more bits of the codeword can change the number of unsatisfied parity checks and / or channel information of the codeword. Therefore, the error corrector 113 determines the new energy function value of the bit. In one embodiment, the error corrector 113 only determines the updated energy function values ​​of the bits affected by the flipping of one or more bits and bypasses the determination of the energy function values ​​of bits whose energy function values ​​do not change. If applicable, the error corrector 113 also determines the updated value (e.g., the new maximum value) of the least reliable energy function value.

[0046] Additionally, the processing device increments the iteration count to proceed to the next iteration. As further described below, the bit-flipping criterion may differ between iterations. Error corrector 113 can use the current iteration count to find or otherwise determine the current bit-flipping criterion. Furthermore, error corrector 113 can use the iteration count to determine whether a stopping criterion has been met.

[0047] At operation 220, at the start of the current decoder iteration (i), the processing device determines whether the least reliable energy function value from the previous decoder iteration (i-1) satisfies the bit-flipping criterion for the current iteration of the bit-flipping decoding process. For example, when the maximum value of the energy function value of the codeword from the previous iteration (i-1) is greater than or equal to the bit-flipping criterion, the error corrector 113 determines that at least one bit in the codeword will be flipped in the current iteration. On the other hand, when the maximum value of the energy function value of the codeword from the previous iteration (i-1) is less than the bit-flipping criterion, the error corrector 113 determines that no bit will be flipped in the current iteration. When the least reliable energy function value satisfies the bit-flipping criterion, method 200 proceeds to operation 225 to flip one or more bits in the current iteration of the decoding process. When the least reliable energy function value fails to satisfy the bit-flipping criterion, the error corrector 113 has determined that no bit will be flipped, bypassing the comparison of other energy function values ​​of the codeword with the bit-flipping criterion, and method 200 proceeds to operation 235.

[0048] At operation 225, when the energy function value of a given bit of the codeword satisfies the bit-flipping criterion, the processing device flips one or more bits of the codeword. For example, similar to the description of operation 210, error corrector 113 can traverse the codeword in a predetermined order and evaluate each bit of the codeword by comparing its energy function value with the bit-flipping criterion of the current iteration to determine whether to flip the bit. When the energy function value of a bit of the codeword does not satisfy the bit-flipping criterion, error corrector 113 does not flip the bit. When the energy function value of a bit of the codeword satisfies the bit-flipping criterion, error corrector 113 flips the bit.

[0049] At operation 230, the processing device updates the energy function value of the codeword. For example, flipping one or more bits of the codeword can change the number of unsatisfied parity checks and / or channel information of the codeword. Therefore, error corrector 113 determines the new energy function value of the bit. In one embodiment, error corrector 113 only determines the updated energy function value of those bits affected by the flipping of one or more bits and bypasses the determination of the energy function value of bits whose energy function value does not change. If applicable, error corrector 113 also determines the updated value of the least reliable energy function value (e.g., the new maximum value). Therefore, error corrector 113 tracks the energy value of the least reliable bit in each iteration and uses this energy function in one or more subsequent iterations to determine whether to skip an iteration (bypassing the comparison of other energy function values ​​of the codeword with the bit flipping criterion).

[0050] At operation 235, the processing device increments / increments the iteration count. As further described below, the bit flip criterion may differ between iterations. Error corrector 113 may use the current iteration count to find or otherwise determine the current bit flip criterion. Additionally, error corrector 113 may use the iteration count to determine whether a stopping criterion has been met.

[0051] At operation 240, the processing device determines whether a stopping criterion is met. The stopping criterion may include an indication that no errors were detected in the codeword. In some embodiments, the stopping criterion may include a null parity check (i.e., zero unmet parity checks), indicating that the codeword no longer contains error bits. In some embodiments, the stopping criterion may include a maximum number of iterations or a maximum time duration. For example, error corrector 113 may be operable to perform a maximum number of iterations (e.g., 30 iterations, 40 iterations, 100 iterations, etc.), and when this number of iterations is reached, error corrector 113 outputs the resulting corrected codeword. When the stopping criterion is not met, error corrector 113 performs another iteration. For example, when the stopping criterion is not met, method 200 returns to operation 220, and error corrector 113 determines whether the least reliable energy function value satisfies the bit-flipping criterion for the next iteration, which may differ between iterations (as further described below). When the stopping criterion is met, method 200 proceeds to operation 245.

[0052] At operation 245, the processing device outputs a correction codeword or a failure indication if it is unable to decode the codeword. For example, error corrector 113 may transmit the correction codeword or failure indication to host 120. In one embodiment, the failure indication triggers an escalation of the decoding process. For example, error corrector 113 may use an MSA decoder to decode the codeword in response to a BF decoder failure.

[0053] Figure 3 This is a block diagram illustrating, according to some embodiments, an exemplary table 300 containing the least reliable / maximum energy function values ​​and bit-flipping criteria for iteration of a bit-flipping decoder. Although Figure 3 This section describes specific instances of iterative counting, the maximum energy function value, and the bit-flip criterion, but these instances should be understood as examples only. Other mappings of iterative counting to the bit-flip criterion are possible.

[0054] Table 300 contains an iteration count 305 from 0 to N, an instance maximum energy function value 310 for each iteration, and a bit flip criterion 315 for each iteration. As described above, error corrector 113 determines the bit energy function value based on the number of unsatisfied parity checks associated with it and channel information. Using the determined energy function value, the processing device determines the most unreliable bit / energy function value 310 (e.g., the maximum energy function value) of the previous iteration (i-1), which will be used in the current iteration (i) to determine whether to bypass the comparison of other energy function values ​​with the bit flip criterion of the current iteration (i). Error corrector 113 may make this determination in the current iteration, as indicated by iteration count 305, or in the previous iteration. In one embodiment, error corrector 113 uses table 300 or another data structure to map the current iteration count 305 to the corresponding bit flip criterion 315. For example, error corrector 113 may store and maintain a copy of table 300 in memory devices 130 / 140 and / or local memory 119.

[0055] Using the instance values ​​in Table 300, the maximum energy function value 310 satisfies (e.g., is greater than) the bit-flipping criterion 315 in iterations 0, 1, and 2. In each of these iterations, the error corrector 113 compares the codeword's energy function value with the bit-flipping criterion and thus flips one or more bits. However, when iteration count 305 reaches iteration 3, the maximum energy function value 310 does not satisfy the bit-flipping criterion 315 (e.g., 4 is less than 5). As described above, the maximum energy function value 310 of iteration 3 corresponds to the maximum energy function value calculated in iteration 2 for iteration 3. Therefore, the error corrector 113 bypasses the comparison of the codeword energy function value (except for the maximum value) with the bit-flipping criterion and continues to the next iteration. The value of the bit-flipping criterion 315 decreases in iteration 4 compared to iteration 3. In some embodiments, the maximum energy function value 310 being equal to the bit-flipping criterion 315 is determined to satisfy the bit-flipping criterion 315. In other embodiments, the maximum energy function value 310 is determined to be equal to the bit flip criterion 315 as not satisfying the bit flip criterion 315 and the iteration continues to bypass comparing the energy function value with the bit flip criterion 315 until the maximum energy function value 310 exceeds the bit flip criterion 315, for example in iteration 5.

[0056] Figure 4 This is a flowchart of another example of a method 400, which uses the least reliable bit energy function value to provide bit flips to bypass one or more decoding iterations according to some embodiments of this disclosure. Method 400 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, special-purpose logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions running or executed on the processing device), or a combination thereof. In some embodiments, method 400 is performed by… Figure 1Error corrector 113 is executed. Although shown in a specific sequence or order, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0057] At operation 405, the processing device receives a codeword from the memory device. As described with reference to operation 205, the codeword may be received from the host system 120 during a read operation and contains a combination of data bits and parity bits.

[0058] At operation 410, the processing device determines the energy function value of the bits of the codeword. For example, the processing device may use one or more of the following to determine the energy function value of the bit: the number of unsatisfied parity checks of the bits of the codeword, the channel information of the bit, optional soft information, and / or the weight / scalar of the bit's position in the memory device 130, as described with reference to operation 210.

[0059] At operation 415, the processing device determines the energy function value of the least reliable bit in the codeword. For example, the processing device determines the maximum value among the energy function values ​​of the codeword, as described with reference to operation 215.

[0060] At operation 420, the processing unit determines that the least reliable energy function value fails to meet the bit-flipping criterion for the current iteration of the bit-flipping decoding process. For example, error corrector 113 maps the current iteration count to the bit-flipping criterion, as referenced. Figure 3 The description compares the least reliable energy function value with the bit flip criterion, as described in operation 220 above.

[0061] At operation 425, the processing device increments / increments the iteration count in response to determining that the least reliable energy function value fails to meet the bit-flip criterion for the current iteration. As described above, the error corrector 113 saves processing power and time by bypassing comparisons of other energy function values ​​of the codeword with the bit-flip criterion and continuing to the next iteration.

[0062] Figure 5 This describes an example machine of computer system 500, within which a set of instructions is executable to cause the machine to perform any or more of the methodologies discussed herein. In some embodiments, computer system 500 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., a memory subsystem). Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., to execute an operating system to perform operations corresponding to...). Figure 1(Operation of error corrector 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer-to-peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0063] A machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by the machine. Furthermore, while a single machine is described, the term "machine" should also be considered as any collection of machines that individually or jointly execute a set (or more) of instructions to perform any or more of the methodologies discussed herein.

[0064] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.) and a data storage system 518, which communicate with each other via a bus 530.

[0065] Processing device 502 represents one or more general-purpose processing devices, such as a microprocessor, central processing unit, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or multiple processors implementing combinations of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 500 may further include a network interface device 508 for communication via network 520.

[0066] Data storage system 518 may include machine-readable storage medium 524 (also referred to as computer-readable medium) thereon storing one or more sets of instructions 526 or software embodying any or more of the methodologies or functions described herein. Instructions 526 may also reside wholly or at least partially within main memory 504 and / or processing device 502 during execution by computer system 500, which also constitute machine-readable storage medium. Machine-readable storage medium 524, data storage system 518, and / or main memory 504 may correspond to... Figure 1 The memory subsystem 110.

[0067] In one embodiment, instruction 526 includes instructions for implementing a bit-flipping decoder (e.g., by...). Figure 1 The error corrector 113 implements functional instructions. Although the machine-readable storage medium 524 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered as a single medium or multiple media containing one or more sets of instructions. The term "machine-readable storage medium" should also be considered as any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any or more of the methodologies of this disclosure. Therefore, the term "machine-readable storage medium" should be considered as including (but not limited to) solid-state memory, optical media, and magnetic media.

[0068] Some parts of the foregoing detailed description have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Algorithms are generally conceived here as self-consistent sequences of operations that lead to desired results. Operations are operations that require the physical manipulation of physical quantities. Usually, but not always, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has proven convenient, sometimes primarily for common reasons, to refer to these signals as bits, values, elements, symbols, characters, items, numbers, or the like.

[0069] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels for application to those quantities. This disclosure may relate to the operation and processes of a computer system or similar electronic computing device that manipulate and transform data representing physical (electronic) quantities in the registers and memories of the computer system into other data similarly represented in the memory or registers of the computer system or other such information storage systems.

[0070] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. For example, a computer system or other data processing system (e.g., controller 115) may implement computer implementation methods 200 and 400 in response to its processor executing a computer program (e.g., a sequence of instructions) contained in memory or other non-transitory machine-readable storage media. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0071] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used in conjunction with the teachings herein, or it can be demonstrated that it is convenient to construct more specialized devices to perform the methods. The structures of various such systems will be presented as set forth in the appended claims. Furthermore, this disclosure is not described with reference to any particular programming language. It should be understood that various programming languages ​​can be used to implement the teachings of this disclosure described herein.

[0072] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any means for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0073] In the foregoing description, embodiments of the present disclosure have been described with reference to specific examples. It should be understood that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the specification and drawings should be regarded as illustrative rather than limiting.

Claims

1. A method comprising: receiving a codeword stored in a memory device; determining a plurality of energy function values for the codeword; determining a least reliable one of the energy function values for the codeword; in response to determining that the least reliable energy function value fails to satisfy a bit flip criterion for a current iteration of a bit flip decoding of the codeword, bypassing an iteration of the bit flip decoding of the codeword by bypassing a comparison of the plurality of energy function values to the bit flip criterion for the current iteration; and incrementing an iteration count in response to bypassing the iteration of the bit flip decoding.

2. The method of claim 1, wherein the bit flip criterion for the current iteration is different than a bit flip criterion for a subsequent iteration and the least reliable energy function value satisfies the bit flip criterion for the subsequent iteration.

3. The method of claim 2, further comprising: in response to determining that the energy function value for a bit of the codeword satisfies the bit flip criterion for the subsequent iteration, flipping the bit.

4. The method of claim 1, further comprising: determining that the least reliable energy function value also fails to satisfy a bit flip criterion for a subsequent iteration of a bit flip decoding of the codeword; and incrementing an iteration count again in response to determining that the least reliable energy function value fails to satisfy the bit flip criterion for the subsequent iteration.

5. The method of claim 1, wherein the least reliable energy function value is determined during a previous iteration of the bit flip decoding of the codeword.

6. The method of claim 1, wherein the determining the energy function values for the codeword includes: retrieving an energy function value for a bit of the codeword from a lookup table using a number of unsatisfied parity checks and channel information, the channel information indicating whether a current state of the bit is the same as a state of the bit read from the memory device.

7. The method of claim 6, wherein the determining the energy function values for the codeword further includes using soft information associated with the bit of the codeword, wherein the soft information comprises a soft bit, wherein the soft bit indicates whether the bit of the codeword is strong or weak.

8. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: receive a codeword stored in a memory device; determine a plurality of energy function values for the codeword; determine a least reliable one of the energy function values for the codeword; in response to determining that the least reliable energy function value fails to satisfy a bit flip criterion for a current iteration of a bit flip decoding of the codeword, bypassing an iteration of the bit flip decoding of the codeword by bypassing a comparison of the plurality of energy function values to the bit flip criterion for the current iteration; and increment an iteration count in response to bypassing the iteration of the bit flip decoding.

9. The non-transitory computer-readable storage medium of claim 8, wherein the bit flip criterion for the current iteration is different than a bit flip criterion for a subsequent iteration and the least reliable energy function value satisfies the bit flip criterion for the subsequent iteration.

10. The non-transitory computer-readable storage medium of claim 9, wherein the processing device is further to: flip a bit of the codeword in response to determining that the energy function value for the bit of the codeword satisfies the bit flipping criterion for the subsequent iteration.

11. The non-transitory computer-readable storage medium of claim 8, wherein the processing device is further to: determine that the least reliable energy function value also fails to satisfy a bit flipping criterion for a subsequent iteration of bit flipping decoding of the codeword; and increment an iteration count again in response to determining that the least reliable energy function value fails to satisfy the bit flipping criterion for the subsequent iteration.

12. The non-transitory computer-readable storage medium of claim 8, wherein the least reliable energy function value is determined during a previous iteration of the bit flipping decoding of the codeword.

13. The non-transitory computer-readable storage medium of claim 8, wherein the determining the energy function value for the codeword includes: retrieving an energy function value for a bit of the codeword from a lookup table using a number of unsatisfied parity checks and lane information, the lane information indicating whether a current state of the bit is the same as a state of the bit read from the memory device.

14. The non-transitory computer-readable storage medium of claim 13, wherein the determining the energy function value for the codeword further includes using soft information associated with the bit of the codeword, wherein the soft information comprises a soft bit, wherein the soft bit indicates whether the bit of the codeword is strong or weak.

15. A system comprising: a memory device; and a processing device operably coupled with the memory device to: receive a codeword stored in the memory device; determine a plurality of energy function values for the codeword; determine a least reliable one of the energy function values for the codeword; in response to determining that the least reliable energy function value fails to satisfy a bit flipping criterion for a current iteration of bit flipping decoding of the codeword, bypass an iteration of the bit flipping decoding of the codeword by bypassing a comparison of the plurality of energy function values to the bit flipping criterion for the current iteration, wherein the least reliable energy function value of the plurality of energy function values is determined during a previous iteration of the bit flipping decoding of the codeword; and increment an iteration count in response to bypassing the iteration of the bit flipping decoding.

16. The system of claim 15, wherein the bit flipping criterion for the current iteration is different than a bit flipping criterion for a subsequent iteration and the least reliable energy function value satisfies the bit flipping criterion for the subsequent iteration.

17. The system of claim 16, wherein the processing device is further to: flip a bit of the codeword in response to determining that the energy function value for the bit of the codeword satisfies the bit flipping criterion for the subsequent iteration.

18. The system of claim 15, wherein the processing device is further to: determine that the least reliable energy function value also fails to satisfy a bit flipping criterion for a subsequent iteration of bit flipping decoding of the codeword; and incrementing an iteration count again in response to determining that the least reliable energy function value fails to satisfy the bit flip criterion for the subsequent iteration.

19. The system of claim 15, wherein the determining the energy function value of the codeword includes: retrieving an energy function value of a bit of the codeword from a lookup table using a number of unsatisfied parity checks and channel information, the channel information indicating whether a current state of the bit is the same as a state of the bit read from the memory device.

20. The system of claim 19, wherein the determining the energy function value of the codeword further includes using soft information associated with the bit of the codeword, wherein the soft information comprises a soft bit, wherein the soft bit indicates whether the bit of the codeword is strong or weak.

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