CV detection circuit and method for capacitive MEMS sensor

Abstract

The invention discloses a CV detection circuit and method for a capacitive MEMS sensor, relates to the field of sensors, and is used for improving the measurement precision of the CV detection circuit. A detection electrode of a capacitor array circuit of the CV detection circuit is used for being connected with a sensitive detection structure of the capacitive MEMS sensor and is connected to the amplifier circuit; the amplifier circuit, the demodulation circuit and the filter circuit are connected in sequence; the clock power supply is connected with the clock generation circuit; the clock generation circuit generates a first clock signal and a second clock signal which are not overlapped, the first clock signal is connected to the demodulation circuit, and the second clock signal is connected to the capacitor array circuit. According to the invention, the precise measurement of the variation of the micro capacitance is realized, and the area overhead is saved.

Description

Technical Field

[0001] The present invention relates to the technical field of sensors, and in particular to a CV detection circuit and method for a capacitive MEMS sensor. Background Art

[0002] Capacitive MEMS sensors are favored by the market because of their small size, good stability, reliability, and high sensitivity. In recent years, with the continuous progress of micro-machining technology, the process of capacitive MEMS sensors has become increasingly mature, which has led to an increasing demand in the fields of consumer electronics, automotive, industrial control, medical, aerospace, military, etc. Its core working principle is to use the principle of charge conservation to convert inertial force into a capacitance change through a micro-electro-mechanical system (MEMS), and then a CV (capacitance-to-voltage) detection circuit converts this capacitance change into a voltage signal for subsequent processing. Since the capacitance change is very small, usually in the order of aF, it is particularly important to use a dedicated CV detection circuit to detect and process the small capacitance change of MEMS.

[0003] In the traditional CV detection circuit, when detecting a small capacitance change, on the one hand, it is affected by factors such as the matching accuracy between the interface circuit matching capacitance and the mechanical structure detection capacitance, clock noise, circuit parasitic capacitance, and offset, which will seriously affect its detection accuracy. This requires the CV detection circuit to have sufficient matching accuracy to reduce the influence of mismatch on the signal itself. On the other hand, process deviations will be introduced during the processing of MEMS sensors. The internal structure of MEMS sensors is delicate, with internal components such as a mass block MASS, comb teeth, beams, and gas, as shown in Figure 1 the figure. The mass block is generally required to be in the order of 10-4mg, the comb tooth gap is generally required to be below 10um, and the gas pressure is generally required to be controlled at a low pressure. However, during the manufacturing process, process errors will cause these parameters to deviate from the designed required values, and there will be inconsistencies in different batches and different axes. For different processes, design schemes, and mechanical structures with different ranges, the detection capacitance values between the internal mass block and the fixed comb teeth are also different. This requires the CV detection circuit to have a wide range of adaptability and gain adjustability to meet the matching requirements of different mechanical structures. At the same time, in the traditional solutions, no description is made on the power supply scheme of the modulation and demodulation clock, and the power supply is directly supplied, resulting in a relatively large clock jitter, introducing new noise during the signal modulation and demodulation processes, thereby affecting the detection accuracy of the CV detection circuit. Summary of the Invention

[0004] The object of the present invention is to provide a CV detection circuit and method for a capacitive MEMS sensor to improve the measurement accuracy of the CV detection circuit for all or part of the above problems.

[0005] The technical solution adopted by the present invention is as follows: A CV detection circuit for a capacitive MEMS sensor, which includes a capacitor array circuit, a clock generation circuit, a clock power supply, an amplifier circuit, a demodulation circuit, and a filtering circuit; the detection electrodes of the capacitor array circuit are used to be connected to the sensitive detection structure of the capacitive MEMS sensor and connected to the amplifier circuit; the amplifier circuit, the demodulation circuit, and the filtering circuit are connected in sequence; the clock power supply is connected to the clock generation circuit; the clock generation circuit generates two non-overlapping first clock signal and a second clock signal, the first clock signal is input into the demodulation circuit, and the second clock signal is input into the capacitor array circuit.

[0006] Further, the capacitor array circuit includes a first capacitor group connected to a first detection electrode and a second capacitor group connected to a second detection electrode; the first capacitor group and the second capacitor group are respectively connected to a common terminal, and the common terminal is input with the second clock signal; both the first capacitor group and the second capacitor group include a coarse adjustment capacitor circuit and a fine adjustment capacitor branch.

[0007] Further, the coarse adjustment capacitor circuit includes two groups of adjustable capacitors connected in parallel, and the fine adjustment capacitor branch includes a digital-to-analog converter and a fixed capacitor connected in series.

[0008] Further, the amplifier circuit includes a fully differential operational amplifier, a first feedback resistor, a second feedback resistor, a first feedback capacitor, and a second feedback capacitor; the first feedback resistor and the first feedback capacitor are connected in parallel between the non-inverting input terminal and the inverting output terminal of the fully differential amplifier, and the second feedback resistor and the second feedback capacitor are connected in parallel between the inverting input terminal and the non-inverting output terminal of the fully differential amplifier.

[0009] Further, the clock power supply includes an error amplifier, a buffer, a PMOS transistor, a first fixed resistor, and a first variable resistor; the inverting input terminal of the error amplifier is input with a reference signal, the non-inverting input terminal is input with a feedback signal, and the output terminal is connected to the input terminal of the buffer; the output terminal of the buffer is connected to the gate of the PMOS transistor; the source of the PMOS transistor is connected to the power supply, and the drain is used as the output terminal of the clock power supply and is connected in series with the first fixed resistor and the first variable resistor in sequence; the non-inverting input terminal of the error amplifier is connected between the first fixed resistor and the first variable resistor.

[0010] Further, the clock generation circuit includes a ring oscillator circuit, a driving buffer circuit, and a non-overlapping clock generation circuit; an output end of the ring oscillator circuit is connected to an input end of the driving buffer circuit, an output end of the driving buffer circuit is connected to an input end of the non-overlapping clock generation circuit, and the non-overlapping clock generation circuit outputs a first clock signal and a second clock signal that are non-overlapping in two phases.

[0011] Further, the first clock signal is further used to access the capacitive MEMS sensor.

[0012] On the other hand, the present invention further provides a CV detection method for a capacitive MEMS sensor. The CV detection method is implemented based on the above-mentioned CV detection circuit for a capacitive MEMS sensor, and the CV detection method includes: Connect the capacitive MEMS sensor to a detection electrode of the capacitor array circuit; Connect a clock signal to the capacitive MEMS sensor; Adjust the capacitance value of the capacitor connected to the capacitor array circuit to a matching value.

[0013] Further, connecting a clock signal to the capacitive MEMS sensor includes: Connect the first clock signal to the capacitive MEMS sensor.

[0014] Further, adjusting the capacitance value of the capacitor connected to the capacitor array circuit to a matching value includes: Adjust the capacitance value of the coarse-tuning capacitor circuit in the capacitor array circuit so that, under the action of the second clock signal, the fine-tuning capacitor branch in the capacitor array circuit converts the change amount of the voltage value into the change amount of the connected capacitance value.

[0015] In summary, due to the adoption of the above technical solutions, the beneficial effects of the present invention are: This application can achieve precise matching of the capacitance of the sensitive detection structure by means of the capacitor array circuit, reduce the fixed error introduced by mismatch, and achieve precise measurement of the change amount of the tiny capacitance. Moreover, by supplying power to the clock generation circuit through the clock power supply, the influence of power supply noise on the clock in the traditional scheme of directly supplying power to the clock generation circuit is avoided, the noise introduced by clock jitter is reduced, and the detection accuracy of the CV detection circuit is further improved. Description of the Drawings

[0016] The present invention will be described by way of examples with reference to the accompanying drawings, where: Figure 1 is a schematic structural diagram of the sensitive detection structure of the capacitive MEMS sensor.

[0017] Figure 2It is a schematic structural diagram of the CV detection circuit of a capacitive MEMS sensor.

[0018] Figure 3 It is a schematic structural diagram of a capacitor array circuit.

[0019] Figure 4 It is a schematic structural diagram of a clock power supply.

[0020] Figure 5 It is a schematic structural diagram of a clock generation circuit. Detailed implementation mode

[0021] All features disclosed in this specification, or steps in all methods or processes disclosed, except for mutually exclusive features and / or steps, can be combined in any way.

[0022] Any feature disclosed in this specification (including any additional claims, abstract) can be replaced by other equivalent or similar-purpose alternative features unless specifically stated. That is, unless specifically stated, each feature is only an example in a series of equivalent or similar features.

[0023] Aiming at the problem of poor detection accuracy of the CV detection circuit of traditional capacitive MEMS sensors, the embodiment of the present application provides a CV detection circuit for a capacitive MEMS sensor, aiming to improve the detection accuracy of the CV detection circuit.

[0024] The CV detection circuit for a capacitive MEMS sensor provided by the present application includes a capacitor array circuit CARR, a clock generation circuit CLKGEN, a clock power supply LDO, an amplifier circuit AMP, a demodulation circuit CHOPPER, and a filter circuit LPF. As Figure 2 shown, the detection electrode of the capacitor array circuit CARR is used to be connected to the sensitive detection structure of the capacitive MEMS sensor and connected to the amplifier circuit AMP. The amplifier circuit AMP, the demodulation circuit CHOPPER, and the filter circuit LPF are connected in sequence, and the detection result is output by the filter circuit LPF. The clock power supply LDO is connected to the clock generation circuit CLKGEN. The clock generation circuit CLKGEN generates two non-overlapping first clock signal CLK and second clock signal CLKB, wherein the first clock signal CLK is connected to the demodulation circuit CHOPPER, and the second clock signal CLKB is connected to the capacitor array circuit CARR.

[0025] The operation of the capacitive MEMS sensor also requires a clock signal. As an alternative implementation, the clock signal used by the capacitive MEMS sensor can be the first clock signal CLK described above, that is, the first clock signal CLK is also used to be connected to the capacitive MEMS sensor. Of course, the capacitive MEMS sensor can also be separately connected to an independent clock signal.

[0026] The equivalent capacitances Cs1 and Cs2 of the sensitive detection structure of the capacitive MEMS sensor together constitute the input signal of the CV detection circuit. The capacitive array circuit CARR reads the weak capacitance signal generated by the sensitive detection structure and modulates it, and then it is amplified by the amplifier circuit AMP, demodulated by the demodulation circuit CHOPPER, and filtered by the filter circuit LPF to obtain a high-quality detection signal.

[0027] As Figure 2 shown, as an alternative implementation, the amplifier circuit AMP includes a fully differential operational amplifier OPA1, a first feedback resistor Rf1, a second feedback resistor Rf2, a first feedback capacitor Cf1, and a second feedback capacitor Cf2. The first feedback resistor Rf1 and the first feedback capacitor Cf1 are connected in parallel between the non-inverting input terminal Vp and the inverting output terminal Von of the fully differential operational amplifier OPA1; the second feedback resistor Rf2 and the second feedback capacitor Cf2 are connected in parallel between the inverting input terminal Vn and the non-inverting output terminal Vop of the fully differential operational amplifier OPA1. The two feedback resistors of the amplifier circuit AMP are used to provide a suitable DC operating point for the fully differential operational amplifier OPA1. The two feedback capacitors of the amplifier circuit AMP and the previous-stage input together constitute a charge amplification circuit, which amplifies the weak charge variation and then outputs it. The two together constitute a high-pass filter, which filters the low-frequency noise and retains the high-frequency signal components for output to the demodulation circuit CHOPPER.

[0028] As an alternative implementation, the capacitive array circuit CARR includes a first capacitor bank connected to the first detection electrode ST and a second capacitor bank connected to the second detection electrode SB. The first capacitor bank and the second capacitor bank are respectively connected to a common terminal, and the second clock signal CLKB is connected to the common terminal. Both the first capacitor bank and the second capacitor bank include a coarse-tuning capacitor circuit and a fine-tuning capacitor branch, and the two branches are connected in parallel. The coarse-tuning capacitor circuit is used to (roughly) adjust the capacitance value of the capacitive array circuit CARR (that is, directly adjust the capacitance value), and the fine-tuning capacitor branch is used to convert the change in the voltage value into a change in the connected capacitance value to achieve fine adjustment of the matching capacitance. That is, the capacitance value adjustment problem is converted into a voltage value adjustment problem, and the connected capacitance of the fine-tuning capacitor branch is finely adjusted by quantifying and adjusting the voltage.

[0029] In some feasible embodiments, the coarse-tuning capacitance circuit includes two groups of adjustable capacitors connected in parallel with each other, and the fine-tuning capacitance branch includes a digital-to-analog converter and a fixed capacitor connected in series with each other. As Figure 3 shown, the first capacitor group includes an adjustable capacitor Cb1 and an adjustable capacitor Cb2, and the two adjustable capacitors are connected in parallel between the first detection electrode ST and the common terminal. In addition, between the first detection electrode ST and the common terminal, there is also a fine-tuning capacitance branch formed by connecting a fixed resistor Cb3 and a first digital-to-analog converter CLKBF1 in series, and the input end of the first digital-to-analog converter CLKBF1 is connected to the second clock signal CLKB. Similarly, the second capacitor group includes an adjustable capacitor Cb4 and an adjustable capacitor Cb5, and the two adjustable capacitors are connected in parallel between the second detection electrode SB and the common terminal. In addition, between the second detection electrode SB and the common terminal, there is also a fine-tuning capacitance branch formed by connecting a fixed resistor Cb6 and a second digital-to-analog converter CLKBF2 in series, and the input end of the second digital-to-analog converter CLKBF2 is connected to the second clock signal CLKB. The adjustment step of the adjustable capacitor Cb1 and the adjustable capacitor Cb4 is greater than the adjustment step of the adjustable capacitor Cb2 and the adjustable capacitor Cb5. That is, although the adjustable capacitor Cb1 and the adjustable capacitor Cb2 are both classified into the coarse-tuning capacitance branch, the adjustment accuracy of the adjustable capacitor Cb2 is relatively higher than that of the adjustable capacitor Cb1. The same is true for the adjustable capacitor Cb4 and the adjustable capacitor Cb5.

[0030] The capacitive array circuit CARR with the above structure refers to the adjustable capacitors Cb1 and Cb4 as coarse-tuning capacitors (or capacitive arrays), and the adjustable capacitors Cb2 and Cb5 as fine-tuning capacitors (or capacitive arrays). In some feasible embodiments, both the coarse-tuning capacitors and the fine-tuning capacitors are composed of binary capacitive arrays and are controlled by an M-bits register (M is an integer). Among them, the coarse-tuning capacitor has an adjustment step value of 0.5 pF, and the fine-tuning capacitor has an adjustment step value of 10 fF. By configuring the register, capacitors with different capacitance values can be selected to be connected to the circuit. Therefore, the adjustable capacitors Cb1 and Cb4 achieve the coarse adjustment function of the matching capacitor, while the adjustable capacitors Cb2 and Cb5 achieve the fine adjustment function of the matching capacitor. In this way, a wide-range and high-precision capacitive matching can be achieved, which can meet the matching requirements of different sensitive detection structures and is applicable to various types of capacitive MEMS sensors. In addition, in traditional capacitive matching arrays, the precise matching with the detection capacitor of the sensitive detection structure is often achieved by reducing the capacitance value of the least significant bit capacitor. However, this solution is often limited by the process and cannot accurately manufacture capacitors at the fF level. In the embodiments of the present application, the fine-tuning capacitor branch adopts capacitive array digital-to-analog conversion (capacitive array DAC) technology and utilizes the principle of capacitance conservation, that is: Q = C×V, where Q represents the electric charge quantity, C represents the capacitance value, and V represents the voltage difference across the capacitor. By keeping the capacitance C unchanged and changing the voltage V, the purpose of equivalently changing the capacitance C is achieved. The specific implementation scheme is that the first digital-to-analog converter CLKBF1 (or the second digital-to-analog converter CLKBF2) with Nbits (N is an integer) quantifies the second clock signal CLKB, that is, quantifies the voltage applied to the fixed capacitor Cb3 (or the fixed capacitor Cb6). The minimum quantization step is , thus realizing the refinement decomposition of the matching capacitor and solving the problem that tiny capacitors cannot be processed and realized by the process. The capacitance values of the fixed capacitor Cb3 and the fixed capacitor Cb6 can be designed to be equal.

[0031] The minimum precision matching capacitance value that the capacitive array circuit CARR with the above structure can reach is: , In the formula, C represents the matching capacitance value, |Cb3| represents the capacitance value of the fixed capacitor Cb3, and N represents the number of bits of the digital-to-analog converter.

[0032] Regarding the problem of relatively large modulation and demodulation clock noise in the existing CV detection circuit, in this application, the clock power supply LDO supplies power to the clock generation circuit CLKGEN alone. By using the voltage stabilization technology of the clock power supply LDO, the influence of power supply noise on the modulation and demodulation clocks is reduced, and further the detection accuracy of weak signals is improved.

[0033] As an alternative embodiment, as Figure 4As shown, the clock power supply LDO includes an error amplifier EA, a buffer BUFFER, a PMOS transistor PM1, a first fixed resistor R1, and a first variable resistor VR1. The inverting input terminal of the error amplifier EA is connected to a reference signal Vref, the non-inverting input terminal is connected to a feedback signal Vfb, and the output terminal is connected to the input terminal of the buffer BUFFER. The output terminal of the buffer BUFFER is connected to the gate G of the PMOS transistor PM1. The source S of the PMOS transistor PM1 is connected to the power supply VDD, and the drain D is used as the output terminal of the clock power supply LDO, outputting an output voltage VCK. The drain D is also sequentially connected in series with the first fixed resistor R1 and the first variable resistor VR1. The first variable resistor VR1 is grounded. The non-inverting input terminal of the error amplifier EA is connected between the first fixed resistor R1 and the first variable resistor VR1.

[0034] In the clock power supply LDO with the above structure, the error amplifier EA is used to amplify the difference between the reference signal Vref and the feedback signal Vfb. The buffer BUFFER is used to enhance the drive and ensure the bandwidth of the clock power supply LDO. The PMOS transistor PM1, the first fixed resistor R1, and the first variable resistor VR1 together provide a stable output voltage VCK, while suppressing the noise of the power supply and ground signals, and providing a stable and low-noise power supply for the clock generation circuit CLKGEN.

[0035] The ability of the clock power supply LDO to suppress power supply noise in the sensor signal frequency band is as follows: , In the formula, PSR is the noise suppression index, and Gain_EA is the low-frequency gain of the error amplifier EA.

[0036] As Figure 5 shown is the circuit diagram of the clock generation circuit CLKGEN in an alternative embodiment. As Figure 5 shown, the clock generation circuit CLKGEN includes a ring oscillator OSC, a drive buffer circuit BUF, and a non-overlapping clock generation circuit NOCGC. The output terminal of the ring oscillator OSC is connected to the input terminal of the drive buffer circuit BUF. The output terminal of the drive buffer circuit BUF is connected to the input terminal of the non-overlapping clock generation circuit NOCGC. The non-overlapping clock generation circuit NOCGC outputs two non-overlapping first clock signals CLK and second clock signals CLKB respectively. The ring oscillator OSC adopts a scheme with adjustable output frequency, avoiding clock offset caused by process errors. The clock generation circuit CLKGEN uses the voltage (VCK) output by the clock power supply LDO as the power supply, reducing the impact of clock jitter on weak signals.

[0037] For the demodulation circuit CHOPPER, the demodulation clock it uses has the same frequency as the modulation clock, i.e., the first clock signal CLK. After demodulation, the high-frequency signal is restored to the initial frequency, and the low-frequency noise introduced by the circuit is modulated to the high frequency by this clock signal at the same time. The demodulation circuit CHOPPER realizes the spectral separation of the signal and the noise.

[0038] The filtering circuit LPF uses a low-pass filter circuit, such as a Butterworth-type filter, which has the characteristics of good flatness in the passband and its bandwidth has an adjustable function. By selecting a suitable bandwidth configuration, a good filtering effect on high-frequency noise can be achieved. The filtering circuit LPF finally outputs the detection signals C2Vop (in-phase output terminal) and C2Von (inverted output terminal).

[0039] The CV detection circuit provided by this application combines the differential capacitance of the sensitive detection structure and uses the configurable capacitor array circuit CARR to achieve the matching requirements of wide range and high precision. Using the principle of charge conservation, a digital-to-analog converter is used to quantify the clock signal, which is equivalent to processing the weak signal for the capacitor. The advantage of this structure is that while the interface capacitance matching meets the requirements of wide matching range and high precision, it saves a large amount of area overhead, reduces the nonlinear problems caused by the excessive area of high-bit capacitors, and improves the linearity of the system. At the same time, using the clock supply power LDO as the power supply of the clock generation circuit greatly reduces the signal noise and distortion introduced by the power supply (jitter) noise during the clock modulation and demodulation process, thereby further improving the detection ability of the circuit for weak signals. This application adopts a fully differential structure circuit, which minimizes the nonlinear problems caused by parasitic capacitance mismatch.

[0040] On the other hand, an embodiment of this application also provides a CV detection method for a capacitive MEMS sensor, and this CV detection method is implemented based on the above-mentioned CV detection circuit for a capacitive MEMS sensor. This CV detection method includes: 1) Connect the capacitive MEMS sensor to the detection electrode of the capacitor array circuit CARR. As Figure 2 shown, the capacitor array circuit CARR and the equivalent capacitances Cs1 and CS2 of the sensitive detection structure of the capacitive MEMS sensor together constitute the input signal of the CV detection circuit.

[0041] 2) Connect a clock signal to the capacitive MEMS sensor. For example, the first clock signal CLK generated by the clock generation circuit CLKGEN can be connected.

[0042] 3) Adjust the capacitance value connected to the capacitor array circuit CARR to the matching value.

[0043] As an alternative implementation, the method for adjusting the capacitance value of the capacitance array circuit CARR connected thereto to a matching value includes: Adjusting the capacitance value of the coarse-tuning capacitance circuit in the capacitance array circuit CARR, and adjusting the voltage of the fine-tuning capacitance branch in the capacitance array circuit, so that the fine-tuning capacitance branch converts the change amount of the voltage value into the change amount of the capacitance value.

[0044] In some feasible implementations, the capacitance array circuit CARR adopts the circuit structure as shown in Figure 3 Then, adjusting the capacitance value of the coarse-tuning capacitance circuit in the capacitance array circuit CARR includes: Adjusting the capacitance values of the adjustable capacitor Cb1 and the adjustable capacitor Cb4 to achieve coarse tuning of the matching capacitance; Adjusting the capacitance values of the adjustable capacitor Cb2 and the adjustable capacitor Cb5 to achieve fine tuning of the matching capacitance.

[0045] On this basis, the fine-tuning capacitance branch (formed by connecting the fixed capacitor Cb3 in series with the first digital-to-analog converter CLKBF1, or the fixed capacitor Cb6 in series with the second digital-to-analog converter CLKBF2) including the digital-to-analog converter converts the change amount of the voltage value into the change amount of the capacitance value under the action of the second clock signal CLKB. Specifically, the first digital-to-analog converter CLKBF1 (or the second digital-to-analog converter CLKBF2) quantizes the second clock signal CLKB, thereby realizing the quantization of the voltage of the fixed capacitor Cb3 (or the fixed capacitor Cb6). According to the principle of capacitance conservation, the quantization of the connected capacitance is realized.

[0046] The present invention is not limited to the foregoing specific implementations. The present invention extends to any new feature or any new combination disclosed in this specification, as well as any new method or process step or any new combination disclosed.

Claims

1. A CV detection circuit for a capacitive MEMS sensor, characterized in that: The invention comprises a capacitor array circuit (CARR), a clock generation circuit (CLKGEN), a clock power supply (LDO), an amplifier circuit (AMP), a demodulation circuit (CHOPPER) and a filter circuit (LPF); the detection electrode of the capacitor array circuit (CARR) is used to be connected to the sensitive detection structure of the capacitive MEMS sensor and connected to the amplifier circuit (AMP); the amplifier circuit (AMP), the demodulation circuit (CHOPPER) and the filter circuit (LPF) are connected in sequence; the clock power supply is connected to the clock generation circuit (CLKGEN); the clock generation circuit (CLKGEN) generates a first clock signal (CLK) and a second clock signal (CLKB) of two non-overlapping phases, the first clock signal (CLK) is connected to the demodulation circuit (CHOPPER), and the second clock signal (CLKB) is connected to the capacitor array circuit (CARR).

2. The CV detection circuit for a capacitive MEMS sensor according to claim 1, characterized in that: The capacitor array circuit (CARR) includes a first capacitor group connected to a first detection electrode (ST), and a second capacitor group connected to a second detection electrode (SB); the first capacitor group and the second capacitor group are respectively connected to a common end, and the common end is connected to the second clock signal (CLKB); the first capacitor group and the second capacitor group both include a coarse adjustment capacitor circuit and a fine adjustment capacitor branch.

3. The CV detection circuit for a capacitive MEMS sensor as claimed in claim 2, characterized in that: The coarse adjustment capacitor circuit includes two groups of adjustable capacitors connected in parallel, and the fine adjustment capacitor branch includes a digital-to-analog converter and a fixed capacitor connected in series.

4. The CV detection circuit for a capacitive MEMS sensor according to claim 1, characterized in that: The amplifier circuit (AMP) comprises a fully differential operational amplifier (OPA1), a first feedback resistor (Rf1), a second feedback resistor (Rf2), a first feedback capacitor (Cf1) and a second feedback capacitor (Cf2); the first feedback resistor (Rf1) and the first feedback capacitor (Cf1) are connected in parallel between the non-inverting input terminal and the inverting output terminal of the fully differential operational amplifier (OPA1), and the second feedback resistor (Rf2) and the second feedback capacitor (Cf2) are connected in parallel between the inverting input terminal and the non-inverting output terminal of the fully differential operational amplifier (OPA1).

5. The CV detection circuit for a capacitive MEMS sensor according to claim 1, characterized in that: The clock power supply (LDO) comprises an error amplifier (EA), a buffer (BUFFER), a PMOS tube (PM1), a first fixed resistor (R1) and a first variable resistor (VR1); the inverting input terminal of the error amplifier (EA) is connected to a reference signal (Vref), the non-inverting input terminal is connected to a feedback signal (Vfb), and the output terminal is connected to the input terminal of the buffer (BUFFER); the output terminal of the buffer (BUFFER) is connected to the gate of the PMOS tube (PM1); the source of the PMOS tube (PM1) is connected to a power supply, the drain serves as the output terminal of the clock power supply (LDO), and is connected in series with the first fixed resistor (R1) and the first variable resistor (VR1) in sequence; the non-inverting input terminal of the error amplifier (EA) is connected between the first fixed resistor (R1) and the first variable resistor (VR1).

6. The CV detection circuit for a capacitive MEMS sensor according to claim 1, characterized in that: The clock generation circuit (CLKGEN) includes a ring oscillation circuit (OSC), a drive buffer circuit (BUF) and a non-overlapping clock generation circuit (NOCGC); the output end of the ring oscillation circuit (OSC) is connected to the input end of the drive buffer circuit (BUF), the output end of the drive buffer circuit (BUF) is connected to the input end of the non-overlapping clock generation circuit (NOCGC), and the non-overlapping clock generation circuit (NOCGC) outputs a first clock signal (CLK) and a second clock signal (CLKB) with two non-overlapping phases respectively.

7. The CV detection circuit for a capacitive MEMS sensor according to claim 1, characterized in that: The first clock signal (CLK) is also used to access the capacitive MEMS sensor.

8. A CV detection method for a capacitive MEMS sensor, characterized in that: The CV detection method is implemented based on the CV detection circuit for a capacitive MEMS sensor according to any one of claims 1 to 7, and the CV detection method includes: Connecting the capacitive MEMS sensor to the detection electrode of the capacitive array circuit (CARR); Access the clock signal for the capacitive MEMS sensor; The capacitance connected to the capacitor array circuit (CARR) is adjusted to a matching value.

9. The CV detection method for a capacitive MEMS sensor according to claim 8, characterized in that: Access the clock signal for the capacitive MEMS sensor, including: The first clock signal (CLK) is connected to the capacitive MEMS sensor.

10. The CV detection method for a capacitive MEMS sensor according to claim 8, characterized in that: The capacitor size connected to the capacitor array circuit (CARR) is adjusted to a matching value, including: adjusting the capacitance value of the coarse adjustment capacitance circuit in the capacitance array circuit (CARR), and, The voltage of the fine tuning capacitor branch in the capacitor array circuit (CARR) is adjusted so that the fine tuning capacitor branch converts the change in voltage value into the change in connected capacitance value.

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