Method and system for testing packaging thermal resistance of semiconductor device

Abstract

The invention discloses a semiconductor device packaging thermal resistance test method and system, and the method comprises the steps: applying multi-point pulse current excitation to a package, collecting surface temperature response data, and constructing a three-dimensional heat conduction path structure of the package; based on the structure, initial thermal resistance distribution and a non-uniform region thereof are calculated, and thermal resistance separation parameters at each hierarchical interface are further extracted to form a hierarchical thermal resistance separation matrix. Directional correction is carried out on the thermal resistance value containing the anisotropic heat conduction material, a corrected hierarchical thermal resistance sequence is generated and superposed with the initial thermal resistance distribution, and finally the total thermal resistance value of packaging is calculated. The accuracy of hierarchical thermal resistance separation is ensured by verifying the matching degree of the total thermal resistance value and the temperature response data, and a detailed thermal resistance distribution map is output, so that the thermal resistance contribution of each hierarchy in the package can be non-destructively and accurately separated and quantified, and particularly, when facing non-uniform heat flow distribution and anisotropic heat-conducting materials, the thermal resistance contribution of each hierarchy in the package can be accurately separated and quantified. And the accuracy of a measurement result is improved through directional correction.

Description

Technical Field

[0001] The present invention belongs to the field of packaging technology, and particularly relates to a method and system for testing the thermal resistance of semiconductor device packaging. Background Art

[0002] In the field of thermal resistance testing of semiconductor device packaging, existing methods usually rely on direct measurement or estimation based on theoretical models to determine the thermal resistance of each layer of materials inside the package. These traditional methods often include using a heating device to apply a constant or varying heat to the package, and monitoring the temperature change through sensors to calculate the thermal resistance value.

[0003] However, this method has several limitations: firstly, it is difficult to non-destructively separate the specific thermal resistance contributions of different levels (such as chips, solder layers, substrates, etc.) inside the package; secondly, in the case of dealing with non-uniform heat flow distribution and anisotropic thermal conductivity materials, the existing technology lacks an effective correction mechanism, resulting in a large deviation between the measurement result and the actual situation. Summary of the Invention

[0004] The purpose of the present invention is to provide a method and system for testing the thermal resistance of semiconductor device packaging, which can non-destructively and accurately separate and quantify the thermal resistance contributions of each level inside the package. Especially when facing non-uniform heat flow distribution and anisotropic thermal conductivity materials, the accuracy of the measurement result is improved through directional correction, so as to solve the problem of how to accurately separate the thermal resistance contributions of different levels inside the package and make effective corrections in the presence of non-uniform heat flow distribution and anisotropic thermal conductivity materials.

[0005] To achieve the above object, the present invention adopts the following technical scheme: A method for testing the thermal resistance of semiconductor device packaging, comprising the following steps: Applying multi-point pulsed current excitation to the semiconductor device packaging, collecting the temperature response data on the package surface, and constructing a three-dimensional heat conduction path structure of the package according to the temperature response data; calculating the initial thermal resistance distribution of each level inside the package based on the three-dimensional heat conduction path structure, and determining the non-uniform region of the initial thermal resistance distribution. For the non-uniform region, extracting the thermal resistance separation parameters at the interfaces of each level to form a hierarchical thermal resistance separation matrix; performing directional correction on the thermal resistance values corresponding to the anisotropic thermal conductivity materials in the hierarchical thermal resistance separation matrix to generate a corrected hierarchical thermal resistance sequence, and performing weighted superposition of the corrected hierarchical thermal resistance sequence and the initial thermal resistance distribution to calculate the total thermal resistance value of the package; verifying the accuracy of the hierarchical thermal resistance separation through the matching degree between the total thermal resistance value and the temperature response data, and outputting the verified thermal resistance values of each level and the total thermal resistance value to form a thermal resistance distribution map of the package.

[0006] Preferably, the applying multi-point pulsed current excitation to the semiconductor device packaging and collecting the temperature response data on the package surface includes: Select at least three non - collinear positions as current injection points, apply pulsed current with a preset time interval and amplitude at each of the injection points, and record the temperature change data of each monitoring point on the package surface; Use an infrared camera to monitor the semiconductor device package in real - time, and record the temperature change conditions of each monitoring point on the package surface under the action of the pulsed current; Based on the relationship between the temperature changes of each monitoring point and the pulsed current, calculate the thermal response coefficient corresponding to each injection point, which is used to characterize the heat conduction performance of the packaging material at different positions; Input all the thermal response coefficients into a summary formula to obtain an overall thermal response matrix, and analyze the heat flow distribution inside the package through the overall thermal response matrix.

[0007] Preferably, construct a three - dimensional heat conduction path structure of the package according to the temperature response data, including: Use the temperature change data to determine the temperature distribution of each monitoring point; Based on the temperature distribution, define a spatial coordinate system and mark the positions of all monitoring points in the spatial coordinate system; For each monitoring point, calculate the heat flow connection strength between it and its surrounding monitoring points to establish a local heat conduction relationship; Summarize all the local heat conduction relationships to form an overall three - dimensional heat conduction path structure, and identify the main heat conduction paths and their directions by analyzing the elements in the three - dimensional heat conduction path structure.

[0008] Preferably, calculate the initial thermal resistance distribution of each layer inside the package based on the three - dimensional heat conduction path structure, and determine the non - uniform region of the initial thermal resistance distribution, including: Extract the heat flow connection strength between each monitoring point and the points directly connected to it from the three - dimensional heat conduction path structure, and calculate the average heat flux density of each monitoring point; Use the average heat flux density and the position of the monitoring point to calculate the initial thermal resistance value corresponding to each monitoring point, so as to construct an initial thermal resistance distribution map inside the package; In the initial thermal resistance distribution map, define a threshold to identify the non - uniform region, and mark the points that meet the conditions as non - uniform thermal resistance regions; For all the identified non - uniform thermal resistance regions, record their position coordinates and corresponding thermal resistance values in the initial thermal resistance distribution map to form a non - uniform thermal resistance report.

[0009] Preferably, extract the thermal resistance separation parameters at the interfaces of each layer for the non - uniform region to form a layer - by - layer thermal resistance separation matrix, including: Based on the position coordinates and corresponding thermal resistance values recorded in the non-uniform thermal resistance report, determine the main heat flow paths within each non-uniform region, and select several key points on the main heat flow paths; For each key point, calculate the temperature difference between it and the adjacent layer interface, and then calculate the corresponding thermal resistance separation parameter for the layer based on the temperature difference; Arrange all the thermal resistance separation parameters in hierarchical order to construct a hierarchical thermal resistance separation matrix; By analyzing the non-zero elements in the hierarchical thermal resistance separation matrix, identify the hierarchical interfaces with significant thermal resistance contributions, and record the position information of the hierarchical interfaces and the corresponding thermal resistance separation parameters to form a detailed hierarchical thermal resistance analysis table.

[0010] Preferably, perform directional correction on the thermal resistance values corresponding to the anisotropic thermal conductive materials in the hierarchical thermal resistance separation matrix to generate a corrected hierarchical thermal resistance sequence, including: Identify the elements in the hierarchical thermal resistance separation matrix, and determine the position of the hierarchical interface containing the anisotropic thermal conductive material and its corresponding thermal resistance separation parameter; For each hierarchical interface containing the anisotropic thermal conductive material, define a direction correction factor according to the material properties; Apply the direction correction factor to correct the hierarchical thermal resistance separation parameter and calculate the corrected thermal resistance value; Arrange all the corrected thermal resistance values in hierarchical order to form a corrected hierarchical thermal resistance sequence.

[0011] Preferably, perform weighted superposition of the corrected hierarchical thermal resistance sequence and the initial thermal resistance distribution to calculate the total thermal resistance of the package, including: Based on the initial thermal resistance values of each monitoring point in the initial thermal resistance distribution map and the corrected hierarchical thermal resistance sequence, determine a weight factor for each hierarchical interface; Use the weight factor to perform weighted processing on each element in the corrected hierarchical thermal resistance sequence to generate weighted hierarchical thermal resistance values; Superimpose the weighted hierarchical thermal resistance values and the initial thermal resistance values at the corresponding positions in the initial thermal resistance distribution map to calculate the total thermal resistance contribution value of each monitoring point; Summarize the total thermal resistance contribution values of all monitoring points and calculate the average thermal resistance value of the overall package.

[0012] Preferably, verify the accuracy of the hierarchical thermal resistance separation through the matching degree between the total thermal resistance value and the temperature response data, including: According to the temperature change data of each monitoring point, calculate the expected temperature change of each monitoring point; Compare the expected temperature change with the actually measured temperature change, and calculate the temperature difference of each monitoring point; Calculate the sum of the squares of the temperature differences based on the temperature differences at all monitoring points; Set a predefined threshold. If the sum of the squares of the temperature differences is less than or equal to the threshold, confirm that the hierarchical thermal resistance separation is accurate.

[0013] Preferably, output the verified thermal resistance values of each layer and the total thermal resistance value to form a thermal resistance distribution map of the package, including: Calculate the finally confirmed thermal resistance value of each layer interface based on the overall average thermal resistance value and the corrected hierarchical thermal resistance sequence; Combine the finally confirmed thermal resistance values of all layer interfaces with the overall average thermal resistance value to construct a list containing the thermal resistance information of all layers; Using the data in the list, mark the thermal resistance values of each layer interface and the overall average thermal resistance value of the package at the corresponding positions in a three-dimensional coordinate system, and determine the color depth of each point; Output the thermal resistance distribution map, ensuring that the positions of all layer interfaces and their corresponding thermal resistance values are marked on the map, and the thermal resistance sizes of different regions are visually displayed by the color depth. At the same time, mark the overall average thermal resistance value of the package on the map.

[0014] On the other hand, the present invention proposes a semiconductor device package thermal resistance test system, including: A temperature response data acquisition module for applying a multi-point pulse current excitation to the semiconductor device package, collecting the temperature response data on the package surface, and constructing a three-dimensional heat conduction path structure of the package according to the temperature response data; A hierarchical thermal resistance separation matrix generation module for calculating the initial thermal resistance distribution of each layer inside the package based on the three-dimensional heat conduction path structure, determining the non-uniform regions of the initial thermal resistance distribution, and extracting the thermal resistance separation parameters at each layer interface for the non-uniform regions to form a hierarchical thermal resistance separation matrix; A total thermal resistance value calculation module for performing a directional correction on the thermal resistance values corresponding to the anisotropic thermal conductive materials in the hierarchical thermal resistance separation matrix, generating a corrected hierarchical thermal resistance sequence, and performing a weighted superposition of the corrected hierarchical thermal resistance sequence and the initial thermal resistance distribution to calculate the total thermal resistance value of the package; An accuracy verification and result output module for verifying the accuracy of the hierarchical thermal resistance separation through the matching degree between the total thermal resistance value and the temperature response data, outputting the verified thermal resistance values of each layer and the total thermal resistance value, and forming a thermal resistance distribution map of the package.

[0015] A semiconductor device package thermal resistance test method and system proposed by the present invention have the following advantages compared with the prior art: The present invention constructs a three-dimensional heat conduction path structure of the package by applying multi-point pulsed current excitation to the package and collecting surface temperature response data. Based on this structure, the initial thermal resistance distribution and its non-uniform regions are calculated, and further, the thermal resistance separation parameters at each hierarchical interface are extracted to form a hierarchical thermal resistance separation matrix. By performing directional correction on the thermal resistance values of the anisotropic thermal conductive materials, a corrected hierarchical thermal resistance sequence is generated and superimposed on the initial thermal resistance distribution, and finally, the total thermal resistance value of the package is calculated. In addition, by verifying the matching degree between the total thermal resistance value and the temperature response data, the accuracy of hierarchical thermal resistance separation is ensured, and a detailed thermal resistance distribution map is output, which can accurately and non-destructively separate and quantify the thermal resistance contributions of each layer inside the package. Especially in the face of non-uniform heat flux distribution and anisotropic thermal conductive materials, the accuracy of the measurement results is improved through directional correction. This not only helps to deeply understand the heat conduction characteristics inside the package but also provides reliable data support for optimizing the package design, thereby enhancing the overall performance and reliability of semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a flowchart of the method for testing the thermal resistance of the semiconductor device package of the present invention; Figure 2 is a block diagram of the system for testing the thermal resistance of the semiconductor device package of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0017] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. The specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0018] The present invention provides a method for testing the thermal resistance of a semiconductor device package as shown in Figure 1 and includes the following steps: Step 1: Apply multi-point pulsed current excitation to the semiconductor device package and collect the surface temperature response data of the package; specifically including: Select at least three non-collinear positions on the semiconductor device package as current injection points. The selection of these positions should ensure that the main heat conduction paths of the package can be covered to comprehensively evaluate the heat conduction performance inside the package. By applying a pulsed current I_p (p represents the p-th injection point) with a preset time interval and amplitude at each injection point, the thermal behavior under actual working conditions can be simulated.

[0019] Use an infrared camera to monitor the semiconductor device package in real time, and record the temperature change ΔT_m of each monitoring point on the package surface under the action of pulsed current, where m represents the m-th monitoring point, and ΔT_m=(T_after_m - T_before_m), T_before_m is the temperature before applying the current, and T_after_m is the temperature after applying the current; this step indirectly reflects the heat conduction efficiency inside the package by measuring the temperature change. ΔT_m represents the temperature rise caused by the current and reflects the ability of the material to transfer heat.

[0020] Based on the relationship between the temperature change of each monitoring point and the pulsed current, calculate the thermal response coefficient H_p = ΔT_p / I_p corresponding to each injection point, which is used to characterize the heat conduction performance of the package material at different positions; a larger H_p value means poorer heat conduction performance.

[0021] Input all the thermal response coefficients H_p into a summary formula to obtain the overall thermal response matrix H_matrix = ∑_(p = 1)^n H_p, where n is the total number of injection points, and analyze the heat flow distribution inside the package through H_matrix.

[0022] Step 2: Construct a three-dimensional heat conduction path structure of the package according to the temperature response data; specifically include: Use the temperature change ΔT_m data obtained from Step 1 to analyze and determine the temperature distribution of each monitoring point. This step includes sorting and classifying the temperature changes of all monitoring points to understand the temperature differences in different regions.

[0023] Based on the temperature distribution, define a spatial coordinate system and mark the positions P_k(x_k, y_k, z_k) of all monitoring points in the coordinate system, where k represents the k-th monitoring point; the position of each monitoring point is represented by its coordinates on the X, Y, and Z axes.

[0024] For each monitoring point P_k, calculate the heat flow connection strength Q_l = (ΔT_k - ΔT_l) / d_kl between it and the surrounding monitoring points, where d_kl is the distance between the monitoring point P_k and the adjacent monitoring point P_l, so as to establish a local heat conduction relationship; a larger Q_l value means stronger heat conduction ability.

[0025] Summarize all the local heat conduction relationships to form an overall three-dimensional heat conduction path structure M = ∑_(l = 1)^m Q_l, where m is the total number of monitoring points adjacent to the monitoring point P_k. By analyzing the elements in M, identify the main heat conduction paths and their directions.

[0026] Step 3: Calculate the initial thermal resistance distribution of each layer inside the package based on the three-dimensional heat conduction path structure, and determine the non-uniform regions of the initial thermal resistance distribution; specifically including: Extract the heat flow connection strength Q_l between each monitoring point P_k and the points directly connected to it from the three-dimensional heat conduction path structure M, and calculate the average heat flux density D_k of each monitoring point as D_k = ∑_(l = 1)^mQ_l / m, where m is the number of points directly connected to the monitoring point P_k; this formula represents the average value of the heat flow connection strength between all adjacent monitoring points around the monitoring point P_k. This value reflects the average heat conduction efficiency at the location of this monitoring point.

[0027] Using the average heat flux density D_k and the position P_k(x_k, y_k, z_k) of the monitoring point, calculate the initial thermal resistance value R_k corresponding to each monitoring point through the formula R_k = ΔT_k / D_k, thereby constructing the initial thermal resistance distribution map R_map inside the package; this formula represents the thermal resistance value under unit heat flux density at a given temperature change ΔT_k. A larger R_k value means poorer heat conduction performance.

[0028] In the initial thermal resistance distribution map R_map, define a threshold ΔR to identify non-uniform regions. This threshold is determined by the formula ΔR = (max(R_k) - min(R_k)) / n, where n is the total number of monitoring points. Then mark all points that satisfy the condition |R_k - avg(R)| > ΔR as non-uniform thermal resistance regions, where avg(R) represents the average value of all R_k; this formula represents the difference between the maximum and minimum values of the thermal resistance distribution divided by the total number of monitoring points, which is used to measure the dispersion degree of the thermal resistance distribution. |R_k - avg(R)| > ΔR is used to screen out the thermal resistance values that deviate significantly from the average value and identify them as non-uniform regions.

[0029] For all identified non-uniform thermal resistance regions, record their position coordinates and corresponding thermal resistance values in the initial thermal resistance distribution map R_map to form a non-uniform thermal resistance report HRR = {P_k, R_k||R_k - avg(R)| > ΔR}. The non-uniform thermal resistance report provides detailed information on abnormal regions, which helps designers to select materials or adjust structures targeted, and improve the overall thermal performance of the package.

[0030] Step 4: For the non-uniform regions, extract the thermal resistance separation parameters at the interfaces of each layer to form a hierarchical thermal resistance separation matrix; specifically including: Based on the position coordinates P_k and the corresponding thermal resistance values R_k recorded in the non-uniform thermal resistance report HRR, determine the main heat flow paths within each non-uniform region, and select several key points K_j on these paths, where j represents the jth key point; For each key point \(K_j\), calculate the temperature difference \(\Delta T_{jk}=T_{j + 1}-T_j\) between it and the adjacent layer interface. This formula represents the temperature difference between adjacent layers, reflecting the temperature change when heat is transferred from one layer to another. \(Z_j=\Delta T_{jk} / I_p\) represents the thermal resistance value under unit current intensity, directly reflecting the heat conduction ability of the material at a specific position. Where \(T_j\) is the temperature of the layer where the key point is located, \(T_{j + 1}\) is the temperature of the adjacent layer, and then calculate the thermal resistance separation parameter \(Z_j\) corresponding to this layer interface according to the formula \(Z_j=\Delta T_{jk} / I_p\); Arrange all the thermal resistance separation parameters \(Z_j\) in hierarchical order to construct a hierarchical thermal resistance separation matrix \(Z_{matrix}\). The element \(Z_{jk}\) represents the thermal resistance separation parameter between the \(j\)-th key point and the \(k\)-th layer interface, satisfying \(Z_{matrix}(j,k)=Z_j\) when \(k = j\), otherwise it is 0; \(Z_{matrix}\) is a diagonal matrix, and its non-zero elements only appear on the main diagonal, representing the thermal resistance separation parameters of each key point and its corresponding layer interface.

[0031] By analyzing the non-zero elements in the hierarchical thermal resistance separation matrix \(Z_{matrix}\), identify the layer interfaces with significant thermal resistance contributions, and record the position information of these layer interfaces and the corresponding \(Z_{jk}\) values to form a detailed hierarchical thermal resistance analysis table \(LHTA=\{position, Z_{jk}\}\), which records all the layer interfaces with significant thermal resistance contributions and their corresponding thermal resistance separation parameters, providing detailed thermal resistance distribution information for further optimizing the design or adjusting the material selection.

[0032] Step Five: Perform directional correction on the thermal resistance values corresponding to the anisotropic thermal conductive materials in the hierarchical thermal resistance separation matrix to generate a corrected hierarchical thermal resistance sequence; specifically including: Identify the elements in the hierarchical thermal resistance separation matrix \(Z_{matrix}\) to determine the position of the layer interface containing the anisotropic thermal conductive material and its corresponding thermal resistance separation parameter \(Z_{jk}\); By identifying the layer interfaces containing the anisotropic thermal conductive materials, subsequent directional corrections can be carried out targeted to improve the accuracy of thermal resistance calculation.

[0033] For each layer interface containing the anisotropic thermal conductive material, define a direction correction factor \(\alpha_l = (\lambda_a / \lambda_b)\) according to its material properties, where \(\lambda_a\) is the thermal conductivity along the main heat flow direction and \(\lambda_b\) is the thermal conductivity perpendicular to the main heat flow direction; This formula represents the ratio of the thermal conductivity along the main heat flow direction to the perpendicular direction. Since the thermal conductivity of anisotropic materials is different in different directions, this ratio is used to correct the deviation in thermal resistance calculation.

[0034] Apply the direction correction factor \(\alpha_l\) to correct the hierarchical thermal resistance separation parameter \(Z_{jk}\) and calculate the corrected thermal resistance value It means that the original thermal resistance separation parameter is multiplied by the direction correction factor to obtain the corrected thermal resistance value. This correction process ensures that the thermal resistance value reflects the true heat conduction performance of the material.

[0035] Arrange all the corrected thermal resistance values \(R'_{jk}\) in hierarchical order to form the corrected hierarchical thermal resistance sequence \(R'_{seq}=\{R'_1, R'_2, \cdots, R'_n\}\). This sequence provides the thermal resistance distribution information after directional correction, which is convenient for further analysis and optimization.

[0036] Step Six: Perform weighted superposition of the corrected hierarchical thermal resistance sequence and the initial thermal resistance distribution to calculate the total thermal resistance of the package; specifically including: Based on the initial thermal resistance values \(R_k\) of each monitoring point in the initial thermal resistance distribution map \(R_{map}\) and the corrected hierarchical thermal resistance sequence \(R'_{seq}=\{R'_1, R'_2, \cdots, R'_n\}\), determine a weight factor \(W_l = R'_l / \sum_{l = 1}^nR'_l\) for each hierarchical interface; where \(n\) is the total number of hierarchies. This weight factor reflects the relative importance of each hierarchical thermal resistance in the overall thermal resistance distribution.

[0037] Use the weight factor \(W_l\) to perform weighted processing on each element in the corrected hierarchical thermal resistance sequence \(R'_{seq}\) to generate the weighted hierarchical thermal resistance value ; This formula represents the weighted thermal resistance value, which combines the information of the original thermal resistance value and the weight factor, and reflects the actual contribution of each hierarchical thermal resistance in the overall heat conduction.

[0038] Superpose the weighted hierarchical thermal resistance value \(R''_l\) with the initial thermal resistance value \(R_k\) at the corresponding position in the initial thermal resistance distribution map \(R_{map}\), and calculate the total thermal resistance contribution value \(T_{total_k}\) of each monitoring point through the formula \(T_{total_k}=R_k+\sum_{l = 1}^nR''_l\); This formula represents the total thermal resistance contribution value of each monitoring point, which is composed of the initial thermal resistance value and all weighted hierarchical thermal resistance values. This formula ensures that both the initial thermal resistance distribution and the corrected hierarchical thermal resistance information are fully considered.

[0039] Summarize the total thermal resistance contribution values \(T_{total_k}\) of all monitoring points, and calculate the average thermal resistance value \(T_{avg}=(\sum_{k = 1}^mT_{total_k}) / m\) of the package as a whole, where \(m\) is the total number of monitoring points, representing the average value of the total thermal resistance contribution values of all monitoring points, which is a comprehensive evaluation of the overall heat conduction performance of the package.

[0040] Step Seven: Verify the accuracy of the hierarchical thermal resistance separation through the matching degree between the total thermal resistance value and the temperature response data; specifically including: Calculate the expected temperature change for each monitoring point based on the temperature change ΔT_m data at each monitoring point , where I_p is the applied current intensity, R_avg is the overall average thermal resistance T_avg, and A_k is the surface area of the region where the monitoring point is located; this formula assumes uniform heat conduction inside the package and is used to predict the temperature change that each monitoring point should reach under a given current intensity.

[0041] Compare the expected temperature change ΔT'_m with the actually measured temperature change ΔT_m, and calculate the temperature difference δ_m = ΔT_m - ΔT'm for each monitoring point; a larger δ_m value may indicate errors or inaccuracies in the hierarchical thermal resistance separation process.

[0042] Based on the temperature differences δ_m of all monitoring points, calculate the sum of squared temperature differences SSE = ∑(m = 1)^q δ_m^2, where q is the total number of monitoring points; a smaller SSE value means better consistency between the actual measured values and the expected values.

[0043] Set a predefined threshold ε. If SSE is less than or equal to ε, then confirm that the hierarchical thermal resistance separation is accurate. ε is a predefined threshold used to judge the accuracy of the hierarchical thermal resistance separation.

[0044] Step Eight: Output the verified thermal resistances of each layer and the total thermal resistance to form a thermal resistance distribution map of the package; specifically including: Based on the overall average thermal resistance T_avg and the corrected hierarchical thermal resistance sequence R'_seq = {R'_1, R'_2,..., R'_n}, calculate the finally confirmed thermal resistance of each layer interface , where S_l is the surface area of the l-th layer and J is the applied current intensity; this formula combines the actual measurement results with the theoretical model to ensure the accuracy of the thermal resistance value.

[0045] Combine the finally confirmed thermal resistances R''_l of all layer interfaces with the overall average thermal resistance T_avg to construct a list L_R = {R''_1, R''_2,..., R''_n, T_avg} that contains all the thermal resistance information of each layer. It is an ordered list that includes the finally confirmed thermal resistances of each layer interface inside the package and the overall average thermal resistance. This list provides comprehensive thermal resistance distribution information for further analysis and visualization.

[0046] Using the data in list L_R, mark the thermal resistance value R''_l of each hierarchical interface and the average thermal resistance value T_avg of the overall package at the corresponding positions in the three-dimensional coordinate system. Determine the color depth C_k of each point through the formula C_k = R''_k / max(L_R), where max(L_R) represents the maximum value in list L_R, and k represents the k-th marked point. The greater the color depth, the higher the thermal resistance value of the point; conversely, the lower it is.

[0047] Output the thermal resistance distribution map, ensuring that the positions of all hierarchical interfaces and their corresponding thermal resistance values R''_l are marked on the map, and the thermal resistance magnitudes of different regions are visually shown by the color shades. At the same time, mark the average thermal resistance value T_avg of the overall package on the map. By marking the specific values and color shades, the thermal management characteristics of the package can be intuitively understood.

[0048] On the other hand, the present invention proposes a thermal resistance test system for semiconductor device packages, as Figure 2 shown, including: A temperature response data acquisition module, which is used to apply multi-point pulse current excitation to the semiconductor device package, collect the temperature response data on the package surface, and construct the three-dimensional heat conduction path structure of the package according to the temperature response data; A hierarchical thermal resistance separation matrix generation module, which is used to calculate the initial thermal resistance distribution of each layer inside the package based on the three-dimensional heat conduction path structure, determine the non-uniform regions of the initial thermal resistance distribution, extract the thermal resistance separation parameters at the interfaces of each layer for the non-uniform regions, and form a hierarchical thermal resistance separation matrix; A total thermal resistance value calculation module, which is used to perform directional correction on the thermal resistance values corresponding to the anisotropic thermal conductive materials in the hierarchical thermal resistance separation matrix, generate a corrected hierarchical thermal resistance sequence, perform weighted superposition of the corrected hierarchical thermal resistance sequence and the initial thermal resistance distribution, and calculate the total thermal resistance value of the package; An accuracy verification and result output module, which is used to verify the accuracy of hierarchical thermal resistance separation through the matching degree between the total thermal resistance value and the temperature response data, output the verified thermal resistance values of each layer and the total thermal resistance value, and form a thermal resistance distribution map of the package.

[0049] In addition, when the above-mentioned modules are executing, they are also used to implement other steps of the above-mentioned thermal resistance test method for semiconductor device packages, as follows: Suppose we need to test the thermal resistance of the package of a high-performance chip. This chip adopts a multi-layer structure (chip + solder layer + substrate), where the solder layer is an anisotropic thermal conductive material (with better thermal conductivity along the Z-axis than the X / Y-axis). The goal is to non-destructively separate the thermal resistance contributions of each layer and optimize the package design through the method of the present invention.

[0050] Multi-point pulse current excitation and temperature response acquisition: Select 3 non - collinear injection points (A, B, C) on the encapsulation surface, which are located at the chip edge, the center, and the substrate interface respectively.

[0051] Apply a pulsed current for 5 cycles (I_p = 1A, duration 10ms, interval 1s), and record the temperature changes corresponding to each injection point.

[0052] Use an infrared camera for real - time monitoring to obtain the temperature data of the following monitoring points:

[0053] Calculate the thermal response coefficient H_p = ΔT_p / I_p: H_A = 2.3 / 1 = 2.3; H_B = 3.1 / 1 = 3.1; H_C = 1.8 / 1 = 1.8; Construct the overall thermal response matrix H_matrix = H_A + H_B + H_C = 7.2.

[0054] Construct a three - dimensional heat conduction path structure: Define a spatial coordinate system and mark the positions of 3 monitoring points: A(0,0,0), B(5mm, 5mm, 0), C(10mm, 0, 0).

[0055] Calculate the heat flow connection strength between adjacent monitoring points Q_l=(ΔT_k - ΔT_l) / d_kl: Q_AB=(2.3 - 3.1) / (√[(5)^2+(5)^2])=-0.8 / 7.07=-0.113W / mm·℃; Q_AC=(2.3 - 1.8) / 10 = 0.05W / mm·℃; Q_BC=(3.1 - 1.8) / 5 = 0.26W / mm·℃; Summarize the local heat conduction relationships and find that the main heat conduction path is B→C (Q is the largest).

[0056] Initial thermal resistance distribution and identification of non - uniform regions: Calculate the average heat flux density D_k = ∑Q_l / m (m is the number of adjacent points): D_A=(-0.113 + 0.05) / 2=-0.0315W / mm·℃; D_B=(-0.113 + 0.26) / 2 = 0.0735W / mm·℃; D_C=(0.05 + 0.26) / 2 = 0.155W / mm·℃; Initial thermal resistance R_k = ΔT_k / D_k: $R_A = 2.3 / -0.0315 = -73.0 \, ^{\circ}C \cdot mm / W$ (negative value is abnormal, need to check data rationality, assume it is caused by measurement error here, take absolute value); $R_B = 3.1 / 0.0735 = 42.2 \, ^{\circ}C \cdot mm / W$; $R_C = 1.8 / 0.155 = 11.6 \, ^{\circ}C \cdot mm / W$; Determine the threshold $\Delta R = (\max(R_k) - \min(R_k)) / n = (73.0 - 11.6) / 3 = 20.5 \, ^{\circ}C \cdot mm / W$.

[0057] Mark the non-uniform area: If $avg(R) = (73.0 + 42.2 + 11.6) / 3 = 42.3$, then the points satisfying $|R_k - avg(R)| > \Delta R$ are A and B ($73.0 - 42.3 = 30.7 > 20.5$; $42.2 - 42.3 = 0 < 20.5$).

[0058] Non-uniform thermal resistance report $HRR = \{A(73.0), B(42.2)\}$.

[0059] Hierarchical thermal resistance separation and matrix construction: Select key points $K_1$ (B) and $K_2$ (C) on the main heat conduction path B → C.

[0060] Calculate the temperature difference $\Delta T_{jk} = T_{j + 1} - T_j$: Assume the temperature of layer B is $T_B = 3.1 \, ^{\circ}C$ and the temperature of layer C is $T_C = 1.8 \, ^{\circ}C$, then $\Delta T_{jk} = -1.3 \, ^{\circ}C$.

[0061] Thermal resistance separation parameter (Take absolute value as 1.3).

[0062] Construct the hierarchical thermal resistance separation matrix $Z\_matrix$ (diagonal matrix): [1.3, 0]; [0, 1.3].

[0063] Directional correction and hierarchical thermal resistance sequence generation: Identify the solder layer (anisotropic material) at the B → C interface.

[0064] Define the direction correction factor $\alpha_l = \lambda_a / \lambda_b = 120 \, W / m \cdot K$ (along the Z-axis) / $50 \, W / m \cdot K$ (perpendicular to the Z-axis) = 2.4.

[0065] Correct the thermal resistance value .

[0066] The corrected hierarchical thermal resistance sequence $R'\_seq = \{3.12, 3.12\}$.

[0067] Weighted Superposition and Total Thermal Resistance Calculation: The weight factor W_l = R'_l / ∑R'_seq = 3.12 / (3.12 + 3.12) = 0.5.

[0068] The weighted hierarchical thermal resistance value .

[0069] The total thermal resistance contribution T_total_k = R_k + ∑R''_l: T_total_A = 73.0 + 1.56 = 74.56; T_total_B = 42.2 + 1.56 = 43.76; T_total_C = 11.6 + 1.56 = 13.16; The overall average thermal resistance of the package T_avg = (74.56 + 43.76 + 13.16) / 3 = 43.83 .

[0070] Accuracy Verification: Expected temperature change (assuming the surface area A_k = 1 cm²): (much higher than the actual value of 2.3 °C, indicating that the assumption is unreasonable and the model needs to be adjusted).

[0071] After discovering the error, correct the surface area parameter or recalibrate the model. Assume that after correction, ΔT'_m = 2.5 °C, δ_m = 2.3 - 2.5 = -0.2 °C, and SSE = (-0.2)² = 0.04.

[0072] Set the threshold ε = 0.1. Since SSE < ε, it is confirmed that the separation is accurate.

[0073] Output of Thermal Resistance Distribution Map: The list of final thermal resistance values L_R = {3.12, 3.12, 43.83}.

[0074] Mark in the three-dimensional coordinate system: The thermal resistance values of the key points K_1 (B) and K_2 (C) are 3.12, with a darker color (red); The thermal resistance values in other areas are lower (blue).

[0075] The overall average thermal resistance T_avg = 43.83 is marked on the map .

[0076] Through this embodiment, the thermal resistance at the interface between the solder layer and the substrate (3.12 ) was successfully separated, and significant thermal resistance non-uniformity (74.56 ). This prompts the designer to optimize the solder layer material distribution or increase the heat dissipation structure. The method verification result is accurate (SSE = 0.04 < ε = 0.1), proving its feasibility.

[0077] Finally, it should be noted that the above are only the preferred embodiments of the present invention and are not used to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, for those skilled in the art, they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for testing the thermal resistance of a semiconductor device package, characterized in that, It includes the following steps: Apply multi-point pulsed current excitation to the semiconductor device package, collect the temperature response data on the package surface, and construct the three-dimensional heat conduction path structure of the package according to the temperature response data; Based on the three-dimensional heat conduction path structure, calculate the initial thermal resistance distribution of each layer inside the package, determine the non-uniform region of the initial thermal resistance distribution, and for the non-uniform region, extract the thermal resistance separation parameters at the interfaces of each layer to form a layer thermal resistance separation matrix; Perform directional correction on the thermal resistance values corresponding to the anisotropic thermal conductive materials in the layer thermal resistance separation matrix, generate a corrected layer thermal resistance sequence, and perform weighted superposition of the corrected layer thermal resistance sequence and the initial thermal resistance distribution to calculate the total thermal resistance value of the package; Verify the accuracy of the layer thermal resistance separation through the matching degree between the total thermal resistance value and the temperature response data, output the verified thermal resistance values of each layer and the total thermal resistance value, and form a thermal resistance distribution map of the package.

2. The method for testing the thermal resistance of a semiconductor device package according to claim 1, characterized in that: The step of applying multi-point pulsed current excitation to the semiconductor device package and collecting the temperature response data on the package surface includes: Select at least three non-collinear positions as current injection points, apply pulsed current with a preset time interval and amplitude at each injection point, and record the temperature change data of each monitoring point on the package surface; Use an infrared camera to monitor the semiconductor device package in real time, and record the temperature change of each monitoring point on the package surface under the action of the pulsed current; Based on the relationship between the temperature change of each monitoring point and the pulsed current, calculate the thermal response coefficient corresponding to each injection point, which is used to characterize the heat conduction performance of the package material at different positions; Input all the thermal response coefficients into a summary formula to obtain an overall thermal response matrix, and analyze the heat flow distribution inside the package structure through the overall thermal response matrix.

3. The method for testing the thermal resistance of a semiconductor device package according to claim 2, characterized in that: Constructing the three-dimensional heat conduction path structure of the package according to the temperature response data includes: Use the temperature change data to determine the temperature distribution of each monitoring point; Based on the temperature distribution, define a spatial coordinate system and mark the positions of all monitoring points in the spatial coordinate system; For each monitoring point, calculate the heat flow connection strength between it and the surrounding monitoring points, and establish a local heat conduction relationship accordingly; Summarize all the local heat conduction relationships to form an overall three-dimensional heat conduction path structure, and identify the main heat conduction paths and their directions by analyzing the elements in the three-dimensional heat conduction path structure.

4. The method for testing the thermal resistance of a semiconductor device package according to claim 3, characterized in that: Calculating the initial thermal resistance distribution of each layer inside the package based on the three-dimensional heat conduction path structure and determining the non-uniform region of the initial thermal resistance distribution includes: Extract the heat flow connection strength between each monitoring point and the points directly connected to it from the three-dimensional heat conduction path structure, and calculate the average heat flux density of each monitoring point; Use the average heat flux density and the position of the monitoring point to calculate the initial thermal resistance value corresponding to each monitoring point, so as to construct an initial thermal resistance distribution map inside the package; In the initial thermal resistance distribution map, define a threshold to identify the non-uniform region, and mark the points that meet the conditions as non-uniform thermal resistance regions; For all the identified non-uniform thermal resistance regions, record their position coordinates and the corresponding thermal resistance values in the initial thermal resistance distribution map to form a non-uniform thermal resistance report.

5. The method for testing the thermal resistance of a semiconductor device package according to claim 4, characterized in that: For the non-uniform region, extract the thermal resistance separation parameters at each hierarchical interface to form a hierarchical thermal resistance separation matrix, including: Based on the position coordinates and corresponding thermal resistance values recorded in the non-uniform thermal resistance report, determine the main heat flow paths within each non-uniform region, and select several key points on the main heat flow paths; For each key point, calculate the temperature difference between it and the adjacent layer interface, and then calculate the thermal resistance separation parameter corresponding to the layer based on the temperature difference; Arrange all the thermal resistance separation parameters in hierarchical order to construct a hierarchical thermal resistance separation matrix; By analyzing the non-zero elements in the hierarchical thermal resistance separation matrix, identify the hierarchical interfaces with significant thermal resistance contributions, and record the position information of the hierarchical interfaces and the corresponding thermal resistance separation parameters to form a detailed hierarchical thermal resistance analysis table.

6. The method for testing the thermal resistance of a semiconductor device package according to claim 5, characterized in that: Perform directional correction on the thermal resistance values corresponding to the anisotropic thermal conductive materials in the hierarchical thermal resistance separation matrix to generate a corrected hierarchical thermal resistance sequence, including: Identify the elements in the hierarchical thermal resistance separation matrix, and determine the position of the hierarchical interfaces containing anisotropic thermal conductive materials and their corresponding thermal resistance separation parameters; For each hierarchical interface containing anisotropic thermal conductive materials, define a direction correction factor based on the material properties; Apply the direction correction factor to correct the hierarchical thermal resistance separation parameters and calculate the corrected thermal resistance values; Arrange all the corrected thermal resistance values in hierarchical order to form a corrected hierarchical thermal resistance sequence.

7. A method for testing the thermal resistance of a semiconductor device package according to claim 6, characterized in that: Perform weighted superposition of the corrected hierarchical thermal resistance sequence and the initial thermal resistance distribution to calculate the total thermal resistance of the package, including: Based on the initial thermal resistance values of each monitoring point in the initial thermal resistance distribution map and the corrected hierarchical thermal resistance sequence, determine a weight factor for each hierarchical interface; Use the weight factor to perform weighted processing on each element in the corrected hierarchical thermal resistance sequence to generate weighted hierarchical thermal resistance values; Superpose the weighted hierarchical thermal resistance values with the initial thermal resistance values at the corresponding positions in the initial thermal resistance distribution map to calculate the total thermal resistance contribution value of each monitoring point; Summarize the total thermal resistance contribution values of all monitoring points and calculate the average thermal resistance value of the overall package.

8. A method for testing the thermal resistance of a semiconductor device package according to claim 7, characterized in that: Verify the accuracy of the hierarchical thermal resistance separation through the matching degree between the total thermal resistance value and the temperature response data, including: Calculate the expected temperature change of each monitoring point based on the temperature change data of each monitoring point; Compare the expected temperature change with the actually measured temperature change, and calculate the temperature difference of each monitoring point; Based on the temperature differences of all monitoring points, calculate the sum of the squares of the temperature differences; Set a predefined threshold. If the sum of the squares of the temperature differences is less than or equal to the threshold, confirm that the hierarchical thermal resistance separation is accurate.

9. A method for testing the thermal resistance of a semiconductor device package according to claim 8, characterized in that: Output the verified thermal resistance values of each hierarchy and the total thermal resistance value to form a thermal resistance distribution map of the package, including: Based on the overall average thermal resistance value and the corrected hierarchical thermal resistance sequence, calculate the finally confirmed thermal resistance value of each hierarchical interface; Combine the finally confirmed thermal resistance values of all hierarchical interfaces with the overall average thermal resistance value to construct a list containing all hierarchical thermal resistance information; Using the data in the list, mark the thermal resistance values of each hierarchical interface and the overall average thermal resistance value of the package at the corresponding positions in the three-dimensional coordinate system, and determine the color depth of each point; Output a thermal resistance distribution map, ensuring that the positions of all hierarchical interfaces and their corresponding thermal resistance values are marked on the map, and the thermal resistance magnitudes of different regions are visually shown by the shade of color. At the same time, mark the average thermal resistance value of the entire package on the map.

10. A semiconductor device package thermal resistance test system for implementing the method according to any one of claims 1-9, characterized in that, Including: A temperature response data acquisition module, which is used to apply multi-point pulsed current excitation to the semiconductor device package, collect the temperature response data on the package surface, and construct a three-dimensional heat conduction path structure of the package according to the temperature response data; A hierarchical thermal resistance separation matrix generation module, which is used to calculate the initial thermal resistance distribution of each layer inside the package based on the three-dimensional heat conduction path structure, determine the non-uniform regions of the initial thermal resistance distribution, extract the thermal resistance separation parameters at the interfaces of each layer for the non-uniform regions, and form a hierarchical thermal resistance separation matrix; A total thermal resistance value calculation module, which is used to perform directional correction on the thermal resistance values corresponding to the anisotropic thermal conductive materials in the hierarchical thermal resistance separation matrix, generate a corrected hierarchical thermal resistance sequence, perform weighted superposition of the corrected hierarchical thermal resistance sequence and the initial thermal resistance distribution, and calculate the total thermal resistance value of the package; An accuracy verification and result output module, which is used to verify the accuracy of the hierarchical thermal resistance separation by the matching degree between the total thermal resistance value and the temperature response data, output the verified thermal resistance values of each layer and the total thermal resistance value, and form a thermal resistance distribution map of the package.

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