Accelerated Reliability Testing Method and Device for Semiconductor Devices Based on Stress Superposition

Abstract

Accelerated reliability test method and device for semiconductor devices based on stress superposition, which relates to the technical field of power semiconductor device testing. Obtain the acceleration factors of each key stress factor for different failure types and the interaction coefficients between each key stress factor under the current actual application scenario, obtain the optimal stress factor superposition sequence for each failure type, and construct the test content flow sequence for each failure type; test the current type of power semiconductor device according to the test content flow sequence of each failure type to obtain performance indicators; construct a failure database, and construct a feature matrix vector according to the performance indicators and store it in the failure database; perform statistical analysis on each feature matrix vector in the failure database to obtain the reliability level associated with each feature matrix, and perform reliability assessment on the performance indicators according to the failure database to obtain the reliability level of the current type of power semiconductor device, significantly improving the test efficiency and the accuracy of test results.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor device testing, and particularly to a semiconductor device accelerated reliability testing method and device based on stress superposition. Background Art

[0002] A Chinese patent with the publication number CN102073004A discloses a method for testing the reliability of semiconductor devices, which includes the following steps: measuring the NBTI curve of the first group of semiconductor devices; measuring the 1 / f noise power spectrum density and drain current of the first group of semiconductor devices at a predetermined frequency under the condition of biasing the first group of semiconductor devices in a gate electric field; measuring the equivalent oxide thickness of the gate dielectric of the first group of semiconductor devices; then biasing the second group of semiconductor devices in the gate electric field, measuring the 1 / f noise power spectrum density and drain current of the second group of semiconductor devices at the predetermined frequency; measuring the equivalent oxide thickness of the gate dielectric of the second group of semiconductor devices; and using the NBTI curve of the first group of semiconductor devices to evaluate the degradation characteristics of the second group of semiconductor devices.

[0003] A Chinese patent with the publication number CN116953466A discloses a semiconductor device environmental reliability testing method and system, which includes the following steps: dividing field effect transistors into multiple test batches; placing the field effect transistors in the test group in multiple test environments; placing the field effect transistors in the control group in a control environment; applying the same gate voltage to the gates of the field effect transistors in the same test batch, and applying multiple drain voltages to the drains of each field effect transistor respectively to obtain the drain current; obtaining the reliability score of the field effect transistor according to the change frequency and change amplitude of the test environment, the drain voltage and the drain current; and determining the environmental reliability according to the reliability score of the field effect transistor.

[0004] Existing semiconductor device reliability testing methods may ignore some stress factors that have an important impact on device failure in actual applications, or misjudge some non-critical factors as critical factors, thereby affecting the accuracy and effectiveness of subsequent tests. At the same time, the possible interaction between stress factors is not considered, and the test sequence is arranged randomly, which may not accurately simulate the failure situation in actual applications, resulting in the test results not being able to truly reflect the reliability of the device under the combined action of multiple stresses, and wasting test time and resources.

[0005] The existing reliability test methods for semiconductor devices do not construct a failure database. The reliability assessment may lack accurate data support and scientific analysis methods, and cannot comprehensively consider the influence of various factors such as actual application scenarios, design parameters, failure types, and stress factor combinations on the device reliability. It can only conduct relatively simple and one-sided evaluations, and it is difficult to give accurate reliability levels. Regarding the important information about the device failure mode and reliability, it cannot be effectively mined and utilized, and cannot provide strong support for subsequent test optimization, device design improvement, and reliability assessment, which is not conducive to accurately judging the quality and performance of semiconductor devices. Summary of the Invention

[0006] In order to solve the above technical problems, the object of the present invention is to provide an accelerated reliability test method for semiconductor devices based on stress superposition, including the following steps:

[0007] Step S1: Obtain the actual application scenario, design parameters, and performance indicators of the current type of power semiconductor device, obtain the key stress factors of the current type of power semiconductor device according to the actual application scenario, and set several key stress test contents;

[0008] Step S2: Obtain the acceleration factors of each key stress factor for different failure types and the interaction coefficients between each key stress factor under the current actual application scenario, obtain the optimal stress factor superposition order for each failure type based on the acceleration factors and interaction coefficients, and construct a test content flow sequence for each failure type according to several key stress test contents and the optimal stress factor superposition order for each failure type;

[0009] Step S3: Test the current type of power semiconductor device according to the test content flow sequence of each failure type, obtain performance indicators, judge the performance indicators, and feedback the performance indicators to the failure database or conduct a reliability assessment on the performance indicators according to the judgment results;

[0010] Step S4: Construct a failure database, construct a feature matrix vector according to the performance indicators and store it in the failure database, and the feature matrix vector is associated with the actual application scenario, design parameters, failure type, and stress factor combination;

[0011] Step S5: Conduct statistical analysis on each feature matrix vector in the failure database, obtain the reliability level associated with each feature matrix, conduct a reliability assessment on the performance indicators according to the failure database, and obtain the reliability level of the current type of power semiconductor device.

[0012] Further, the process of obtaining the key stress factors of the current type of power semiconductor device according to the actual application scenario includes:

[0013] Obtain the change range and typical values of each stress factor of the current type of power semiconductor device according to the actual application scenario, and preset a stress-failure type matrix, where the stress-failure type matrix includes the failure types corresponding to each stress factor;

[0014] Previously, according to the change range of the stress factor, the typical values of other stress factors, and the stress-failure type matrix, conduct multiple single-stress failure type tests and single-stress accelerated life tests on the current type of power semiconductor device, obtain the performance indicators corresponding to the multiple single-stress failure type tests and the acceleration factors corresponding to the stress factors, conduct statistical analysis on the performance indicators corresponding to the multiple single-stress failure type tests, obtain the performance failure coefficient and the failure rate, and according to the performance failure coefficient, the failure rate, and the acceleration factors corresponding to the stress factors, obtain the risk coefficients of the failure types corresponding to the stress factors;

[0015] Obtain the risk coefficients of each failure type corresponding to different stress factors, preset a risk coefficient threshold, and if there is a risk coefficient of the failure type corresponding to a stress factor that is greater than the risk coefficient threshold, mark the stress factor as a key stress factor.

[0016] Further, the process of conducting statistical analysis on the performance indicators corresponding to the multiple single-stress failure type tests to obtain the performance failure coefficient and the failure rate includes:

[0017] Preset a reliability standard sequence for the performance indicators, compare the time series sequence of the performance indicators corresponding to each single-stress failure type test with the reliability standard sequence, and obtain the mean square error of each single-stress failure type test;

[0018] Preset an error threshold interval, determine whether the mean square error falls within the error threshold interval. If it does not fall within, determine that the performance indicator of the current failure type test is a failure of the power semiconductor device;

[0019] If it falls within, select a threshold point within the error threshold interval to divide sub-intervals of different performance failure coefficients, and conduct a secondary judgment on the mean square error to generate the performance failure coefficient of the current failure type test. For example, a performance failure coefficient of 1 indicates a complete loss of function and endangers safety; a performance failure coefficient of 0.8 indicates a significant performance decline and immediate repair is required; a performance failure coefficient of 0.3 indicates a slight performance decline and is tolerable;

[0020] Obtain the total running time of multiple failure type tests and the cumulative number of times when the performance indicator is a failure of the power semiconductor device, and obtain the failure rate according to the total running time and the cumulative number of times. The failure rate = cumulative number of times / total running time;

[0021] The process of obtaining the risk coefficient of the stress factor according to the performance failure coefficient, the failure rate, and the acceleration factor corresponding to the stress factor includes:

[0022] ;

[0023] Wherein, represents the risk coefficient, represents the performance failure coefficient, represents the failure rate, and AF represents the acceleration factor.

[0024] Furthermore, the process of setting several key stress test contents includes:

[0025] Obtaining several key stress test contents of the current power semiconductor device according to the key stress factors, design parameters, and performance indicators

[0026] Furthermore, the process of obtaining the acceleration factors of each key stress factor and the interaction coefficients between each key stress factor for different failure types in the current actual application scenario includes:

[0027] Matching the failure types corresponding to each key stress factor included in the stress-failure type matrix. If there are consistent failure types corresponding to different key stress factors, obtain the change ranges and typical values of different key stress factors of the current type of power semiconductor device according to the actual application scenario;

[0028] Conduct multi-stress accelerated life tests on the current type of power semiconductor device according to the change ranges of different key stress factors and the typical values of other stress factors, and obtain the measured acceleration factors under different combinations of key stress factors;

[0029] Conduct single-stress accelerated life tests on the current type of power semiconductor device for different key stress factors according to the change ranges of different key stress factors and the typical values of other stress factors, and obtain the acceleration factors of different key stress factors;

[0030] Obtain the interaction coefficients between different key stress factors according to the acceleration factors of different key stress factors and the measured acceleration factors of different combinations of key stress factors.

[0031] Furthermore, the calculation formulas for obtaining the interaction types and interaction coefficients between each key stress factor are:

[0032] ;

[0033] Wherein, represents the measured acceleration factor under the combination of key stress factor i and key stress factor j, represents the acceleration factor of key stress factor i, represents the acceleration factor of key stress factor j, represents the interaction coefficient between key stress factor i and key stress factor j;

[0034] When occurs, there is a synergistic effect between the critical stress factor i and the critical stress factor j;

[0035] When occurs, there is an independent effect between the critical stress factor i and the critical stress factor j;

[0036] When occurs, there is an antagonistic effect between the critical stress factor i and the critical stress factor j;

[0037] Synergistic effect: The failure risk when two stresses are superimposed is higher than the sum of the individual stresses. Antagonistic effect: One stress alleviates the effect of the other stress (e.g., low temperature reduces the electromigration rate). Independent effect: There is no obvious interaction between the stresses.

[0038] Furthermore, the process of obtaining the optimal stress factor superposition order for each failure type based on the acceleration factor and the interaction coefficient, and constructing the test content flow sequence for each failure type based on the optimal stress factor superposition order for each failure type includes:

[0039] Construct a target function based on the acceleration factor of each critical stress factor of the failure type and the interaction coefficient between each critical stress factor, determine the constraint conditions (including failure mechanism constraints: e.g., "temperature must be applied before voltage", time constraint: total test time ≤ T_max, physical constraint: e.g., humidity cannot exceed the material's moisture absorption limit), preset several stress factor superposition orders, perform chromosome coding on several stress factor superposition orders to generate an initial population, and construct a fitness function for the stress factor superposition order based on the target function;

[0040] Among them, the specific formula of the target function is:

[0041] ;

[0042] ;

[0043] Among them, represents the total acceleration factor. When applying synergistic stresses continuously, the total acceleration factor is the product of the individual acceleration factors of each stress multiplied by the synergistic coefficient. When applying antagonistic effects continuously, the antagonistic influence is eliminated through the interval time, is the interval time, is the recovery constant (material characteristic parameter), represents the allowable residual stress ratio (usually taken as 0.05 - 0.1), is the acceleration factor when the k-th stress acts alone, is the interaction coefficient between the i-th and j-th stresses. i and j represent different key stress factors, which are used to identify the interaction between two stress factors. i, j = 1, 2,..., n, and i < j (to avoid double-counting the interaction of the same pair of stress factors). n represents the total number of key stress factors (i.e., the number of stress types involved in the test. For example, n = 3 means three stresses: temperature, voltage, and current);

[0044] Pre-obtain the life prediction error coefficient caused by the un-avoided antagonistic effect between two stress factors, and the fitness function is:

[0045] ;

[0046] ;

[0047] Among them, represents the reference acceleration factor (without considering the interaction), , represent the weight coefficients, is the reference test time (the total time without optimization), represents the life prediction error coefficient caused by the un-avoided antagonistic effect between stress factors, 0 , including stress switching and interval time, is the k-th stress factor switching time, is the l-th interval time. m represents the total number of stress factor switches, and p represents the total number of interval times;

[0048] The above formulas are all calculated by removing the dimension and taking their numerical values. The formulas are obtained by collecting a large amount of data and software simulation to get a formula closest to the real situation. The preset parameters and preset thresholds in the formulas are set by those skilled in the art according to the actual situation or obtained through a large amount of data simulation;

[0049] Based on the initial population, fitness function, and constraint conditions, obtain the best superposition order of stress factors for the failure type through an improved genetic algorithm (i.e., the stress factor superposition order with the maximum fitness function). For example, if stress factors A and B are synergistic, they are preferably applied continuously, and the order = [A → B]. If stress C and D are antagonistic, they need to be applied at intervals: the order = [C → X → D]), and the interval stress X is a stress that has no significant interaction with C / D;

[0050] According to the best superposition order of stress factors for the failure type, obtain the test order between the test contents of each key stress. Connect the test contents of each key stress according to the test order to generate the test content flow sequence of the failure type.

[0051] Under the synergistic effect, the correct sequence can maximize the acceleration factor, shorten the test time, and improve efficiency. Taking the accelerated life test of insulated gate bipolar transistors (IGBTs) as an example, the synergistic effect between temperature and voltage can significantly enhance the acceleration factor by optimizing the stress application sequence. First, apply voltage stress to locate weak links (such as oxide layer defects), and then accelerate degradation through temperature stress. Utilize the superposition effect of electric field and thermal activation to avoid the saturation effect of a single stress. The acceleration factor of IGBTs is increased to 1.3 times the theoretical value, and the test time is shortened by 50%.

[0052] Under the antagonistic effect, the wrong sequence may lead to inaccurate test results and fail to truly reflect the failure situation of the product in actual use. Taking metal-oxide-semiconductor field-effect transistors (MOSFETs) as an example, in the accelerated life test, there is an antagonistic effect between temperature and current. Applying high current stress first causes the device to heat up rapidly, and the high temperature generated by the self-heating effect inhibits the hot carrier injection effect, resulting in relatively small changes in threshold voltage drift and drain current. When applying high temperature stress subsequently, since a certain thermal stable state has been formed inside the device, the additional temperature increase has a weakened effect on the device performance, and the hot carrier injection effect cannot be fully excited, thus leading to the test results being unable to truly reflect the failure situation of the device in actual use.

[0053] By reasonably arranging the sequence of stress application, ensure the effectiveness and accuracy of stress superposition, and avoid wasting resources. Taking metal-oxide-semiconductor field-effect transistors (MOSFETs) as an example, apply high temperature stress first to change the lattice structure and electron state inside the device, creating favorable conditions for hot carrier injection. At this time, applying high current stress further enables the full play of the hot carrier injection effect, and at the same time, the self-heating effect further exacerbates the degradation of the device, making the threshold voltage drift and drain current change more significantly, and being closer to the failure situation of the device in actual use due to long-term heating and current action.

[0054] Furthermore, the process of testing the current type of power semiconductor device according to the test content flow sequence of each failure type, obtaining performance indicators, judging the performance indicators, and feeding back the performance indicators to the failure database or conducting reliability assessment of the performance indicators includes:

[0055] Test the current type of power semiconductor device in sequence according to the test content flow sequence of the failure type to obtain each performance indicator of the current type of power semiconductor device during the test process;

[0056] Obtain the failure thresholds of various performance indicators of the current type of power semiconductor device, compare each performance indicator of the current power semiconductor device with the corresponding failure threshold. If there is a performance indicator greater than the failure threshold, mark the current type of power semiconductor device as unqualified in the test, determine the failure type of the current type of power semiconductor device according to the failure type corresponding to the test content sequence, extract the numerical time series of each performance indicator and the single-item key stress test content that has been tested, generate a stress factor combination according to the single-item key stress test content that has been tested, and upload the actual application scenario, design parameters, failure type, numerical time series of each performance indicator, and stress factor combination of the current type of power semiconductor device to the failure database;

[0057] If each performance indicator is less than or equal to the failure threshold, perform a reliability assessment.

[0058] Furthermore, the process of constructing a failure database and storing the feature matrix vector constructed according to the performance indicators in the failure database includes:

[0059] Perform correlation analysis on the numerical time series of each performance indicator, obtain the evaluation standard deviation of each performance indicator and the Pearson correlation coefficient between each performance indicator, construct a feature matrix vector according to the evaluation standard deviation of each performance indicator and the Pearson correlation coefficient between each performance indicator, and store the feature matrix vector in association with the actual application scenario, design parameters, failure type, and stress factor combination in the failure database.

[0060] Furthermore, the process of performing statistical analysis on each feature matrix vector in the failure database to obtain the reliability level associated with each feature matrix includes:

[0061] Cluster the actual application scenarios, design parameters, and failure types associated with each feature matrix vector in the failure database. Cluster several feature matrices with the same associated actual application scenarios, design parameters, and failure types to obtain several groups of feature matrix vector cluster centers;

[0062] Perform statistical analysis on the stress factor combinations associated with each feature matrix included in each group of feature matrix vector cluster centers, obtain the reliability level corresponding to the stress factor combinations associated with each feature matrix included in each group of feature matrix vector cluster centers, and associate the reliability level corresponding to the stress factor combination with the feature matrix associated with the stress factor combination.

[0063] Furthermore, the calculation formula for obtaining the reliability level corresponding to the stress factor combinations associated with each feature matrix included in each group of feature matrix vector cluster centers by performing statistical analysis on the stress factor combinations associated with each feature matrix included in each group of feature matrix vector cluster centers is:

[0064] ;

[0065] Wherein, represents the reliability level of the stress factor combination z in the stress factor matrix vector clustering center y, represents the number of stress factor combinations z, The total number of stress factor combinations in the stress factor matrix vector clustering center y.

[0066] Furthermore, the process of obtaining the reliability level of the current type of power semiconductor device by performing reliability assessment on performance indicators according to the failure database includes:

[0067] Extract the numerical time series of each performance indicator for correlation analysis, obtain the evaluation standard deviation of each performance indicator and the Pearson correlation coefficient between each performance indicator, and generate stress factor combinations according to the current single key stress test content that has been tested;

[0068] Input the actual application scenario, design parameters, failure types corresponding to the test content flow sequence, and stress factor combinations of the current type of power semiconductor device into the failure database for retrieval, and obtain the characteristic matrix vectors whose associated actual application scenarios, design parameters, failure types, and stress factor combinations are consistent with those of the actual application scenario, design parameters, failure types corresponding to the test content flow sequence, and stress factor combinations of the current type of power semiconductor device;

[0069] Compare the evaluation standard deviation of each performance indicator and the Pearson correlation coefficient between each performance indicator with the characteristic matrix vectors to obtain the similarity coefficient of each characteristic matrix vector. The process of obtaining the similarity coefficient can be obtained through existing technologies such as cosine similarity and Euclidean distance, and the specific obtaining process will not be elaborated. Preset a similarity threshold. If the similarity coefficient of the characteristic matrix vector is greater than the similarity threshold, then obtain the reliability level of the current type of power semiconductor device according to the reliability level associated with the characteristic matrix vector.

[0070] A semiconductor device accelerated reliability test device based on stress superposition, wherein the semiconductor device accelerated reliability test device based on stress superposition includes a semiconductor device accelerated reliability test method program based on stress superposition. When the semiconductor device accelerated reliability test method program based on stress superposition is executed by the semiconductor device accelerated reliability test device based on stress superposition, the steps of the semiconductor device accelerated reliability test method as described in any one of the above are implemented.

[0071] Compared with the prior art, the beneficial effects of the present invention are:

[0072] 1. Precise positioning of key stress factors: By presetting the stress-failure type matrix and conducting multiple single-stress failure type tests and single-stress accelerated life tests based on the change range and typical values of stress factors, and then calculating the risk coefficient according to the performance failure coefficient, failure rate, and acceleration factor, so as to accurately mark the key stress factors. Compared with traditional empirical judgment or broad screening, this method can more accurately identify the stress factors that have a significant impact on device failure, avoid test result deviations caused by missing key factors, and lay a solid foundation for subsequent tests and analyses.

[0073] 2. Optimization of the stress factor superposition order: After obtaining the acceleration factors and interaction coefficients of the key stress factors for different failure types, by constructing an objective function and constraint conditions, using an improved genetic algorithm to determine the optimal stress factor superposition order, and constructing the corresponding test content flow sequence. This method fully considers the synergistic or antagonistic relationship between stresses. Compared with a random or fixed stress application order, it can more effectively accelerate the device failure process, shorten the test cycle, and at the same time ensure that the test results more truly reflect the failure situation in actual use, greatly improving the test efficiency and the accuracy of the results.

[0074] 3. Efficient test process and feedback mechanism: Test the device according to the test content flow sequence of the failure type, obtain the performance indicators in real time and compare them with the failure threshold. If the performance indicator is greater than the failure threshold, upload the relevant information to the failure database in a timely manner; if it does not exceed the threshold, conduct a reliability assessment. This dynamic test process and timely feedback mechanism can not only quickly capture the failure situation of the device, but also flexibly respond to different test results, providing rich data support for further analysis and improvement.

[0075] 4. Construction of a comprehensive failure database: Conduct a correlation analysis on the performance indicators, obtain the evaluation standard deviation and Pearson correlation coefficient, construct a feature matrix vector, and store it in the failure database in association with the actual application scenario, design parameters, failure type, and stress factor combination. This database not only covers a large amount of device information, but also provides a comprehensive and systematic data basis for subsequent statistical analysis and reliability assessment through scientific feature extraction and association methods, helping to deeply explore the internal laws of device failure.

[0076] 5. Accurate reliability assessment: By statistically analyzing the feature matrix vectors in the failure database, the reliability levels corresponding to different combinations of stress factors are obtained. When assessing the reliability of new performance indicators, by comparing the similarity with the relevant feature matrix vectors in the database, the reliability level of the device is determined based on the reliability level associated with the feature matrix vector with high similarity. This reliability assessment method based on big data and scientific algorithms can more comprehensively and accurately reflect the reliability level of the device compared with traditional single-index or simple model assessments, providing a strong decision-making basis for product design optimization, quality control, and market application. Description of the Drawings

[0077] Figure 1 It is a schematic diagram of the accelerated reliability test method for semiconductor devices based on stress superposition according to the embodiment of the present application. Detailed Embodiment

[0078] Next, the technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present application.

[0079] As Figure 1 shown, the accelerated reliability test method for semiconductor devices based on stress superposition includes the following steps:

[0080] Step S1: Obtain the actual application scenario, design parameters, and performance indicators of the current type of power semiconductor device, obtain the key stress factors of the current type of power semiconductor device according to the actual application scenario, and set several key stress test contents;

[0081] Step S2: Obtain the acceleration factors of each key stress factor for different failure types and the interaction coefficients between each key stress factor in the current actual application scenario, obtain the optimal stress factor superposition order for each failure type based on the acceleration factors and interaction coefficients, and construct the test content flow sequence for each failure type according to several key stress test contents and the optimal stress factor superposition order for each failure type;

[0082] Step S3: Test the current type of power semiconductor device according to the test content flow sequence of each failure type, obtain the performance indicators, determine the performance indicators, and feedback the performance indicators to the failure database or conduct a reliability assessment on the performance indicators according to the determination results;

[0083] Step s4: Construct a failure database, construct a feature matrix vector according to performance metrics and store it in the failure database, where the feature matrix vector is associated with the combination of actual application scenarios, design parameters, failure types, and stress factors;

[0084] Step s5: Conduct statistical analysis on each feature matrix vector in the failure database, obtain the reliability level associated with each feature matrix, and perform reliability assessment on the performance metrics according to the failure database to obtain the reliability level of the current type of power semiconductor device.

[0085] It should be further noted that in the specific implementation process, the process of obtaining the key stress factors of the current type of power semiconductor device according to the actual application scenario includes:

[0086] Obtain the change range and typical value of each stress factor of the current type of power semiconductor device according to the actual application scenario. The typical value represents the mean value of the stress factor of the current type of power semiconductor device in the actual application scenario. For example, the mean working temperature of a certain device is 70 , and the standard deviation is 10 , then it can be roughly considered that its normal working temperature fluctuates between 60 and 80 . Then 70 can be used as a typical value of the temperature stress factor. Preset a stress-failure type matrix, which directly corresponds the stress factors in the application scenario to the possible failure types of the device. The stress-failure type matrix includes the failure types corresponding to each stress factor. For example, high temperature - thermal fatigue (solder crack), voltage surge - PN junction breakdown, current overload - metallization layer melting;

[0087] Pre-conduct multiple single-stress failure type tests and single-stress accelerated life tests on the current type of power semiconductor device according to the change range of the stress factor, the typical values of other stress factors, and the stress-failure type matrix. In the single-stress failure type test and single-stress accelerated life test, the value corresponding to the stress factor changes within its change range, and other stress factors remain their typical values unchanged. Obtain the performance metrics corresponding to the multiple single-stress failure type tests and the acceleration factor corresponding to the stress factor. Among them, conducting accelerated life tests is a well-known technical means for those skilled in the art, and the specific steps will not be elaborated here. Conduct statistical analysis on the performance metrics corresponding to the multiple single-stress failure type tests, obtain the performance failure coefficient and failure rate, and obtain the risk coefficient of the failure type corresponding to the stress factor according to the performance failure coefficient, failure rate, and acceleration factor corresponding to the stress factor;

[0088] Obtain the risk coefficients of each failure type corresponding to different stress factors, preset a risk coefficient threshold. If the risk coefficient of the failure type corresponding to a stress factor is greater than the risk coefficient threshold, mark the stress factor as a critical stress factor.

[0089] It should be further noted that in the specific implementation process, the process of statistically analyzing the performance indicators corresponding to multiple single-stress failure type tests to obtain the performance failure coefficient and failure rate includes:

[0090] Preset a reliability standard sequence for performance indicators, compare the time series sequence of the performance indicators corresponding to each single-stress failure type test with the reliability standard sequence, and obtain the mean square error of each single-stress failure type test;

[0091] Preset an error threshold interval, determine whether the mean square error falls within the error threshold interval. If it does not fall within, determine that the performance indicator of the current failure type test is a power semiconductor device failure;

[0092] If it falls within, select a threshold point within the error threshold interval to divide the sub-intervals of different performance failure coefficients, and perform a secondary judgment on the mean square error to generate the performance failure coefficient of the current failure type test. For example, a performance failure coefficient of 1 indicates a complete loss of function and endangers safety; a performance failure coefficient of 0.8 indicates a significant performance decline and requires immediate repair; a performance failure coefficient of 0.3 indicates a slight performance decline and is tolerable;

[0093] Obtain the total running time of multiple failure type tests and the cumulative number of times the performance indicator is a power semiconductor device failure, and obtain the failure rate based on the total running time and the cumulative number of times. The failure rate = cumulative number of times / total running time;

[0094] The process of obtaining the risk coefficient of a stress factor based on the performance failure coefficient, failure rate, and acceleration factor corresponding to the stress factor includes:

[0095] ;

[0096] Wherein, represents the risk coefficient, represents the performance failure coefficient, represents the failure rate, and AF represents the acceleration factor.

[0097] It should be further noted that in the specific implementation process, the process of setting several key stress test contents includes:

[0098] Obtain the actual application scenarios, design parameters (including rated voltage, rated current, maximum surge current, maximum junction temperature, operating temperature range, vibration / shock resistance, humidity sensitivity level, etc.), and performance indicators (including on-state voltage drop, switching time, off-state leakage current, voltage overshoot, avalanche resistance, etc.) of the current type of power semiconductor device. According to the actual application scenario, obtain the key stress factors of the current type of power semiconductor device. It should be further noted that the stress factors include temperature, voltage, current, etc. According to the key stress factors, design parameters, and performance indicators, obtain several key stress test contents of the current power semiconductor device. For example, the key stress factors of the temperature cycle test: high temperature (such as 150 ), and low temperature (such as -40 ), alternating, design parameters: coefficient of thermal expansion (CTE) of the material, thickness of the chip solder layer, performance indicators: fatigue life of the solder layer, junction temperature (Tj) distribution; the key stress factors of the voltage overshoot test: over-rated voltage (such as +20%V_rated), design parameters: doping concentration of the PN junction, field limiting ring structure, performance indicators: breakdown voltage (V_br), reverse recovery time (t_rr).

[0099] It should be further noted that in the specific implementation process, the process of obtaining the acceleration factors of each key stress factor for different failure types and the interaction coefficient between each key stress factor under the current actual application scenario includes:

[0100] Match the failure types corresponding to each key stress factor included in the stress-failure type matrix. If there are consistent failure types corresponding to different key stress factors, obtain the change range and typical values of different key stress factors of the current type of power semiconductor device according to the actual application scenario;

[0101] According to the change range of different key stress factors and the typical values of other stress factors, conduct a multi-stress accelerated life test on the current type of power semiconductor device to obtain the measured acceleration factors under different combinations of key stress factors;

[0102] According to the change range of different key stress factors and the typical values of other stress factors, conduct a single-stress accelerated life test on the current type of power semiconductor device for different key stress factors to obtain the acceleration factors of different key stress factors;

[0103] According to the acceleration factors of different key stress factors and the measured acceleration factors of different combinations of key stress factors, obtain the interaction coefficient between different key stress factors.

[0104] It should be further noted that in the specific implementation process, the calculation formula for obtaining the interaction type and interaction coefficient between each key stress factor is:

[0105] ;

[0106] Wherein, represents the measured acceleration factor under the combination of the key stress factor i and the key stress factor j, represents the acceleration factor of the key stress factor i, represents the acceleration factor of the key stress factor j, represents the interaction coefficient between the key stress factor i and the key stress factor j;

[0107] When there is a synergistic effect between the key stress factor i and the key stress factor j;

[0108] When there is an independent effect between the key stress factor i and the key stress factor j;

[0109] When there is an antagonistic effect between the key stress factor i and the key stress factor j;

[0110] Synergistic effect: The failure risk when two stresses are superimposed is higher than the sum of the single stresses. Antagonistic effect: One stress alleviates the influence of another stress (such as low temperature reducing the electromigration rate). Independent effect: There is no obvious interaction between the stresses.

[0111] It should be further noted that in the specific implementation process, the process of obtaining the optimal stress factor superposition order for each failure type based on the acceleration factor and the interaction coefficient, and constructing the test content flow sequence for each failure type based on the optimal stress factor superposition order for each failure type includes:

[0112] Construct a target function according to the acceleration factor of each key stress factor of the failure type and the interaction coefficient between each key stress factor, determine the constraint conditions (including failure mechanism constraints: such as "temperature must be applied before voltage", time constraint: the total test time ≤ T_max, physical constraint: such as humidity cannot exceed the material moisture absorption limit), preset several stress factor superposition orders, perform chromosome coding on several stress factor superposition orders, generate an initial population, and construct a fitness function for the stress factor superposition order according to the target function;

[0113] Among them, the specific formula of the target function is:

[0114] ;

[0115] ;

[0116] Among them, Denote the total acceleration factor. When applying combined stresses continuously, the total acceleration factor is the product of the individual acceleration factors of each stress multiplied by the synergy coefficient. When applying antagonistic effects continuously, the antagonistic influence is eliminated through the interval time. is the interval time, is the recovery constant (a material characteristic parameter), denotes the allowable proportion of residual stress (usually taken as 0.05 - 0.1), is the acceleration factor when the k-th stress acts alone, is the interaction coefficient between the i-th and j-th stresses. i and j represent different key stress factors, used to identify the interaction between two stress factors. i, j = 1, 2,..., n, and i < j (to avoid double-counting the interaction of the same pair of stress factors), where n represents the total number of key stress factors (i.e., the number of stress types involved in the test. For example, n = 3 represents three stresses: temperature, voltage, and current);

[0117] Pre-acquire the life prediction error coefficient caused by the un-avoided antagonistic effect between two stress factors, the fitness function is:

[0118] ;

[0119] ;

[0120] Among them, denotes the reference acceleration factor (without considering interaction), 、 denote the weight coefficients, is the reference test time (the total time without optimization), denotes the life prediction error coefficient caused by the un-avoided antagonistic effect between stress factors, 0 , including stress switching and interval time, is the switching time of the k-th stress factor, is the l-th interval time. m represents the total number of stress factor switches, and p represents the total number of interval times;

[0121] The above formulas are all calculated by taking the numerical values after removing the dimensions. The formulas are obtained by collecting a large amount of data and performing software simulations to get a formula closest to the actual situation. The preset parameters and preset thresholds in the formulas are set by those skilled in the art according to the actual situation or obtained through a large amount of data simulations;

[0122] Based on the initial population, fitness function, and constraint conditions, obtain the optimal stress factor superposition order for the failure type (i.e., the stress factor superposition order with the maximum fitness function) through an improved genetic algorithm. For example, if stress factors A and B are synergistic, they should be applied continuously in priority, and the order = [A → B]. If stress C and D are antagonistic, they need to be applied at intervals: the order = [C → X → D], where the interval stress X is a stress that has no significant interaction with C / D;

[0123] According to the optimal stress factor superposition order of the failure type, obtain the test order between the key stress test contents, and connect the key stress test contents according to the test order to generate the test content sequence of the failure type.

[0124] Under the synergistic effect, the correct order can maximize the acceleration factor, shorten the test time, and improve the efficiency. Taking the accelerated life test of insulated gate bipolar transistors (IGBTs) as an example, the synergistic effect between temperature and voltage can significantly increase the acceleration factor by optimizing the stress application order. First, apply the voltage stress to locate the weak links (such as oxide layer defects), and then accelerate the degradation through the temperature stress. Utilize the superposition effect of electric field and thermal activation to avoid the saturation effect of a single stress, and increase the acceleration factor of IGBTs to 1.3 times the theoretical value, shortening the test time by 50%;

[0125] Under the antagonistic effect, the wrong order may lead to inaccurate test results and cannot truly reflect the failure situation of the product in actual use. Taking metal-oxide-semiconductor field-effect transistors (MOSFETs) as an example, in the accelerated life test, there is an antagonistic effect between temperature and current. Applying a high current stress first causes the device to heat up rapidly, and the high temperature generated by the self-heating effect inhibits the hot carrier injection effect, resulting in relatively small changes in the threshold voltage drift and drain current. When applying a high temperature stress later, since a certain thermal stable state has been formed inside the device, the additional temperature increase has a weakened effect on the device performance and cannot fully stimulate the hot carrier injection effect, thus leading to the test results not being able to truly reflect the failure situation of the device in actual use;

[0126] By reasonably arranging the stress application order, ensure the effectiveness and accuracy of stress superposition, and avoid wasting resources. Taking metal-oxide-semiconductor field-effect transistors (MOSFETs) as an example, first apply a high temperature stress to change the lattice structure and electron state inside the device, creating favorable conditions for hot carrier injection. Then apply a high current stress, and the hot carrier injection effect can be fully exerted. At the same time, the self-heating effect further exacerbates the degradation of the device, making the threshold voltage drift and drain current change more significantly, and being closer to the failure situation of the device due to long-term heating and current action in actual use.

[0127] It should be further noted that in the specific implementation process, the process of testing the current type of power semiconductor device according to the test content flow sequence of each failure type, obtaining performance indicators, judging the performance indicators, and feeding back the performance indicators to the failure database or conducting reliability evaluation on the performance indicators includes:

[0128] Test the current type of power semiconductor device successively according to the test content flow sequence of the failure type to obtain each performance indicator of the current type of power semiconductor device during the test process;

[0129] Obtain the failure thresholds of each performance indicator of the current type of power semiconductor device, compare each performance indicator of the current power semiconductor device with the corresponding failure threshold. If there is a performance indicator greater than the failure threshold, mark the current type of power semiconductor device as unqualified in the test, determine the failure type of the current type of power semiconductor device according to the failure type corresponding to the test content flow sequence, extract the numerical time series of each performance indicator and the single-item key stress test content that has been tested, generate a stress factor combination according to the single-item key stress test content that has been tested, and upload the actual application scenario, design parameters, failure type, numerical time series of each performance indicator, and stress factor combination of the current type of power semiconductor device to the failure database;

[0130] If each performance indicator is less than or equal to the failure threshold, conduct reliability evaluation.

[0131] It should be further noted that in the specific implementation process, the process of constructing a failure database and storing the feature matrix vector constructed according to the performance indicators in the failure database includes:

[0132] Conduct correlation analysis on the numerical time series of each performance indicator to obtain the evaluation standard deviation of each performance indicator and the Pearson correlation coefficient between each performance indicator. Construct a feature matrix vector according to the evaluation standard deviation of each performance indicator and the Pearson correlation coefficient between each performance indicator, and store the feature matrix vector in association with the actual application scenario, design parameters, failure type, and stress factor combination in the failure database.

[0133] It should be further noted that in the specific implementation process, the process of statistically analyzing each feature matrix vector in the failure database to obtain the reliability level associated with each feature matrix includes:

[0134] Cluster the actual application scenarios, design parameters, and failure types associated with each feature matrix vector in the failure database. Cluster several feature matrices with the same associated actual application scenarios, design parameters, and failure types to obtain several groups of feature matrix vector cluster centers;

[0135] Perform a statistical analysis on the stress factor combinations associated with each feature matrix included in the clustering center of each group of feature matrix vectors, obtain the reliability level corresponding to the stress factor combination associated with each feature matrix included in the clustering center of each group of feature matrix vectors, and associate the reliability level corresponding to the stress factor combination with the feature matrix associated with the stress factor combination.

[0136] It should be further noted that in the specific implementation process, when performing a statistical analysis on the stress factor combinations associated with each feature matrix included in the clustering center of each group of feature matrix vectors to obtain the calculation formula for the reliability level corresponding to the stress factor combination associated with each feature matrix included in the clustering center of each group of feature matrix vectors:

[0137] ;

[0138] Among them, represents the reliability level of the stress factor combination z in the feature matrix vector clustering center y, represents the number of stress factor combinations z, The total number of stress factor combinations in the feature matrix vector clustering center y.

[0139] It should be further noted that in the specific implementation process, the process of obtaining the reliability level of the current type of power semiconductor device by performing a reliability assessment on the performance indicators according to the failure database includes:

[0140] Extract the numerical time series of each performance indicator for correlation analysis, obtain the evaluation standard deviation of each performance indicator and the Pearson correlation coefficient between each performance indicator, and generate a stress factor combination according to the current single key stress test content that has been tested;

[0141] Input the actual application scenario, design parameters, failure types corresponding to the test content flow sequence, and stress factor combination of the current type of power semiconductor device into the failure database for retrieval, and obtain the feature matrix vectors whose associated actual application scenario, design parameters, failure types, and stress factor combination are consistent with the actual application scenario, design parameters, failure types corresponding to the test content flow sequence, and stress factor combination of the current type of power semiconductor device;

[0142] Compare the evaluation standard deviation of each performance indicator and the Pearson correlation coefficient between each performance indicator with the feature matrix vectors to obtain the similarity coefficient of each feature matrix vector. The process of obtaining the similarity coefficient can be obtained through existing technologies such as cosine similarity and Euclidean distance. The specific obtaining process will not be elaborated here. Preset a similarity threshold. If the similarity coefficient of the feature matrix vector is greater than the similarity threshold, then obtain the reliability level of the current type of power semiconductor device according to the reliability level associated with the feature matrix vector.

[0143] An accelerated reliability test device for semiconductor devices based on stress superposition, wherein the accelerated reliability test device for semiconductor devices based on stress superposition includes a program for the accelerated reliability test method of semiconductor devices based on stress superposition. When the program for the accelerated reliability test method of semiconductor devices based on stress superposition is executed by the accelerated reliability test device for semiconductor devices based on stress superposition, the steps of the accelerated reliability test method of semiconductor devices based on stress superposition as described in any one of the above are realized.

[0144] The above embodiments are only used to illustrate the technical method of the present invention and not to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical method of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical method of the present invention.

Claims

1. A semiconductor device accelerated reliability test method based on stress superposition, characterized in that It includes the following steps: Step S1: Obtain the actual application scenario, design parameters, and performance indicators of the current type of power semiconductor device. According to the actual application scenario, obtain the key stress factors of the current type of power semiconductor device, and set several key stress test contents; Step S2: Obtain the acceleration factors of each key stress factor for different failure types and the interaction coefficients between each key stress factor under the current actual application scenario. Based on the acceleration factors and interaction coefficients, obtain the optimal stress factor superposition order for each failure type, and construct the test content flow sequence for each failure type, including: Obtain the stress-failure type matrix, match the failure types corresponding to each key stress factor included in the stress-failure type matrix. If there are consistent failure types corresponding to different key stress factors, obtain the change range and typical values of different key stress factors of the current type of power semiconductor device according to the actual application scenario; According to the change range of different key stress factors and the typical values of other stress factors, conduct multi-stress accelerated life tests on the current type of power semiconductor device to obtain the measured acceleration factors under different combinations of key stress factors; According to the change range of different key stress factors and the typical values of other stress factors, conduct single-stress accelerated life tests on different key stress factors of the current type of power semiconductor device to obtain the acceleration factors of different key stress factors; According to the acceleration factors of different key stress factors and the measured acceleration factors of different combinations of key stress factors, obtain the interaction coefficients between different key stress factors; Construct an objective function based on the acceleration factors of each key stress factor of the failure type and the interaction coefficients between each key stress factor, determine the constraint conditions, preset several stress factor superposition orders, perform chromosome coding on several stress factor superposition orders to generate an initial population, and construct a fitness function for the stress factor superposition order based on the objective function; Obtain the optimal stress factor superposition order of the failure type through an improved genetic algorithm based on the initial population, fitness function, and constraint conditions; According to the optimal stress factor superposition order of the failure type, obtain the test order between each key stress test content, and connect each key stress test content according to the test order to generate the test content flow sequence of the failure type; Among them, the constraint conditions include failure mechanism constraints, time constraints, and physical constraints; The specific formula of the objective function is: ； ； Among them, represents the total acceleration factor, is the interval time, is the recovery constant, represents the allowable residual stress ratio, is the acceleration factor when the k-th stress acts alone, is the interaction coefficient between the i-th and j-th stresses, where i and j represent different key stress factors, i, j = 1, 2,..., n, and i < j, and n represents the total number of key stress factors; Step S3: Test the current type of power semiconductor device according to the test content flow sequence of each failure type, obtain the performance indicators, judge the performance indicators, and feedback the performance indicators to the failure database or conduct reliability evaluation on the performance indicators according to the judgment results; Step S4: Construct a failure database, and construct a feature matrix vector according to the performance indicators and store it in the failure database. The feature matrix vector is associated with the actual application scenario, design parameters, failure type, and stress factor combination; Step s5: Statistically analyze each feature matrix vector in the failure database to obtain the reliability level associated with each feature matrix vector. Conduct a reliability assessment of the performance metrics based on the failure database to obtain the reliability level of the current type of power semiconductor device.

2. The accelerated reliability test method for semiconductor devices based on stress superposition according to claim 1, wherein The process of obtaining the key stress factors of the current type of power semiconductor device according to the actual application scenario includes: Obtain the change range and typical values of each stress factor of the current type of power semiconductor device according to the actual application scenario, and preset a stress-failure type matrix, where the stress-failure type matrix includes the failure types corresponding to each stress factor; Previously, based on the change range of the stress factor, the typical values of other stress factors, and the stress-failure type matrix, conduct multiple single-stress failure type tests and single-stress accelerated life tests on the current type of power semiconductor device to obtain the performance metrics corresponding to the multiple single-stress failure type tests and the acceleration factor corresponding to the stress factor. Statistically analyze the performance metrics corresponding to the multiple single-stress failure type tests to obtain the performance failure coefficient and the failure rate. Based on the performance failure coefficient, the failure rate, and the acceleration factor corresponding to the stress factor, obtain the risk coefficient of the failure type corresponding to the stress factor; Obtain the risk coefficients of each failure type corresponding to different stress factors, and preset a risk coefficient threshold. If the risk coefficient of the failure type corresponding to the stress factor is greater than the risk coefficient threshold, mark the stress factor as a key stress factor.

3. The semiconductor device accelerated reliability test method based on stress superposition according to claim 2, wherein Obtain several key stress test contents of the current power semiconductor device based on the key stress factors, design parameters, and performance metrics.

4. The accelerated reliability test method for semiconductor devices based on stress superposition according to claim 3, wherein, The process of determining the performance metrics and feedbacking the performance metrics to the failure database or conducting a reliability assessment based on the determination result includes: Test the current type of power semiconductor device sequentially according to the test content sequence of the failure type to obtain each performance metric of the current type of power semiconductor device during the test process; Obtain the failure threshold of each performance metric of the current type of power semiconductor device, compare each performance metric of the current power semiconductor device with the corresponding failure threshold. If there is a performance metric greater than the failure threshold, mark the current type of power semiconductor device as unqualified in the test. Determine the failure type of the current type of power semiconductor device according to the failure type corresponding to the test content sequence. Extract the numerical time series of each performance metric and the single key stress test content that has been tested, generate a stress factor combination based on the single key stress test content that has been tested, and upload the actual application scenario, design parameters, failure type, numerical time series of each performance metric, and stress factor combination of the current type of power semiconductor device to the failure database; If each performance metric is less than or equal to the failure threshold, conduct a reliability assessment.

5. The accelerated reliability test method for semiconductor devices based on stress superposition according to claim 4, characterized in that Construct a failure database. The process of constructing a feature matrix vector based on the performance metrics and storing it in the failure database includes: Perform correlation analysis on the numerical time series of each performance metric to obtain the evaluation standard deviation of each performance metric and the Pearson correlation coefficient between each performance metric. Construct a feature matrix vector based on the evaluation standard deviation of each performance metric and the Pearson correlation coefficient between each performance metric, and store the feature matrix vector in association with the actual application scenario, design parameters, failure type, and stress factor combination in the failure database.

6. The accelerated reliability test method for semiconductor devices based on stress superposition according to claim 5, wherein The process of performing statistical analysis on each feature matrix vector in the failure database to obtain the reliability level associated with each feature matrix vector includes: Cluster the actual application scenarios, design parameters, and failure types associated with each feature matrix vector in the failure database. Cluster several feature matrix vectors with the same associated actual application scenarios, design parameters, and failure types to obtain several groups of feature matrix vector cluster centers. Perform statistical analysis on the stress factor combinations associated with each feature matrix vector included in each group of feature matrix vector cluster centers to obtain the reliability level corresponding to the stress factor combinations associated with each feature matrix vector included in each group of feature matrix vector cluster centers, and associate the reliability level corresponding to the stress factor combination with the feature matrix vector associated with the stress factor combination.

7. The accelerated reliability test method for semiconductor devices based on stress superposition according to claim 6, characterized in that The process of performing reliability assessment on the performance metrics based on the failure database to obtain the reliability level of the current type of power semiconductor device includes: Extract the numerical time series of each performance metric for correlation analysis to obtain the evaluation standard deviation of each performance metric and the Pearson correlation coefficient between each performance metric, and generate a stress factor combination based on the current single key stress test content that has been tested. Input the actual application scenario, design parameters, failure type corresponding to the test content flow sequence, and stress factor combination of the current type of power semiconductor device into the failure database for retrieval to obtain the associated actual application scenario, design parameters, failure type, and stress factor combination, and a feature matrix vector that is consistent with the actual application scenario, design parameters, failure type corresponding to the test content flow sequence, and stress factor combination of the current type of power semiconductor device. Compare the evaluation standard deviation of each performance metric and the Pearson correlation coefficient between each performance metric with the feature matrix vector to obtain the similarity coefficient of each feature matrix vector. Preset a similarity threshold. If the similarity coefficient of the feature matrix vector is greater than the similarity threshold, obtain the reliability level of the current type of power semiconductor device based on the reliability level associated with the feature matrix vector.

8. An accelerated reliability test device for semiconductor devices based on stress superposition, characterized in that: The semiconductor device accelerated reliability test device based on stress superposition includes a semiconductor device accelerated reliability test method program based on stress superposition. When the semiconductor device accelerated reliability test method program based on stress superposition is executed by the semiconductor device accelerated reliability test device based on stress superposition, the steps of the semiconductor device accelerated reliability test method according to any one of claims 1 to 7 are implemented.

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