A bandgap reference source circuit

Abstract

This invention discloses a bandgap reference source circuit, relating to the field of integrated circuit technology, used to reduce the power consumption and complexity of traditional bandgap reference source circuits. The bandgap reference source circuit includes: an NMOS transistor, a first PMOS transistor, a second PMOS transistor, a first resistor, a second resistor, and a transistor network. The source of the NMOS transistor is connected to a power supply to maintain its conduction state during the power-on process of the bandgap reference power supply circuit. The drain of the NMOS transistor is connected to the output terminal of the bandgap reference source circuit and is connected to the transistor network based on the first and second resistors. The two ends of the transistor network are respectively connected to the drains of the first and second PMOS transistors to enable the current mirror formed by the first and second PMOS transistors to function normally.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a bandgap reference source circuit. Background Technology

[0002] A bandgap reference source circuit is a common circuit structure in chips, used to provide the chip with a reference voltage V that does not change with the supply voltage or temperature. REF (Typically 1.2V). Please refer to [reference needed]. Figure 1 , Figure 1 The structural diagram of the bandgap reference source circuit provided in the background of this application.

[0003] Existing bandgap reference source circuits require a startup circuit ( Figure 1 (not shown in the image), power supply voltage V DD During power-on, when the gate voltage (V) of PM1 E ) equals V DD When this happens, the circuit will enter and lock into an incorrect steady state, causing it to malfunction. An additional startup circuit is needed to restore the circuit to its normal steady state, but this increases circuit complexity and power consumption. Meanwhile, the auxiliary operational amplifier A1 and its bias circuit in the existing bandgap reference source circuit ( Figure 1 (Not shown in the image) This will further increase the overall power consumption of the circuit, making it unsuitable for some low-power applications. Summary of the Invention

[0004] In view of the above-mentioned technical status, the present invention provides a bandgap reference source circuit to reduce the power consumption of the bandgap reference source circuit.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A bandgap reference source circuit includes: an NMOS transistor, a first PMOS transistor, a second PMOS transistor, a first resistor, a second resistor, and a transistor network;

[0007] The drain of the NMOS transistor is connected to the power supply to maintain its conduction state during the power-on process of the bandgap reference power supply circuit; the source of the NMOS transistor is connected to the output terminal of the bandgap reference source circuit and is connected to the transistor network based on the first resistor and the second resistor.

[0008] The two ends of the transistor network are respectively connected to the drains of the first PMOS transistor and the second PMOS transistor, so as to enable the current mirror composed of the first PMOS transistor and the second PMOS transistor to work normally.

[0009] In one optional embodiment of this application, the NMOS transistor is a depletion-type NMOS transistor, and the threshold voltage of the NMOS transistor is less than zero.

[0010] In one optional embodiment of this application, a capacitor is also included;

[0011] One end of the capacitor is connected to the gate of the NMOS transistor and the drain of the second PMOS transistor, and the other end is grounded.

[0012] In one optional embodiment of this application, the transistor network includes: a first transistor, a second transistor, a third transistor, and a fourth transistor;

[0013] The emitter area ratio of the first transistor and the second transistor is 1:N; the emitter area ratio of the third transistor and the fourth transistor is 1:1;

[0014] The collector of the fourth transistor is connected to the drain of the second PMOS transistor, the emitter of the fourth transistor is grounded, and the base of the fourth transistor is connected to the second resistor and the collector of the second transistor, respectively.

[0015] The emitter of the second transistor is grounded, and the base of the second transistor is connected to the collector of the first transistor, one end of the first resistor, and the base of the third transistor.

[0016] The emitter of the first transistor is grounded, and the base of the first transistor is connected to the other end of the first resistor;

[0017] The emitter of the third transistor is grounded, and the collector of the third transistor is connected to the drain of the first PMOS transistor.

[0018] In one optional embodiment of this application, a third resistor is also included;

[0019] One end of the third resistor is connected to the first resistor and the second resistor, respectively, and the other end of the third resistor is connected to the source of the NMOS transistor and the output terminal of the bandgap reference source circuit, respectively.

[0020] In one optional embodiment of this application, the resistance values ​​of the first resistor and the second resistor are equal.

[0021] In one optional embodiment of this application, the first PMOS transistor and the second PMOS transistor constitute a 1:1 current mirror.

[0022] In one optional embodiment of this application, the bandgap reference voltage output from the output terminal of the bandgap reference source circuit is expressed by the following formula:

[0023]

[0024] Among them, V REF The bandgap reference voltage is represented by: T; temperature; k and q are constants; N represents the ratio of the emitter area of ​​the second transistor to that of the first transistor; R1 represents the resistance value of the first resistor; R3 represents the resistance value of the third resistor; V BE,Q2 This represents the voltage between the base and emitter of the second transistor.

[0025] Compared with the prior art, the present invention provides a bandgap reference source circuit. This circuit connects the source of an NMOS transistor to the power supply to enable the bandgap reference source circuit to start up via the NMOS transistor, reducing the complexity of the circuit structure. It maintains the conduction state during the power-on startup process of the bandgap reference source circuit, thus solving the problem of erroneous steady state in traditional bandgap reference source circuits. At the same time, a current mirror clamping device composed of a first PMOS transistor, a second PMOS transistor, and a transistor network is constructed to clamp the voltage of the node where the first and second resistors are connected to the transistor network, saving additional bias circuitry and reducing the overall power consumption of the circuit. Attached Figure Description

[0026] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0027] Figure 1 The structural diagram of the bandgap reference source circuit provided in the background of this application;

[0028] Figure 2 This is a schematic diagram of the bandgap reference source circuit provided in an embodiment of this application. Detailed Implementation

[0029] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0030] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0031] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0032] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0033] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0034] A bandgap reference source circuit is a common circuit structure in chips, used to provide the chip with a reference voltage V that does not change with the supply voltage or temperature. REF (Typically 1.2V). Please refer to [reference needed]. Figure 1 , Figure 1 The structural diagram of the bandgap reference source circuit provided in the background of this application.

[0035] Figure 1 In the diagram, the emitter area ratio of transistor Q1 to transistor Q2 is 1:N, and the resistance values ​​of resistors R2 and R3 are equal (R2 = R3).

[0036] In practical applications, the virtual short-circuit characteristic of the auxiliary operational amplifier A1 causes the voltage V at node A to... A With the voltage V at node B B Since R2 = R3, the current flowing through resistors R2 and R3 is also equal, that is:

[0037]

[0038] Among them, I R2 This represents the current flowing through resistor R2; VD V represents the voltage at node D; B V represents the voltage at node B. A I represents the voltage at node A; R3 R1 represents the current flowing through resistor R3; R2 represents the resistance value of resistor R2; R3 represents the resistance value of resistor R3.

[0039] Furthermore, since transistor Q1 is connected in series with resistor R3, and transistor Q2 is connected in series with resistor R2, the current flowing through transistors Q1 and Q2 is equal. Therefore, the voltage at node A is the voltage V between the base and emitter of transistor Q1. BE,Q1 The voltage at node C is equal to the voltage V between the base and emitter of transistor Q2. BE,Q2 Therefore, the voltage drop across resistor R1 can be expressed by the following formula (1):

[0040]

[0041] Among them, V R1 The voltage drop across resistor R1 is represented by T; temperature is represented by K and q, which are constants; and N represents the ratio of the emitter area of ​​transistor Q2 to that of transistor Q1.

[0042] The current flowing through resistor R1 can be expressed by the following formula (2):

[0043]

[0044] Among them, I R1 This represents the current flowing through resistor R1.

[0045] Based on the above formula (2), it can be seen that the current flowing through resistor R1 is a positive temperature coefficient current, and its positive temperature coefficient is related to the resistance values ​​of N and R1. Therefore, the final bandgap reference voltage can be expressed by the following formula (3):

[0046]

[0047] Among them, V REF This represents the bandgap reference voltage.

[0048] Because the voltage V between the base and emitter of transistor Q1 BE,Q1 It has a negative temperature coefficient; therefore, by adjusting the proportional relationship between N, R1, R3, and R4 in the above formula, the formula can be adjusted. The positive temperature coefficient is related to the voltage V BE,Q1 The negative temperature coefficients of V are opposites, which in turn makes V REF Its temperature coefficient is approximately 0, and it hardly changes with temperature, thus providing a stable bandgap reference voltage.

[0049] Existing bandgap reference source circuits require a startup circuit ( Figure 1 (not shown in the image), power supply voltage V DD During power-on, when the gate voltage (V) of PM1 E ) equals V DD When this happens, the circuit will enter and lock into an incorrect steady state, causing it to malfunction. An additional startup circuit is needed to restore the circuit to its normal steady state, but this increases circuit complexity and power consumption. Meanwhile, the auxiliary operational amplifier A1 and its bias circuit in the existing bandgap reference source circuit ( Figure 1 (Not shown in the image) This will further increase the overall power consumption of the circuit, making it unsuitable for some low-power applications.

[0050] In view of the above-mentioned technical status, the present invention provides a bandgap reference source circuit to reduce the power consumption of the bandgap reference source circuit.

[0051] Please refer to the bandgap reference source voltage provided in the embodiments of this application. Figure 2 , Figure 2 This is a schematic diagram of the bandgap reference source circuit provided in an embodiment of this application.

[0052] like Figure 2 As shown, the bandgap reference source circuit includes: an NMOS transistor (i.e., NMOS), a first PMOS transistor (i.e., PMOS1), a second PMOS transistor (i.e., PMOS2), a first resistor R1, a second resistor R2, and a transistor network.

[0053] The drain of the NMOS transistor is connected to the power supply VDD to maintain its conduction state during the power-on process of the bandgap reference power supply circuit.

[0054] The source of the NMOS transistor is connected to the output of the bandgap reference circuit, and the source of the NMOS transistor is connected to the transistor network based on the first resistor R1 and the second resistor R2.

[0055] The two ends of the transistor network are connected to the drains of PMOS1 and PMOS2 respectively, which is used to enable the current mirror formed by PMOS1 and PMOS2 to work normally. PMOS1 and PMOS2 are 1:1 current mirrors.

[0056] The transistor network includes: a first transistor Q1, a second transistor Q2, a third transistor Q3, and a fourth transistor Q4.

[0057] The emitter area ratio of the first transistor Q1 to the second transistor Q2 is 1:N, and the emitter area ratio of the third transistor Q3 to the fourth transistor Q4 is 1:1.

[0058] The collector of the fourth transistor Q4 is connected to the drain of PMOS2, the emitter of the fourth transistor Q4 is grounded, and the base of the fourth transistor Q4 is connected to the second resistor R1 and the collector of the second transistor Q2 respectively.

[0059] The emitter of the second transistor Q2 is grounded, and the base of the second transistor Q2 is connected to the collector of the first transistor Q1, one end of the second resistor R2, and the collector of the third transistor Q3.

[0060] The emitter of the first transistor Q1 is grounded, and the base of the first transistor Q1 is connected to the other end of the first resistor R1.

[0061] The emitter of the third transistor Q3 is grounded, and the collector of the third transistor Q3 is connected to the drain of PMOS1.

[0062] The bandgap reference source circuit further includes: a third resistor R3, one end of which is connected to the first resistor R1 and the second resistor R2 respectively, and the other end of which is connected to the source of the NMOS transistor and the output terminal of the bandgap reference source circuit respectively.

[0063] The resistance values ​​of the first resistor R1 and the second resistor R2 are equal.

[0064] In one optional embodiment of this application, the bandgap reference source circuit further includes: capacitor C1;

[0065] One end of capacitor C1 is connected to the gate of NMOS and the drain of PMOS2, and the other end is grounded. This makes the rise rate of the NMOS gate voltage during power-on more gradual, preventing the bandgap reference voltage V output by the bandgap reference source circuit from being too high. REF A significant voltage overshoot occurred during the power-on startup process.

[0066] In practical applications, the NMOS transistor is a depletion-mode NMOS transistor, with a threshold voltage less than zero. As the power supply voltage gradually increases from 0 to VDD, the gate voltage V of the NMOS transistor... A Starting from 0, it gradually increases due to the threshold voltage V of the NMOS transistor. TH,NM1 The voltage is less than 0. Therefore, the gate voltage V of the NMOS transistor is... GS,NM1 Always greater than the threshold voltage V of the NMOS transistor TH,NM1 The NMOS transistor always remains in the on state, and there is no erroneous steady state.

[0067] During the power supply voltage application process, the node voltages V at nodes C, D, and E are... C V D V E It also gradually begins to rise, when the node voltage V D V EWhen the threshold voltages of the third transistor Q3 and the fourth transistor Q4 are reached, the current mirror composed of PMOS1 and PMOS2 begins to work normally, so that a negative feedback loop consisting of node E-node D-node F-node A-node B-node C-node E is formed in the circuit, thereby enabling the bandgap reference source circuit to maintain normal operation.

[0068] Furthermore, when the bandgap reference source circuit is working normally, since PMOS1 and PMOS2 are current mirrors in a 1:1 ratio, the current flowing through the third transistor Q3 and the fourth transistor Q4 is equal. Also, because the emitter area ratio of the third transistor Q3 and the fourth transistor Q4 is 1:1, the voltage V at node D is equal. D and the voltage V at node E E Similarly, the current flowing through the first resistor R1 and the second resistor R2 is also the same.

[0069] Right now,

[0070] Furthermore, since the first transistor Q1 is connected in series with the first resistor R1, and the second transistor Q2 is connected in series with the second resistor R2, the current flowing through the first transistor Q1 and the second transistor Q2 is also equal. At this time, the voltage V at node C is equal to the voltage across the second transistor R2. C Equal to the voltage V between the base and emitter of the first transistor Q1 BE,Q1 Therefore, the voltage drop across resistor R1 can be expressed by the following formula (4):

[0071]

[0072] Among them, V R1 This represents the voltage drop across resistor R1; V C V represents the voltage at node C. D V represents the voltage at node D; BE,Q1 This represents the voltage between the base and emitter of the first transistor Q1; V BE,Q2 The voltage between the base and emitter of the second transistor Q2 is represented by ; T represents the temperature; k and q are constants; N represents the ratio of the emitter area of ​​the second transistor Q2 to that of the first transistor Q1.

[0073] Furthermore, the current flowing through resistor R1 can be expressed by the following formula (5):

[0074]

[0075] Among them, I R1 This indicates the current flowing through resistor R1; R1 represents the resistance value of the first resistor R1.

[0076] Therefore, the current flowing through resistor R1 is a current with a positive temperature coefficient, which is related to the resistance values ​​of N and the first resistor R1.

[0077] The final output bandgap reference voltage of the bandgap reference source circuit can be expressed by the following formula (6):

[0078]

[0079] Furthermore, due to the voltage V between the base and emitter of transistor Q2... BE,Q2 It has a negative temperature coefficient; therefore, by adjusting the ratio of N, R1, and R3 in the above formula (6), the equation can be optimized. Partial positive temperature coefficient and V BE,Q2 The negative temperature coefficients are opposites of each other, so that the bandgap reference voltage V REF The temperature coefficient is approximately zero, which in turn makes the bandgap reference voltage V... REF It is almost unaffected by temperature changes.

[0080] In practical applications, applications such as Figure 2 The bandgap reference source circuit shown is similar to... Figure 1 The bandgap reference circuit shown has a temperature coefficient of the same order of magnitude (less than 10 ppm).

[0081] In summary, the bandgap reference circuit described herein connects the drain of an NMOS transistor to the power supply, thereby enabling the bandgap reference source circuit to start up via the NMOS transistor. This reduces the complexity of the circuit structure and maintains the conduction state during the power-on startup process of the bandgap reference source circuit, thus solving the problem of erroneous steady state in traditional bandgap reference source circuits. At the same time, by constructing a current mirror consisting of a first PMOS transistor, a second PMOS transistor, and a transistor network, the voltage of the node connected to the first and second resistors and the transistor network is clamped, saving additional bias circuitry and reducing the overall power consumption of the circuit.

[0082] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A bandgap reference source circuit, characterized by Comprise: NMOS tube, first PMOS tube, second PMOS tube, first resistance, second resistance and triode network, the first PMOS tube and the second PMOS tube constitute 1:1 current mirror, the resistance of the first resistance and the second resistance is equal; The drain of the NMOS tube is connected with the power supply, for keeping on in the process of starting up on the band gap reference power supply circuit; The source of the NMOS tube is connected with the output end of the band gap reference source circuit, and is connected with the triode network based on the first resistance and the second resistance; The two ends of the triode network are connected with the drain of the first PMOS tube and the second PMOS tube respectively, for making the current mirror constituted by the first PMOS tube and the second PMOS tube work normally; The triode network comprises: first triode, second triode, third triode and fourth triode; The ratio of the emitter area of the first triode and the second triode is 1:N; The ratio of the emitter area of the third triode and the fourth triode is 1:1; Wherein, the collector of the fourth triode is connected with the drain of the second PMOS tube, the emitter of the fourth triode is grounded, and the base of the fourth triode is connected with the collector of the second triode and the second resistance respectively; The emitter of the second triode is grounded, and the base of the second triode is connected with the collector of the first triode, one end of the first resistance and the base of the third triode; The emitter of the first triode is grounded, and the base of the first triode is connected with the other end of the first resistance; The emitter of the third triode is grounded, and the collector of the third triode is connected with the drain of the first PMOS tube.

2. The bandgap reference circuit of claim 1, wherein, The NMOS tube is depletion mode NMOS tube, and the threshold voltage of the NMOS tube is less than zero.

3. The bandgap reference circuit of claim 1, wherein, Further comprise: Capacitor; One end of the capacitor is connected with the gate of the NMOS tube and the drain of the second PMOS tube, and the other end is grounded.

4. The bandgap reference circuit of claim 1, wherein, Further comprise: Third resistance; One end of the third resistance is connected with the first resistance and the second resistance respectively, and the other end of the third resistance is connected with the source of the NMOS tube and the output end of the band gap reference source circuit respectively.

5. The bandgap reference circuit of claim 4, wherein, The band gap reference voltage output by the output end of the band gap reference source circuit is represented by the following formula: ； wherein, represents the bandgap reference voltage; T represents temperature; k, q are constants; N represents the ratio of the areas of the second transistor and the first transistor emitter; R1 represents the resistance value of the first resistor; R3 represents the resistance value of the third resistor; represents the voltage between the base and the emitter of the second transistor.

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