Test point insertion method and device based on circuit cost, equipment and storage medium

Abstract

The invention discloses a test point insertion method and device based on circuit cost, equipment and a storage medium, and relates to the technical field of EDA. Determining the insertion point type of the current round and the updated candidate test point set of the last round, and selecting candidate test points from the candidate test point set to insert the candidate test points into the circuit for cost simulation; respectively calculating cost difference values of circuit cost simulation before and after the candidate test points are inserted, and selecting target test points and corresponding target insertion sites of which the cost difference values meet a difference value threshold value; and inserting the target test point into the netlist data, and updating the candidate test point set according to the number of the remaining insertion points. According to the scheme, for different types of control points and observation points, corresponding cost functions are constructed according to respective circuit characteristics, the circuit characteristics are perfectly matched, the circuit fault coverage rate and the observable fault number are greatly improved, and the algorithm implementation speed is optimized. In the later DFT test stage, the test complexity and the number of test vectors are remarkably reduced, the scanning test efficiency is improved, and the influence of untestable faults is reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of EDA technology, and particularly to a test point insertion method, device, equipment and storage medium based on circuit cost. Background Art

[0002] In the design and manufacturing process of integrated circuits (ICs), testing is a crucial step. With the expansion of the scale and the increase in complexity of integrated circuits, traditional testing methods are gradually difficult to cover all possible faults. This results in some faults being difficult to detect, affecting the quality of the final product. To improve testing efficiency, designers have introduced TPI technology to enhance test coverage, especially to further improve the testing ability in methods such as built-in self-test (BIST) and scan testing. Test Point Insertion (TPI) is a design technology for adding control points and observation points in circuit design to improve the testing of digital circuits, especially in large-scale integrated circuits, to increase test coverage, reduce test complexity, optimize test efficiency, and reduce test time.

[0003] The basic principle of TPI is to make circuit nodes that were originally difficult to access or measure directly activatable or monitorable by the test system by adding control points and observation points. However, when the TPI algorithm inserts test points, although it enhances the testability of the circuit, it may also introduce new test pattern redundancies. To make full use of the inserted test points to increase coverage, the test generation process may generate a large number of similar or duplicate test patterns. Although these patterns contribute to increasing coverage to a certain extent, their actual contribution to fault detection may not be significant. As the complexity of integrated circuits continues to increase, the interaction relationships between various modules in the circuit become increasingly complex. When the TPI algorithm processes such complex circuits, in order to ensure test coverage and fault coverage, it often needs to consider more test scenarios and conditions. This makes the test generation process more complex, and the number of generated test patterns also increases accordingly. For example, in a complex chip containing multiple functional modules, inserting test points may affect the signal transmission and interaction between different modules. To ensure that these interaction processes can be fully tested, the test generation tool needs to generate a large number of test patterns to cover various possible situations. Even in some cases, although these patterns do not contribute much to the improvement of coverage, they are still retained to ensure comprehensiveness. Summary of the Invention

[0004] The embodiments of the present application provide a test point insertion method, device, equipment and storage medium based on circuit cost, which solves the problem that the relevant TPI algorithms have insufficient fault detection coverage.

[0005] On the one hand, the present application provides a test point insertion method based on circuit cost, and the method includes: Read netlist data, and determine a candidate test point set according to the circuit scale and the set number of insertion points; Determine the type of insertion point in this round and the candidate test point set updated in the previous round, select a candidate test point from the candidate test point set, and insert it into the circuit for cost simulation; Calculate the cost difference of the circuit cost simulation before and after inserting the candidate test point respectively, and select the target test point and the corresponding target insertion site whose cost difference meets the difference threshold; Insert the target test point into the netlist data, and update the candidate test point set according to the remaining number of insertion points.

[0006] Specifically, the step of selecting a candidate test point from the candidate test point set and inserting it into the circuit for cost simulation includes: Simulate the entire netlist data, calculate the controllability and observability COP value, Sandia controllability and observability SCOP value of each line, and the test count TC value simulation parameter, and set the line number statistical value corresponding to the simulation parameter; According to the relationship between the COP value, SCOP value, and TC value of each line and their respective set thresholds, determine the line number statistical value that meets various simulation parameters in the netlist data of this round; Determine the cost function of the insertion point type in this round based on the magnitude relationship of the line number statistical values of various simulation parameters; Perform cost simulation on the netlist data based on the cost function of the insertion point type in this round, and calculate the cost value of each line and the entire circuit.

[0007] Specifically, the step of determining the line number statistical value that meets various simulation parameters in the netlist data of this round includes: Poll all lines in the netlist data, and calculate the corresponding COP value, SCOP value, and TC value respectively; When the COP value of the selected line exceeds the COP threshold, increment the line number statistical value of the COP information by one; when the SCOP value exceeds the SCOP threshold, increment the line number statistical value of the SCOP information by one; when the TC value exceeds the TC threshold, increment the line number statistical value of the TC information by one.

[0008] Specifically, the step of determining the cost function of the insertion point type in this round based on the magnitude relationship of the line number statistical values of various simulation parameters includes: Determine the simulation parameter with the largest line number statistical value of each type as the core calculation cost, and the remaining simulation parameters as the auxiliary calculation cost; Design a cost function based on the insertion point type, core calculation cost, and auxiliary calculation cost in this round.

[0009] Specifically, the calculation formulas for various simulation parameters are as follows:

[0010]

[0011]

[0012] Among them, and represent the probabilities of 0 and 1 on line n, represents the probability that can be observed at the output on line n; and represent the controllable values of 0 and 1 on line n, represents the observable value on line n; and represent the total values of 0 and 1 on line n.

[0013] Specifically, calculate the cost difference of circuit cost simulation before and after inserting the candidate test points respectively, and select the target insertion site whose cost difference meets the cost threshold; including: Poll all candidate test points in the candidate test point set, insert the selected candidate test points into different positions in the circuit in turn, and calculate the simulation cost values at different insertion sites according to the cost function of this round; Calculate the simulation cost difference before and after different insertion points, and screen out the maximum simulation cost difference; Calculate the cost difference before and after insertion according to the following formula: Δ C = Cold − Cnew Among them, Cold represents the circuit cost simulation value before insertion, Cnew represents the maximum simulation cost value selected after insertion; When ΔC is greater than the cost difference threshold, the insertion site corresponding to the maximum simulation cost difference is determined as the target insertion site.

[0014] Specifically, inserting the target insertion site into the netlist data and updating the candidate test point set according to the remaining number of insertion points includes: Insert the target test point into the netlist data, move it from the candidate test point set to the result array, and update the number of inserted points; Execute the next round of steps of extracting candidate test points and cost simulation calculation to determine the target insertion site. When the number of inserted points reaches the set value, or the updated candidate test point set is empty, end the test.

[0015] On the other hand, the present application provides a test point insertion device based on circuit cost, and the device includes: A determination module, configured to read netlist data and determine a candidate test point set according to the circuit scale and the set number of insertion points; A cost simulation module, configured to determine the type of insertion points in this round and the candidate test point set updated in the previous round, select candidate test points from the candidate test point set, and insert them into the circuit for cost simulation; A selection module, configured to calculate the cost difference of the circuit cost simulation before and after inserting the candidate test points respectively, and select target test points and corresponding target insertion sites whose cost differences meet the difference threshold; An update module, configured to insert the target test points into the netlist data and update the candidate test point set according to the remaining number of insertion points.

[0016] On another aspect, the present application provides a computer device, which includes a processor and a memory. At least one instruction, at least one program, a code set or an instruction set is stored in the memory, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to implement the test point insertion method based on circuit cost described in the above aspect.

[0017] On another aspect, the present application provides a computer-readable storage medium, in which at least one instruction, at least one program, a code set or an instruction set is stored, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by a processor to implement the test point insertion method based on circuit cost described in the above aspect.

[0018] The beneficial effects brought by the technical solutions provided in the embodiments of the present application at least include: For different types of control points and observation points, the present application constructs corresponding cost functions according to their respective and circuit characteristics, which perfectly fits the characteristics of the circuit, greatly improves the circuit fault coverage rate and the number of observable faults, and optimizes the implementation speed of the algorithm. Especially in the later DFT test stage, it significantly reduces the test complexity and the number of test vectors, improves the efficiency of scan testing and reduces the impact of untestable faults. Description of the Drawings

[0019] Figure 1 is a flowchart of the test point insertion method based on circuit cost provided by the embodiment of the present application; Figure 2 shows a flowchart of circuit testability simulation provided by the embodiment of the present application; Figure 3 lists the algorithm flowchart of the test point insertion method based on circuit cost of the present application; Figure 4Exemplarily, a schematic diagram of cost simulation before and after different types and quantities of insertion points is given; Figure 5 It is a structural block diagram of a test point insertion device based on circuit cost provided by an embodiment of the present application; Figure 6 It shows a structural block diagram of a computer device provided by an exemplary embodiment of the present application. Detailed implementation manners

[0020] To make the objectives, technical solutions, and advantages of the present application clearer, the following will further describe the embodiments of the present application in detail with reference to the accompanying drawings.

[0021] As used herein, "a plurality of" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after.

[0022] Figure 1 It is a flowchart of a test point insertion method based on circuit cost provided by an embodiment of the present application, including the following steps: S1. Read the netlist data, and determine a candidate test point set according to the circuit scale and the set number of insertion points; In the test point insertion technology of Test Point Insertion (TPI), it plays an important role in reducing test complexity and optimizing testing in large-scale integrated circuits. For a circuit that needs to perform fault diagnosis testing, it is first necessary to read the netlist data of the circuit structure and convert it into TPI data for subsequent test simulation.

[0023] In some embodiments, data verification is required during the TPI data conversion process. As Figure 2 shown, after data conversion at the program start entry, it is necessary to check the TPI data through a dictionary or database, and correct the possibly incorrect TPI data. After the check is correct, the data is then forced to be unified and then simulated and analyzed.

[0024] Test simulation requires inserting a certain number of test points according to actual requirements, that is, the number of insertion points, and the number of insertion points is usually determined by the circuit function and scale. Similarly, the candidate test point set is also set based on the circuit scale and function. Different candidate test points play different functions after being inserted into the circuit to meet subsequent coverage testing. In some embodiments, the candidate test points can be determined and established according to different types of insertion points. In particular, in the present application, the set data is established based on the three types of CP1 control points, CP0 control points, and OP observation points. Correspondingly, the set number of insertion points represents the sum of these three types of points.

[0025] S2. Determine the type of the current insertion point and the set of candidate test points updated in the previous round, select a candidate test point from the set of candidate test points, and insert it into the circuit for cost simulation; The insertion simulation process is iteratively looped according to the number of insertion points. For a certain round of simulation steps in the process, first, it is necessary to determine the type of the current insertion point being executed, and then select a candidate test point from the set of candidate test points updated in the previous round. The data in this set may be updated in each round, especially in the case where a candidate test point was clearly selected for insertion in the previous round, and the set data needs to be updated.

[0026] After selecting the candidate test point, insert it into various positions in the circuit and perform simulation calculations based on the cost function. The core significance of introducing the cost function for circuit simulation is to quantitatively evaluate the effectiveness of test vectors, optimize the test process, and ultimately reduce the test cost and time. By simulating and calculating the cost function, it can be determined whether the current test vector effectively initializes the circuit. If the "test cost" (i.e., the number of unknown flip - flops) of the test vector is lower than the current cost, then retain this vector as a candidate. This directly avoids blind testing and improves the efficiency of the initialization phase.

[0027] S3. Calculate the cost differences of the circuit cost simulations before and after inserting the candidate test points respectively, and select the target test points and the corresponding target insertion sites whose cost differences meet the difference threshold; Considering the large circuit scale, the greedy algorithm can be used to poll all insertion points for simulation, and determine whether the insertion condition is met according to the difference in the simulation cost values before and after insertion. For the candidate test points that meet the cost difference threshold, they can be inserted into the corresponding target insertion sites.

[0028] In the overall circuit analysis and simulation of the Test Point Insertion technology, the cost value (cost) of each circuit represents the resource consumption required for the physical implementation of the circuit component. According to the definition in digital circuit design, cost usually refers to the number of logic gates, the number of transistors (such as each gate input consuming two transistors), the number of input terminals (literals), and the number of inverters (complements) required to construct the circuit, etc. These resources directly affect the complexity, area, and manufacturing cost of the circuit. For example, in the CMOS process, the number of input terminals of the logic gate directly determines the usage of transistors, which in turn affects the physical layout and production cost of the chip. Therefore, the smaller the cost value, the better the circuit is in terms of resource efficiency and cost control.

[0029] S4. Insert the target test points into the netlist data and update the set of candidate test points according to the remaining number of insertion points.

[0030] This step is a necessary condition for loop iteration. When there are a large number of set insertion points, the candidate test point set needs to be updated every time a target insertion site is executed and confirmed. For cases that do not meet the cost threshold, the subsequent iteration logic is also entered, and TP points are reselected according to the insertion point type of the next round until the polling program ends.

[0031] In the embodiments of the present application, candidate TP points are selected by polling according to the type, that is, the CP1 control point is selected first, then the CP0 control point is selected, and finally the OP observation point is inserted into the simulation in sequence. When the CP1 control point meets the standard, a CP0 control point is randomly selected, and so on. This is because in the design for testability (DFT) of digital circuits, CP0 (Control Point 0) and CP1 (Control Point 1) are two types of core control points, and their functions, trigger logics, and selection sequences directly affect test coverage and resource optimization, as specifically shown below: 1. Fault coverage priority: CP1 often covers critical paths or highly sensitive code patterns.

[0032] 2. Timing constraint strictness: The trigger conditions and propagation delays of CP1 have more stringent requirements.

[0033] 3. Cost function optimization: The comprehensive resource consumption (timing + area) weight of CP1 is higher.

[0034] 4. Physical cascade dependence: The output of CP1 directly affects the functions of subsequent circuits.

[0035] By dynamically adjusting the cost function, hierarchical verification strategy, and physically aware optimization process, it can be ensured that the insertion order of CP1 and CP0 meets the design objectives, while maximizing test coverage and resource efficiency.

[0036] The insertion algorithm provided by the present application has great advantages when applied to the DFT field, specifically reflected in the following aspects: 1. Significantly improve fault coverage By inserting control points and observation points, TPI solves the problem of nodes that are difficult to observe and control in the circuit, making these nodes easier to test. The main goal of DFT is to ensure that the circuit has high fault coverage, especially in large-scale integrated circuits. The application of TPI enables the test point design to more comprehensively cover all key fault points, thereby significantly improving the overall fault coverage and effectively guaranteeing the quality and reliability of the circuit.

[0037] 2. Reduce test complexity and the number of test vectors TPI simplifies the test generation process by making the states of certain nodes directly controllable, reducing the number of test vectors required for testing. In DFT, simplifying the generation of test vectors can effectively reduce test costs and complexity. Reducing the number of test vectors also directly shortens the test time, thereby reducing the time and storage costs of test execution and improving the efficiency of DFT testing.

[0038] 3. Reduce the impact of untestable and redundant faults TPI makes previously untestable or redundant faults testable, reducing the untestable faults in DFT testing. In DFT design, fewer untestable faults allow test resources to be concentrated on more critical fault points.

[0039] 4. Improve the efficiency of scan testing The control points and observation points inserted by TPI make specific nodes in the scan chain easier to test, simplifying the design of scan testing. In the scan testing design of DFT, TPI can greatly optimize the controllability and observability of the scan chain, making test generation simpler, reducing the scan chain length and test time, and improving the execution speed and efficiency of testing.

[0040] 5. Support built-in self-test function (BIST) By inserting appropriate test points in the circuit, TPI can support the built-in self-test (BIST) function to ensure self-detection within the chip. BIST is one of the important technologies in DFT for improving the self-testing ability of circuits. The application of TPI in BIST can effectively increase the testability of the circuit, enabling BIST to detect more faults and improving the accuracy and efficiency of its detection, which is particularly important for some applications with high reliability requirements.

[0041] 6. Improve the accessibility of test signals and simplify fault diagnosis The additional observation points of TPI enable more signals to be directly observed, improving the accessibility of test signals. DFT relies on monitoring specific signals for fault diagnosis. TPI improves the observability of signals, simplifies the fault diagnosis process, allows the test system to locate the fault position faster, and thus improves the efficiency of fault repair.

[0042] 7. Flexible application in high-density IC design TPI can flexibly select key nodes for inserting test points and optimize the test structure according to different design requirements. In DFT, the testability and performance of high-density designs are balanced. The flexible insertion method of TPI can enhance the test ability without affecting the core functions of the circuit, enabling the design to have high testability in different application scenarios.

[0043] Figure 3 The algorithm flowchart of the test point insertion method based on circuit cost in this application is listed. After the program starts, the number of TP selection points is set first, that is, the total number of inserted points of each type. Subsequently, the candidate test point set is set according to the required function type. Considering the fault coverage rate and diagnostic efficiency, the number of candidate test points can be determined based on the circuit scale.

[0044] This application provides a method for calculating the number of candidate test points. First, determine the circuit scan cell scale. For example, through simulation, we obtain that the number of gate levels is cell_n, and the number of TP selection points to be inserted is insert_n, and calculate the number of candidate test points candiate_n. The following calculation formula is used to determine the number of sampling points:

[0045] After determining then, it is allocated according to the proportion according to the type of points to be inserted in the circuit. In this application, it is determined according to the setting quantity ratio of the original CP1 control points, CP0 control points, and OP observation points.

[0046] Before formally calculating the cost information of each wire on the entire netlist, we also need to determine which cost function to use for calculation. On the premise of ensuring that the candidate test point set is not empty, select the corresponding type of TP points and insert them into the circuit for simulation testing. This process can specifically include the following steps: 1), Simulate the entire netlist data, calculate the controllability-observability COP value of each wire, the Sandia controllability-observability SCOP value, and the test count TC value simulation parameters, and set the line quantity statistical value of the corresponding simulation parameters; In this solution, controllability refers to the difficulty of controlling the logic value (0 or 1) of internal circuit nodes through input signals. For example, the fewer input assignment times required to set the value of a certain node to 1, the higher the controllability. Observability refers to the difficulty of observing the logic state of internal circuit nodes through output signals. If the information of a node can be efficiently propagated to the output end, its observability is high. The calculation formulas of these three simulation parameters in this application are as follows:

[0047]

[0048]

[0049] Among them, and represent the probabilities of 0 and 1 on wire n, represents the probability that the wire n can be observed at the output; and represent the controllable values of 0 and 1 on line n, represent the observable values on line n; and represent the total values of 0 and 1 on line n.

[0050] 2), According to the relationships between the COP value, SCOP value, and TC value of each line and their respective set thresholds, determine the statistical values of the number of lines that meet various simulation parameters in the current round of netlist data; For the above three types of parameter information, set corresponding thresholds respectively. Poll all wires in the netlist data, and calculate the corresponding COP value, SCOP value, and TC value respectively. For the corresponding value on each wire, compare it with the corresponding threshold. If it exceeds the threshold, the statistical value of the number of corresponding lines is incremented by 1. That is, when the COP value of the selected line exceeds the COP threshold, the statistical value of the number of lines with COP information is incremented by one; when the SCOP value exceeds the SCOP threshold, the statistical value of the number of lines with SCOP information is incremented by one; when the TC value exceeds the TC threshold, the statistical value of the number of lines with TC information is incremented by one.

[0051] For example, after polling all wires, the number of COP values exceeding the COP threshold COP_threshold is 100, the number of SCOP values exceeding the SCOP threshold SCOP_shreshold is 200, and the number of TC values exceeding the TC threshold TC_threshold is 1000.

[0052] 3), Determine the cost function of the current round of insertion point type based on the magnitude relationship of the statistical values of the number of lines for various simulation parameters; As mentioned above, different insertion point types will have different effects on the circuit. Therefore, specific analysis is required when evaluating the influence. Especially in terms of the cost function, different types require constructing different cost functions. Even for the same type but different functional candidate test points, the effects produced when inserted at the same position are also different. So more refined consideration is needed, and specifically it can be as follows: A. Determine the simulation parameter with the largest statistical value of the number of lines of each type as the core calculation cost, and the remaining simulation parameters as the auxiliary calculation cost; B. Design a cost function based on the current round of insertion point type, core calculation cost, and auxiliary calculation cost.

[0053] Taking the previous example, the number of COP_threshold is 100, the number of SCOP_shreshold is 200, and the number of TC_threshold is 1000. Then we choose to focus on the TC calculation cost function formula.

[0054] Specifically, when determining the cost function, it is necessary to ensure that the cost value of each wire is greater than 0. A cost value of 0 represents a non - physical abnormal state in test point insertion, which essentially stems from the disconnection between the algorithm model and physical implementation. It can lead to the failure of the optimization goal, the neglect of timing constraints, and the inability to activate the test point function, ultimately resulting in the failure of CP1 selection. The core of solving this problem lies in correcting the cost model, enhancing physical verification, and ensuring the compatibility of the tool chain. Through multi - dimensional cost calculation and a strict timing - driven process, such problems can be effectively avoided, improving the success rate of test point insertion and the testability of the circuit.

[0055] In a possible implementation, the cost function under different types can be constructed as follows: 1. Cost function of CP1 control points CP1 is mostly used for high - priority fault coverage (such as critical path timing repair or cascade control), and its cost function needs to integrate dynamic testability gain and timing sensitivity. The formula of the CP1 cost function is as follows:

[0056] is the fault detection probability gain, which is used to calculate the increase in the detection probability of target faults (such as stuck - at faults) after inserting CP1; slack is the reciprocal of the timing margin, representing the timing margin of the path where CP1 is located, and the smaller the margin (the larger the reciprocal), the higher the cost; is the dynamic test complexity, which represents the impact of CP1 on test pattern generation. For example, continuously increasing the number of test patterns or the length of the scan chain after the insertion point will change this value; and and are physical constraint parameters for balancing test coverage.

[0057] 2. Cost function of CP0 control points CP0 is usually used for basic control functions (such as system - level timing control or low - priority fault detection), and its cost function focuses on static resource consumption and controllability optimization. The formula of the CP0 cost function is as follows:

[0058] represents the type - 0 controllability index, which quantifies the difficulty of driving a node to logic 0; is the static timing constraint, is the overhead area; and and are adjustment parameters 3. Cost function of OP observation points OP is used to enhance the fault propagation ability, and its cost function focuses on improving observability and maintaining signal integrity. The formula of the OP cost function is as follows:

[0059] represents the difficulty of quantifying the propagation of node values to the main output; represents the number of newly added fault propagation paths after inserting OP. The more paths, the lower the cost; is the reciprocal of the noise margin, representing the crosstalk or signal attenuation introduced by OP; 、 and are weight coefficients.

[0060] 4) Perform cost simulation on the netlist data based on the cost function of the current round of insertion point type, and calculate the cost values of each line and the entire circuit.

[0061] For the candidate test points selected for insertion in the set, it is necessary to continuously test at different positions of the inserted circuit (link) to determine the best target insertion site. This process specifically includes the following: a. Insert the selected candidate test points into different positions in the circuit in turn, and calculate the simulation cost values at different insertion sites according to the cost function of this round; a. Calculate the difference in simulation costs before and after different insertion points, and screen out the maximum simulation cost difference; Suppose a candidate test point is selected and inserted into 100 sites respectively. Calculate the circuit cost values after 100 insertions respectively, and then sort them in descending order to select the maximum value. Then use the following formula to calculate the cost difference before and after insertion: ΔC = C old −C new where C old represents the circuit cost simulation value before insertion, and C new represents the maximum simulation cost value selected after insertion.

[0062] c. When ΔC is greater than the cost difference threshold, the insertion site corresponding to the maximum simulation cost difference is determined as the target insertion site, and the corresponding candidate test point is the target test point (target insertion point); on the contrary, when ΔC is less than the cost difference threshold, it means that this insertion point will not reduce the test cost, but jump out of the current loop and continue to select other candidate test points from the set. The cost difference threshold here is an empirical value set according to the actual circuit function.

[0063] Furthermore, after finding the target insertion site that meets the conditions, insert the target test point into the netlist data, and at the same time store the target test point and the target insertion site in the result array, print relevant information, and update the number of inserted points.

[0064] Execute the next step of extracting candidate test points and performing cost simulation calculation to determine the target insertion site. When the number of inserted points reaches the set TP selection points, or when the updated candidate test point set is empty, end the test.

[0065] Figure 4 Exemplarily, schematic diagrams of cost simulation before and after different types and numbers of insertion points are given. Taking the ATPG Log with CP0 = 5, CP1 = 5, and OP = 5 as an example. Among them, -ctrl0 sets the number of CP0 control points, -ctrl1 sets the number of CP1 control points, and -obs sets the number of OP observation points. Figure 4 The above figure is the pre-insertion simulation, and the following figure is the experimental test result of the post-insertion simulation. According to the simulation results, when additional control points or observation points are inserted, the fault coverage rate of the circuit has been greatly improved to varying degrees, and the number of observable fault points has also been increased to a certain extent.

[0066] In summary, for different types of control points and observation points in this application, corresponding cost functions are constructed according to their respective and circuit characteristics, which perfectly fits the characteristics of the circuit, greatly improving the circuit fault coverage rate and the number of observable faults. In addition, when selecting candidate test points, the corresponding cost difference threshold adaptively sets values for different scale circuits and circuit types, which can also optimize the speed of algorithm implementation to a certain extent.

[0067] Figure 5 The structural block diagram of the test point insertion device based on circuit cost provided by the embodiment of the present application is shown. The device includes: A determination module 510, configured to read netlist data and determine a candidate test point set according to the circuit scale and the set number of insertion points; A cost simulation module 520, configured to determine the type of insertion points in this round and the updated candidate test point set in the previous round, select candidate test points from the candidate test point set, and insert them into the circuit for cost simulation; A selection module 530, configured to calculate the cost difference of the circuit cost simulation before and after inserting the candidate test points respectively, and select the target test points and corresponding target insertion sites whose cost differences meet the difference threshold; An update module 540, configured to insert the target test points into the netlist data and update the candidate test point set according to the remaining number of insertion points.

[0068] The test point insertion device based on circuit cost provided by the embodiment of the present application can be applied to the test point insertion method based on circuit cost provided in the above embodiment. For related details, refer to the above method embodiment. Its implementation principle and technical effect are similar and will not be elaborated here.

[0069] It should be noted that the embedded large model acceleration system platform provided in the embodiments of the present application is only illustrated by the above division of each functional module / functional unit. In actual applications, the above functions can be allocated to different functional modules / functional units according to needs, that is, the internal structure of the embedded large model acceleration system platform is divided into different functional modules / functional units to complete all or part of the functions described above. In addition, the implementation manner of the method for the embedded large model acceleration system platform provided in the above method embodiments and the implementation manner of the embedded large model acceleration system platform provided in this embodiment belong to the same concept. For the specific implementation process of the embedded large model acceleration system platform provided in this embodiment, please refer to the above method embodiments and will not be elaborated here.

[0070] Figure 6 The block diagram of the structure of an embedded computer device provided by an exemplary embodiment of the present application is shown. It is a computer device such as a desktop computer, a laptop computer, a handheld computer, and a cloud server. The computer device may include, but is not limited to, a processor and a memory. Among them, the processor and the memory can be connected through a bus or other means. Among them, the processor can be a central processing unit (CPU). The processor can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, graphics processing units (GPUs), embedded neural network processors (NPUs) or other dedicated deep learning coprocessors, discrete gate or transistor logic devices, discrete hardware components, etc. chips, or combinations of the above types of chips.

[0071] The processor may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. The processor may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), or PLA (Programmable Logic Array). The processor may also include a main processor and a coprocessor. The main processor is a processor used to process data in the wake state, also known as the CPU (Central Processing Unit); the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor may be integrated with a GPU (Graphics Processing Unit), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor may further include an AI (Artificial Intelligence) processor, and the AI processor is used to process computational operations related to machine learning.

[0072] As a non-transitory computer-readable storage medium, the memory can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as the program instructions / modules corresponding to the methods in the above embodiments of the present application. The processor executes various functional applications and data processing of the processor by running the non-transitory software programs, instructions, and modules stored in the memory, that is, implements the methods in the above method embodiments. The memory may include a program storage area and a data storage area. Among them, the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created by the processor, etc. In addition, the memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some embodiments, the memory may optionally include a memory remotely set relative to the processor, and these remote memories may be connected to the processor through a network. Examples of the above networks include, but are not limited to, the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0073] In some embodiments, the computer device may also optionally include: a peripheral device interface and at least one peripheral device. The processor, the memory, and the peripheral device interface may be connected through a bus or signal lines. Each peripheral device may be connected to the peripheral device interface through a bus, signal lines, or a circuit board. Specifically, the peripheral devices include at least one of a radio frequency circuit, a display screen, and a keyboard.

[0074] The peripheral device interface can be used to connect at least one peripheral device related to I / O (Input / Output) to the processor and the memory. In some embodiments, the processor, the memory, and the peripheral device interface are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor, the memory, and the peripheral device interface can be implemented on separate chips or circuit boards, and this embodiment does not limit this.

[0075] The display screen is used to display the UI (User Interface). The UI can include graphics, text, icons, videos, and any combination thereof. When the display screen is a touch display screen, the display screen also has the ability to collect touch signals on or above the surface of the display screen. The touch signals can be input to the processor as control signals for processing. At this time, the display screen can also be used to provide virtual buttons and / or virtual keyboards, also known as soft buttons and / or soft keyboards. In some embodiments, there can be one display screen, which is set on the front panel of the computer device; in some other embodiments, there can be at least two display screens, which are respectively set on different surfaces of the computer device or in a foldable design; in some other embodiments, the display screen can be a flexible display screen, which is set on the curved surface or the folding surface of the computer device. Even, the display screen can be set to an irregular non-rectangular shape, that is, a special-shaped screen. The display screen can be prepared from materials such as LCD (Liquid Crystal Display) and OLED (Organic Light-Emitting Diode).

[0076] The power supply is used to supply power to each component in the computer device. The power supply can be alternating current, direct current, a disposable battery, or a rechargeable battery. When the power supply includes a rechargeable battery, the rechargeable battery can be a wired rechargeable battery or a wireless rechargeable battery. A wired rechargeable battery is a battery charged through a wired line, and a wireless rechargeable battery is a battery charged through a wireless coil. The rechargeable battery can also be used to support fast charging technology.

[0077] Those skilled in the art can understand that the structure shown in this embodiment does not constitute a limitation on the computer device, and it can include more or fewer components than shown in the figure, or combine certain components, or adopt different component arrangements.

[0078] Embodiments of this application also disclose a computer-readable storage medium. Specifically, the computer-readable storage medium is used to store a computer program, and when the computer program is executed by a processor, the methods in the above method embodiments are implemented. Those skilled in the art can understand that to implement all or part of the processes in the above method embodiments of this application, it can be completed by instructing relevant hardware through a computer program. The program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the above method embodiments. Among them, the storage medium can be a magnetic disk, an optical disc, a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk drive (HDD), or a solid-state drive (SSD), etc.; the storage medium can also include a combination of the above types of memories.

[0079] This specific embodiment is only an interpretation of the present invention and does not limit the present invention. After reading this specification, those skilled in the art can make modifications to this embodiment without creative contributions as needed, but as long as they are within the scope of the claims of the present invention, they are protected by the patent law.

Claims

1. A test point insertion method based on circuit cost, characterized in that: The method comprises: Read the netlist data and determine the candidate test point set according to the circuit scale and the number of set insertion points; Determine the insertion point type of this round and the candidate test point set updated in the previous round, select candidate test points from the candidate test point set, and insert them into the circuit for cost simulation; Calculate the cost difference of the circuit cost simulation before and after inserting the candidate test point, and select the target test point and the corresponding target insertion site whose cost difference meets the difference threshold; The target test point is inserted into the netlist data, and the candidate test point set is updated according to the number of remaining insertion points.

2. The circuit cost-based test point insertion method according to claim 1, characterized in that: The step of selecting a candidate test point from the candidate test point set and inserting the candidate test point into a circuit for cost simulation includes: Simulate the entire netlist data, calculate the controllable and observable COP value, Sandia controllable and observable SCOP value, and test count TC value simulation parameters of each line, and set the line quantity statistics value corresponding to the simulation parameters; According to the relationship between the COP value, SCOP value, TC value of each line and the respective set thresholds, the statistical value of the number of lines in the current round of netlist data that meet various simulation parameters is determined; Determine the cost function of the current round of insertion point type based on the magnitude relationship of the line quantity statistics of various simulation parameters; The cost function of the insertion point type in this round is used to perform cost simulation on the netlist data and calculate the cost value of each line and the entire circuit.

3. The circuit cost-based test point insertion method according to claim 2, characterized in that: The determining of the statistical value of the number of lines satisfying various simulation parameters in the current round of netlist data includes: Poll all the lines in the netlist data and calculate the corresponding COP value, SCOP value, and TC value respectively; When the COP value of the selected line exceeds the COP threshold, the line quantity statistics value of the COP information is increased by one; when the SCOP value exceeds the SCOP threshold, the line quantity statistics value of the SCOP information is increased by one; when the TC value exceeds the TC threshold, the line quantity statistics value of the TC information is increased by one.

4. The circuit cost-based test point insertion method according to claim 3, characterized in that: The cost function of determining the type of insertion point in this round based on the relationship between the statistical values ​​of the number of lines of various simulation parameters includes: The simulation parameter with the largest statistical value of the number of lines of each type is determined as the core calculation cost, and the remaining simulation parameters are determined as auxiliary calculation costs; A cost function is designed based on the insertion point type, core computation cost, and auxiliary computation cost of this round.

5. The circuit cost-based test point insertion method according to claim 3, characterized in that: The calculation formulas for various simulation parameters are as follows: Among them and represents the probability of 0 and 1 on line n, represents the probability of being observed at the output on line n; and represents the controllable values ​​of 0 and 1 on line n, represents the observable value on line n; and Represents the total number of 0s and 1s on line n.

6. The circuit cost-based test point insertion method according to claim 1, characterized in that: The method of respectively calculating the cost difference of the circuit cost simulation before and after inserting the candidate test point, and selecting the target insertion site where the cost difference meets the cost threshold, comprises: Polling all candidate test points in the candidate test point set, inserting the selected candidate test points into different positions in the circuit in sequence, and calculating simulation cost values ​​at different insertion positions according to the cost function of this round; Calculate the simulation cost difference before and after different insertion points, and select the maximum simulation cost difference; The cost difference before and after insertion is calculated as follows: D C = Cold − Cnew Among them Cold represents the circuit cost simulation value before insertion, Cnew represents the maximum simulation cost value after insertion and screening; When ΔC is greater than the cost difference threshold, the insertion site corresponding to the maximum simulation cost difference is determined as the target insertion site.

7. The circuit cost-based test point insertion method according to claim 1, characterized in that: The step of inserting the target insertion site into the netlist data and updating the candidate test point set according to the number of remaining insertion points includes: Insert the target test point into the netlist data, and move it from the candidate test point set into the result array, and update the number of inserted points; The next round of extracting candidate test points and determining the target insertion site by cost simulation calculation is executed. When the number of inserted points reaches the set value, or the updated candidate test point set is empty, the test ends.

8. A circuit cost-based test point insertion device, characterized in that: The device comprises: A determination module, used for reading the netlist data and determining a set of candidate test points according to the circuit scale and the number of set insertion points; A cost simulation module, used to determine the insertion point type of this round and the candidate test point set updated in the previous round, select candidate test points from the candidate test point set, and insert them into the circuit for cost simulation; A selection module is used to calculate the cost difference of the circuit cost simulation before and after inserting the candidate test point, and select the target test point and the corresponding target insertion site whose cost difference meets the difference threshold; An updating module is used to insert the target test point into the netlist data and update the candidate test point set according to the number of remaining insertion points.

9. A computer device, characterized in that: The computer device includes a processor and a memory, wherein the memory stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to implement the circuit cost-based test point insertion method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The readable storage medium stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by a processor to implement the circuit cost-based test point insertion method as described in any one of claims 1 to 7.

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