Quantum chip layout wiring method and device

Abstract

The invention discloses a quantum chip layout wiring method and device, and the method comprises the steps: creating a target region in response to a quantum chip layout creation instruction; in response to the connection line generation instruction, automatically generating connection lines between the target quantum elements in the target area; the connecting line generation instruction comprises port parameters of connecting lines between the target quantum elements; according to the air bridge generation instruction, an air bridge is automatically generated on the connecting line, and an initial quantum chip layout is obtained; the connecting line generation instruction and the air bridge generation instruction are combined instructions or two independent instructions. A user only needs to select a proper quantum element, the connecting lines can be automatically generated between the target quantum elements in the target area, and the air bridges are uniformly arranged on the connecting lines to obtain an initial quantum chip layout, so that the wiring accuracy is improved, the quantum chip layout design efficiency is improved, errors are avoided, a complex wiring environment is effectively coped with, and the user experience is improved. And the labor intensity and the time cost of designers are reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of quantum computing, particularly to the technical field of superconducting quantum chip design, and specifically to a method and device for wiring the layout of a quantum chip. Background Art

[0002] A quantum chip is a chip based on the principles of quantum mechanics. The research and development of quantum chips can break through the computational power limitations of traditional computers and solve some traditional computational problems. It has powerful parallel computing capabilities and high scalability, and can solve some complex problems, such as optimization problems, quantum chemistry, quantum machine learning, etc.

[0003] Currently, the research and development of quantum chips are still in the primary stage and face many challenges and problems, such as the stability of qubits, quantum error correction, quantum noise, etc. A superconducting quantum chip is a quantum chip made of superconducting materials, which has a relatively high qubit quality and a low error rate, and is one of the most mature and stable experimental platforms in the field of quantum computing currently.

[0004] However, superconducting quantum chips still face some challenges, such as the mutual coupling between qubits, the long-term coherence of qubits, quantum error correction, etc. With the continuous progress of technology and the in-depth research, superconducting quantum chips need to integrate an increasing number of qubits, and the arrangement of various components on the chip is becoming more and more complex. Therefore, the workload and difficulty of the layout design of superconducting quantum chips are also increasing. Summary of the Invention

[0005] In view of the above problems, the present invention is proposed to provide a method and device for wiring the layout of a quantum chip that can overcome or at least partially solve the above problems.

[0006] An embodiment of the present invention provides a method for wiring the layout of a quantum chip, including:

[0007] Responding to a quantum chip layout creation instruction, creating a target area;

[0008] Responding to a connection line generation instruction, automatically generating connection lines between target quantum components in the target area; the connection line generation instruction includes port parameters of the connection lines between the target quantum components;

[0009] According to an air bridge generation instruction, automatically generating air bridges on the connection lines to obtain an initial quantum chip layout; the connection line generation instruction and the air bridge generation instruction are combined instructions or two separate instructions.

[0010] In one or some alternative embodiments, generating an air bridge automatically on the connection line according to the air bridge generation instruction to obtain an initial quantum chip layout includes:

[0011] After generating the connection line, according to the air bridge generation instruction, determine the coordinate positions of the air bridges on the connection line at a preset air bridge spacing, and automatically generate air bridges perpendicular to the connection line at the corresponding coordinate positions; the air bridge generation instruction includes air bridge spacing information and port parameters of the target quantum elements connected by the connection line.

[0012] In one or some alternative embodiments, the above quantum chip layout wiring method further includes:

[0013] In response to an edit instruction for the connection line of the initial quantum chip layout, hide the air bridge layer;

[0014] In response to an edit fan-out point instruction for the connection line, determine the target position of the fan-out point to obtain an updated connection line; wherein, the updated connection line has an arc transition at the target position of the fan-out point.

[0015] In one or some alternative embodiments, the above quantum chip layout wiring method further includes: the determining the target position of the fan-out point in response to an edit fan-out point instruction for the connection line to obtain an updated connection line includes:

[0016] In response to a create fan-out point instruction for the connection line, create a fan-out point;

[0017] In response to a coordinate adjustment instruction for the fan-out point, determine the target position of the fan-out point to obtain an updated connection line.

[0018] In one or some alternative embodiments, the creating a fan-out point in response to a create fan-out point instruction for the connection line includes:

[0019] In response to a create fan-out point instruction for the connection line of the initial quantum chip layout, display a fan-out line on the connection line and create a fan-out point on the fan-out line.

[0020] In one or some alternative embodiments, the connection line includes two spaced-apart connecting lines; the creating a fan-out point in response to a create fan-out point instruction for the connection line of the initial quantum chip layout includes:

[0021] In response to a create fan-out point instruction for the connection line of the initial quantum chip layout, display the fan-out line between the two connecting lines and create a fan-out point on the fan-out line.

[0022] In one or some optional embodiments, in response to the coordinate adjustment instruction for the fan-out point, determining the target position of the fan-out point and obtaining the updated connection line includes:

[0023] In response to a release operation on the dragged fan-out point, determining a release position of the fan-out point as a target position, and obtaining the updated connection line;

[0024] or,

[0025] In response to the coordinate configuration instruction for the fan-out point, a target position of the fan-out point is determined to obtain the updated connection line.

[0026] In one or some optional embodiments, in response to the release operation of the dragged fan-out point, determining the release position of the fan-out point as the target position to obtain the updated connection line specifically includes:

[0027] When a first click operation on the fan-out point is detected, determining the current position of the fan-out point as a starting point;

[0028] When the user drags the fan-out point from the starting point, continuously detecting in real time whether the click on the fan-out point is released;

[0029] When it is detected that the click is released, in response to the release operation of the dragged fan-out point, the release position of the fan-out point is determined as the target position to obtain the updated connection line.

[0030] In one or some optional embodiments, the first click operation is a single click or double click of the left button of a mouse; when the first click operation on the fan-out point is detected, determining the current position of the fan-out point as the starting point specifically includes:

[0031] The operation of the mouse on the fan-out point is detected in real time. When it is detected that the operation on the fan-out point is a left-click or a double-click of the mouse, the current position of the fan-out point is determined as the starting point, and the user's operation of dragging the fan-out point is responded to, and the shape of the fan-out line is linked to the position of the fan-out point.

[0032] In one or some optional embodiments, the step of determining the target position of the fan-out point in response to the coordinate configuration instruction of the fan-out point and obtaining the updated connection line specifically includes:

[0033] When a second click operation on the fan-out point is detected, a coordinate adjustment input box is displayed;

[0034] After the user inputs the coordinate value in the coordinate adjustment input box, in response to the coordinate configuration instruction for the fan-out point, the target position of the fan-out point is determined to obtain the updated connection line.

[0035] In one or some alternative embodiments, after determining the target position of the fan-out point, the updated connection line is obtained by the following method:

[0036] Determine the straight-line segment where the fan-out point is located on the fan-out line, and determine the two end points of the straight-line segment;

[0037] According to the target position of the fan-out point and the two end points, perform an arc transition at the corner of the fan-out line to obtain a reference line;

[0038] Link the connection line in the same way as the reference line to obtain the updated connection line.

[0039] In one or some alternative embodiments, the performing an arc transition at the corner of the fan-out line according to the target position of the fan-out point and the two end points to obtain the reference line includes:

[0040] Determine the corners on the fan-out line with the target position of the fan-out point and the two end points as vertices respectively;

[0041] Determine the center and two tangent points of the circle tangent to both sides of each corner on the angular bisector of each corner according to a preset radius;

[0042] For each corner, construct an arc with the center, the two tangent points and the preset radius;

[0043] Use the corresponding arcs to replace the broken lines between the vertex of each corner and the two tangent points to obtain the reference line.

[0044] In one or some alternative embodiments, the above-mentioned quantum chip layout wiring method further includes:

[0045] In response to an editing instruction to exit the connection line, display the air bridge layer and regenerate the air bridge on the updated connection line.

[0046] In one or some alternative embodiments, the above-mentioned quantum chip layout wiring method further includes:

[0047] During the drawing process of the connection line, detect whether the connection line collides with a specified element;

[0048] If so, determine the start point and the end point spanning the specified element;

[0049] Perform a cross-line operation according to the start point and the end point to generate a cross-line structure spanning the specified element.

[0050] In one or some alternative embodiments, the quantum chip layout creation instruction is a quantum chip layout custom creation instruction; the creation of the target area in response to the quantum chip layout creation instruction includes:

[0051] In response to the quantum chip layout creation instruction, create and display a quantum chip layout editing interface;

[0052] Correspondingly, the automatic generation of connection lines between target quantum elements in the target area in response to the connection line generation instruction includes:

[0053] According to the port parameter correspondence between the quantum elements added by the user in the quantum chip layout editing interface and the target quantum elements, in response to the connection line generation instruction, automatically generate the connection lines between the target quantum elements in the quantum chip layout editing interface.

[0054] In one or some alternative embodiments, the quantum chip layout creation instruction is a quantum chip layout quick creation instruction; the creation of the target area in response to the quantum chip layout creation instruction includes:

[0055] In response to the quantum chip layout creation instruction, create and display a quantum chip layout creation interface;

[0056] Correspondingly, the automatic generation of connection lines between target quantum elements in the target area in response to the connection line generation instruction includes:

[0057] According to the input parameters of the user in the quantum chip layout creation interface, in response to the connection line generation instruction, display a quantum chip layout editing interface, and automatically generate the connection lines between the target quantum elements in the quantum chip layout editing interface.

[0058] In one or some alternative embodiments, the above-mentioned quantum chip layout wiring method further includes:

[0059] In response to any instruction for dragging, removing, adding, or parameter configuring an air bridge, perform corresponding dragging, removing, adding, or parameter configuring operations on the air bridge.

[0060] In one or some alternative embodiments, during the process of automatically generating the connection lines between the target quantum elements in the target area, the method further includes:

[0061] If the connection line is not a straight line, perform arc transitions at each corner of the connection line.

[0062] In one or some alternative embodiments, the connection line includes two spaced-apart connecting lines; the arc transitions at each corner of the connection line are performed in the following manner:

[0063] Determine the center lines of the two connecting lines according to the two end points of each of the two connecting lines of the connecting line;

[0064] Determine the positions of the turning angles of the center line;

[0065] Determine the center of the circle tangent to the two sides of the turning angle and the two tangent points on the angular bisector of each turning angle according to a preset radius;

[0066] For each turning angle, construct an arc with the center of the circle, the two tangent points and the preset radius;

[0067] On the center line, replace the broken line between the vertex of each turning angle and the two tangent points with the corresponding arc respectively to obtain a reference center line;

[0068] Perform the same linkage on the two connecting lines along with the reference center line to obtain the updated connecting line.

[0069] In one or some alternative embodiments, the above quantum chip layout wiring method further includes:

[0070] After responding to the quantum chip layout creation instruction to create a target area, in response to the import request of the quantum chip layout, generate a pre-stored initial quantum chip layout in the target area; wherein, the target area is a quantum chip layout editing interface.

[0071] An embodiment of the present invention provides a quantum chip layout wiring device, including:

[0072] A target area creation module, configured to create a target area in response to a quantum chip layout creation instruction;

[0073] A connecting line generation module, configured to automatically generate a connecting line between target quantum elements in the target area in response to a connecting line generation instruction; the connecting line generation instruction includes port parameters of the connecting line between the target quantum elements;

[0074] An air bridge generation module, configured to automatically generate an air bridge on the connecting line according to an air bridge generation instruction to obtain an initial quantum chip layout; the connecting line generation instruction and the air bridge generation instruction are combined instructions or two separate instructions.

[0075] An embodiment of the present invention provides a computer-readable storage medium, on which computer instructions are stored, and when the instructions are executed by a processor, the above quantum chip layout wiring method is implemented.

[0076] An embodiment of the present invention provides a computer device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, the above-mentioned quantum chip layout wiring method is implemented.

[0077] An embodiment of the present invention provides a computer program product containing instructions. When the computer program product runs on a computer device, the computer device is enabled to execute the above-mentioned quantum chip layout wiring method.

[0078] An embodiment of the present invention provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor, and the processor is used to run a computer program or instruction to implement the above-mentioned quantum chip layout wiring method.

[0079] The beneficial effects of the above technical solutions provided by the embodiments of the present invention at least include:

[0080] For the quantum chip layout wiring method provided by the embodiments of the present invention, users only need to select appropriate quantum components, and then connection lines can be automatically generated between the target quantum components in the target area to achieve fast and automatic wiring. An air bridge is automatically generated on the connection line to achieve uniform deployment of the air bridge, and an initial quantum chip layout is obtained. It can effectively avoid the cumbersome and time-consuming process of manual wiring, improve the accuracy of wiring, enhance the design efficiency of the quantum chip layout, avoid errors, effectively cope with complex wiring environments, and greatly reduce the labor intensity and time cost of designers.

[0081] Other features and advantages of the present invention will be described in the subsequent description. And, partly, they will become obvious from the description or be understood by implementing the present invention. The objectives and other advantages of the present invention can be achieved and obtained by the structures specifically pointed out in the written description, claims, and drawings.

[0082] The following will further describe the technical solutions of the present invention in detail through the drawings and embodiments. Description of the Drawings

[0083] The drawings are used to provide a further understanding of the present invention, and constitute a part of the description. They are used to explain the present invention together with the embodiments of the present invention, and do not constitute a limitation to the present invention. In the drawings:

[0084] Figure 1 It is a schematic flowchart of the quantum chip layout wiring method in the embodiment of the present invention;

[0085] Figure 2 It is a schematic diagram of the graphical user interface shown in the embodiment of the present invention Figure 1 ;

[0086] Figures 3a - 3eSchematic diagrams of 5 types of bit elements in the embodiments of the present invention;

[0087] Figure 4 Schematic diagram of the Manhattan layout structure in the embodiments of the present invention;

[0088] Figures 5a - 5c Schematic diagrams of 3 types of resonators in the embodiments of the present invention;

[0089] Figure 6 Schematic diagram of the air bridge in the embodiments of the present invention;

[0090] Figure 7 Schematic diagram of the pin in the embodiments of the present invention;

[0091] Figure 8 Schematic diagram of the coupler in the embodiments of the present invention;

[0092] Figure 9 Schematic diagram of the marking pattern in the embodiments of the present invention;

[0093] Figure 10 Schematic diagram of the graphical user interface in the embodiments of the present invention Figure 2 ;

[0094] Figure 11 Schematic diagram of the graphical user interface III in the embodiments of the present invention;

[0095] Figure 12 Schematic diagram of the graphical user interface in the embodiments of the present invention Figure 4 ;

[0096] Figure 13 Schematic diagram of the graphical user interface V in the embodiments of the present invention;

[0097] Figure 14 Schematic diagram of the implementation method of arc transition at the corner when generating connection lines in the embodiments of the present invention;

[0098] Figure 15 Schematic diagram of the graphical user interface in the embodiments of the present invention Figure 6 ;

[0099] Figure 16 Schematic diagram of the process of another quantum chip layout routing method in the embodiments of the present invention;

[0100] Figure 17 Schematic diagram of the implementation method of arc transition at the corner when editing connection lines in the embodiments of the present invention;

[0101] Figure 18 Schematic diagram of the graphical user interface in the embodiments of the present invention Figure 7 ;

[0102] Figure 19Schematic diagram of the graphical user interface in the embodiments of the present invention Figure 8 ;

[0103] Figure 20 Schematic diagram of the graphical user interface in the embodiments of the present invention Figure 9 ;

[0104] Figure 21 Schematic diagram of the graphical user interface in the embodiments of the present invention Figure 10 ;

[0105] Figure 22 Schematic diagram of the graphical user interface in the embodiments of the present invention Figure 10 One;

[0106] Figure 23 Schematic diagram of the graphical user interface in the embodiments of the present invention Figure 10 Two;

[0107] Figure 24 Schematic diagram of the graphical user interface in the embodiments of the present invention Figure 10 Three;

[0108] Figure 25 Schematic diagram of the graphical user interface in the embodiments of the present invention Figure 10 Four;

[0109] Figure 26 Schematic diagram of the graphical user interface in the embodiments of the present invention Figure 10 Five;

[0110] Figure 27 Is Figure 26 An enlarged view of the quantum chip layout in;

[0111] Figure 28 Is Figure 27 A partial structural schematic diagram of;

[0112] Figure 29 Schematic diagram of the graphical user interface in the embodiments of the present invention Figure 10 Six;

[0113] Figure 30 Schematic diagram of the graphical user interface in the embodiments of the present invention Figure 10 Seven;

[0114] Figure 31 Schematic diagram of the structure of the quantum chip layout wiring device in the embodiments of the present invention. Detailed implementation manners

[0115] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be fully conveyed to those skilled in the art.

[0116] In the prior art, the wiring of most quantum chip layout design software relies on classical chip design software. During wiring, the characteristics of quantum chips are lost. For example, in classical computing, noise can be achieved through CMOS (Complementary Metal Oxide Semiconductor) multi-metal layers for device connection. However, in quantum chips, due to high noise requirements, multi-metal layers cannot correctly transmit signals. Using classical chip design software is usually cumbersome, requiring manual operation to draw tens of thousands of air bridges. The wiring operation and management logic are complex, increasing the development and design costs of quantum chips. With the development of superconducting quantum chips, there are more and more quantum bits and other components on the quantum chip layout, and the arrangement of components is becoming more and more complex. There are a large number of cumbersome and repetitive tasks during layout design. How to quickly and high-quality draw the superconducting quantum chip layout has become an urgent problem to be solved. Based on this, the inventor has further developed and designed a new quantum electronic design automation (QEDA) software for quantum chip layout design. Based on the professionalism of the QEDA software, to facilitate those skilled in the art to implement the wiring of the quantum chip layout, an embodiment of the present invention proposes a quantum chip layout wiring method. The user only needs to select appropriate quantum components, and then connection lines can be automatically generated between the target quantum components in the target area to achieve rapid automatic wiring, and air bridges can be automatically generated on the connection lines to achieve uniform deployment of air bridges, obtaining an initial quantum chip layout. It can effectively avoid the cumbersome and time-consuming process of manual wiring, improve the accuracy of wiring, enhance the efficiency of quantum chip layout design, avoid errors, and can effectively cope with complex wiring environments, greatly reducing the labor intensity and time cost of designers.

[0117] To better illustrate the embodiments of the present invention, numerous specific details of some basic concepts of the quantum chip layout will be given below first.

[0118] The quantum chip layout can include various different components, including quantum bits, coupling electrodes, resonators, Josephson junctions, couplers, pins (Pads), etc.

[0119] Qubits (e.g., in a cross shape) are arranged in a two-dimensional array, and adjacent qubits are connected by couplers (e.g., in a rectangular shape). Each qubit is also connected to a corresponding resonator (e.g., in a triangular and serpentine line shape). The resonator is connected to a read port and the quantum signal is read through the read port and connected to a readout line. Both the qubit and the coupler are provided with Josephson junctions. Among them, a qubit is usually composed of a qubit capacitor and a Josephson junction. There are various configurations of qubits, including: cross configuration, symmetric fermion configuration, cross-like configuration, coplanar parallel plate configuration, etc.

[0120] Among them, qubits can form various forms of quantum components alone or in combination with other components. Quantum components can be connected through connection lines, and multiple air bridges are deployed at intervals on the connection lines. The connection lines can include readout lines and control lines. Qubits need to be connected to control lines to achieve external control. Some qubits also need to perform signal reading, so they also need to be connected to readout lines. The outside world applies specific magnetic flux or microwave signals to the qubits through the readout lines and control lines in order to achieve control and reading of the quantum state, thereby interacting information.

[0121] When designing the layout of a quantum chip, multiple layers can be divided, such as the qubit layer, the wiring layer, and the air bridge layer. The wiring of the wiring layer can electrically connect the quantum components (qubits, readout cavities, couplers) on the qubit layer and the connection components (control line ports, readout cavity ports, pins) on the wiring layer.

[0122] Next, a method and device for constructing a layout of a quantum chip provided by an embodiment of the present invention will be described with reference to the accompanying drawings.

[0123] An embodiment of the present invention provides a method for wiring a layout of a quantum chip, referring to Figure 1 as shown, including the following steps:

[0124] S101: In response to a quantum chip layout creation instruction, create a target area;

[0125] S102: In response to a connection line generation instruction, automatically generate connection lines between target quantum components in the target area; the connection line generation instruction includes port parameters of the connection lines between the target quantum components;

[0126] S103: According to an air bridge generation instruction, automatically generate air bridges on the connection lines to obtain an initial quantum chip layout; the connection line generation instruction and the air bridge generation instruction are merged instructions or two separate instructions.

[0127] In the embodiments of the present invention, the QEDA software for implementing the quantum chip layout wiring method can be set in a computer device. The interaction interface of the QEDA software is displayed on the display screen of the computer device. The user interacts with the computer device by means of a mouse, keyboard, touch, etc., executes the quantum chip layout wiring method provided by the embodiments of the present invention, and realizes the quantum chip layout wiring.

[0128] In the embodiments of the present invention, in order to more clearly describe the wiring process of the quantum chip layout design, in the QEDA software, the quantum elements include qubit elements, quantum qubit layout structures, resonators, couplers, and pins. Among them, the qubit element is composed of at least two of a qubit capacitor, a Josephson junction, a cavity capacitor, and a resonator.

[0129] In the embodiments of the present invention, in order to mark the size information of the quantum chip, the quantum element may further include a marker for marking the range of the quantum chip layout.

[0130] In a specific example, referring to Figure 2 the graphical user interface of the QEDA software shown, the component selection library of the graphical user interface includes 5 types of qubit elements. Referring to Figures 3a to 3e shown, they are Xmon, Xmon_sd, Xmon_2d, Transmon, and Tmon_1) Referring to Figure 4 shown is the Manhattan junction structure in the quantum qubit layout structure. When designing the quantum chip layout, one or more of these qubit elements and / or this Manhattan layout structure can be used to construct the quantum chip. And for any type of qubit element, input parameters can be set and adjusted, including qubit parameters, squid region parameters, control line parameters, and positioning parameters. For qubit elements that need to connect read lines, readout parameters can also be adjusted. This Manhattan layout structure can also set and adjust input parameters, including handover parameters, pin parameters, and positioning parameters. Referring to Figures 5a to 5c shown, the component selection library of the graphical user interface includes 3 types of resonators (Resonator). Among them, for each type of resonator, input parameters can be set and adjusted, including resonator parameters, coupling part parameters, readout line parameters, and positioning parameters. Referring to Figure 6 shown, the component selection library of the graphical user interface includes 1 type of airbridge. Among them, the airbridge can set and adjust input parameters, including airbridge parameters and positioning parameters. Referring to Figure 7 shown, the component selection library of the graphical user interface includes 1 type of pad. Among them, the pad can set and adjust input parameters, including pin parameters and positioning parameters. Referring to Figure 8As shown, the component selection library of the graphical user interface includes 1 type of coupler, where the coupler can set and adjust input parameters, including coupling part parameters and positioning parameters. Refer to Figure 9 As shown, the component selection library of the graphical user interface includes 1 type of marker, where the coupler can set and adjust positioning parameters.

[0131] In an embodiment of the present invention, during the process of generating the quantum chip layout by the QEDA software, in order to avoid crosstalk, it can be achieved that the connection lines do not cross each other.

[0132] In an embodiment of the present invention, the user instruction for generating the quantum chip layout in the above step S101 can be a quantum chip layout custom creation instruction. The above step S101 responds to the quantum chip layout creation instruction and creates a target area, that is, in response to the quantum chip layout creation instruction, creates and displays a quantum chip layout editing interface; correspondingly, in the above step S102, in response to the connection line generation instruction, automatically generates connection lines between the target quantum components in the target area, that is, according to the port parameter correspondence between the quantum components added by the user in the quantum chip layout editing interface and the target quantum components input, in response to the connection line generation instruction, automatically generates the connection lines between the target quantum components in the quantum chip layout editing interface.

[0133] In a specific embodiment, in the above step S103, according to the air bridge generation instruction, air bridges are automatically generated on the connection lines to obtain an initial quantum chip layout. Specifically, after generating the connection lines, according to the air bridge generation instruction, at a preset air bridge spacing, determine the coordinate positions of the air bridges on the connection lines, and automatically generate air bridges perpendicular to the connection lines at the corresponding coordinate positions.

[0134] In an embodiment of the present invention, the air bridge generation instruction includes preset air bridge spacing information and the port parameters of the target quantum components connected by the connection lines. For any two target quantum components to be connected, according to the port parameters of the two target quantum components in the air bridge generation instruction, the coordinates of the ports of the two target quantum components can be obtained, and since the air bridge generation instruction contains air bridge spacing information, the coordinate positions of each air bridge on the connection line between the two target quantum components can be determined according to the coordinates of the ports of the two target quantum components and the air bridge spacing information, and air bridges are automatically generated perpendicular to the connection line at the corresponding coordinate positions. In this way, after the wiring is completed, air bridges can be evenly deployed on the connection lines, that is, according to the path length of the connection lines, uniform coordinate sampling is performed at a preset spacing to generate multiple air bridges with the same direction.

[0135] Exemplarily, refer toFigure 10 As shown, after the user operates to open the QEDA software, "Custom Creation" can be selected, and then referring to Figure 11 as shown, the graphical user interface is created and displayed as a quantum chip layout editing interface, referring to Figure 12 as shown, the user selects the qubit element Xmon and the pin from the component selection library, and enters the port parameters f1 of the qubit element to be connected and the port parameter Pad1 of the pin in the "PIN Matrix" column in the lower right corner of the quantum chip layout editing interface to establish the corresponding relationship between the ports, referring to Figure 13 as shown, by clicking "Generate Wiring" to issue a control instruction, the connection line between the qubit element Xmon and the pin is automatically generated in the quantum chip layout editing interface, and an air bridge is automatically generated on the connection line to obtain the initial quantum chip layout. In this embodiment, the control instruction includes a combined instruction of a connection line generation instruction and an air bridge generation instruction. Of course, in some other examples, the control instruction can be a separate connection line generation instruction and a separate air bridge generation instruction. When the user issues a connection line generation instruction, the connection line between the qubit element Xmon and the pin is automatically generated in the quantum chip layout editing interface. Then, the user can issue an air bridge generation instruction, and an air bridge is automatically generated on the connection line according to the air bridge generation instruction to obtain the initial quantum chip layout.

[0136] In a specific embodiment, during the process of automatically generating the connection line between the target quantum elements in the target area, the method further includes:

[0137] If the connection line is not a straight line, an arc transition is performed at each corner of the connection line.

[0138] Specifically, it can be that the connection line includes two spaced-apart connecting lines; the arc transition is performed at each corner of the connection line in the following manner:

[0139] According to the two endpoints of each of the two connecting lines of the connection line, determine the center line of the two connecting lines;

[0140] Determine the positions of the corners of the center line;

[0141] According to a preset radius, determine the center of the circle tangent to both sides of the corner and two tangent points on the angular bisector of each corner;

[0142] For each corner, construct an arc with the center of the circle, the two tangent points, and the preset radius;

[0143] On the center line, use the corresponding arcs to replace the broken lines between the vertex of each corner and the two tangent points respectively to obtain a reference center line;

[0144] The two connecting lines are similarly linked with the reference center line to obtain the updated connecting line.

[0145] For example, refer to Figure 14 As shown, take the example of making an arc transition for a corner of the center line. According to the preset radius r, the center O and the two tangent points p1 and p2 of the circle tangent to the two sides of the corner are determined on the angle bisector of the corner. Then, the arc is constructed with the center O, the two tangent points p1 and p2 and the radius r, as shown by the dotted line in the figure, and the arc is used to replace the vertex D of the corner and the broken line between the two tangent points p1 and p2 to obtain the reference center line.

[0146] In a specific embodiment, after obtaining the pre-generated quantum chip layout, any air bridge can be adjusted individually. Specifically, in response to the drag, remove, add or parameter configuration instruction of any air bridge, the air bridge is dragged, removed, added or parameter configuration operations are performed on the air bridge. For example, when the user executes the selection command and clicks the "Move" icon, after selecting any air bridge, the air bridge can be dragged or removed, the air bridge spacing can be adjusted, and the air bridge parameters and positioning parameters of the air bridge can be configured in the graphical user interface to adjust the size and position. Figure 15 As shown, for Figure 13 The quantum chip layout shown is the quantum chip layout after removing the air bridge "Airbridge32".

[0147] The inventors also found that the existing quantum chip layout design software usually cannot easily adjust the connection lines after completing the wiring. To this end, the inventors made further improvements. After obtaining the initial quantum chip layout, refer to Figure 16 As shown, the method may also include:

[0148] S104: In response to an editing instruction for the connection lines of the initial quantum chip layout, hiding the air bridge layer;

[0149] S105: In response to the instruction to edit the fan-out point of the connection line, determine the target position of the fan-out point to obtain an updated connection line; wherein the updated connection line has an arc transition at the target position of the fan-out point.

[0150] In an embodiment of the present invention, when it is necessary to adjust the shape and passing position of the connection line, the user can issue an editing instruction for the connection line of the initial quantum chip layout, hide the air bridge layer, and implement visual connection line editing. The user can determine the target position of the fan-out point through the fan-out point editing instruction, update the connection line in real time, adjust the passing position of the wiring and the shape of the connection line, and adjust the line direction of the connection line. By making the updated connection line have an arc transition at the target position of the fan-out point, the signal transmission of the connection line can be made more accurate and stable.

[0151] In a specific embodiment, the step S105 of determining the target position of the fan-out point in response to the editing fan-out point instruction for the connection line to obtain the updated connection line specifically includes:

[0152] Responding to the creation fan-out point instruction for the connection line, creating a fan-out point;

[0153] Responding to the coordinate adjustment instruction for the fan-out point, determining the target position of the fan-out point to obtain the updated connection line.

[0154] In an embodiment of the present invention, when it is necessary to adjust the shape and passing position of the connection line, the user can click at any position on the connection line, for example, it can be set to a single click or a double click, to issue the creation fan-out point instruction. In response to the creation fan-out point instruction, a fan-out point is created. At this time, if the user issues a coordinate adjustment instruction for the fan-out point, then in response to the coordinate adjustment instruction for the fan-out point, the fan-out point is moved, the target position of the fan-out point is determined, and the shape of the connection line is updated in real time, the passing position of the wiring and the shape of the connection line are adjusted, and the line direction of the connection line is adjusted to obtain the updated connection line. Moreover, during the process of updating the connection line, an arc transition is made at the target position of the fan-out point.

[0155] In a specific embodiment, since generally the connection line includes two spaced-apart connecting wires, in order to facilitate the simultaneous update of the two connecting wires of the connection line, the step of responding to the creation fan-out point instruction for the connection line and creating a fan-out point specifically includes:

[0156] Responding to the creation fan-out point instruction for the connection line of the initial quantum chip layout, displaying a fan-out line on the connection line, and creating a fan-out point on the fan-out line.

[0157] By displaying a fan-out line between the two connecting wires, it is convenient for the user to select a suitable fan-out point. By adjusting the coordinates of the fan-out point on the fan-out line, the passing position and the shape of the fan-out line are adjusted. According to the adjusted shape of the fan-out line, the adjustment of the two connecting wires of the connection line can be realized to obtain the updated connection line.

[0158] Exemplarily, the coordinate adjustment instruction of the fan-out point may be a release operation of the dragged fan-out point. Accordingly, the above-mentioned response to the coordinate adjustment instruction of the fan-out point, determining the target position of the fan-out point, and obtaining the updated connection line specifically include:

[0159] In response to a release operation on the dragged fan-out point, a release position of the fan-out point is determined as a target position to obtain the updated connection line.

[0160] In a specific embodiment, in response to the release operation of the dragged fan-out point, determining the release position of the fan-out point as the target position to obtain the updated connection line specifically includes:

[0161] When a first click operation on the fan-out point is detected, determining the current position of the fan-out point as a starting point;

[0162] When the user drags the fan-out point from the starting point, continuously detecting in real time whether the click on the fan-out point is released;

[0163] When it is detected that the click is released, in response to the release operation of the dragged fan-out point, the release position of the fan-out point is determined as the target position to obtain the updated connection line.

[0164] Specifically, the first click operation may be a single click or double click of the left button of the mouse; during the fan-out point editing process, the operation of the mouse on the fan-out point may be detected in real time. When it is detected that the operation on the fan-out point is a single click or double click of the left button of the mouse, the current position of the fan-out point is determined as the starting point, and the operation of the user dragging the fan-out point is responded to, and the shape of the fan-out line is linked to the position of the fan-out point.

[0165] If the user issues a first click operation on the fan-out point and drags it, during the movement of the fan-out point, the shape of the fan-out line can be linked to the position of the fan-out point. When the user stops dragging the fan-out point and releases it, a coordinate adjustment instruction of the fan-out point is issued, and the release position of the fan-out point is determined as the target position, and the coordinate information of the target position of the fan-out point is obtained. At this time, the shape of the fan-out line no longer changes, and the shapes of the two connecting lines of the connecting line are updated in real time according to the shape of the fan-out line. In addition, in the process of updating the connecting line, an arc transition is performed at the target position of the two connecting lines corresponding to the fan-out point, so as to obtain the updated connecting line.

[0166] Exemplarily, the coordinate adjustment instruction of the fan-out point may be a coordinate configuration instruction for the fan-out point. Accordingly, the above-mentioned response to the coordinate adjustment instruction for the fan-out point, determining the target position of the fan-out point, and obtaining the updated connection line specifically include:

[0167] In response to the coordinate configuration instruction for the fan-out point, a target position of the fan-out point is determined to obtain the updated connection line.

[0168] In a specific embodiment, in response to the coordinate configuration instruction of the fan-out point, determining the target position of the fan-out point and obtaining the updated connection line specifically include:

[0169] When a second click operation on the fan-out point is detected, a coordinate adjustment input box is displayed; after the user inputs the coordinate value in the coordinate adjustment input box, in response to the coordinate configuration instruction of the fan-out point, the target position of the fan-out point is determined to obtain the updated connection line.

[0170] The above-mentioned second click operation can be a right click or double click of the mouse. In this way, the user can first right click the mouse above the fan-out point, thereby triggering the display of the coordinate adjustment input box in the quantum chip layout editing interface. After the user enters the coordinates of the target position of the fan-out point in the coordinate adjustment input box, the user interacts with the interface to issue a coordinate configuration instruction for the fan-out point. In response to the configuration instruction for the fan-out point, the coordinate information of the target position of the fan-out point is obtained, and the position of the fan-out point is jumped from the current position to the target position. The shape of the fan-out line is also linked accordingly. At this time, the shape of the fan-out line no longer changes, and the shapes of the two connecting lines of the connecting line are updated in real time according to the shape of the fan-out line. In addition, in the process of updating the connecting line, an arc transition is performed at the target position of the two connecting lines corresponding to the fan-out point, that is, the updated connecting line is obtained.

[0171] In a specific embodiment, after the target position of the fan-out point is determined by moving the fan-out point through the above-mentioned dragging instruction of the fan-out point or by the coordinate configuration instruction of the fan-out point, the updated connection line can be obtained in the following manner:

[0172] Determine the straight line segment where the fan-out point is located on the fan-out line, and determine the two endpoints of the straight line segment;

[0173] According to the target position of the fan-out point and the two end points, the corners of the fan-out line are subjected to arc transition to obtain a reference line;

[0174] The connecting line is linked with the reference line in the same manner to obtain the updated connecting line.

[0175] After determining the target position of the fan-out point on the fan-out line, find the straight line segment where the fan-out point was located before moving, and obtain the coordinates of the fan-out point and the two endpoints of the straight line segment (for the convenience of description, the two end points can be defined as the starting point and the end point, respectively). After the fan-out point moves, the straight line segment passing through the fan-out point and the two end points becomes a broken line segment. If the connecting line is directly updated in the same linkage according to the shape of the line segment, it will affect the signal transmission accuracy and stability of the connecting line. Therefore, according to the target position of the fan-out point and the two end points, the corners of the fan-out line can be made into an arc transition to obtain a reference line. Compared with the original fan-out line, the reference line realizes an arc transition at the angle of the broken line. The connecting line is made to be linked with the reference line in the same way, and the updated connecting line is smoother, which can improve the signal transmission accuracy and stability of the updated connecting line.

[0176] In a specific embodiment, the above-mentioned performing arc transition on the corner of the fan-out line according to the target position of the fan-out point and the two end points to obtain the reference line specifically includes:

[0177] Determine, on the fan-out line, a turning angle with a target position of the fan-out point and the two end points as vertices;

[0178] According to a preset radius, determine the center and two tangent points of a circle tangent to two sides of the corner on the angle bisector of each corner;

[0179] For each corner, construct an arc with the center, the two tangent points and the preset radius;

[0180] The reference line is obtained by replacing the vertex of each corner and the broken line between the two tangent points with the corresponding arc.

[0181] For example, refer to Figure 17 As shown in FIG. 1 , an example is to make an arc transition for a corner with the target position of the fan-out point of the fan-out line as the vertex. According to the preset radius r, the center O and the two tangent points q1 and q2 of the circle tangent to the two sides of the corner are determined on the angle bisector of the corner. Then, the arc is constructed with the center O, the two tangent points q1 and q2 and the radius r, as shown in FIG. Figure 17 As shown by the dotted line in , the arc is used to replace the broken line between the target position of the fan-out point and the two tangent points q1 and q2 to obtain the reference line.

[0182] In a specific example, referring to Figure 13 As shown, the user clicks the "Fan-out Point Mode" icon (i.e. Figure 13In response to the editing instruction for the connecting line, the air bridge layer is hidden. At this time, the user clicks at any position of the connecting line, such as single-click or double-click, and issues a fan-out point creation instruction for the connecting line. In response to the fan-out point creation instruction for the connecting line, a fan-out line is displayed between the two connecting lines of the connecting line, a fan-out point is created on the fan-out line, and the starting point and end point of the straight line segment where the fan-out point is located on the fan-out line are determined, and an "×" cursor can be displayed at the fan-out point, the starting point and the end point. At this time, if the user clicks the left mouse button to select the fan-out point, the click operation serves as the starting trigger of the drag operation to trigger the human-computer interface interaction. If the user drags the fan-out point, the shape of the fan-out line can be linked with the position of the fan-out point during the process of dragging the fan-out point, and the animation of the fan-out line change process during the dragging of the fan-out point can be dynamically displayed. In addition, during the movement of the fan-out point, the QEDA software front-end interface detects in real time whether the mouse is released. When the mouse is detected to be released, the QEDA software back-end program responds to the release operation instruction of the dragged fan-out point, and determines the release position of the fan-out point as the target position, that is, the coordinate information of the release position of the fan-out point is used as the coordinate of the target position of the fan-out point. According to the target position of the fan-out point and the two end points, the corners of the fan-out line are subjected to arc transition to obtain a reference line, and the connecting line is similarly linked with the reference line to realize the arc transition processing at the corners of the two connecting lines of the connecting line to obtain the updated connecting line, and the reference line is used as a reference. Figure 18 As shown in the figure, it is the quantum chip layout after dragging the fan-out point and updating the connection line. It can be seen from the figure that the connection line at the corner formed at the target position of the corresponding fan-out point is processed with an arc.

[0183] Of course, in some other embodiments, reference Figure 20 As shown, if after creating a fan-out point, the user does not drag the fan-out point, but issues a coordinate configuration instruction for the fan-out point, for example, by right-clicking the fan-out point, and the QEDA software front-end interface program determines that the mouse is clicked above the fan-out point, then refer to Figure 21 As shown, the click operation serves as the starting trigger of the input box to trigger the human-computer interface interaction, and the QEDA software front-end interface actually displays the fan-out point coordinate adjustment input box. The user enters the coordinate value in the coordinate adjustment input box, that is, the coordinate of the target position of the fan-out point, clicks "Confirm", and issues a coordinate configuration instruction. The QEDA software back-end program responds to the coordinate configuration instruction and obtains the coordinate of the target position of the fan-out point entered by the user. Figure 21As shown, the position of the fan-out point jumps from the current position to the target position, and the shape of the fan-out line also moves accordingly. At this time, according to the target position of the fan-out point and the two end points, an arc transition is made at the corner of the fan-out line to obtain a reference line. The connection line moves in the same way as the reference line to achieve an arc transition at the corners of the two connection lines of the connection line, and the updated connection line is obtained. Refer to Figure 22 As shown, it is the quantum chip layout after dragging the fan-out point and updating the connection line. It can be seen from the figure that an arc treatment is made on the connection line at the corner formed at the target position corresponding to the fan-out point.

[0184] Furthermore, after obtaining the quantum chip layout after dragging the fan-out point and updating the connection line, the method may further include: in response to an edit instruction for the connection line of the initial quantum chip layout being exited, displaying an air bridge layer and regenerating an air bridge on the updated connection line. Still referring to Figure 19 Or Figure 23 Taking the quantum chip layout shown as an example, the user clicks the "fan-out point mode" icon again to issue an edit instruction for exiting the connection line. In response to the edit instruction for exiting the connection line, the air bridge layer is redisplayed in the target area. Since the shape of the connection line has changed, an air bridge is regenerated on the updated connection line.

[0185] In an embodiment of the present invention, the user instruction for the quantum chip layout in the above step S101 may also be a quantum chip layout quick creation instruction. The above step S101 responds to the quantum chip layout creation instruction to create a target area. It may be that, in response to the quantum chip layout creation instruction, a quantum chip layout creation interface is created and displayed; correspondingly, in the above step S102, in response to the connection line generation instruction, connection lines are automatically generated between the target quantum elements in the target area. It may be that, according to the input parameters of the user in the quantum chip layout creation interface, in response to the connection line generation instruction, a quantum chip layout editing interface is displayed, and the connection lines are automatically generated between the target quantum elements in the quantum chip layout editing interface.

[0186] In a specific embodiment, in the above step S103, according to the air bridge generation instruction, an air bridge is automatically generated on the connection line to obtain the initial quantum chip layout. Specifically, it may be that after the connection line is generated, according to the air bridge generation instruction, the coordinate positions of the air bridges are determined on the connection line according to a preset air bridge spacing, and air bridges are automatically generated perpendicular to the connection line at the corresponding coordinate positions. In this way, after the wiring is completed, air bridges can be evenly deployed on the connection line, that is, according to the path length of the connection line, coordinate uniform sampling is performed according to the preset spacing to generate multiple air bridges with the same direction.

[0187] Exemplarily, refer toFigure 24 As shown, after the user operates to open the QEDA software, "Quick Creation" can be selected to create and display the quantum chip layout creation interface. By setting parameters, the quantum chip layout can be automatically and quickly constructed. Refer to Figure 25 As shown, in the quantum chip layout creation interface, input chip-related parameters, select qubit elements and set parameters, set pins, coupler and other parameters, and click "Complete Settings" to send a control instruction. Then the graphical user interface jumps to the quantum chip layout editing interface. Refer to Figure 19 and Figure 20 As shown, connection lines between quantum elements are generated in the target area of the editing interface, and air bridges are generated on the connection lines to obtain the initial quantum chip layout. From Figure 26 and Figure 27 It can be seen that in the embodiments of the present invention, during the generation of the quantum chip layout, the pins can be evenly arranged on the four sides, and the directions of the connection lines can be evenly distributed as much as possible to maximize the use of the layout space. In this embodiment, the control instruction includes a combined instruction of a connection line generation instruction and an air bridge generation instruction. Of course, in some other examples, the control instruction can be a separate connection line generation instruction and a separate air bridge generation instruction. The specific implementation method can refer to the implementation method of the prior art and will not be elaborated here.

[0188] In the embodiments of the present invention, during the process of obtaining the Figure 27 shown initial quantum chip layout, if the connection line is not a straight line, fillet transitions are also performed at each corner of the connection line. The specific implementation method can refer to the above description about Figure 14 and will not be elaborated here.

[0189] In the embodiments of the present invention, after the initial quantum chip layout is obtained by executing the quantum chip layout quick creation instruction, the method of editing the connection lines and the fan-out points is the same as that after the initial quantum chip layout is obtained by the quantum chip layout custom creation instruction. The implementation process can refer to the descriptions of steps S104 and S105 above and will not be elaborated here.

[0190] The inventor also found that when the wiring scheme in the existing quantum chip layout design software encounters a collision, it usually adopts the method of bypassing or directly crossing elements or crossing two connection lines. Therefore, in the embodiments of the present invention, during the process of generating the initial quantum chip layout, the method may further include:

[0191] During the drawing process of the connection line, detect whether the connection line collides with a specified element;

[0192] If so, determine the starting point and the ending point that span the specified element;

[0193] Perform a cross-line operation based on the starting point and the ending point to generate a cross-line structure that crosses the specified element.

[0194] Specifically, it can be that during the quantum chip layout wiring process, it is possible to detect in real time whether a connection line collides with a quantum component. If the quantum component involved in the collision is the specified element, for example, the specified element is a coupler, then determine the starting point and the ending point for crossing the specified element, and automatically generate a cross-line structure that crosses the line between the starting point and the ending point of crossing the specified element. This cross-line structure can be a cross-line air bridge, enabling the connection line to cross the specified element in special scenarios without generating cross-interference.

[0195] Refer to Figure 27 As shown, in this quantum chip layout, multiple connection lines respectively collide with different couplers. When a collision is detected, the starting point and the ending point of the connection line can be determined based on the quantum component to which the connection line is connected, a rectangular frame with the connection line as the center line is generated, the intersection coordinates of the rectangular frame and the coupler it crosses are determined, and the positions on both sides of the coupler corresponding to the rectangular frame are respectively determined as the starting point and the ending point for crossing the coupler; perform a cross-line operation based on the starting point and the ending point to generate a cross-line air bridge that crosses the coupler, refer to Figure 28 As shown, it is Figure 27 a partial structural schematic diagram of the position of the cross-line air bridge formed by crossing the coupler in

[0196] In a specific embodiment, the method may further include: after responding to a quantum chip layout creation instruction to create a target area, in response to an import request for an initial quantum chip layout, generating the pre-stored initial quantum chip layout in the target area; wherein, the target area is a quantum chip layout editing interface.

[0197] Exemplarily, refer to Figure 29 As shown, after the user operates to open the QEDA software, selects "Custom Creation", and the graphical user interface jumps to the quantum chip layout editing interface, or during the quantum chip layout creation process when the graphical user interface is in the quantum chip layout editing interface, the user clicks the "Edit" icon, then clicks "Import Case" and selects the corresponding pre-stored initial quantum chip layout, and clicks "OK" to send an import request instruction for the initial quantum chip layout. In response to the import request for the initial quantum chip layout, refer to Figure 30 As shown, generate the pre-stored initial quantum chip layout in the target area.

[0198] In the embodiments of the present invention, refer to Figure 26 and Figure 27As shown, when the user clicks on the "Move" icon, it is also possible to initiate a drag instruction for different quantum components including bit elements, pins, couplers, air bridges, etc. In response to the drag instruction for any quantum component, move the quantum component to achieve adjustment of the position and angle of the quantum component, and update the shape of the quantum chip layout in real time.

[0199] In an embodiment of the present invention, referring to Figure 26 and Figure 27 As shown, when the user selects any quantum component in the quantum chip layout, it is also possible to adjust the parameters of the quantum component, initiate a parameter adjustment instruction for the quantum component. In response to the parameter adjustment instruction for any quantum component, it is possible to achieve adjustment of the size and position of the quantum component, and update the shape of the quantum chip layout in real time.

[0200] Based on the same inventive concept, an embodiment of the present invention further provides a quantum chip layout wiring device, a related storage medium, a computer device, a computer program product containing instructions, and a chip. Since the principles of the problems solved by these devices, the related storage medium, the computer device, the computer program product containing instructions, and the chip are similar to those of the foregoing quantum chip layout wiring method, the implementation of these devices, the related storage medium, the computer device, the computer program product containing instructions, and the chip can refer to the implementation of the foregoing method, and the repeated parts will not be described again.

[0201] An embodiment of the present invention provides a quantum chip layout wiring device. Referring to Figure 31 As shown, it includes:

[0202] A target area creation module 101, configured to create a target area in response to a quantum chip layout creation instruction;

[0203] A connection line generation module 102, configured to automatically generate connection lines between target quantum components in the target area in response to a connection line generation instruction; the connection line generation instruction includes port parameters of the connection lines between the target quantum components;

[0204] An air bridge generation module 103, configured to automatically generate air bridges on the connection lines according to an air bridge generation instruction to obtain an initial quantum chip layout; the connection line generation instruction and the air bridge generation instruction are combined instructions or two separate instructions.

[0205] An embodiment of the present invention provides a computer-readable storage medium, on which computer instructions are stored, and when the instructions are executed by a processor, the foregoing quantum chip layout wiring method is implemented.

[0206] An embodiment of the present invention provides a computer device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, the above-mentioned quantum chip layout routing method is implemented.

[0207] An embodiment of the present invention provides a computer program product containing instructions. When the computer program product runs on a computer device, the computer device is enabled to execute the above-mentioned quantum chip layout routing method.

[0208] An embodiment of the present invention provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor, and the processor is used to run a computer program or instruction to implement the above-mentioned quantum chip layout routing method.

[0209] Unless otherwise specifically stated, terms such as processing, computing, operation, determination, display, etc. can refer to the actions and / or processes of one or more processing or computing systems, or similar devices, which operate on and transform data represented as physical (such as electronic) quantities in the registers or memories of the processing system into other data similarly represented as physical quantities in the memories, registers, or other such information storage, transmission, or display devices of the processing system. Information and signals can be represented using any of a variety of different technologies and methods. For example, the data, instructions, commands, information, signals, bits, symbols, and code chips mentioned throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0210] It should be understood that the specific order or hierarchy of steps in the disclosed process is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process can be rearranged without departing from the scope of the present disclosure. The appended method claims present the elements of the various steps in an exemplary order and are not intended to be limited to the specific order or hierarchy.

[0211] In the above detailed description, various features are combined in a single embodiment to simplify the present disclosure. This method of disclosure should not be interpreted as reflecting an intention that the embodiments of the claimed subject matter require more features than are clearly recited in each claim. On the contrary, as reflected in the appended claims, the present invention lies in a state with fewer features than all the features of the disclosed single embodiment. Therefore, the appended claims are hereby expressly incorporated into the detailed description, where each claim stands alone as a separate preferred embodiment of the present invention.

[0212] Those skilled in the art should also understand that all the illustrative logical blocks, modules, circuits, and algorithm steps described in conjunction with the embodiments herein can be implemented as electronic hardware, computer software, or a combination thereof. To clearly illustrate the interchangeability between hardware and software, the above-described various illustrative components, blocks, modules, circuits, and steps have been generally described in terms of their functions. Whether such a function is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Skilled technicians can implement the described functions in a flexible manner for each specific application, but such implementation decisions should not be construed as departing from the scope of protection of this disclosure.

[0213] The steps of the methods or algorithms described in conjunction with the embodiments herein can be directly embodied as hardware, software modules executed by a processor, or a combination thereof. The software modules can be located in a RAM memory, a flash memory, a ROM memory, an EPROM memory, an EEPROM memory, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium well-known in the art. An exemplary storage medium is connected to the processor so that the processor can read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an ASIC. The ASIC can be located in a user terminal. Of course, the processor and the storage medium can also exist as discrete components in the user terminal.

[0214] For software implementation, the techniques described in this application can be implemented using modules (e.g., procedures, functions, etc.) that perform the functions described in this application. These software codes can be stored in a memory unit and executed by a processor. The memory unit can be implemented inside the processor or outside the processor. In the latter case, it is communicatively coupled to the processor via various means, which are well-known in the art.

[0215] The above description includes examples of one or more embodiments. Of course, it is impossible to describe all possible combinations of components or methods for the purpose of describing the above embodiments, but those of ordinary skill in the art should recognize that the various embodiments can be further combined and arranged. Therefore, the embodiments described herein are intended to cover all such changes, modifications, and variations that fall within the scope of protection of the appended claims. In addition, with respect to the term "comprising" used in the specification or claims, this term is covered in a manner similar to the term "including" as interpreted when "including," is used as a transitional word in the claims. In addition, any term "or" used in the specification and claims of the patent application is intended to mean "non-exclusive or."

Claims

1. A method for quantum chip layout routing, comprising: In response to a quantum chip layout creation instruction, create a target area; In response to a connection line generation instruction, automatically generate connection lines between target quantum elements in the target area; The connection line generation instruction includes port parameters of the connection lines between the target quantum elements; According to an air bridge generation instruction, automatically generate air bridges on the connection lines to obtain an initial quantum chip layout; The connection line generation instruction and the air bridge generation instruction are merged instructions or two separate instructions.

2. The method according to claim 1, wherein, The step of, according to the air bridge generation instruction, automatically generating air bridges on the connection lines to obtain an initial quantum chip layout includes: After generating the connection lines, according to the air bridge generation instruction, determine the coordinate positions of the air bridges on the connection lines at a preset air bridge spacing, and automatically generate air bridges perpendicular to the connection lines at the corresponding coordinate positions; the air bridge generation instruction includes air bridge spacing information and port parameters of the target quantum elements connected by the connection lines.

3. The method according to claim 1 or 2, wherein, It further includes: In response to an edit instruction for the connection lines of the initial quantum chip layout, hide the air bridge layer; In response to an edit fan-out point instruction for the connection lines, determine the target position of the fan-out point to obtain updated connection lines; wherein, the updated connection lines have an arc transition at the target position of the fan-out point.

4. The method according to claim 3, wherein, It further includes: The step of, in response to an edit fan-out point instruction for the connection lines, determining the target position of the fan-out point to obtain updated connection lines includes: In response to a create fan-out point instruction for the connection lines, create a fan-out point; In response to a coordinate adjustment instruction for the fan-out point, determine the target position of the fan-out point to obtain updated connection lines.

5. The method according to claim 4, wherein, The step of, in response to a create fan-out point instruction for the connection lines, creating a fan-out point includes: In response to a create fan-out point instruction for the connection lines of the initial quantum chip layout, display a fan-out line on the connection lines and create a fan-out point on the fan-out line.

6. The method according to claim 5, wherein, The connection lines include two spaced-apart lines; the step of, in response to a create fan-out point instruction for the connection lines of the initial quantum chip layout, creating a fan-out point includes: In response to a create fan-out point instruction for the connection lines of the initial quantum chip layout, display the fan-out line between the two lines and create a fan-out point on the fan-out line.

7. The method according to any one of claims 4 - 6, wherein, The step of, in response to a coordinate adjustment instruction for the fan-out point, determining the target position of the fan-out point to obtain updated connection lines includes: In response to a release operation on the dragged fan-out point, determine the release position of the fan-out point as the target position to obtain the updated connection lines; Or, In response to a coordinate configuration instruction for the fan-out point, determine the target position of the fan-out point to obtain the updated connection lines.

8. The method according to claim 7, wherein, The step of, in response to a release operation on the dragged fan-out point, determining the release position of the fan-out point as the target position to obtain the updated connection lines specifically includes: When detecting a first click operation on the fan-out point, determine the current position of the fan-out point as the starting point; During the process of the user dragging the fan-out point from the starting point, continuously and real-time detect whether the click on the fan-out point is released; When it is detected that the click is released, in response to the release operation of the dragged fan-out point, the release position of the fan-out point is determined as the target position to obtain the updated connection line.

9. The method according to claim 8, wherein, The first click operation is a single click or double click of the left button of the mouse; when the first click operation on the fan-out point is detected, the current position of the fan-out point is determined as the starting point, specifically including: The operation of the mouse on the fan-out point is detected in real time. When it is detected that the operation on the fan-out point is a left-click or a double-click of the mouse, the current position of the fan-out point is determined as the starting point, and the user's operation of dragging the fan-out point is responded to, and the shape of the fan-out line is linked to the position of the fan-out point.

10. The method according to claim 7, wherein, The step of determining the target position of the fan-out point in response to the coordinate configuration instruction of the fan-out point and obtaining the updated connection line specifically includes: When a second click operation on the fan-out point is detected, a coordinate adjustment input box is displayed; After the user inputs the coordinate value in the coordinate adjustment input box, in response to the coordinate configuration instruction for the fan-out point, the target position of the fan-out point is determined to obtain the updated connection line.

11. The method according to claim 7, wherein After determining the target position of the fan-out point, the updated connection line is obtained by: Determine the straight line segment where the fan-out point is located on the fan-out line, and determine the two endpoints of the straight line segment; According to the target position of the fan-out point and the two end points, the corners of the fan-out line are subjected to arc transition to obtain a reference line; The connecting line is linked with the reference line in the same manner to obtain the updated connecting line.

12. The method according to claim 11, wherein The step of performing arc transition on the corner of the fan-out line according to the target position of the fan-out point and the two end points to obtain the reference line includes: Determine, on the fan-out line, a turning angle with a target position of the fan-out point and the two end points as vertices; According to a preset radius, determine the center and two tangent points of a circle tangent to two sides of the corner on the angle bisector of each corner; For each corner, construct an arc with the center, the two tangent points and the preset radius; The reference line is obtained by replacing the vertex of each corner and the broken line between the two tangent points with the corresponding arc.

13. The method according to any one of claims 4 - 6, wherein Also includes: In response to exiting the editing instruction for the connection line, the air bridge layer is displayed, and the air bridge is regenerated on the updated connection line.

14. The method according to claim 1 or 2, wherein Also includes: During the connection line drawing process, detecting whether the connection line collides with a specified element; If so, determine the start and end points of the span across the specified element; A cross-line operation is performed according to the starting point and the end point to generate a cross-line structure that crosses the designated element.

15. The method according to claim 1 or 2, wherein The quantum chip layout creation instruction is a quantum chip layout custom creation instruction; the creating of the target area in response to the quantum chip layout creation instruction includes: In response to the quantum chip layout creation instruction, create and display a quantum chip layout editing interface; Accordingly, in response to the connection line generation instruction, automatically generating a connection line between the target quantum elements in the target area includes: According to the port parameter correspondence between the quantum components added by the user in the quantum chip layout editing interface and the target quantum components input, in response to the connection line generation instruction, the connection line is automatically generated between the target quantum components in the quantum chip layout editing interface.

16. The method according to claim 1 or 2, wherein The quantum chip layout creation instruction is a quantum chip layout quick creation instruction; the creation of the target area in response to the quantum chip layout creation instruction includes: In response to the quantum chip layout creation instruction, a quantum chip layout creation interface is created and displayed; Correspondingly, the automatic generation of the connection line between the target quantum components in the target area in response to the connection line generation instruction includes: According to the input parameters of the user in the quantum chip layout creation interface, in response to the connection line generation instruction, a quantum chip layout editing interface is displayed, and the connection line is automatically generated between the target quantum components in the quantum chip layout editing interface.

17. The method according to claim 1 or 2, wherein It also includes: In response to any instruction for dragging, removing, adding, or parameter configuration of the air bridge, corresponding operations of dragging, removing, adding, or parameter configuration are performed on the air bridge.

18. The method according to claim 1 or 2, wherein During the process of automatically generating the connection line between the target quantum components in the target area, the method further includes: If the connection line is not a straight line, an arc transition is performed at each corner of the connection line.

19. The method according to claim 18, wherein The connection line includes two spaced-apart connecting lines; the arc transition is performed at each corner of the connection line in the following manner: According to the two endpoints of each of the two connecting lines of the connection line, the center line of the two connecting lines is determined; The positions of the corners of the center line are determined; According to a preset radius, the center of the circle tangent to both sides of the corner and two tangent points are determined on the angle bisector of each corner; For each corner, an arc is constructed with the center of the circle, the two tangent points, and the preset radius; On the center line, the broken line between the vertex of each corner and the two tangent points is replaced by a corresponding arc respectively to obtain a reference center line; The two connecting lines are linked in the same way as the reference center line to obtain the updated connection line.

20. The method according to claim 1, wherein, It also includes: After creating the target area in response to the quantum chip layout creation instruction, in response to the import request of the quantum chip layout, an initial quantum chip layout stored in advance is generated in the target area; where the target area is the quantum chip layout editing interface.

21. A quantum chip layout wiring device, comprising: A target area creation module, configured to create a target area in response to the quantum chip layout creation instruction; A connection line generation module, configured to automatically generate a connection line between the target quantum components in the target area in response to the connection line generation instruction; The connection line generation instruction includes the port parameters of the connection line between the target quantum components; An air bridge generation module, configured to automatically generate an air bridge on the connection line according to the air bridge generation instruction to obtain an initial quantum chip layout; The connection line generation instruction and the air bridge generation instruction are combined instructions or two separate instructions.

22. A computer-readable storage medium, on which computer instructions are stored, and when the instructions are executed by a processor, the quantum chip layout wiring method according to any one of claims 1-20 is implemented.

23. A computer device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, and when the processor executes the program, the quantum chip layout wiring method according to any one of claims 1-20 is implemented.

24. A computer program product containing instructions, and when the computer program product runs on a computer device, the computer device is caused to execute the quantum chip layout wiring method according to any one of claims 1-20.

25. A chip, the chip includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is used to run a computer program or instruction to implement the quantum chip layout wiring method according to any one of claims 1-20.

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