Memory controller and memory system including same

Abstract

The invention relates to a memory controller and a memory system including the same. A storage system includes: a plurality of storage modules; a plurality of module controllers configured to control the plurality of memory modules, respectively; and a plurality of interface circuits configured to connect the plurality of memory modules with the plurality of module controllers, in which at least one target interface circuit is configured to connect a target module controller of the plurality of module controllers with a target memory module of the plurality of memory modules according to a setting signal, or other module controllers different from the target module controller are connected with the target storage module.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10 - 2023 - 0185698, filed on December 19, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate to semiconductor design technology, and more particularly, to a storage system including a memory controller for performing an error correction operation. Background Art

[0004] A storage system can store data provided from an external device and provide the stored data to an external device. The storage system can include an error correction circuit to ensure data reliability. Recently, a memory device can store data and an error correction code together, and the error correction circuit can use the error correction code read from the memory device to perform an error correction operation of detecting and correcting an error in the data read from the memory device. Summary of the Invention

[0005] Embodiments of the present disclosure relate to a memory controller capable of flexibly adjusting error correction ability according to settings and a storage system including the memory controller.

[0006] According to an embodiment of the present disclosure, a storage system includes: a plurality of storage modules; a plurality of module controllers configured to respectively control the plurality of storage modules; and a plurality of interface circuits configured to connect the plurality of storage modules to the plurality of module controllers, wherein, according to a setting signal, at least one target interface circuit is configured to connect a target module controller among the plurality of module controllers to a target storage module among the plurality of storage modules, or connect another module controller different from the target module controller to the target storage module.

[0007] According to an embodiment of the present disclosure, a storage system includes: a first storage module to a third storage module; a first module controller to a third module controller configured to respectively generate user data and an error correction code for the first storage module to the third storage module; and a first interface circuit to a third interface circuit configured to respectively send user data and an error correction code to the first storage module to the third storage module / receive user data and an error correction code from the first storage module to the third storage module through independent channels, wherein the first module controller and the second module controller are configured to respectively increase the size of the error correction code according to a setting signal to generate a first extended error correction code and a second extended error correction code, and wherein the third interface circuit is configured to send the first extended error correction code and the second extended error correction code to the third storage module and receive the first extended error correction code and the second extended error correction code from the third storage module according to the setting signal.

[0008] According to an embodiment of the present disclosure, a memory controller includes: a first module controller to a third module controller configured to generate user data and an error correction code for a first storage module to a third storage module, respectively; and a first interface circuit to a third interface circuit configured to send the user data and the error correction code to the first storage module to the third storage module and receive the user data and the error correction code from the first storage module to the third storage module through independent channels, wherein the first module controller and the second module controller are configured to increase the size of the error correction code according to a setting signal to generate a first extended error correction code and a second extended error correction code, respectively, and wherein the third interface circuit is configured to send the first extended error correction code and the second extended error correction code to the third storage module and receive the first extended error correction code and the second extended error correction code from the third storage module according to the setting signal.

[0009] In addition, according to an embodiment of the present disclosure, a storage system can improve the error correction ability only in an extended mode that requires high-performance error correction ability, thereby performing the error correction operation flexibly according to the system environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram showing a data processing system according to an embodiment of the present disclosure.

[0011] Figure 2 is a block diagram showing a storage system according to a first embodiment of the present disclosure.

[0012] Figure 3 is a diagram showing a first physical interface circuit according to an embodiment of the present disclosure Figure 2 of.

[0013] Figure 4 is a block diagram showing a storage system according to a second embodiment of the present disclosure.

[0014] Figure 5 is a diagram for describing the connection between a third physical interface circuit and a third storage module according to an embodiment of the present disclosure Figure 4 of.

[0015] Figure 6 is a diagram for describing the input / output signals between the module control logic and the memory interface logic according to an embodiment of the present disclosure Figure 4 of.

[0016] Figure 7A and Figure 7B is a diagram showing a third physical interface circuit according to an embodiment of the present disclosure Figure 6 of.

[0017] Figure 8A and Figure 8BIt is a diagram for describing the configuration of a storage system according to a setting signal in accordance with an embodiment of the present disclosure.

[0018] Figure 9 It is a diagram for describing a modification example of a storage system according to an embodiment of the present disclosure.

[0019] Figure 10 It is a diagram for describing another modification example of a storage system according to an embodiment of the present disclosure. Detailed Description of the Invention

[0020] Various embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. However, the embodiments of the present disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Throughout the present disclosure, the same reference numerals in the multiple drawings and embodiments of the present disclosure refer to the same components.

[0021] It should be understood that when an element is referred to as being "coupled" or "connected" to another element, this may mean that the two are directly coupled, or that the two are electrically connected to each other through another intervening circuit. It should also be understood that when the terms "comprising", "including" and "having" are used in this specification, they specify the presence of the stated features, numbers, steps, operations, elements, components and / or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components and / or combinations thereof. In the present disclosure, unless the context clearly indicates otherwise, the singular forms are also intended to include the plural forms.

[0022] Figure 1 It is a block diagram showing a data processing system 1 according to an embodiment of the present disclosure.

[0023] Reference Figure 1 , the data processing system 1 may include a host device 20 and a storage system 10.

[0024] The storage system 10 may include a memory controller 12 and a memory device 14. The storage system 10 may store data under the control of the host device 20 (such as a cellular phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game player, a TV, a tablet PC or an in-vehicle infotainment system). The host device 20 may be an external device of the storage system 10.

[0025] According to the host interface as a communication method with the host device 20, the storage system 10 can be manufactured as any one of various types of storage modules. The storage system 10 can be configured with any one of various types of storage modules, such as solid state drives (SSDs), multimedia cards in the form of MMC, eMMC, RS_MMC, and micro MMC, secure digital cards in the form of SD, mini SD, and micro SD, universal serial bus (USB) storage modules, universal flash storage (UFS) devices, Personal Computer Memory Card International Association (PCMCIA) card type storage modules, Peripheral Component Interconnect (PCI) card type storage modules, Express PCI (PCI-E) card type storage modules, CompactFlash (CF) cards, SmartMedia cards, and Memory Sticks.

[0026] The storage system 10 can be manufactured in any one of various package types. For example, the storage system 10 can be manufactured in any one of various package types, such as Package on Package (POP), System in Package (SIP), System on Chip (SOC), Multi-Chip Package (MCP), Chip on Board (COB), Wafer-Level Fabrication Package (WFP), Wafer-Scale Package (WSP), etc.

[0027] The memory device 14 can store data. The memory device 14 operates under the control of the memory controller 12. The memory device 14 can include a memory cell array that includes a plurality of memory cells for storing data. In an embodiment, the memory cell array can include a plurality of memory blocks. Each memory block can include a plurality of memory cells. A memory block can be a unit of an erase operation. One memory block can include a plurality of pages. In an embodiment, a page can be a unit for storing data in the memory device 14 or reading data stored in the memory device 14.

[0028] In an embodiment, the memory device 14 can be a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, vertical NAND flash memory, NOR flash memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive RAM (MRAM), Ferroelectric RAM (FRAM), Spin Transfer Torque RAM (STT_RAM), etc.

[0029] The memory device 14 can receive commands and addresses from the memory controller 12 and access the area selected by the address of the memory cell array. That is, the memory device 14 can perform the operation indicated by the command on the area selected by the address. For example, the memory device 14 can perform a write operation (e.g., a programming operation) to write data to the area selected by the address. During a read operation, the memory device 14 can read data from the area selected by the address.

[0030] The memory controller 12 can control the overall operation of the storage system 10. The memory controller 12 can control the memory device 14 to perform a write operation, a read operation, or other operations according to a request from the host device 20. For example, during a write operation, the memory controller 12 can provide a write command, an address, and data to the memory device 14. During a read operation, the memory controller 12 can provide a read command and an address to the memory device 14.

[0031] The host device 20 can communicate with the storage system 10 using a communication method or standard (e.g., Universal Serial Bus (USB), Serial ATA (SATA), Serial Attached SCSI (SAS), High-Speed Inter-Chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), Express PCI (PCIe), Non-Volatile Memory Express (NVMe), Compute Express Link (CXL), Universal Flash Storage (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load-Reduced DIMM (LRDIMM)).

[0032] In an embodiment, the host device 20 can communicate with the storage system 10 through a first interface 30. The first interface 30 can be referred to as a host interface. The first interface 30 can include an interface implemented based on the Compute Express Link (CXL) protocol. The CXL protocol can use a serial interface. The CXL interface is a PCIe-based interface and can be an interface designed for a central processing unit (CPU), a graphics processing unit (GPU), and various types of accelerators to use memory more efficiently. By connecting the storage system 10 to the host device 20 via the CXL interface, the memory capacity of a computer system such as a data center and a server can be increased, and various processors in the computer system can share the memory device.

[0033] The memory controller 12 and the memory device 14 can communicate through a second interface 40. The second interface 40 can be referred to as a memory interface. The second interface 40 can include an interface implemented based on the Dual In-line Memory Module (DIMM) protocol.

[0034] Figure 2 It is a block diagram showing a storage system 10A according to a first embodiment of the present disclosure.

[0035] Referring to Figure 2 , the storage system 10A may include a memory controller 100 and a memory device 200.

[0036] The memory controller 100 may include a host interface circuit (HIC) 110, a module control logic 120, and a memory interface logic 130.

[0037] The host interface circuit 110 may communicate with a host device ( Figure 1 20 in) through a host interface. The host interface circuit 110 may communicate with the host through a CXL interface.

[0038] The module control logic 120 may be coupled to the memory device 200 through the memory interface logic 130 and control the overall operation of the memory device 200.

[0039] The memory interface logic 130 may communicate with the memory device 200 through a memory interface. The memory interface logic 130 may send control signals including a chip select signal and a command / address signal to the memory device 200 through a control signal line CTRL, and send and receive data and a strobe signal to / from the memory device 200 through data lines DQ<0:39> and a strobe line DQS, respectively. According to an embodiment, the memory interface logic 130 may send a clock signal to the memory device 200 through a separate clock line (not shown). The memory interface logic 130 may communicate with the memory device 200 through a DIMM interface.

[0040] The memory device 200 may include a plurality of memory modules that communicate independently with the memory controller 100 through separate channels CH0 and CH1. When the memory device 200 is composed of a plurality of memory modules, the memory interface logic 130 may be composed of a plurality of physical interface circuits PHY corresponding to the plurality of memory modules respectively to communicate with the corresponding memory modules through dedicated channels. In addition, the module control logic 120 may also be composed of a plurality of module controllers MC corresponding to the plurality of physical interface circuits PHY respectively to control the corresponding memory modules.

[0041] For example, as Figure 2As shown, the memory device 200 may include a first memory module 200A and a second memory module 200B, and each of the first memory module 200A and the second memory module 200B may include 10 memory packages. The module control logic 120 may include a first module controller 122 and a second module controller 124 for controlling the first memory module 200A and the second memory module 200B, respectively. The memory interface logic 130 may include a first physical interface circuit 132 and a second physical interface circuit 134 that communicate with the first memory module 200A and the second memory module 200B through a first channel CH0 and a second channel CH1, respectively.

[0042] The first physical interface circuit 132 may be coupled to 10 memory packages 201 to 210 through the first channel CH0. The first physical interface circuit 132 may send / receive data to / from the 10 memory packages 201 to 210 through 40 data lines DQ<0:39>. For example, the memory package 201 may input and output data through 4 data lines DQ<0:3>, while the memory package 202 may input and output data through 4 data lines DQ<4:7>. In this case, the number of bits of data input and output at a time may be determined according to the burst length. For example, when the burst length is set to 16, each of the memory packages 201 to 210 may input and output 8 bytes (i.e., 4 * 16 bits) of data at a time.

[0043] The first physical interface circuit 132 may send / receive a strobe signal to / from the 10 memory packages 201 to 210 through a strobe line DQS. The strobe signal may be sent together with the data to synchronize the input and output of the data. According to an embodiment, when the strobe signal is differentially input, two strobe lines DQS may be arranged.

[0044] In addition, the first physical interface circuit 132 may send control signals including a chip select signal and a command / address signal to the memory packages 201 to 210 through a control signal line CTRL. The control signal line CTRL may be commonly coupled to the memory packages 201 to 210 and shared among the memory packages 201 to 210. The first physical interface circuit 132 may send a clock signal to the memory device 200 through a separate clock line (not shown).

[0045] Each of the memory packages 201 to 220 may include one or more memory chips (e.g., DRAM chips). Multiple memory chips included in the memory package may be stacked using 3DS (three-dimensional stacking) or wire bonding. However, embodiments of the present disclosure are not limited thereto, and each of the memory packages 201 to 220 may include different types of memory chips. For example, at least one of the memory packages 201 to 220 may have a configuration different from that of other memory packages, and / or may be coupled to the memory controller 100 by using a different method. The form factor of the storage module may have various forms, such as an Add-in Card (AIC) and an Enterprise and Data Center SSD Form Factor (EDSFF).

[0046] Some (e.g., 8) of the 10 memory packages 201 to 210, such as the memory packages 201 to 208, may be used to store user data, and the remaining two memory packages 209 and 210 (e.g., two) may be used to store error correction codes. Therefore, 32-bit user data and 8-bit error correction codes for each burst length may be input to / output from one storage module. For example, when the burst length is set to 16, the memory packages 201 to 208 may input / output 64 bytes of user data at a time, and the memory packages 209 and 210 may input / output 16 bytes of error correction codes at a time.

[0047] The second physical interface circuit 134 may be coupled to the 10 memory packages 211 to 220 through the second channel CH1. The second physical interface circuit 134 may have substantially the same configuration as the first physical interface circuit 132.

[0048] Figure 3 is a circuit diagram showing the first physical interface circuit 132 according to an embodiment of the present disclosure Figure 2 of.

[0049] Refer to Figure 3 , the first physical interface circuit 132 may include a first transmitter 132_1 to a fifth transmitter 132_5, a first synchronizer 132_6 and a second synchronizer 132_7, a data transmission circuit 132_8, and a first receiver 132_9 and a second receiver 132_10.

[0050] The first physical interface circuit 132 may receive an internal clock signal ICLK, an internal chip select signal ICS, an internal command / address signal IC / A#, and write data WDATA from the first module controller 122, and transmit read data RDATA to the memory device 200. The internal clock signal ICLK may be provided to the first physical interface circuit 132 and the second physical interface circuit 134 in common, or may be provided to the first physical interface circuit 132 and the second physical interface circuit 134 separately. The read data RDATA and the write data WDATA may consist of parallel data having a predetermined bit position (e.g., 640 bits). For reference, the internal command / address signal IC / A# may consist of a plurality of bits, and a reference numeral "#" indicating a plurality of bits is assigned.

[0051] The first transmitter 132_1 may receive the internal clock signal ICLK to output differential clock signals CLK_t and CLK_c. According to an embodiment, in order to minimize skew, a delay line for variably delaying the internal clock signal ICLK by a predetermined time according to the result of the training operation may be provided in front of the first transmitter 132_1. The differential clock signals CLK_t and CLK_c may be transmitted to the memory packages 201 to 208 through separate clock lines (not shown).

[0052] The first synchronizer 132_6 may receive the internal chip select signal ICS in synchronization with an edge (e.g., a rising edge) of the internal clock signal ICLK. The second transmitter 132_2 may receive the output signal of the first synchronizer 132_6 to output the chip select signal CS. The first synchronizer 132_6 may be implemented with a D flip-flop. According to an embodiment, in order to minimize the skew, a delay line for variably delaying the internal clock signal ICLK by a predetermined time according to the result of the training operation may be provided in front of the first synchronizer 132_6.

[0053] The second synchronizer 132_7 may receive the internal command / address signal IC / A# in synchronization with an edge (e.g., a rising edge) of the internal clock signal ICLK. The third transmitter 132_3 may receive the output signal of the second synchronizer 132_7 to output the command / address signal C / A#. The second synchronizer 132_7 may be implemented with a D flip-flop. According to an embodiment, in order to minimize skew, a delay line for variably delaying the internal clock signal ICLK by a predetermined time according to the result of the training operation may be provided in front of the second synchronizer 132_7. Although Figure 3 A case where the second synchronizer 132_7 and the third transmitter 132_3 are provided one by one is shown, but they may be provided in numbers corresponding to the number of bits of the internal command / address signal IC / A#.

[0054] The chip select signal CS and the command / address signal C / A# can be sent to the memory packages 201 to 208 through the control signal line CTRL. According to an embodiment, the differential clock signals CLK_t and CLK_C can also be sent to the memory packages 201 to 208 through the control signal line CTRL.

[0055] The data transfer circuit 132_8 can serialize the write data WDATA to generate a write strobe signal WDQS based on the serialized data. For example, the data transfer circuit 132_8 can serialize 640-bit write data WDATA in a 16:1 manner to generate a write strobe signal WDQS based on the serialized data. The fourth transmitter 132_4 can receive the serialized data from the data transfer circuit 132_8 to output data DATA, and the fifth transmitter 132_5 can transmit the write strobe signal WDQS generated by the data transfer circuit 132_8 as differential strobe signals DQS_t and DQS_c. The fifth transmitter 132_5 can generate differential strobe signals DQS_t and DQS_c corresponding to the write strobe signal WDQS.

[0056] The first receiver 132_9 can receive the data DATA provided from the memory packages 201 to 208 to output the data DATA to the data transfer circuit 132_8, and the second receiver 132_10 can receive the differential strobe signals DQS_t and DQS_c provided from the memory packages 201 to 208 to generate a read strobe signal RDQS and send the read strobe signal RDQS to the data transfer circuit 132_8. The second receiver 132_10 can compare the voltage levels of the differential strobe signals DQS_t and DQS_c to generate a read strobe signal RDQS. The data transfer circuit 132_8 can generate read data RDATA by deserializing the data DATA transmitted from the first receiver 132_9 according to the read strobe signal RDQS. For example, the data transfer circuit 132_8 can deserialize the data serially input via 40 data lines DQ<0:39> in 16-bit units according to the read strobe signal RDQS to generate 640-bit read data RDATA.

[0057] The data transfer circuit 132_8 can include a serializer / deserializer (SERDES) and a strobe generator. According to an embodiment, the strobe generator can receive an internal clock signal ICLK to generate a write strobe signal WDQS. Although Figure 3 the case where the fourth transmitter 132_4 and the first receiver 132_9 are set one by one is shown, they can be set in a number corresponding to the number of data lines DQ<0:39> (e.g., 40).

[0058] Data DATA can be sent to / received from memory packages 201 to 208 through data lines DQ<0:39>. Differential strobe signals DQS_t and DQS_c can be sent to / received from memory packages 201 to 208 through strobe line DQS.

[0059] As described above, physical interface circuits 132 and 134 can correspond to memory modules 200A and 200B and module controllers 122 and 124 one by one. Each physical interface circuit can send write data WDATA or read data RDATA to the corresponding module controller in parallel / receive write data WDATA or read data RDATA from the corresponding module controller in parallel, and send the data converted according to the burst length to the corresponding memory module / receive it from the corresponding memory module. In this case, write data WDATA, read data RDATA, and data DATA can each include user data UD and error correction code ECC.

[0060] During a write operation, each module controller can generate an error correction code based on data corresponding to a request from host device 20, and provide write data WDATA including both the data and the error correction code to the physical interface circuit. The physical interface circuit can serialize write data WDATA according to the burst length to output data DATA having 64 bytes of user data UD and 16 bytes of error correction code ECC to memory packages 201 to 210. Thus, memory packages 201 to 208 can store 64 bytes of user data UD, and memory packages 209 and 210 can store 16 bytes of error correction code ECC. During a read operation, each physical interface circuit can receive 64 bytes of user data UD and 16 bytes of error correction code ECC, and deserialize the received user data UD and the received error correction code ECC into read data RDATA to output the read data RDATA to the corresponding module controller. The module controller can use the error correction code to correct errors in the user data, and provide the error-corrected data to host device 20.

[0061] In storage system 10A according to the above embodiment, each storage module can transmit only dedicated user data and dedicated error correction codes through the corresponding physical interface circuit. That is, each storage module can store only a fixed number of error correction codes (or bits). In the following embodiments, a method of changing the error correction capability by selectively sending / receiving error correction codes for different storage modules to / from a specific storage module will be described.

[0062] Figure 4is a block diagram showing a storage system 10B according to a second embodiment of the present disclosure. Figure 5 is for describing Figure 4 the connection between a third physical interface circuit 336 and a third storage module 400C according to an embodiment of the present disclosure.

[0063] Referring Figure 4 , the storage system 10B may include a memory controller 300 and a memory device 400.

[0064] The memory device 400 may include a plurality of storage modules that communicate with the memory controller 300 independently through separate channels CH0 to CH2. For example, the memory device 400 may include a first storage module 400A to a third storage module 400C, and the first storage module 400A to the third storage module 400C communicate with the memory controller 300 through a first channel CH0 to a third channel CH2, respectively. Each of the first storage module 400A to the third storage module 400C may include 10 memory packages. Specifically, the first module 400A may include memory packages 401 to 410, the second module 400B may include memory packages 411 to 420, and the third module 400C may include memory packages 421 to 430. According to the arrangement, the memory packages of each of the first storage module 400A to the third storage module 400C may be divided into lower memory packages and upper memory packages. For example, based on the horizontal direction or the vertical direction, 5 of the 10 memory packages may be defined as lower memory packages, and the remaining 5 of the 10 memory packages may be defined as upper memory packages.

[0065] The memory controller 300 may include a host interface circuit (HIC) 310, a module control logic 320, and a memory interface logic 330.

[0066] The host interface circuit 310 may communicate with a host device ( Figure 1 in 20) through a host interface.

[0067] The module control logic 320 may be coupled to the memory device 400 through the memory interface logic 330 and control the overall operation of the memory device 400. The module control logic 320 may include a first module controller (MC) 322 to a third module controller (MC) 326 for controlling the first storage module 400A to the third storage module 400C, respectively.

[0068] The memory interface logic 330 can communicate with the memory device 400 through a memory interface. The memory interface logic 330 can include a first physical interface circuit (PHY) 332 to a third physical interface circuit (PHY) 336, which connect the first memory module 400A to the third memory module 400C to the first module controller 322 to the third module controller 326 respectively. The first physical interface circuit 332 to the third physical interface circuit 336 can send control signals to the first memory module 400A to the third memory module 400C respectively through independent channels and send data and strobe signals to the first memory module 400A to the third memory module 400C / receive data and strobe signals from them.

[0069] Figure 4 The first physical interface circuit 332 and the second physical interface circuit 334 can have a configuration substantially the same as Figure 2 the first physical interface circuit 132 and the second physical interface circuit 134. That is to say, the first physical interface circuit 332 and the second physical interface circuit 334 can send control signals including chip select signals and command / address signals to the corresponding memory module through control signal lines ( Figure 2 CTRL), and send data and strobe signals to the corresponding memory module / receive data and strobe signals from the corresponding memory module through data lines ( Figure 2 DQ<0:39>) and strobe lines ( Figure 2 DQS) respectively. User data and error correction codes can be stored in the memory package or read from the memory package via the data line DQ<0:39>. Therefore, the first physical interface circuit 332 can only transmit data and error correction codes for the first memory module 400A, while the second physical interface circuit 334 can only transmit user data and error correction codes for the second memory module 400B.

[0070] On the other hand, different from the first physical interface circuit 332 and the second physical interface circuit 334, the third physical interface circuit 336 can be coupled to the lower memory package and the upper memory package of the third memory module 400C through separate data lines, strobe lines and control signal lines respectively.

[0071] Refer to Figure 5 , the third physical interface circuit 336 can be coupled to the lower memory packages 421 to 425 of the third memory module 400C through the lower data line DQ<0:19>, the lower strobe line DQS1 and the first control signal line CTRL1. In addition, the third physical interface circuit 336 can be coupled to the upper memory packages 426 to 430 of the third memory module 400C through the upper data line DQ<20:39>, the upper strobe line DQS2 and the second control signal line CTRL2.

[0072] The third physical interface circuit 336 may transmit user data and an error correction code for the third storage module 400C, or transmit an error correction code for each of the first storage module 400A and the second storage module 400B different from the third storage module 400C, according to the setting signal M_SEL in Figure 5 . The setting signal M_SEL may be generated based on a request from the host device 20. For example, when the setting signal M_SEL is set to a logic low level, the third physical interface circuit 336 may operate in a normal mode, in which only the user data and the error correction code for the third storage module 400C are transmitted to / from the third storage module 400C through the lower data lines DQ<0:19> and the upper data lines DQ0<20:39>. On the other hand, when the setting signal M_SEL is set to a logic high level, the third physical interface circuit 336 may operate in an extended mode, in which the error correction code for the first storage module 400A is transmitted to / from the third storage module 400C through the lower data lines DQ<0:19>, and the error correction code for the second storage module 400B is transmitted to / from the third storage module 400C through the upper data lines DQ<20:39>.

[0073] In Figure 4 and Figure 5 , a case in which the lower memory packages 421 to 425 and the upper memory packages 426 to 430 are classified according to the arrangement has been described as an example, but embodiments of the present disclosure are not limited thereto. According to an embodiment, in addition to the arrangement, the memory packages in the third storage module 400C may be classified according to a shape, a stacking method, a memory type, etc. Further, in Figure 4 and Figure 5 , a case in which 5 memory packages in the third storage module 400C are assigned to the lower memory packages 421 to 425 and the remaining 5 memory packages are assigned to the upper memory packages 426 to 430 has been described as an example, but embodiments of the present disclosure are not limited thereto. According to an embodiment, each storage module may include 2n memory packages, where n is a positive integer, and each module controller may control m memory packages (where m is a positive integer) among the 2n storage packages to store an error correction code for the first storage module 400A, and control the remaining (i.e., 2n - m) memory packages to store an error correction code for the second storage module 400B. For example, m may be set to n.

[0074] Figure 6 is a diagram for describing input / output signals between the module control logic 320 and the memory interface logic 330 according to an embodiment of the present disclosure. Figure 4 ​

[0075] Reference Figure 6 , the first module controller 322 can generate a first internal chip select signal ICS1 and a first internal command / address signal IC / A#1 in response to a request from the host device 20.

[0076] During a write operation, the first module controller 322 can generate an error correction code based on data corresponding to a request from the host device 20 to output first write data WDATA1 including both the data and the error correction code to the first physical interface circuit 332. The first module controller 322 can selectively adjust the size (i.e., bit width or bandwidth) of the error correction code according to a setting signal M_SEL. The first module controller 322 can expand the size of the error correction code by 1 / 2 of the bits of the first write data WDATA1 according to the setting signal M_SEL. For example, when the setting signal M_SEL is set to a logic low level, the first module controller 322 can generate a 128-bit error correction code using 512-bit data. The first module controller 322 can provide 640-bit first write data WDATA1 including 512-bit data and 128-bit error correction code to the first physical interface circuit 332. On the other hand, when the setting signal M_SEL is set to a logic high level, the first module controller 322 can generate a 448-bit (i.e., 320 + 128) error correction code using 512-bit data. The first module controller 322 can provide 640-bit first write data WDATA1 including 512-bit data and 128-bit error correction code, and at the same time provide 320-bit first extended write data WDATA1_E including the extended 320-bit error correction code to the third physical interface circuit 336.

[0077] During a read operation, the first module controller 322 may receive first read data RDATA1 sent from the first physical interface circuit 332. The first module controller 322 may use an error correction code included in the first read data RDATA1 to correct an error included in the data, and output the error-corrected data to the host device 20. The first module controller 322 may selectively receive first extended read data RDATA1_E sent from the third physical interface circuit 336 in response to a set signal M_SEL, and extend the size of the error correction code by 1 / 2 of the number of bits of the first write data WDATA1. For example, when the set signal M_SEL is set to a logic low level, the first module controller 322 may use a 128-bit error correction code to correct an error in 512-bit data, and when the set signal M_SEL is set to a logic high level, the first module controller 322 may use a 448-bit (i.e., 320 + 128) error correction code that adds the first extended read data RDATA1_E to correct an error in 512-bit data.

[0078] The first physical interface circuit 332 may receive a first internal chip select signal ICS1 and a first internal command / address signal IC / A#1 from the first module controller 322, and send the first write data WDATA1 and the first read data RDATA1 to / receive the first write data WDATA1 and the first read data RDATA1 from the first module controller 322. The first physical interface circuit 332 may send a control signal including a chip select signal and a command / address signal to the first storage module 400A through a control signal line CTRL, and send data and a strobe signal to / receive data and a strobe signal from the first storage module 400A through data lines DQ<0:39> and a strobe line DQS, respectively.

[0079] The second module controller 324 may have substantially the same configuration as the first module controller 322. The second module controller 324 may generate a second internal chip select signal ICS2 and a second internal command / address signal IC / A#2 according to a request from the host device 20. The second module controller 324 may selectively adjust the size of the error correction code according to the setting signal M_SEL. During a write operation, the second module controller 324 may extend the size of the error correction code by 1 / 2 bit of the second write data WDATA2 according to the setting signal M_SEL. The second module controller 324 may provide 512-bit data and 128-bit error correction code as the second write data WDATA2 to the second physical interface circuit 334, and provide the extended 320-bit error correction code as the second extended write data WDATA2_E to the third physical interface circuit 336. During a read operation, the second module controller 324 may selectively receive the second extended read data RDATA2_E sent from the third physical interface circuit 336 according to the setting signal M_SEL to extend the size of the error correction code by 1 / 2 (i.e., 320 bits) of the bits of the second write data WDATA2.

[0080] The second physical interface circuit 334 may have substantially the same configuration as the first physical interface circuit 332. The second physical interface circuit 334 may receive the second internal chip select signal ICS2 and the second internal command / address signal IC / A#2 from the second module controller 324, and send the second write data WDATA2 and the second read data RDATA2 to / receive the second write data WDATA2 and the second read data RDATA2 from the second module controller 324. The second physical interface circuit 334 may send a control signal including a chip select signal and a command / address signal to the second storage module 400B through the control signal line CTRL, and send and receive data and a strobe signal to / from the second storage module 400B through the data lines DQ<0:39> and the strobe line DQS, respectively.

[0081] The third module controller 326 can generate a third internal chip select signal ICS3 and a third internal command / address signal IC / A#3 according to requests from the host device 20. During a write operation, the third module controller 326 can generate an error correction code based on data corresponding to the request from the host device 20 to output third write data WDATA3 including both the data and the error correction code to the third physical interface circuit 336. During a read operation, the third module controller 326 can use the error correction code included in the third read data RDATA3 sent from the third physical interface circuit 336 to correct the error included in the data and output the corrected data to the host device 20. When the setting signal M_SEL is set to a logic high level, the third module controller 326 can be deactivated.

[0082] When the setting signal M_SEL is set to a logic low level, the third physical interface circuit 336 can receive the third internal chip select signal ICS3 and the third internal command / address signal IC / A#3 from the third module controller 326, and send the third write data WDATA3 and the third read data RDATA3 to the third module controller 326 / receive the third write data WDATA3 and the third read data RDATA3 from the third module controller 326. When the setting signal M_SEL is set to a logic high level, the third physical interface circuit 336 can receive the first internal chip select signal ICS1 and the first internal command / address signal IC / A#1 from the first module controller 322, and send the first extended write data WDATA1_E and the first extended read data RDATA1_E to the first module controller 322 / receive the first extended write data WDATA1_E and the first extended read data RDATA1_E from the first module controller 322. In addition, when the setting signal M_SEL is set to a logic high level, the third physical interface circuit 336 can receive the second internal chip select signal ICS2 and the second internal command / address signal IC / A#2 from the second module controller 324, and send the second extended write data WDATA2_E and the second extended read data RDATA2_E to the second module controller 324 / receive the second extended write data WDATA2_E and the second extended read data RDATA2_E from the second module controller 324.

[0083] The first physical interface circuit 332 to the third physical interface circuit 336 can commonly receive an internal clock signal ICLK and provide it as a clock signal to each storage module. The first extended write data WDATA1_E and the first extended read data RDATA1_E can be defined as a first extended error correction code, while the second extended write data WDATA2_E and the second extended read data RDATA2_E can be defined as a second extended error correction code.

[0084] Figure 7A and Figure 7B is a circuit diagram of the third physical interface circuit 336 according to an embodiment of the present disclosure. Figure 6 of the third physical interface circuit 336.

[0085] Referring to Figure 7A and Figure 7B , the third physical interface circuit 336 may include a first transmitter 336_1 to a ninth transmitter 336_9, a first selection circuit 336_10 to an eighth selection circuit 336_17, a first synchronizer 336_18 to a fourth synchronizer 336_21, a down data transmission circuit 336_22, an up data transmission circuit 336_23, and a first receiver 336_24 to a fourth receiver 336_27.

[0086] The first transmitter 336_1 may receive an internal clock signal ICLK and transmit the received internal clock signal ICLK as differential clock signals CLK_t and CLK_c. According to an embodiment, in order to minimize skew, a delay line for variably delaying the internal clock signal ICLK by a predetermined time according to the result of a training operation may be provided in front of the first transmitter 336_1. The differential clock signals CLK_t and CLK_c may be transmitted to the third storage module 400C through separate clock lines (not shown).

[0087] The first selection circuit 336_10 may select one of a third internal chip select signal ICS3 and a first internal chip select signal ICS1 according to a setting signal M_SEL. For example, when the setting signal M_SEL is set to a logic high level, the first selection circuit 336_10 may select the first internal chip select signal ICS1. The first synchronizer 336_18 may receive the output signal of the first selection circuit 336_10 in synchronization with the edge (e.g., rising edge) of the internal clock signal ICLK. The first synchronizer 336_18 may receive the output signal of the first selection circuit 336_10 according to the internal clock signal ICLK. The second transmitter 336_2 may receive the output signal of the first synchronizer 336_18 and output its output signal as a down chip select signal CS_L. The first synchronizer 336_18 may be implemented with a D flip-flop. According to an embodiment, a delay line may be provided in front of the first synchronizer 336_18.

[0088] The second selection circuit 336_11 can select one of the third internal command / address signal IC / A#3 and the first internal command / address signal IC / A#1 according to the setting signal M_SEL. For example, when the setting signal M_SEL is set to a logic high level, the second selection circuit 336_11 can select the first internal command / address signal IC / A#1. The second synchronizer 336_19 can receive the output signal of the second selection circuit 336_11 in synchronization with the internal clock signal ICLK. The third transmitter 336_3 can receive the output signal of the second synchronizer 336_19 and output its output signal as the next command / address signal C / A#_L. According to an embodiment, a delay line can be provided in front of the second synchronizer 336_19. Although Figure 7A the case where the second selection circuit 336_11, the second synchronizer 336_19, and the third transmitter 336_3 are provided one by one is shown, they can be provided in a number corresponding to the number of bits of the next command / address signal C / A#_L.

[0089] The next chip select signal CS_L and the next command / address signal C / A#_L can be transmitted to the lower memory packages 421 to 425 through the first control signal line CTRL1.

[0090] The third selection circuit 336_12 can select one of the third internal chip select signal ICS3 and the second internal chip select signal ICS2 according to the setting signal M_SEL. For example, when the setting signal M_SEL is set to a logic high level, the third selection circuit 336_12 can select the second internal chip select signal ICS2. The third synchronizer 336_20 can receive the output signal of the third selection circuit 336_12 in synchronization with the internal clock signal ICLK. The fourth transmitter 336_4 can receive the output signal of the third synchronizer 336_20 and output its output signal as the upper chip select signal CS_H. According to an embodiment, a delay line can be provided in front of the third synchronizer 336_20.

[0091] The fourth selection circuit 336_13 can select one of the third internal command / address signal IC / A#3 and the second internal command / address signal IC / A#2 according to the setting signal M_SEL. For example, when the setting signal M_SEL is set to a logic high level, the fourth selection circuit 336_13 can select the second internal command / address signal IC / A#2. The fourth synchronizer 336_21 can receive the output signal of the fourth selection circuit 336_13 synchronously with the internal clock signal ICLK. The fifth transmitter 336_5 can receive the output signal of the fourth synchronizer 336_21 and output its output signal as the upper command / address signal C / A#_H. According to an embodiment, a delay line can be provided at the front end of the fourth synchronizer 336_21. Although Figure 7A it is shown that the fourth selection circuit 336_13, the fourth synchronizer 336_21, and the fifth transmitter 336_5 are provided one by one, they can be provided in a number corresponding to the number of bits of the upper command / address signal C / A#_H.

[0092] The upper chip select signal CS_H and the upper command / address signal C / A#_H can be transmitted to the upper memory packages 426 to 430 through the second control signal line CTRL2.

[0093] Referring to Figure 7B , the fifth selection circuit 336_14 can select one of the lower data of the third write data WDATA3 (hereinafter referred to as the third lower write data WDATA3_L) and the first extended write data WDDATA1_E according to the setting signal M_SEL. For example, when the setting signal M_SEL is set to a logic high level, the fifth selection circuit 336_14 can select the first extended write data WDATA1_E. The lower data transmission circuit 336_22 can serialize the output signal of the fifth selection circuit 336_14 to generate a lower write strobe signal WDQS_L based on the serialized data. The sixth transmitter 336_6 can receive the serialized data from the lower data transmission circuit 336_22 to output the lower data DATA_L, and the seventh transmitter 336_7 can transmit the lower write strobe signal WDQS_L generated by the lower data transmission circuit 336_22 as differential strobe signals DQS_t_L and DQS_c_L. The seventh transmitter 336_7 can generate the differential strobe signals DQS_t_L and DQS_c_L corresponding to the lower write strobe signal WDQS_L.

[0094] The first receiver 336_24 may receive lower data DATA_L provided from the lower memory packages 421 to 425 to output the lower data DATA_L to the lower data transmission circuit 336_22, while the second receiver 336_25 may receive differential strobe signals DQS_t_L and DQS_c_L provided from the lower memory packages 421 to 425 to generate a lower read strobe signal RDQS_L, and send the lower read strobe signal RDQS_L to the lower data transmission circuit 336_22. The second receiver 336_25 may compare the voltage levels of the differential strobe signals DQS_t_L and DQS_c_L to generate the lower read strobe signal RDQS_L. The lower data transmission circuit 336_22 may deserialize the lower data DATA_L transmitted from the first receiver 336_24 according to the lower read strobe signal RDQS_L. The sixth selection circuit 336_15 may select the deserialized lower data according to the setting signal M_SEL to output one of the lower data (hereinafter referred to as the third lower read data RDATA3_L) of the third read data RDATA3 and the first extended read data RDATAD1_E. For example, when the setting signal M_SEL is set to a logic high level, the sixth selection circuit 336_15 may output the deserialized lower data as the first extended read data RDATAD1_E.

[0095] The lower data transmission circuit 336_22 may include a serializer / deserializer (SERDES) and a strobe generator. According to an embodiment, the strobe generator may receive an internal clock signal ICLK to generate a lower write strobe signal WDQS_L. Although Figure 7B The case where the fifth selection circuit 336_14, the sixth selection circuit 336_15, the sixth transmitter 336_6, and the first receiver 336_24 are set one by one is shown, but they may be set in a number corresponding to the number of the lower data lines DQ<0:19> (for example, 20).

[0096] The lower data DATA_L may be received / sent to the lower memory packages 421 to 425 through the lower data lines DQ<0:19>, and the differential strobe signals DQS_t_L and DQS_c_L may be received / sent to the lower memory packages 421 to 425 through the lower strobe line DQS1.

[0097] The seventh selection circuit 336_16 can select one of the upper data of the third write data WDATA3 (hereinafter referred to as the third upper write data WDATA3_H) and the second extended write data WDATA2_E according to the setting signal M_SEL. When the setting signal M_SEL is set to a logic high level, the seventh selection circuit 336_16 can select the second extended write data WDATA2_E. The upper data transmission circuit 336_23 can serialize the output signal of the seventh selection circuit 336_16 to generate an upper write strobe signal WDQS_H based on the serialized data. The eighth transmitter 336_8 can receive the serialized data from the upper data transmission circuit 336_23 to output the upper data DATA_H, and the ninth transmitter 336_9 can transmit the upper write strobe signal WDQS_H generated by the upper data transmission circuit 336_23 as differential strobe signals DQS_t_H and DQS_c_H.

[0098] The third receiver 336_26 can receive the upper data DATA_H provided from the upper memory packages 426 to 430 to output the upper data DATA_H to the upper data transmission circuit 336_23, and the fourth receiver 336_27 can receive the differential strobe signals DQS_t_H and DQS_c_H provided from the upper memory packages 426 to 430 to generate an upper read strobe signal RDQS_H and transmit the upper read strobe signal RDQS_H to the upper data transmission circuit 336_23. The upper data transmission circuit 336_23 can deserialize the upper data DATA_H transmitted from the third receiver 336_26 according to the upper read strobe signal RDQS_H. The eighth selection circuit 336_17 can select the deserialized upper data according to the setting signal M_SEL and output it as one of the upper data of the third read data RDATA3 (hereinafter referred to as the third upper read data RDATA3_H) and the second extended read data RDATA2_E. For example, when the setting signal M_SEL is set to a logic high level, the eighth selection circuit 336_17 can output the deserialized upper data as the second extended read data RDATA2_E.

[0099] The upper data transmission circuit 336_23 can include a serializer / deserializer (SERDES) and a strobe generator. According to an embodiment, the strobe generator can receive an internal clock signal ICLK to generate an upper write strobe signal WDQS_H. Although Figure 7B the case where the seventh selection circuit 336_16, the eighth selection circuit 336_17, the eighth transmitter 336_8, and the third receiver 336_26 are set one by one is shown, they can be set in a number corresponding to the number of upper data lines DQ<20:39> (for example, 20).

[0100] The upper data DATA_H can be sent to / received from the upper memory packages 426 to 430 through the upper data lines DQ<20:39>, and the differential strobe signals DQS_t_H and DQS_c_H can be sent to / received from the upper memory packages 426 to 430 through the upper strobe line DQS2.

[0101] In the following, reference will be made to Figures 4 to 8B to describe the configuration of the memory system 10B according to the setting signal M_SEL.

[0102] Figure 8A and Figure 8B are diagrams for describing the configuration of the memory system 10B according to the setting signal M_SEL in accordance with an embodiment of the present disclosure.

[0103] Referring to Figure 8A , when the setting signal M_SEL is set to a logic low level, the third physical interface circuit 336 can receive the third internal chip select signal ICS3 provided by the third module controller 326 to generate the lower chip select signal CS_L and the upper chip select signal CS_H, and receive the third internal command / address signal IC / A#3 provided by the third module controller 326 to generate the lower command / address signal C / A#_L and the upper command / address signal C / A#_H (see Figure 7A ). The third physical interface circuit 336 can receive the third lower write data WDATA3_L provided by the third module controller 326 to generate the lower data DATA_L, and receive the third upper write data WDATA3_H provided by the third module controller 326 to generate the upper data DATA_H (see Figure 7B ). In addition, the third physical interface circuit 336 can receive the lower read strobe signal RDQS_L and the lower data DATA_L from the lower memory packages 421 to 425 to output the third lower read data RDATA3_L to the third module controller 326, and can receive the upper read strobe signal RDQS_H and the upper data DATA_H from the upper memory packages 426 to 430 to output the third upper read data RDATA3_H to the third module controller 326 (see Figure 7B ).

[0104] The lower chip select signal CS_L and the lower command / address signal C / A#_L can be sent to the lower memory packages 421 to 425 through the first control signal line CTRL1, while the upper chip select signal CS_H and the upper command / address signal C / A#_H can be sent to the upper memory packages 426 to 430 through the second control signal line CTRL2. The lower data DATA_L can be sent to the lower memory packages 421 to 425 / received from the lower memory packages 421 to 425 through the lower data lines DQ<0:19>, while the upper data DATA_H can be sent to the upper memory packages 426 to 430 / received from the upper memory packages 426 to 430 through the upper data lines DQ<20:39>. For reference, the differential strobe signals DQS_t_L and DQS_c_L together with the lower data DATA_L can be sent to the lower memory packages 421 to 425 / received from the lower memory packages 421 to 425 through the lower strobe line DQS1, while the differential strobe signals DQS_t_H and DQS_c_H together with the upper data DATA_H can be sent to the upper memory packages 426 to 430 / received from the upper memory packages 426 to 430 through the upper strobe line Q2S2.

[0105] Thus, as Figure 8A shown, when the setting signal M_SEL is at a logic low level, the third physical interface circuit 336 can send the user data and error correction code for the third memory module 400C to the third memory module 400C / receive the user data and error correction code from the third memory module 400C through the data lines DQ<0:39>. In this case, 8 of the 10 memory packages 421 to 430, i.e., 421 to 428, can be used to store the user data UD, and the remaining two memory packages 429 and 430 can be used to store the error correction code ECC. Additionally, Figure 8A shows a case where the memory packages 429 and 430 are used to store the error correction code ECC, but the embodiments of the present disclosure are not limited thereto, and the error correction code ECC can be stored in some of the 10 memory packages 421 to 430 (e.g., 425 and 430).

[0106] Referring to Figure 8B, when the setting signal M_SEL is set to a logic high level, the third physical interface circuit 336 can receive the first internal chip select signal ICS1 provided by the first module controller 322 to generate the lower chip select signal CS_L, and receive the second internal chip select signal ICS2 provided by the second module controller 324 to generate the upper chip select signal CS_H. The third physical interface circuit 336 can receive the first internal command / address signal IC / A#1 provided by the first module controller 322 to generate the lower command / address signal C / A#_L, and receive the second internal command / address signal IC / A#2 provided by the second module controller 324 to generate the upper command / address signal C / A#_H (see Figure 7A ). The third physical interface circuit 336 can receive the first extended write data WDATA1_E provided by the first module controller 322 to generate the lower data DATA_L, and receive the second extended write data WDATA2_E provided by the second module controller 324 to generate the upper data DATA_H (see Figure 7B ). In addition, the third physical interface circuit 336 can receive the lower read strobe signal RDQS_L and the lower data DATA_L from the lower memory packages 421 to 425 to output the first extended read data RDATA1_E to the first module controller 322, and receive the upper read strobe signal RDQS_H and the upper data DATA_H from the upper memory packages 426 to 430 to output the second extended read data RDATA2_E to the second module controller 324 (see Figure 7B ).

[0107] Therefore, as Figure 8B shown, when the setting signal M_SEL is at a logic high level, the third physical interface circuit 336 can send to / receive from the lower memory packages 421 to 425 the first extended error correction code (i.e., the first extended write data WDATA1_E and the first extended read data RDATA1_E) through the lower data lines DQ<0:19>, and send to / receive from the upper memory packages 426 to 430 the second extended error correction code (i.e., the second extended write data WDATA2_E and the second extended read data RDATA2_E) through the upper data lines DQ<20:39>. That is to say, the third physical interface circuit 336 can transmit the error correction codes for each of the first storage module 400A and the second storage module 400B that are different from the third storage module 400C.

[0108] As described above, when the setting signal M_SEL is set to a logic low level, the memory system 10B can operate in the normal mode to input / output 64 bytes of user data and 16 bytes of error correction code for each of the first to third memory modules. On the other hand, when the setting signal M_SEL is set to a logic high level, the memory system 10B can operate in the extended mode to input / output 40 bytes of error correction code in addition to inputting / outputting 64 bytes of user data and 16 bytes of error correction code for each of the first and second memory modules. That is, the memory system 10B can use 56 bytes (i.e., 16 + 40) of error correction code for each of the first and second memory modules by adding the 40-byte extended error correction code and the 16-byte error correction code. In this case, each of the first and second extended error correction codes can have a size of 40 bytes corresponding to half of the 64-byte user data and 16-byte error correction code. The memory system 10B can change the error correction capability in consideration of a case where an increase in memory capacity is required or a case where high-performance error correction capability is required. Therefore, it is possible to flexibly respond to the system environment by increasing the error correction capability only in the extended mode where high-performance error correction capability is required.

[0109] In the above embodiment, as an example, the case where the memory package storing user data and error correction code is provided in each memory module has been described, but the embodiments of the present disclosure are not limited thereto. In the normal mode, only user data can be stored in each memory module, and in the extended mode, the error correction code for other memory modules can be stored in one memory module.

[0110] Figure 9 is a diagram for describing a modified example of the memory system 10C according to an embodiment of the present disclosure.

[0111] Referring to Figure 9 , the memory system 10C may include a memory controller 500 and a memory device 600.

[0112] The memory device 600 may include a plurality of memory modules that communicate with the memory controller 500 independently through separate channels CH0 to CH2. For example, as Figure 9 shown, the memory device 600 may include first memory modules 601 to 608, second memory modules 609 to 616, and third memory modules 617 to 624 that communicate with the memory controller 500 through the first channel CH0 to the third channel CH2, respectively.

[0113] The memory controller 500 may include a host interface circuit (HIC) 510, module control logic 520, and memory interface logic 530.

[0114] The host interface circuit 510 can communicate with a host device ( Figure 1 20 in

[0115] The module control logic 520 can be coupled to the memory device 600 through the memory interface logic 530 and control the overall operation of the memory device 600. The module control logic 520 can include a first module controller (MC) 522 to a third module controller (MC) 526 for separately controlling the first memory module to the third memory modules 601 to 608, 609 to 616, and 617 to 624, respectively.

[0116] The memory interface logic 530 can communicate with the memory device 600 through the memory interface. The memory interface logic 530 can include a first physical interface circuit (PHY) 532 to a third physical interface circuit (PHY) 536, which connect the first to the third memory modules 601 to 608, 609 to 616, and 617 to 624 to the first module controller 522 to the third module controller 526 through independent channels, respectively.

[0117] Unlike Figure 4 the memory device 300 of Figure 9 each of the first to third memory modules 601 to 608, 609 to 616, and 617 to 624 can include 8 memory packages. The first physical interface circuit 532 to the third physical interface circuit 536 can send user data to / receive user data from the 8 memory packages through 32 data lines, respectively. When the burst length is set to 16, the 8 memory packages can input and output 64 bytes of data at a time.

[0118] In Figure 9Among them, the first physical interface circuit 532 can only transmit 64-byte user data for the first storage modules 601 to 608, while the second physical interface circuit 534 can only transmit 64-byte user data for the second storage modules 609 to 616. On the other hand, according to the setting signal M_SEL, the third physical interface circuit 536 can transmit 64-byte user data for the third storage modules 617 to 624, or transmit the first extended error correction code and the second extended error correction code for the first storage modules 601 to 608 and the second storage modules 609 to 616. In the normal mode where the setting signal M_SEL is at a logic low level, the third physical interface circuit 536 can transmit user data for the third storage modules 617 to 624 through the data line. In the extended mode where the setting signal M_SEL is at a logic high level, the third physical interface circuit 536 can send / receive the first extended error correction code to / from the lower memory packages 617 to 620 through the lower data line, and send / receive the second extended error correction code to / from the upper memory packages 621 to 624 through the upper data line.

[0119] Figure 10 FIG. is for describing another modified storage system 10D according to an embodiment of the present disclosure.

[0120] Referring to Figure 10 , the storage system 10D may include a memory controller 700 and a memory device 800.

[0121] The memory device 800 may include a plurality of sub-storage modules that communicate independently with the memory controller 700 through separate sub-channels SUB_CH. For example, as Figure 10 shown, the memory device 800 may include first to sixth sub-storage modules 801 to 810, 811 to 820, 821 to 830, 831 to 840, 841 to 850, and 851 to 860 that communicate with the memory controller 700 through the first to sixth sub-channels SUB_CH, respectively.

[0122] The memory controller 700 may include a host interface circuit 710, first to sixth sub-module controllers 721 to 726, and first to sixth physical interface circuits 731 to 736.

[0123] The first to sixth physical interface circuits 731 to 736 can connect the first to sixth sub-module controllers 721 to 726 with the first to sixth sub-storage modules 801 to 810, 811 to 820, 821 to 830, 831 to 840, 841 to 850, and 851 to 860, respectively. Each sub-storage module may correspond to a memory bank. InFigure 10 In this case, two memory banks (i.e., two sub-memory modules) form a memory module. That is to say, two sub-channels SUB_CH can form a channel CH.

[0124] Figure 10 The first to fourth sub-module controllers 721 to 724 of Figure 4 may have substantially the same configuration as the first module controller 322 and the second module controller 324 of Figure 4 , and the first to fourth physical interface circuits 731 to 734 may have substantially the same configuration as the first physical interface circuit 332 and the second physical interface circuit 334 of Figure 10 The fifth sub-module controller 725 and the sixth sub-module controller 726 of Figure 4 may have substantially the same configuration as the third module controller 326 of Figure 4 , and the fifth physical interface circuit 735 and the sixth physical interface circuit 736 may have substantially the same configuration as the third physical interface circuit 336 of

[0125] When the setting signal M_SEL is set to a logic low level, the memory system 10D can operate in the normal mode to input / output 64 bytes of user data and 16 bytes of error correction code to / from each of the first to sixth sub-memory modules 801 to 810, 811 to 820, 821 to 830, 831 to 840, 841 to 850, and 851 to 860. On the other hand, when the setting signal M_SEL is set to a logic high level, the memory system 10D can operate in the extended mode to input / output 64 bytes of user data and 16 bytes of error correction code to / from each of the first to fourth sub-memory modules 801 to 810, 811 to 820, 821 to 830, and 831 to 840, input / output 40 bytes of error correction code for the first sub-memory module 801 to 810 and 40 bytes of error correction code for the second sub-memory module 811 to 820 to / from the fifth sub-memory module 841 to 850, and input / output 40 bytes of error correction code for the third sub-memory module 821 to 830 and 40 bytes of error correction code for the fourth sub-memory module 841 to 850 to / from the sixth sub-memory module 851 to 860.

[0126] Various embodiments of the present disclosure have been described in the accompanying drawings and the specification. Although specific terms are used herein, these terms are only used to describe the embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above embodiments, and many variations are possible within the spirit and scope of the present disclosure. Those skilled in the art should be aware that, in addition to the embodiments disclosed herein, various modifications can be made based on the technical scope of the present disclosure. These embodiments can be combined to form additional embodiments.

[0127] It should be noted that although the technical spirit of the present disclosure has been described in connection with the embodiments of the present disclosure, this is only for descriptive purposes and should not be construed as a limitation. Those of ordinary skill in the art should understand that various changes can be made without departing from the technical spirit of the present disclosure and the appended claims.

[0128] For example, for the logic gates and transistors provided as examples in the above embodiments, different positions and types can be implemented according to the polarity of the input signal.

Claims

1. A storage system, comprising: Multiple storage modules; A plurality of module controllers, which respectively control the plurality of storage modules; as well as A plurality of interface circuits connect the plurality of storage modules with the plurality of module controllers, wherein, according to a setting signal, at least one target interface circuit connects a target module controller among the plurality of module controllers with a target storage module among the plurality of storage modules, or connects another module controller different from the target module controller with the target storage module.

2. The storage system according to claim 1, in, the target interface circuit: in response to the setting signal having a first logic level, transmitting user data and an error correction code for the target memory module between the target module controller and the target memory module, and The target interface circuit transmits the extended error correction code for other memory modules different from the target memory module between the other module controller and the target memory module in response to the setting signal having the second logic level.

3. The storage system according to claim 2, wherein: Each of the other module controllers generates user data and an error correction code for a corresponding memory module, generates the extended error correction code by increasing a size of the error correction code according to the setting signal, and outputs the extended error correction code to the target interface circuit.

4. The storage system according to claim 2, in, Each of the plurality of memory modules includes 2n memory packages, where n is a positive integer, and Among them, according to the setting signal, the target interface circuit transmits the extended error correction code for the first storage module in the other storage modules to the n memory packages of the target storage module, and transmits the extended error correction code for the second storage module in the other storage modules to the remaining n memory packages of the target storage module.

5. The storage system according to claim 1, in, Each of the plurality of memory modules includes 2n memory packages, where n is a positive integer, and Wherein, the target interface circuit is coupled to n memory packages of the target storage module through a first data line for transmitting upper data and a first select line for transmitting an upper select signal, and is coupled to the remaining n memory packages of the target storage module through a second data line for transmitting lower data and a second select line for transmitting a lower select signal.

6. The storage system according to claim 5, wherein: Each of the plurality of interface circuits except the target interface circuit is coupled to 2n memory packages of a corresponding memory module through a data line transmitting upper data and lower data and a strobe line transmitting a strobe signal.

7. The storage system according to claim 1, in, Each of the plurality of memory modules comprises m memory packages, and Among them, k memory packages are configured to store user data, and the remaining (mk) memory packages are configured to store error correction codes, where m is a positive integer of 2 or more, and k is a positive integer less than m.

8. The storage system according to claim 1, wherein: Each of the plurality of memory modules comprises m memory packages, Wherein m is a positive integer of 2 or more, and the m memory packages are configured to store user data.

9. The storage system according to claim 1, wherein: The target interface circuit comprises: A first receiver, which receives and reads data from the target storage module; a first selection circuit, which selects data from the first module controller or the target module controller according to the setting signal; a first serializer / deserializer that serializes the output signal of the first selection circuit and deserializes the lower read data; a first transmitter that transmits the serialized data from the first serializer / deserializer as down write data to the target memory module; a second selection circuit, which selects the deserialized data from the first serializer / deserializer to output to the first module controller or the target module controller according to the setting signal; A second receiver, which receives read data from the target storage module; a third selection circuit, which selects data from the second module controller or the target module controller according to the setting signal; a second serializer / deserializer, which serializes the output signal of the third selection circuit and deserializes the upper read data; a second transmitter that transmits the serialized data from the second serializer / deserializer as write-on data to the target memory module; and A fourth selection circuit selects the deserialized data from the second serializer / deserializer to be output to the second module controller or the target module controller.

10. The storage system according to claim 9, wherein: The target interface circuit also includes: a fifth selection circuit, which selects a control signal from the first module controller or the target module controller according to the setting signal; a third transmitter, which transmits the output signal of the fifth selection circuit as a down control signal to the target memory module; a sixth selection circuit for selecting a control signal from the second module controller or the target module controller according to the setting signal; and A fourth transmitter transmits the output signal of the sixth selection circuit as an upper control signal to the target memory module.

11. The storage system according to claim 1, further comprising: A host interface circuit that communicates with a host using a computing fast link interface.

12. The storage system according to claim 1, wherein: The storage system has a form factor of an add-in card, or enterprise and data center SSD form factor.

13. A storage system comprising: A first storage module to a third storage module; A first module controller to a third module controller, which respectively generate user data and error correction codes for the first storage module to the third storage module; as well as The first interface circuit to the third interface circuit respectively send the user data and the error correction code to the first storage module to the third storage module through independent channels and receive the user data and the error correction code from the first storage module to the third storage module, wherein the first module controller and the second module controller respectively increase the size of the error correction code according to the setting signal to generate a first extended error correction code and a second extended error correction code, and The third interface circuit sends the first extended error correction code and the second extended error correction code to the third storage module / receives the first extended error correction code and the second extended error correction code from the third storage module according to the setting signal.

14. The storage system according to claim 13, wherein: A size of each of the first extended error correction code and the second extended error correction code corresponds to a half of the number of bits of the user data and the error correction code.

15. The storage system according to claim 13, in, In response to the setting signal having a first logic level, the first to third interface circuits send x bits of user data and y bits of error correction code to the first to third storage modules, and receive x bits of user data and y bits of error correction code from the first to third storage modules, respectively; and Wherein, in response to the setting signal with a second logic level, the first interface circuit and the second interface circuit send x bits of user data and y bits of error correction code to the first storage module and the second storage module respectively and receive x bits of user data and y bits of error correction code from the first storage module and the second storage module, and the third interface circuit sends the first extended error correction code and the second extended error correction code to the third storage module and receives the first extended error correction code and the second extended error correction code from the third storage module, and the first extended error correction code and the second extended error correction code each have a size of (x+y) / 2 bits.

16. The storage system according to claim 13, in, Each of the first to third memory modules includes 2n memory packages, where n is a positive integer, and Wherein, according to the setting signal, the third interface circuit sends the first extended error correction code to the n memory packages of the third storage module and receives the first extended error correction code from the n memory packages of the third storage module, and sends the second extended error correction code to the remaining n memory packages of the third storage module and receives the second extended error correction code from the remaining n memory packages of the third storage module.

17. The storage system according to claim 13, wherein: The setting signal is generated based on a request from the host.

18. A memory controller comprising: A first module controller to a third module controller, which respectively generate user data and error correction codes for the first storage module to the third storage module; as well as The first interface circuit to the third interface circuit respectively send the user data and the error correction code to the first storage module to the third storage module through independent channels and receive the user data and the error correction code from the first storage module to the third storage module, wherein the first module controller and the second module controller respectively increase the size of the error correction code according to the setting signal to generate a first extended error correction code and a second extended error correction code, and The third interface circuit sends the first extended error correction code and the second extended error correction code to the third storage module according to the setting signal, and receives the first extended error correction code and the second extended error correction code from the third storage module.

19. The memory controller according to claim 18, wherein: A size of each of the first extended error correction code and the second extended error correction code corresponds to a half of the number of bits of the user data and the error correction code.

20. The memory controller according to claim 18, in, In response to the setting signal having a first logic level, the first interface circuit to the third interface circuit respectively transmit x bits of user data and y bits of error correction code to the first storage module to the third storage module and receive x bits of user data and y bits of error correction code from the first storage module to the third storage module, and Wherein, in response to the setting signal with a second logic level, the first interface circuit and the second interface circuit send x bits of user data and y bits of error correction code to the first storage module and the second storage module respectively and receive x bits of user data and y bits of error correction code from the first storage module and the second storage module, and the third interface circuit sends the first extended error correction code and the second extended error correction code to the third storage module and receives the first extended error correction code and the second extended error correction code from the third storage module, and the first extended error correction code and the second extended error correction code each have a size of (x+y) / 2 bits.

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