Manufacturing method of epitaxial layer of super junction power device

Abstract

The invention relates to a manufacturing method of an epitaxial layer of a super junction power device. The method comprises the following steps: providing a first conductive type substrate with high doping concentration, and growing a first conductive type semiconductor with low doping concentration on one side of the first conductive type substrate to form a first conductive type epitaxial layer; growing a second conductive type semiconductor to form a second conductive type epitaxial layer; forming a barrier layer on the front surface of the wafer, then selectively etching the barrier layer, then etching and penetrating through the second conductive type epitaxial layer to form a plurality of trapezoidal grooves, and finally removing the barrier layer to obtain a second conductive type column; and growing a first conductive type semiconductor on the front surface of the wafer, filling the trapezoidal groove, and forming a first conductive type column of the super junction power device by the first conductive type semiconductor in the trapezoidal groove. The width of the P-type column is not limited by filling difficulty any more, the method is compatible with an existing process, and the manufacturing method is simple.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly to a method for manufacturing an epitaxial layer of a superjunction power device. Background Art

[0002] A superjunction power MOSFET device is a power device in which N-columns and P-columns are arranged at intervals to achieve charge balance during voltage withstand. Its on-resistance has great advantages compared with traditional power devices. With the development of superjunction power MOSFET devices, in order to pursue lower on-resistance, the width of its cell (the total width of one N-column and one P-column) is also developing in the direction of getting smaller and smaller.

[0003] Currently, the international advanced manufacturer Infineon has compressed the cell width of the superjunction power MOSFET device to 4.5 micrometers through multiple epitaxial manufacturing processes. Domestic manufacturers adopting the trench filling scheme have encountered the dilemma that the cell width cannot be further compressed because they directly etch trenches on the N-type epitaxial layer and then grow P-type semiconductors to fill the trenches to form P-type columns. As Figure 9 shown, it is a schematic cross-sectional structure diagram of an epitaxial layer of a superjunction power device manufactured by the existing trench process. Under the existing trench process, in order to have sufficient electron conduction paths to reduce the on-resistance, the width of the top of the P-type column 9 is often smaller than the width of the top of the N-type column 8, that is, the P-type column 9 is narrower, and due to the etching angle problem, the bottom of the P-type column 9 will become very pointed, resulting in great difficulty in trench filling and inability to mass-produce commercial products.

[0004] In order to solve the above process problems, a new manufacturing process is needed to solve the trench filling problem. Summary of the Invention

[0005] Therefore, the present invention provides a method for manufacturing an epitaxial layer of a superjunction power device, so that the width of the P-type column is no longer restricted by the filling difficulty, is compatible with the existing process, and the manufacturing method is simple.

[0006] To solve the above technical problems, the present invention provides a method for manufacturing an epitaxial layer of a superjunction power device, including the following steps: Step 1: Provide a first-conductive-type substrate with a high doping concentration, and grow a first-conductive-type semiconductor with a low doping concentration on one side of the first-conductive-type substrate to form a first-conductive-type epitaxial layer. The side of the first-conductive-type substrate away from the first-conductive-type epitaxial layer is the back surface of the wafer, and the side of the first-conductive-type epitaxial layer away from the first-conductive-type substrate is the first plane; Step 2: Grow a second-conductive-type semiconductor on the first plane to form a second-conductive-type epitaxial layer. The side of the second-conductive-type epitaxial layer away from the first-conductive-type epitaxial layer is the front surface of the wafer; Step 3: Form a barrier layer on the front side of the wafer, then selectively etch the barrier layer, then etch and penetrate the second-conductivity-type epitaxial layer to form a plurality of trapezoidal trenches, and finally remove the barrier layer. The second-conductivity-type epitaxial layer between adjacent trapezoidal trenches becomes the second-conductivity-type columns of the superjunction power device; Step 4: Grow a first-conductivity-type semiconductor on the front side of the wafer and fill the trapezoidal trenches. The first-conductivity-type semiconductor in the trapezoidal trenches forms the first-conductivity-type columns of the superjunction power device, and then grind the front side of the wafer to remove the first-conductivity-type semiconductor on the front side of the wafer.

[0007] In an embodiment of the present invention, the first conductivity type is N type and the second conductivity type is P type; or, the first conductivity type is P type and the second conductivity type is N type.

[0008] In an embodiment of the present invention, the first-conductivity-type columns have a top-wide and bottom-narrow morphology, and the second-conductivity-type columns have a top-narrow and bottom-wide morphology.

[0009] The present invention provides a method for manufacturing an epitaxial layer of a superjunction power device, including the following steps: Step 1: Provide a first-conductivity-type substrate with a high doping concentration; Step 2: Grow a second-conductivity-type semiconductor on one side of the first-conductivity-type substrate to form a second-conductivity-type epitaxial layer. The side of the second-conductivity-type epitaxial layer away from the first-conductivity-type substrate is the front side of the wafer; Step 3: Form a barrier layer on the front side of the wafer, then selectively etch the barrier layer, then etch and penetrate the second-conductivity-type epitaxial layer to form a plurality of trapezoidal trenches, and finally remove the barrier layer. The second-conductivity-type epitaxial layer between adjacent trapezoidal trenches becomes the second-conductivity-type columns of the superjunction power device; Step 4: Grow a first-conductivity-type semiconductor on the front side of the wafer and fill the trapezoidal trenches. The first-conductivity-type semiconductor in the trapezoidal trenches forms the first-conductivity-type columns of the superjunction power device, and then grind the front side of the wafer to remove the first-conductivity-type semiconductor on the front side of the wafer.

[0010] In an embodiment of the present invention, the first conductivity type is N type and the second conductivity type is P type; or, the first conductivity type is P type and the second conductivity type is N type.

[0011] In an embodiment of the present invention, the first-conductivity-type columns have a top-wide and bottom-narrow morphology, and the second-conductivity-type columns have a top-narrow and bottom-wide morphology.

[0012] The above technical solution of the present invention has the following advantages compared with the prior art: The manufacturing method of the epitaxial layer of a superjunction power device according to the present invention etches the P-type epitaxial layer and then grows an N-type semiconductor to fill the trench to form an N-type column, replacing the prior art process of etching the N-type epitaxial layer and then growing a P-type semiconductor to fill the trench to form a P-type column. Since the width of the trench etched in the present invention can be wider, the difficulty of forming the N-type column in the present invention is lower, and the width of the P-type column is only determined by the distance between adjacent trenches. In theory, the width of the P-type column can be made narrower than the prior art process. The present invention can be applied to superjunction power devices with an ultra-small cell width. The width of the P-type column is no longer limited by filling difficulties, and the process of the present invention is compatible with the prior art process, and the manufacturing method is simple. Description of the Drawings

[0013] In order to make the content of the present invention easier to be clearly understood, the present invention will be further described in detail below according to the specific embodiments of the present invention and in conjunction with the drawings.

[0014] Figure 1 It is a schematic cross-sectional structure diagram of forming a column of the first conductivity type in Step 4 of Embodiment 1 of the present invention.

[0015] Figure 2 It is a schematic cross-sectional structure diagram of forming an epitaxial layer of the first conductivity type in Step 1 of Embodiment 1 of the present invention.

[0016] Figure 3 It is a schematic cross-sectional structure diagram of forming an epitaxial layer of the second conductivity type in Step 2 of Embodiment 1 of the present invention.

[0017] Figure 4 It is a schematic cross-sectional structure diagram of forming a trapezoidal trench in Step 3 of Embodiment 1 of the present invention.

[0018] Figure 5 It is a schematic cross-sectional structure diagram of the first conductivity type substrate provided in Step 1 of Embodiment 2 of the present invention.

[0019] Figure 6 It is a schematic cross-sectional structure diagram of forming an epitaxial layer of the second conductivity type in Step 2 of Embodiment 2 of the present invention.

[0020] Figure 7 It is a schematic cross-sectional structure diagram of forming a trapezoidal trench in Step 3 of Embodiment 2 of the present invention.

[0021] Figure 8 It is a schematic cross-sectional structure diagram of forming a column of the first conductivity type in Step 4 of Embodiment 2 of the present invention.

[0022] Figure 9 It is a schematic cross-sectional structure diagram of the epitaxial layer of a superjunction power device manufactured by the prior art process. Detailed Description of the Invention

[0023] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, so that those skilled in the art can better understand the present invention and be able to implement it, but the embodiments given are not intended to limit the present invention.

[0024] In the present invention, when directions (up, down, left, right, front, and back) are described, it is only for the convenience of describing the technical solution of the present invention, rather than indicating or implying that the technical features referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention.

[0025] In the present invention, the meaning of "several" is one or more, the meaning of "multiple" is two or more, and "greater than", "less than", "exceeding", etc. are understood not to include the present number; "above", "below", "within", etc. are understood to include the present number. In the description of the present invention, if "first" and "second" are described, they are only used to distinguish technical features and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the technical features indicated or the sequence relationship of the technical features indicated.

[0026] Embodiment 1 This embodiment provides a manufacturing method for an epitaxial layer of a superjunction power device, including the following steps: Step 1: As Figure 2 shown, provide an N-type substrate 1 with a high doping concentration, grow an N-type semiconductor with a low doping concentration on one side of the N-type substrate 1 to form an N-type epitaxial layer 2. The side of the N-type substrate 1 away from the N-type epitaxial layer 2 is the back surface of the wafer, and the side of the N-type epitaxial layer 2 away from the N-type substrate 1 is the first plane; Step 2: As Figure 3 shown, grow a P-type semiconductor on the first plane to form a P-type epitaxial layer 3. The side of the P-type epitaxial layer 3 away from the N-type epitaxial layer 2 is the front surface of the wafer; Step 3: As Figure 4 shown, form a barrier layer on the front surface of the wafer, then selectively etch the barrier layer, and then etch and penetrate the P-type epitaxial layer 3 to form a plurality of trapezoidal trenches 5. Finally, remove the barrier layer. The P-type epitaxial layer between adjacent trapezoidal trenches 5 becomes the P-type columns 4 of the superjunction power device. In the present invention, the P-type columns have a shape that is narrow at the top and wide at the bottom, which is significantly different from the existing process; Step 4: As Figure 1 shown, grow an N-type semiconductor on the front surface of the wafer and fill the trapezoidal trenches 5. The N-type semiconductor in the trapezoidal trenches 5 constitutes the N-type columns 6 of the superjunction power device. Then, grind the front surface of the wafer to remove the N-type semiconductor on the front surface of the wafer. In the present invention, the N-type columns have a shape that is wide at the top and narrow at the bottom, which is significantly different from the existing process.

[0027] Example 2 In Example 2, the N-type epitaxial layer 2 that serves as a transition is removed compared to Example 1. Therefore, the on-resistance of Example 2 can be made lower, and it includes the following steps: Step 1: As shown in Figure 5 , provide an N-type substrate 1 with a high doping concentration; Step 2: As shown in Figure 6 , grow a P-type semiconductor on one side of the N-type substrate 1 to form a P-type epitaxial layer 3. The side of the P-type epitaxial layer 3 away from the N-type substrate 1 is the front side of the wafer; Step 3: As shown in Figure 7 , form a barrier layer on the front side of the wafer, then selectively etch the barrier layer, then etch and penetrate the P-type epitaxial layer 3 to form a plurality of trapezoidal trenches 5, and finally remove the barrier layer. The P-type epitaxial layer between adjacent trapezoidal trenches 5 becomes the P-type column 4 of the superjunction power device; Step 4: As shown in Figure 8 , grow an N-type semiconductor on the front side of the wafer and fill the trapezoidal trenches. The N-type semiconductor in the trapezoidal trenches constitutes the N-type column 6 of the superjunction power device, and then grind the front side of the wafer to remove the N-type semiconductor on the front side of the wafer.

[0028] Currently, in the existing process, in order to have sufficient electron conduction paths to reduce the on-resistance, the N-type columns are wider than the P-type columns. In the present invention, by etching the P-type epitaxial layer and then growing an N-type semiconductor to fill the trenches to form N-type columns, it replaces the existing process of etching the N-type epitaxial layer and then growing a P-type semiconductor to fill the trenches to form P-type columns. Since the width of the trenches etched in the present invention can be wider, the difficulty of forming N-type columns in the present invention is lower, and the width of the P-type columns is only determined by the distance between adjacent trenches. Theoretically, the width of the P-type columns can be made narrower than the existing process.

[0029] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the examples, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention, and they should all be covered within the scope of the claims of the present invention.

Claims

1. A method for manufacturing an epitaxial layer of a super junction power device, characterized in that: The steps include: Step 1: providing a first conductive type substrate with a high doping concentration, growing a first conductive type semiconductor with a low doping concentration on one side of the first conductive type substrate to form a first conductive type epitaxial layer, wherein a side of the first conductive type substrate away from the first conductive type epitaxial layer is a back side of the wafer, and a side of the first conductive type epitaxial layer away from the first conductive type substrate is a first plane; Step 2: growing a second conductive type semiconductor on the first plane to form a second conductive type epitaxial layer, wherein a side of the second conductive type epitaxial layer away from the first conductive type epitaxial layer is the front side of the wafer; Step 3: forming a barrier layer on the front side of the wafer, then selectively etching the barrier layer, then etching and penetrating the second conductive type epitaxial layer to form a plurality of trapezoidal grooves, and finally removing the barrier layer, so that the second conductive type epitaxial layer between adjacent trapezoidal grooves becomes the second conductive type column of the super junction power device; Step 4: Grow a first conductive type semiconductor on the front side of the wafer and fill the trapezoidal groove. The first conductive type semiconductor in the trapezoidal groove constitutes a first conductive type column of the super junction power device. Then grind the front side of the wafer to remove the first conductive type semiconductor on the front side of the wafer.

2. The method for manufacturing an epitaxial layer of a super junction power device according to claim 1, characterized in that: The first conductivity type is N type, and the second conductivity type is P type; or, the first conductivity type is P type, and the second conductivity type is N type.

3. The method for manufacturing an epitaxial layer of a super junction power device according to claim 1, characterized in that: The first conductive type column has a shape that is wide at the top and narrow at the bottom, and the second conductive type column has a shape that is narrow at the top and wide at the bottom.

4. A method for manufacturing an epitaxial layer of a super junction power device, characterized in that: The steps include: Step 1: providing a first conductive type substrate with a high doping concentration; Step 2: growing a second conductive type semiconductor on one side of the first conductive type substrate to form a second conductive type epitaxial layer, wherein a side of the second conductive type epitaxial layer away from the first conductive type substrate is the front side of the wafer; Step 3: forming a barrier layer on the front side of the wafer, then selectively etching the barrier layer, then etching and penetrating the second conductive type epitaxial layer to form a plurality of trapezoidal grooves, and finally removing the barrier layer, so that the second conductive type epitaxial layer between adjacent trapezoidal grooves becomes the second conductive type column of the super junction power device; Step 4: Grow a first conductive type semiconductor on the front side of the wafer and fill the trapezoidal groove. The first conductive type semiconductor in the trapezoidal groove constitutes a first conductive type column of the super junction power device. Then grind the front side of the wafer to remove the first conductive type semiconductor on the front side of the wafer.

5. The method for manufacturing an epitaxial layer of a super junction power device according to claim 4, characterized in that: The first conductivity type is N type, and the second conductivity type is P type; or, the first conductivity type is P type, and the second conductivity type is N type.

6. The method for manufacturing an epitaxial layer of a super junction power device according to claim 4, characterized in that: The first conductive type column has a shape that is wide at the top and narrow at the bottom, and the second conductive type column has a shape that is narrow at the top and wide at the bottom.

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