SiC epitaxial wafer and preparation method thereof

Abstract

The present disclosure provides a SiC epitaxial wafer and a preparation method thereof, which relates to the field of semiconductor chip technology and aims to reduce the defect density of the SiC epitaxial wafer. The SiC epitaxial wafer comprises: a SiC substrate and an epitaxial layer provided on one side of the SiC substrate. The epitaxial layer comprises: a C-plane and a Si-plane arranged opposite to each other, with either the C-plane or the Si-plane being close to the SiC substrate. The thickness of the epitaxial layer ranges from 50 μm to 500 μm, wherein the defect density of the epitaxial layer ranges from 0.02 / cm 2 ~1 / cm 2 .

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a SiC epitaxial wafer and a preparation method thereof. Background Art

[0002] The withstand voltage of a silicon carbide device is proportional to the thickness of the epitaxial layer on the silicon carbide substrate. For high-voltage silicon carbide devices with withstand voltage specifications ranging from several thousand volts to tens of kilovolts, the required thickness of the SiC epitaxial wafer is between tens and hundreds of microns. A large number of defects (such as triangle defects, carrot defects, large pits, stacking faults, basal plane dislocations, and through-hole defects) can cause localized high electric fields to accumulate on the SiC epitaxial wafer, resulting in lower breakdown voltage, increased leakage current, and reduced thermal stability of the silicon carbide device, thereby reducing the overall reliability and performance of the silicon carbide device. Therefore, low-defect-density SiC epitaxial wafers are key to high-voltage silicon carbide devices. Summary of the Invention

[0003] Embodiments of the present disclosure provide a SiC epitaxial wafer and a method for preparing the same, aiming to reduce the defect density of the SiC epitaxial wafer.

[0004] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0005] In one aspect, a SiC epitaxial wafer is provided. The SiC epitaxial wafer comprises a SiC substrate and an epitaxial layer disposed on one side of the SiC substrate. The epitaxial layer comprises a C-face and a Si-face disposed opposite each other. Either the C-face or the Si-face is adjacent to the SiC substrate. The epitaxial layer has a thickness ranging from 50 μm to 500 μm.

[0006] Among them, the defect density of the epitaxial layer is in the range of 0.02 / cm 2 ~1 / cm 2 .

[0007] The epitaxial layer of the SiC epitaxial wafer provided in the above-mentioned embodiments of the present disclosure has a thickness ranging from 50μm to 500μm, allowing the SiC epitaxial wafer to withstand high electric field strength, thereby reducing the risk of breakdown caused by local electric field concentration, and making the silicon carbide device fabricated from the SiC epitaxial wafer have a higher breakdown voltage. At the same time, the epitaxial layer has two crystal plane structures: C-plane and Si-plane. The choice of SiC epitaxial wafer with Si-plane epitaxy or SiC epitaxial wafer with C-plane epitaxy affects the manufacturing process and performance of the silicon carbide device, making the SiC epitaxial wafer suitable for different application scenarios. Among them, SiC epitaxial wafers with the C-plane away from the SiC substrate are used in silicon carbide devices, which gives the silicon carbide device performance advantages. For example, SiC epitaxial wafers with the C-plane away from the SiC substrate are used in MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), which can improve the MOSFET channel mobility.

[0008] Moreover, the defect density of the epitaxial layer is in the range of 0.02 / cm 2 ~1 / cm 2 , indicating that SiC epitaxial wafers have fewer defects. Fewer defects (such as triangle defects, carrot defects, large pits, stacking faults, basal plane dislocations, and through defects) can reduce the local high electric field concentration of silicon carbide devices, increase the breakdown voltage, reduce leakage current, and improve the thermal stability of silicon carbide devices, ensuring the quality of SiC epitaxial wafers, thereby improving the overall reliability and performance of silicon carbide devices.

[0009] In some embodiments, the material of the epitaxial layer includes nitrogen atoms. In the epitaxial layer, the doping concentration of nitrogen atoms ranges from 1×10 14 cm -3 ~1×10 17 cm -3 .

[0010] In some embodiments, the surface roughness of the epitaxial layer is in the range of 0.1 nm to 1 nm.

[0011] In some embodiments, the epitaxial layer has a thickness ranging from 100 μm to 200 μm.

[0012] In another aspect, a method for preparing a SiC epitaxial wafer is provided. The method for preparing the SiC epitaxial wafer comprises:

[0013] The first epitaxial growth is to form an epitaxial sublayer on one side of the first SiC substrate.

[0014] The first bonding step is to bond the second SiC substrate to a side of the epitaxial sublayer away from the first SiC substrate.

[0015] In the first peeling step, the first SiC substrate is peeled off.

[0016] In the first cycle, the first epitaxy is repeated to obtain a second epitaxial sublayer connected to the first SiC substrate.

[0017] The second bonding step involves bonding the second epitaxial sublayer connected to the first SiC substrate to the epitaxial sublayer connected to the second SiC substrate to obtain a first bonded epitaxial wafer.

[0018] The second peeling step is to peel off one of the second SiC substrate and the first SiC substrate in the first bonded epitaxial wafer to obtain an initial SiC epitaxial wafer.

[0019] Heat treatment or laser treatment: Under inert gas conditions, heat treatment or laser treatment is used to recrystallize the initial SiC epitaxial wafer to obtain a SiC epitaxial wafer.

[0020] It can be understood that the method for preparing SiC epitaxial wafers provided by the above-mentioned embodiments of the present disclosure bonds multiple single-layer epitaxial sublayers together, and the defect density and distribution of the SiC epitaxial wafer body obtained by bonding can be obtained from the defect density and distribution of the single-layer epitaxial sublayer, and the defect distribution of the epitaxial sublayers of different single-layers is different, so that the SiC epitaxial wafer prepared by the present disclosure has fewer through-defects. Through heat treatment or laser treatment, the bonding interface of adjacent epitaxial sublayers can be recrystallized to eliminate interface defects, thereby obtaining a SiC epitaxial wafer with a smooth surface and low defect density, so as to solve the problem of rough surface and more defects of SiC epitaxial wafers obtained by directly growing epitaxial layers on SiC substrates, thereby improving the reliability of silicon carbide devices. Moreover, the doping concentration uniformity of the single-layer epitaxial sublayer before bonding of the present disclosure is better, that is, the doping concentration uniformity of each epitaxial sublayer in the multiple single-layer epitaxial sublayers is better, so that the doping concentration uniformity of the epitaxial layer obtained after bonding is equivalent to the doping concentration uniformity of the single-layer epitaxial sublayer, and an epitaxial layer with better doping concentration uniformity is obtained, which is better than the doping uniformity of the directly grown epitaxial layer.

[0021] In some embodiments, in the second debonding, the second SiC substrate in the first bonded epitaxial wafer is debonded; and before the heat treatment or the laser treatment, the process further includes:

[0022] In the second cycle, the first epitaxy, the first bonding and the first peeling are repeated to obtain a second epitaxial sublayer connected to the second SiC substrate.

[0023] The third bonding step is to bond the second epitaxial sublayer connected to the second SiC substrate to the epitaxial sublayer in the initial SiC epitaxial wafer that is away from the first SiC substrate to obtain a second bonded epitaxial wafer.

[0024] The third peeling step is to peel off the second SiC substrate in the second bonded epitaxial wafer to obtain another initial SiC epitaxial wafer.

[0025] In some embodiments, before the heat treatment or laser treatment, the method further comprises:

[0026] The second cycle, the third bonding, and the third peeling are repeated n times, where n ranges from 1 to 20.

[0027] In some embodiments, in the second stripping process, the first SiC substrate in the first bonded epitaxial wafer is stripped; and before the heat treatment or laser treatment, the process further includes:

[0028] In the third cycle, the first epitaxy is repeated to obtain a third epitaxial sublayer connected to the first SiC substrate.

[0029] The fourth bonding step is to bond the third epitaxial sublayer connected to the first SiC substrate to the epitaxial sublayer in the initial SiC epitaxial wafer that is away from the second SiC substrate to obtain a third bonded epitaxial wafer.

[0030] The fourth peeling step is to peel off the first SiC substrate in the third bonded epitaxial wafer to obtain another initial SiC epitaxial wafer.

[0031] In some embodiments, before the heat treatment or laser treatment, the method further comprises:

[0032] The third cycle, the fourth bonding, and the fourth peeling are repeated n times, where n ranges from 1 to 20.

[0033] In some embodiments, the heat treatment conditions are: in an inert atmosphere, at a temperature ranging from 1400° C. to 2000° C., and for 10 min to 120 min.

[0034] In some embodiments, the laser treatment power range is 10 4 W / cm 2 ~10 6 W / cm 2 .

[0035] In some embodiments, the laser treatment time ranges from 10 min to 120 min.

[0036] In some embodiments, the first extension includes:

[0037] A buffer layer is formed on one side of the first SiC substrate.

[0038] An epitaxial sublayer is formed on a side of the buffer layer away from the first SiC substrate.

[0039] The stripping of the first SiC substrate further includes removing the buffer layer.

[0040] In some embodiments, the epitaxial sublayer has a thickness ranging from 10 μm to 80 μm. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, etc. involved in the embodiments of the present disclosure.

[0042] Figure 1 A schematic structural diagram of a SiC epitaxial wafer provided according to some embodiments of the present disclosure;

[0043] Figure 2 A schematic structural diagram of a SiC epitaxial wafer provided according to some other embodiments of the present disclosure;

[0044] Figure 3 A graph showing the relationship between the thickness of an epitaxial layer and the occurrence frequency of triangular defects according to some examples of the present disclosure;

[0045] Figure 4 A graph showing the correlation between the surface roughness of an epitaxial layer and the number of triangular defects provided according to some examples of the present disclosure;

[0046] Figure 5 A flow chart of a method for preparing a SiC epitaxial wafer according to some embodiments of the present disclosure;

[0047] Figure 6 A structural diagram corresponding to each step of a method for preparing a SiC epitaxial wafer according to some embodiments of the present disclosure;

[0048] Figure 7 Another structural diagram corresponding to each step of a method for preparing a SiC epitaxial wafer according to some embodiments of the present disclosure;

[0049] Figure 8 Another structural diagram corresponding to each step of a method for preparing a SiC epitaxial wafer according to some embodiments of the present disclosure;

[0050] Figure 9 Another structural diagram corresponding to each step of a method for preparing a SiC epitaxial wafer according to some embodiments of the present disclosure;

[0051] Figure 10 A structural diagram corresponding to each step of a method for preparing a SiC epitaxial wafer provided in accordance with Example 1 of the present disclosure;

[0052] Figure 11 A structural diagram corresponding to each step of a method for preparing a SiC epitaxial wafer provided in accordance with Example 2 of the present disclosure;

[0053] Figure 12 This is a surface defect diagram of a SiC epitaxial wafer provided according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0054] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0055] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplary" or "some examples" are intended to indicate that specific features, structures, materials, or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0056] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0057] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0058] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0059] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0060] As used herein, the term "substrate" refers to a material onto which subsequent layers of material may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0061] In addition, in the present disclosure, directional terms such as "upper" and "lower" are defined relative to the orientation of the components in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they can change accordingly according to changes in the orientation of the components in the drawings.

[0062] The technical solutions disclosed herein can be applied to electronic devices, including various types of user equipment or terminal devices, such as computers, mobile phones, tablet computers, wearable devices, and in-vehicle devices. These electronic devices can also be network devices, such as base stations. The electronic devices can also be devices such as power amplifiers used in these electronic devices. The embodiments of this disclosure do not impose any particular limitations on the specific form of these electronic devices.

[0063] It should be noted that, for example, 1 / 2 in the drawings of this disclosure indicates that both component 1 and component 2 can refer to the same component. Figure 2 10 / 10A indicates that the SiC epitaxial wafer 10 and the SiC epitaxial wafer 10A with Si-surface epitaxy can both be represented by this component. Other similar reference numerals appearing in the drawings also follow the above description.

[0064] Silicon carbide (SiC) semiconductor material is an important third-generation semiconductor material, boasting advantages such as a wide bandgap, high breakdown field strength, and high thermal conductivity. SiC devices are currently widely used in high-voltage power systems such as high-voltage transmission, communications power supplies, and new energy electric vehicles. The thin film materials used in SiC device manufacturing require high crystal quality, good doping concentration uniformity, and low film defect density.

[0065] The withstand voltage level of the silicon carbide device is related to the epitaxial layer 2 on the SiC substrate 1 (such as Figure 1 The thickness of the SiC epitaxial wafer 10 is proportional to the thickness of the wafer (shown in Figure 1). For high-voltage SiC devices with withstand voltages ranging from several kilovolts to tens of kilovolts, the required thickness of the SiC epitaxial wafer 10 is between tens and hundreds of microns. A high number of defects (such as dislocations, gap defects, and through-hole defects) can cause localized high electric field concentrations in the SiC epitaxial wafer 10, resulting in lower breakdown voltage, increased leakage current, and reduced thermal stability of the SiC device, thereby reducing the overall reliability and performance of the SiC device. Therefore, SiC epitaxial wafers with low defect density are key to high-voltage SiC devices.

[0066] Furthermore, the SiC epitaxial wafer 10 includes an Si-face epitaxial SiC epitaxial wafer 10A and a C-face epitaxial SiC epitaxial wafer 10B. In the Si-face epitaxial SiC epitaxial wafer 10A, the surface of the epitaxial layer 2 facing away from the SiC substrate 1 is the Si-face; in the C-face epitaxial SiC epitaxial wafer 10B, the surface of the epitaxial layer 2 facing away from the SiC substrate 1 is the C-face. The C-face refers to the (000-1) plane of silicon carbide, where the terminating atoms are carbon atoms. The Si-face refers to the (0001) crystal plane of the silicon carbide wafer, where the terminating atoms are silicon atoms. The choice of Si-face epitaxial SiC epitaxial wafer 10A or C-face epitaxial SiC epitaxial wafer 10B affects the manufacturing process and performance of silicon carbide devices.

[0067] In some embodiments, the SiC epitaxial wafer 10 is a Si-plane epitaxial SiC epitaxial wafer 10A, but the advantage of the C-plane epitaxial SiC epitaxial wafer 10B over the Si-plane epitaxial SiC epitaxial wafer 10A is that the channel mobility of the MOSFET prepared by the C-plane epitaxial SiC epitaxial wafer 10B can be increased from 25 cm 2 / Vs increased to 100cm 2 / Vs, therefore, a high-quality C-plane epitaxial SiC epitaxial wafer 10B is one of the key technologies for improving ultra-high voltage silicon carbide MOSFET devices.

[0068] In some implementations, the SiC epitaxial wafer 10 can be prepared by directly growing an epitaxial layer 2 of a preset thickness on a SiC substrate 1. However, due to the stability of the reactor for growing the epitaxial layer 2 of the SiC epitaxial wafer 10 and the influence of the graphite deposition layer, as the thickness of the epitaxial layer 2 increases, the number of fatal defects such as triangular defects and drop defects will increase significantly. At the same time, the size of the fatal defects will gradually increase with the thickness of the epitaxial layer 2. These factors will lead to a decrease in the yield of the SiC epitaxial wafer 10. The defects of the epitaxial layer 2 can be reduced by optimizing the growth conditions of the epitaxial layer 2, while ensuring the cleanliness of the graphite accessories in the reaction chamber to improve the yield of the SiC epitaxial wafer 10.

[0069] In some examples, in a chemical vapor deposition (CVD) epitaxial device, an epitaxial layer 2 is directly grown on a SiC substrate 1, and the surface roughness of the epitaxial layer 2 (18 μm to 350 μm) is controlled to reduce triangular defects on the surface of the epitaxial layer 2, thereby improving the yield of the SiC epitaxial wafer 10; Figure 3 As shown, Figure 3 A relationship diagram between the thickness of an epitaxial layer and the occurrence frequency of triangular defects is provided for some examples. It can be seen that if the thickness of the epitaxial layer 2 is greater than 18 μm, the occurrence frequency of triangular defects increases significantly. Figure 4 A graph showing the relationship between the surface roughness of an epitaxial layer and the number of triangular defects is provided for some examples. Figure 4 The vertical axis represents the number of triangular defects per wafer [pieces / wf] observed on the surface of the epitaxial layer 2 when the epitaxial layer 2 having a thickness of 18 μm or more is formed on the 4-inch SiC substrate 1. Figure 4 The horizontal axis represents the arithmetic mean roughness (Ra) of the entire surface of the epitaxial layer 2 of the SiC epitaxial wafer 10. It can be seen that if the arithmetic mean roughness (Ra) of the entire surface of the epitaxial layer 2 becomes larger, the triangular defects will also increase significantly; and the growth window of this method is smaller; the optimal epitaxial conditions and rules of different types of epitaxial growth equipment are different.

[0070] At the same time, when growing the epitaxial layer 2 of the SiC epitaxial wafer 10 to a thickness (e.g., >100 μm), the thickness of the epitaxial layer 2 is on the same order of magnitude as the thickness of the SiC substrate 1. This can cause significant stress on the SiC substrate 1 during the growth of the epitaxial layer 2, leading to warping of the epitaxial layer 2. This can also lead to varying temperature differences within the SiC epitaxial wafer 10, making it difficult to control the doping uniformity of the epitaxial layer 2. Furthermore, the growth of the epitaxial layer 2 of the SiC epitaxial wafer 10 is limited by equipment hardware and the evolution of stress and defects during epitaxial growth. This makes it difficult to produce high-quality SiC epitaxial wafers 10, and the difficulty increases exponentially with increasing thickness of the epitaxial layer 2.

[0071] Based on this, the embodiment of the present disclosure provides a method for preparing a SiC epitaxial wafer 10. Figures 5 to 7 As shown, the method for preparing the SiC epitaxial wafer includes:

[0072] S1 : First epitaxy, forming an epitaxial sublayer 21 on one side of the first SiC substrate 11 .

[0073] Exemplarily, the first SiC substrate 11 may be any one of a 4H-SiC substrate, a 6H-SiC substrate, a 3C-SiC substrate, and a polycrystalline SiC substrate.

[0074] Illustratively, the epitaxial sublayer 21 is formed on one side of the first SiC substrate 11 , and the surface of the epitaxial sublayer 21 away from the first SiC substrate 11 is a Si surface. The epitaxial sublayer 21 may be formed epitaxially on the Si surface.

[0075] Exemplarily, the thickness of the epitaxial sub-layer 21 ranges from 10 μm to 80 μm.

[0076] For example, the thickness of the epitaxial sub-layer 21 may be 10 μm, 30 μm, 50 μm, 70 μm or 80 μm, which is not limited here.

[0077] In some embodiments, combined Figure 2 ,like Figure 6 and Figure 7 As shown, the first extension of S1 includes the following steps (1) and (2).

[0078] (1) Buffer layer 3 is formed on one side of first SiC substrate 11 .

[0079] (2) An epitaxial sublayer 21 is formed on the side of the buffer layer 3 away from the first SiC substrate 11 .

[0080] For example, SiHCl3, C3H8 and N2 are introduced at 1550℃~1700℃ to grow a film with a thickness ranging from 1μm to 20μm and a doping concentration ranging from 1×10 17 cm -3 ~2×10 19 cm -3 The buffer layer 3 can make the first SiC substrate 11 and the epitaxial layer 2 more matched, and help form a transition zone between the first SiC substrate 11 and the epitaxial layer 2, thereby reducing the stress caused by lattice mismatch and reducing defects in the growth process of the epitaxial layer 2; at the same time, the doping concentration range of the buffer layer 3 is controlled to be 1×10 17 cm -3 ~2×10 19 cm -3 The mismatch stress between the first SiC substrate 11 and the epitaxial layer 2 caused by the large change in doping concentration can be reduced, thereby reducing the defect density of the epitaxial layer 2 .

[0081] S2 : first bonding, bonding the second SiC substrate 12 to the side of the epitaxial sublayer 21 away from the first SiC substrate 11 .

[0082] Exemplarily, the second SiC substrate 12 may be any one of a 4H-SiC substrate, a 6H-SiC substrate, a 3C-SiC substrate, and a polycrystalline SiC substrate.

[0083] Here, the material of first SiC substrate 11 and the material of second SiC substrate 12 may be the same or different.

[0084] S3 : First peeling: peeling off the first SiC substrate 11 .

[0085] For example, the first stripping method in S3 may be laser stripping or mechanical grinding, and chemical mechanical polishing may be used to remove stripping defects.

[0086] In a case where the buffer layer 3 is formed on one side of the first SiC substrate 11 , the stripping of the first SiC substrate 11 further includes removing the buffer layer 3 .

[0087] Exemplarily, the method for removing the buffer layer 3 may be laser lift-off or grinding process.

[0088] S4: First cycle, repeating the first epitaxial growth S1 to obtain a second epitaxial sublayer 21 connected to the first SiC substrate 11 .

[0089] S5 : Second bonding: bonding the second epitaxial sublayer 21 connected to the first SiC substrate 11 to the epitaxial sublayer 21 connected to the second SiC substrate 12 to obtain a first bonded epitaxial wafer 101 .

[0090] For example, in the first bonded epitaxial wafer 101, the epitaxial sublayer 21 on the side close to the first SiC substrate 11 has a surface close to the first SiC substrate 11 that is a C-plane; the epitaxial sublayer 21 on the side close to the second SiC substrate 12 has a surface close to the second SiC substrate 12 that is a Si-plane.

[0091] S6: Second peeling, peeling off the second SiC substrate 12 (such as Figure 6 ) and the first SiC substrate 11 (as Figure 6 ), and obtain an initial SiC epitaxial wafer 102.

[0092] For example, the second stripping method may be laser stripping or mechanical grinding, and chemical mechanical polishing may be used to remove the stripping defects.

[0093] Illustratively, the initial SiC epitaxial wafer 102 can be obtained by peeling off the second SiC substrate 12 in the first bonded epitaxial wafer 101 . In this case, the initial SiC epitaxial wafer 102 is an initial SiC epitaxial wafer 102A with Si-plane epitaxy.

[0094] Illustratively, the initial SiC epitaxial wafer 102 can be obtained by peeling off the first SiC substrate 11 in the first bonded epitaxial wafer 101 . In this case, the initial SiC epitaxial wafer 102 is an initial SiC epitaxial wafer 102B with C-plane epitaxy.

[0095] S7: heat treatment or laser treatment. Under inert gas conditions, heat treatment or laser treatment is used to recrystallize the initial SiC epitaxial wafer 102 to obtain the SiC epitaxial wafer 10.

[0096] Exemplarily, the heat treatment conditions are: in an inert atmosphere, at a temperature ranging from 1400° C. to 2000° C., for 10 min to 120 min.

[0097] For example, the temperature of the heat treatment may be 1400° C., 1600° C., 1800° C., or 2000° C., etc., which is not limited here.

[0098] For example, the heat treatment time can be 10 min, 50 min, 90 min or 120 min, etc., which is not limited here.

[0099] For example, the inert atmosphere may be any one of argon and nitrogen.

[0100] It can be understood that after the heat treatment, the interface defects Q formed by the bonding of the epitaxial sub-layers 21 in the initial SiC epitaxial wafer 102 disappear after recrystallization through the heat treatment or laser treatment.

[0101] For example, the laser treatment power range is 10 4 W / cm 2 ~10 6 W / cm 2 .

[0102] For example, the power of the laser treatment may be 5×10 4 W / cm 2 , 10 5 W / cm 2 , 2×10 5 W / cm 2 or 10 6 W / cm 2 There is no limit here.

[0103] Exemplarily, the laser treatment time ranges from 10 min to 120 min.

[0104] For example, the laser treatment time may be 10 min, 30 min, 50 min, 70 min, 100 min or 120 min, etc., which is not limited here.

[0105] For example, the Si-plane epitaxial SiC epitaxial wafer 10A can be obtained by subjecting the initial SiC epitaxial wafer 102A to S7 heat treatment or laser treatment.

[0106] Exemplarily, the C-plane epitaxial SiC epitaxial wafer 10B can be obtained by subjecting the C-plane epitaxial initial SiC epitaxial wafer 102B to S7 heat treatment or laser treatment.

[0107] It can be understood that by bonding multiple single-layer epitaxial sublayers 21 together, the body defect density and distribution of the bonded SiC epitaxial wafer 10 can be obtained from the defect density and distribution of the single-layer epitaxial sublayer 21, and the defect distribution of different single-layer epitaxial sublayers 21 is different, so that the epitaxial layer 2 of the SiC epitaxial wafer 10 prepared in the present disclosure has fewer through defects, and the bonding interface of adjacent epitaxial sublayers 21 can be recrystallized through heat treatment or laser treatment to eliminate the interface defect Q, thereby obtaining a SiC epitaxial wafer 10 with a smooth surface and low defect density, solving the problem of large surface roughness and increased defects of the SiC epitaxial wafer 10 caused by directly growing the epitaxial layer 2 on the SiC substrate 1, thereby improving the reliability of the silicon carbide device.

[0108] Moreover, the doping concentration uniformity of the single-layer epitaxial sublayer 21 of the present invention before bonding is good, that is, the doping concentration uniformity of each epitaxial sublayer 21 in the multiple single-layer epitaxial sublayers 21 is good, so that the doping concentration uniformity of the epitaxial layer 2 obtained after bonding is equivalent to the doping concentration uniformity of the single-layer epitaxial sublayer 21, and an epitaxial layer 2 with good doping concentration uniformity is obtained, which is better than the doping uniformity of the directly grown epitaxial layer 2 with a thicker thickness.

[0109] In some embodiments, in the second peeling step S6, the second SiC substrate 12 in the first bonded epitaxial wafer 101 is peeled off; before the heat treatment or laser treatment step S7, as shown in FIG. Figure 8 As shown, it also includes steps S4.1 to S6.1.

[0110] S4.1: Second cycle, repeating the first epitaxy S1, the first bonding S2 and the first peeling S3 to obtain a second epitaxial sublayer 21 connected to the second SiC substrate 12.

[0111] S5.1: Third bonding: bonding the second epitaxial sublayer 21 connected to the second SiC substrate 12 to the epitaxial sublayer 21 in the initial SiC epitaxial wafer 102 away from the first SiC substrate 11 to obtain a second bonded epitaxial wafer 101A.

[0112] S6.1: The third peeling step is to peel off the second SiC substrate 12 in the second bonded epitaxial wafer 101A to obtain another initial SiC epitaxial wafer 102A with Si-surface epitaxy.

[0113] In some embodiments, before the heat treatment or laser treatment, S7 further includes: repeating the second cycle S4.1, the third bonding S5.1 and the third peeling S6.1 n times, where the value of n ranges from 1 to 20.

[0114] For example, the value of n can be 1, 3, 5, 7, 10, 15 or 20, etc., which is not limited here.

[0115] It can be understood that through the above-mentioned n cycles, an initial SiC epitaxial wafer 102A with n+3 overlapping epitaxial sub-layers 21 can be obtained, and then after S7 heat treatment or laser treatment, the interface defects Q between the epitaxial sub-layers 21 are eliminated, and a SiC epitaxial wafer 10A with the expected thickness of the Si-plane epitaxial can be obtained as needed.

[0116] In some embodiments, in the second peeling step S6, the first SiC substrate 11 in the first bonded epitaxial wafer 101 is peeled off; before the heat treatment or laser treatment step S7, as shown in FIG. Figure 9 As shown, it also includes steps S4.2 to S6.2.

[0117] S4.2: The third cycle, repeating the first epitaxy S1 to obtain a third epitaxial sublayer 21 connected to the first SiC substrate 11.

[0118] S5.2: Fourth bonding: bonding the third epitaxial sublayer 21 connected to the first SiC substrate 11 to the epitaxial sublayer 21 in the initial SiC epitaxial wafer 102 away from the second SiC substrate 12 to obtain a third bonded epitaxial wafer 101B.

[0119] S6.2: Fourth peeling: peeling the first SiC substrate 11 in the third bonded epitaxial wafer 101B to obtain another initial SiC epitaxial wafer 102B with C-plane epitaxy.

[0120] In some embodiments, before S7 heat treatment or laser treatment, the method further includes: repeating S4.2 third cycle, S5.2 fourth bonding and S6.2 fourth peeling n times, where n ranges from 1 to 20.

[0121] For example, the value of n can be 1, 3, 5, 7, 10, 15 or 20, etc., which is not limited here.

[0122] It can be understood that through the above-mentioned n cycles, an initial SiC epitaxial wafer 102B with C-face epitaxy and n+3 overlapping epitaxial sub-layers 21 can be obtained, and then after S7 heat treatment or laser treatment, the interface defects Q between the epitaxial sub-layers 21 are eliminated, and a SiC epitaxial wafer 10B with C-face epitaxy of the expected thickness can be obtained as needed.

[0123] The embodiment of the present disclosure provides a SiC epitaxial wafer 10. Figure 1 and Figure 2As shown, the SiC epitaxial wafer 10 includes a SiC substrate 1 and an epitaxial layer 2 disposed on one side of the SiC substrate 1. The epitaxial layer 2 includes a C-plane and a Si-plane disposed opposite each other. Either the C-plane or the Si-plane is adjacent to the SiC substrate 1. The epitaxial layer 2 has a thickness D ranging from 50 μm to 500 μm.

[0124] For example, Figure 1 As shown, the epitaxial layer 2 is a C-plane epitaxial layer 2 .

[0125] For example, Figure 2 As shown, the epitaxial layer 2 is an epitaxial layer 2 grown on a Si surface.

[0126] For example, the thickness D of the epitaxial layer 2 may be in the range of 50 μm, 150 μm, 250 μm, 350 μm, 450 μm or 500 μm, etc., which is not limited here.

[0127] Among them, the defect density of epitaxial layer 2 is in the range of 0.02 / cm 2 ~1 / cm 2 .

[0128] For example, the defects of the epitaxial layer 2 may be triangle defects, carrot defects, large pits, stacking faults, and basal plane dislocations, which are not limited here.

[0129] For example, the defect density of the epitaxial layer 2 may be 0.02 / cm 2 , 0.1 / cm 2 , 0.3 / cm 2 , 0.5 / cm 2 , 0.7 / cm 2 or 1 / cm 2 There is no limit here.

[0130] It can be understood that the SiC substrate is the basis for epitaxial growth, and the SiC substrate provides mechanical support and electrical performance.

[0131] The thickness of the epitaxial layer 2 ranges from 50 μm to 500 μm, enabling the silicon carbide device to withstand high electric field strengths, thereby reducing the risk of breakdown caused by local electric field concentration, and ensuring that the silicon carbide device fabricated from the SiC epitaxial wafer 10 has a higher breakdown voltage. The epitaxial layer 2 also has two crystal plane structures: the C-plane and the Si-plane. The choice of SiC epitaxial wafer 10A with Si-plane epitaxy and the C-plane epitaxial SiC epitaxial wafer 10B affects the manufacturing process and performance of the silicon carbide device, making the SiC epitaxial wafer 10 suitable for different application scenarios. Among them, the C-plane epitaxial SiC epitaxial wafer 10B is used in silicon carbide devices, giving the silicon carbide device performance advantages. For example, the C-plane epitaxial SiC epitaxial wafer 10B can be used in MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) to improve the MOSFET channel mobility.

[0132] Moreover, the defect density of epitaxial layer 2 is in the range of 0.02 / cm 2 ~1 / cm 2 , indicating that the SiC epitaxial wafer 10 has fewer defects (such as triangle defects, carrot defects, large pits, stacking faults, basal plane dislocations, and through-hole defects), which can reduce the local high electric field concentration of silicon carbide devices, increase the breakdown voltage, reduce the leakage current and improve the thermal stability of silicon carbide devices, ensure the quality of the SiC epitaxial wafer 10, and thus improve the overall reliability and performance of silicon carbide devices.

[0133] Here, the defect density can be measured by Lasertec SIGA 88 or KLA 8520.

[0134] In some embodiments, the material of the epitaxial layer 2 includes nitrogen atoms. In the epitaxial layer 2, the doping concentration of nitrogen atoms ranges from 1×10 14 cm -3 ~1×10 17 cm -3 .

[0135] Among them, the material of the epitaxial layer 2 epitaxially grown on the SiC substrate 1 includes SiC, and the epitaxial layer 2 is also doped with nitrogen atoms. The radius of the nitrogen atom is close to that of the carbon atom, and it is easy to replace the carbon site in the crystal lattice, providing free electrons, thereby reducing the resistivity and improving the conductivity of the epitaxial layer 2.

[0136] For example, the doping concentration of nitrogen atoms may be 1×10 14 cm -3 , 1×10 15 cm -3 , 1×10 16 cm -3or 1×10 17 cm -3 There is no limit here.

[0137] It can be understood that nitrogen atoms, as n-type dopants, can provide additional free electrons to improve the conductivity of the SiC epitaxial wafer 10; that is, the doping concentration of nitrogen atoms is controlled to be 1×10 14 cm -3 ~1×10 17 cm -3 Within this range, the conductive properties of the SiC epitaxial wafer 10 can be optimized, the efficiency and thermal stability of the current passing through the SiC epitaxial wafer 10 can be balanced, the carrier recombination loss and the formation of defects can be reduced, and the defect density of the epitaxial layer 2 can be further reduced, thereby reducing the defect density of the SiC epitaxial wafer 10.

[0138] Here, the doping concentration of nitrogen atoms can be measured by the voltage-current (IV) characteristics of a mercury (Hg) probe.

[0139] In some embodiments, the surface roughness Ra of the epitaxial layer 2 ranges from 0.1 nm to 1 nm.

[0140] For example, the surface roughness Ra of the epitaxial layer 2 may be 0.1 nm, 0.3 nm, 0.5 nm, 0.7 nm or 1 nm, etc., which is not limited here.

[0141] It can be understood that controlling the surface roughness Ra of the epitaxial layer 2 within the range of 0.1 nm to 1 nm (scanning range 5 μm×5 μm) indicates that the roughness Ra of the SiC epitaxial wafer 10 is relatively small, which helps to reduce the formation and propagation of crystal defects (such as dislocations and gap defects), improves the crystal structure quality of the epitaxial layer 2, and thus reduces the defect density.

[0142] Here, the surface roughness Ra can be obtained by atomic force microscopy.

[0143] In some embodiments, the epitaxial layer 2 has a thickness ranging from 100 μm to 200 μm.

[0144] For example, the thickness of the epitaxial layer 2 may be 100 μm, 120 μm, 140 μm, 160 μm, 180 μm or 200 μm, etc., which is not limited here.

[0145] It can be understood that controlling the thickness of the epitaxial layer 2 within the range of 100μm~200μm can enable the silicon carbide device to have a higher breakdown voltage capability, and can also effectively disperse the electric field and reduce the possibility of local electric field concentration due to defects, thereby improving the stability of the silicon carbide device.

[0146] Example 1:

[0147] Example 1 provides a SiC epitaxial wafer 10, such as Figure 10 As shown, the method for preparing the SiC epitaxial wafer 10 includes the following steps (1A) to (8A).

[0148] (1A) The first SiC substrate 11 is placed in a high-temperature CVD process at 1630° C. in a hydrogen atmosphere for 15 minutes to obtain a clean SiC surface with atomic steps.

[0149] For example, the first SiC substrate 11 is an 8-inch Si-plane SiC substrate of high crystal quality.

[0150] (2A) The first SiC substrate 11 is heated to 1650°C, and SiHCl3, C3H8 and N2 are introduced into the reaction chamber to grow a SiC substrate with a thickness of 10 μm and a doping concentration of 2×10 18 cm -3 The buffer layer 3 was then grown by adjusting the N2 flow rate to obtain a thickness of 45 μm and a doping concentration of 5×10 14 cm -3 epitaxial sublayer 21.

[0151] (3A) A second SiC substrate 12 is bonded to the side of the epitaxial sublayer 21 facing away from the first SiC substrate 11 .

[0152] For example, the second SiC substrate 12 is a conductive polycrystalline SiC substrate.

[0153] (4A) The first SiC substrate 11 is removed by laser lift-off, with a laser wavelength of 1050 nm and a power of 10 W. While removing the first SiC substrate 11, chemical mechanical polishing is simultaneously used to remove the buffer layer 3 and lift-off defects; and surface impurities and contamination are removed by cleaning.

[0154] (5A) Bond another epitaxial sublayer 21 connected to the first SiC substrate 11 to the epitaxial sublayer 21 connected to the second SiC substrate 12 obtained in the previous step [step (4A)] to obtain a first bonded epitaxial wafer 101.

[0155] (6A) The second SiC substrate 12 is removed by laser lift-off process, and the lift-off surface defects are removed by chemical mechanical polishing to obtain an initial SiC epitaxial wafer 102A with two epitaxial sub-layers 21 grown on the Si surface. The total thickness of the two epitaxial sub-layers is about 85 μm.

[0156] (7A) Repeat steps (5A) and (6A) three times to obtain an initial SiC epitaxial wafer 102A with five epitaxial sub-layers 21 grown on the Si surface. The total thickness of the five epitaxial sub-layers 21 is about 200 μm.

[0157] (8A) The initial SiC epitaxial wafer 102A obtained in step (7A) is placed in a high-temperature furnace for heat treatment to eliminate the bonding interface defects Q between the epitaxial sub-layers 21; the heat treatment conditions are: in an argon atmosphere, at a temperature of 1750°C, for 30 minutes, to obtain a Si-surface epitaxial SiC epitaxial wafer 10A.

[0158] like Figure 12 As shown, Figure 12 (a) shows the surface defects of the 8-inch SiC epitaxial wafer 10 in Example 1 (defect density 0.1 / cm 2 ), Figure 12 (b) shows the surface defects (defect density 2 / cm2) of the epitaxial layer 2 (the thickness of the epitaxial layer 2 is 200 μm) grown directly on the 8-inch SiC substrate 1. 2 ), it can be seen that the surface defects of the SiC epitaxial wafer 10 obtained by the method for preparing the SiC epitaxial wafer 10 disclosed in the present invention are significantly reduced.

[0159] Example 2:

[0160] Example 2 provides a SiC epitaxial wafer 10, such as Figure 11 As shown, the method for preparing the SiC epitaxial wafer 10 includes the following steps (1B) to (8B).

[0161] (1B) The first SiC substrate 11 is placed in a high-temperature CVD process and treated at 1650° C. in a hydrogen atmosphere for 10 minutes to obtain a clean SiC surface with atomic steps.

[0162] For example, the first SiC substrate 11 is an 8-inch Si-plane 4-HSiC substrate with high crystal quality.

[0163] (2B) The first SiC substrate 11 is heated to 1650°C, and SiHCl3, C3H8 and N2 are introduced into the reaction chamber to grow a SiC substrate with a thickness of 10 μm and a doping concentration of 2×10 18 cm -3 The buffer layer 3 was then grown by adjusting the N2 flow rate to obtain a thickness of 35 μm and a doping concentration of 5×10 14 cm -3 epitaxial sublayer 21.

[0164] (3B) A second SiC substrate 12 is bonded to the side of the epitaxial sublayer 21 facing away from the first SiC substrate 11 .

[0165] For example, the second SiC substrate 12 is a highly conductive 6H—SiC substrate.

[0166] (4B) The first SiC substrate 11 is removed by mechanical grinding, and the buffer layer 3 and peeling defects are removed by chemical mechanical polishing; surface impurities and contamination are removed by cleaning.

[0167] (5B) Bond another epitaxial sublayer 21 connected to the first SiC substrate 11 to the epitaxial sublayer 21 connected to the second SiC substrate 12 obtained in the previous step [step (4B)] to obtain a first bonded epitaxial wafer 101.

[0168] (6B) The first SiC substrate 11 is removed by laser mechanical polishing, and the surface defects and the buffer layer 3 are removed by chemical mechanical polishing to obtain an initial SiC epitaxial wafer 102B with two epitaxial sublayers 21 having a total thickness of about 65 μm.

[0169] (7B) Repeat steps (5B) and (6B) three times to obtain an initial SiC epitaxial wafer 102B with five epitaxial sub-layers 21 having a total thickness of about 150 μm.

[0170] (8B) The initial SiC epitaxial wafer 102B obtained in step (7B) is placed in a high-temperature furnace for heat treatment to eliminate the bonding interface defects Q of different epitaxial sub-layers 21; the high-temperature treatment conditions are: in an argon atmosphere, at a temperature of 1650°C, for 50 minutes to obtain a C-face epitaxial SiC epitaxial wafer 10B.

[0171] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention are intended to be covered by the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope of protection of the claims.

Claims

1. A method for preparing a SiC epitaxial wafer, characterized in that: include: First epitaxy, forming an epitaxial sublayer on one side of the first SiC substrate; First bonding: bonding a second SiC substrate to a side of the epitaxial sublayer away from the first SiC substrate; first peeling, peeling off the first SiC substrate; In the first cycle, the first epitaxy is repeated to obtain a second epitaxial sublayer connected to the first SiC substrate; a second bonding step of bonding the second epitaxial sublayer connected to the first SiC substrate to the epitaxial sublayer connected to the second SiC substrate to obtain a first bonded epitaxial wafer; The second peeling step involves peeling off one of the second SiC substrate and the first SiC substrate in the first bonded epitaxial wafer to obtain an initial SiC epitaxial wafer; wherein the initial SiC epitaxial wafer obtained by peeling off the second SiC substrate in the first bonded epitaxial wafer is an initial SiC epitaxial wafer with Si-plane epitaxy; and the initial SiC epitaxial wafer obtained by peeling off the first SiC substrate in the first bonded epitaxial wafer is an initial SiC epitaxial wafer with C-plane epitaxy; Heat treatment or laser treatment, under inert gas conditions, using a temperature range of 1400 ℃ ~ 2000 ℃ heat treatment or power range of 10 4 W / cm 2 ~10 6 W / cm 2 The laser treatment causes the initial SiC epitaxial wafer to recrystallize to obtain the SiC epitaxial wafer.

2. The method for preparing a SiC epitaxial wafer according to claim 1, wherein: In the second stripping, the second SiC substrate in the first bonded epitaxial wafer is stripped; Before the heat treatment or laser treatment, the method further comprises: a second cycle, repeating the first epitaxy, the first bonding, and the first peeling to obtain a second epitaxial sublayer connected to a second SiC substrate; a third bonding step of bonding the second epitaxial sublayer connected to the second SiC substrate to the epitaxial sublayer in the initial SiC epitaxial wafer that is away from the first SiC substrate, to obtain a second bonded epitaxial wafer; The third step is peeling off the second SiC substrate in the second bonded epitaxial wafer to obtain another initial SiC epitaxial wafer.

3. The method for preparing a SiC epitaxial wafer according to claim 2, wherein: Before the heat treatment or laser treatment, the method further comprises: The second cycle, the third bonding, and the third peeling are repeated n times, where n ranges from 1 to 20.

4. The method for preparing a SiC epitaxial wafer according to claim 1, wherein: In the second stripping, the first SiC substrate in the first bonded epitaxial wafer is stripped; Before the heat treatment or laser treatment, the method further comprises: In a third cycle, the first epitaxy is repeated to obtain a third epitaxial sublayer connected to the first SiC substrate; a fourth bonding step of bonding the third epitaxial sublayer connected to the first SiC substrate to the epitaxial sublayer in the initial SiC epitaxial wafer that is away from the second SiC substrate, to obtain a third bonded epitaxial wafer; The fourth peeling step is to peel off the first SiC substrate in the third bonded epitaxial wafer to obtain another initial SiC epitaxial wafer.

5. The method for preparing a SiC epitaxial wafer according to claim 4, wherein: Before the heat treatment or laser treatment, the method further comprises: The third cycle, the fourth bonding, and the fourth peeling are repeated n times, where n ranges from 1 to 20.

6. The method for preparing a SiC epitaxial wafer according to claim 1, wherein: The heat treatment time is: 10min~120min.

7. The method for preparing a SiC epitaxial wafer according to claim 1, wherein: The laser treatment time ranges from 10 min to 120 min.

8. The method for preparing a SiC epitaxial wafer according to claim 1, wherein: The first extension includes: forming a buffer layer on one side of the first SiC substrate; forming an epitaxial sublayer on a side of the buffer layer away from the first SiC substrate; The step of stripping the first SiC substrate further includes removing the buffer layer.

9. The method for preparing a SiC epitaxial wafer according to any one of claims 1 to 8, wherein: The thickness of the epitaxial sublayer ranges from 10 μm to 80 μm.

10. A SiC epitaxial wafer prepared by the method for preparing a SiC epitaxial wafer according to any one of claims 1 to 9, characterized in that: include: A SiC substrate and an epitaxial layer provided on one side of the SiC substrate; The epitaxial layer includes: a C-plane and a Si-plane arranged opposite to each other; either the C-plane or the Si-plane is close to the SiC substrate; the thickness of the epitaxial layer is in the range of 50 μm to 500 μm; The defect density of the epitaxial layer is in the range of 0.02 / cm 2 ~1 / cm 2 .

11. The SiC epitaxial wafer according to claim 10, characterized in that: The material of the epitaxial layer includes: nitrogen atoms; In the epitaxial layer, the doping concentration of the nitrogen atoms is in the range of 1×10 14 cm -3 ~1×10 17 cm -3 .

12. The SiC epitaxial wafer according to claim 10, characterized in that The surface roughness of the epitaxial layer is in the range of 0.1 nm to 1 nm.

13. The SiC epitaxial wafer according to claim 10, characterized in that The thickness of the epitaxial layer ranges from 100 μm to 200 μm.

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