A method for controlling etching and related products

Abstract

The present invention discloses a method for controlling etching and related products, which relate to the field of semiconductor manufacturing technology; the method includes: detecting the width of the back-side etching mark of the etched wafer; and adjusting the distance between the component that controls the etching of the wafer and the wafer in the etching machine according to the width of the back-side etching mark. According to this method, the etching area error in the edge etching process can be accurately identified by detecting the width of the back-side etching mark of the wafer; after adjusting the distance between the component that controls the etching of the wafer and the wafer in the etching machine according to the width of the back-side etching mark, the wafer etching process can be controlled to return to the standard process. Furthermore, the method can immediately detect the width of the back-side etching mark of the wafer after the edge etching is completed, and immediately adjust the distance between the component that controls the etching of the wafer and the wafer in the etching machine, thereby improving the accuracy of the edge etching process and the yield rate of semiconductor products with an immediate feedback mechanism.

Description

Technical Field

[0001] The present invention generally relates to the field of semiconductor manufacturing technology. More specifically, the present invention relates to a method for controlling etching and related products. Background Art

[0002] With the advancement of semiconductor technology, the size of semiconductors continues to shrink. At the same time, the complexity of semiconductor processes and the scrap rate of semiconductor products continue to increase. Semiconductor products are usually produced in the center area of ​​the wafer through processes such as lithography, deposition, and etching. The edge area of ​​the wafer is outside the center area. During the various processes in the center area, some residual particles and films may fall on the front and back of the edge area of ​​the wafer, resulting in wafer edge defects such as peeling, delamination, particle contamination, arcing, and micromasking. Wafer edge defects are a major factor in the increase in semiconductor product scrap rate. Reducing wafer edge defects through the bevel etch process is an important method to improve the yield of semiconductor products.

[0003] The existing edge etching process lacks an abnormality detection mechanism. When the distance between the top plate and the wafer becomes abnormal, the etching machine will not be stopped and adjusted until the etching rate of the semiconductor product is too low or too high. This leads to poor edge etching quality in multiple batches of wafers.

[0004] In view of this, there is an urgent need to provide an edge etching solution to promptly identify the distance error between the top plate and the wafer, thereby adjusting the etching area in real time and reducing the number of scrapped semiconductor products. Summary of the Invention

[0005] In order to at least solve one or more technical problems described in the above background technology section, the present invention proposes the following technical solutions and multiple embodiments thereof.

[0006] In a first aspect, the present invention discloses a method for controlling etching, comprising: detecting the width of the back-side etch mark of an etched wafer; and adjusting the distance between a component in an etcher that controls etching of the wafer and the wafer according to the width of the back-side etch mark.

[0007] In a second aspect, the present invention discloses an apparatus for controlling etching, comprising a processor configured to execute program instructions; and a memory configured to store program instructions, which, when loaded and executed by the processor, causes the apparatus to perform the method according to the first aspect.

[0008] In a third aspect, the present invention discloses a computer-readable storage medium, wherein program instructions are stored therein, and the program instructions are suitable for being loaded by a processor and executing the method according to the first aspect.

[0009] In a fourth aspect, the present invention discloses an etching system, comprising: an etch mark detection device, configured to: detect the width of the etch mark on the back side of an etched wafer; an etching machine, configured to: etch the wafer; and adjust the distance between a component in the etching machine that controls the etching of the wafer and the wafer according to the width of the back side etch mark detected by the etch mark detection device.

[0010] Compared to the prior art, the present application achieves the following unexpected technical effects: through the proposed method, apparatus, computer-readable storage medium, and etching system for controlling etching, after the etching machine completes edge etching of a preceding wafer, the etching area for subsequent wafers can be accurately adjusted based on the width of the etch mark on the back of the preceding wafer, thereby helping to improve the manufacturing precision and yield of semiconductor products. Furthermore, after completing edge etching of a small number of wafers, the width of the etch mark on the back of the edge-etched wafers is detected and the etching machine is adjusted by the automatic process controller of the etching machine, thereby achieving immediate adjustment of the edge etching process and reducing the amount of scrapped semiconductor products. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other objects, features and advantages of the exemplary embodiments of the present invention will become readily understood by reading the following detailed description with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present invention are shown in an illustrative and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0012] Figure 1 An exemplary schematic diagram of a wafer edge region in some embodiments of the present invention is shown.

[0013] Figure 2 An exemplary schematic diagram of a wafer edge etching process in some embodiments of the present invention is shown.

[0014] Figure 3 An exemplary schematic diagram illustrating the relationship between the distance between the top plate and the wafer and the etching area in some embodiments of the present invention.

[0015] Figure 4 An exemplary flow chart of a method for controlling etching in some embodiments of the present invention is shown.

[0016] Figure 5 An exemplary schematic diagram illustrating etching marks on the back side of a wafer in some embodiments of the present invention is shown.

[0017] Figure 6An exemplary schematic diagram showing the structure of an etching machine in some embodiments of the present invention is shown.

[0018] Figure 7 Shown Figure 6 A partial enlarged view of area A corresponding to the dotted box.

[0019] Figure 8 An exemplary schematic diagram of a method for controlling etching in some embodiments of the present invention is shown.

[0020] Figure 9 The block diagram shows the hardware configuration of an apparatus that can implement an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work shall fall within the scope of protection of the present invention.

[0022] It should be understood that the terms "include" and "comprising" used in the description and claims of the present invention indicate the presence of described features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.

[0023] It should also be understood that the terminology used in this specification is for the purpose of describing specific embodiments only and is not intended to limit the present invention. As used in the specification and claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should further be understood that the term "and / or" as used in the specification and claims refers to any and all possible combinations of one or more of the associated listed items, including and including these combinations.

[0024] As used in this specification and claims, the term “if” can be interpreted as “when” or “upon” or “in response to determining” or “in response to detecting,” depending on the context. Similarly, the phrase “if it is determined” or “if [described condition or event] is detected” can be interpreted as meaning “upon determination” or “in response to determining” or “upon detection of [described condition or event]” or “in response to detecting [described condition or event],” depending on the context.

[0025] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0026] As semiconductor technology advances, semiconductor size continues to shrink. At the same time, the complexity of semiconductor processes and the scrap rate of semiconductor products continue to increase. Semiconductor products such as chips and memory devices are typically produced in the center of the wafer through processes such as photolithography, deposition, and etching. Within the wafer, the area outside the center is called the edge. Figure 1 Schematic diagram of the wafer edge region in some embodiments of the present invention is shown. In some embodiments, the wafer edge region is an annular region with a width of 2-3 mm from the wafer edge to the wafer center. Figure 1 As shown in the figure, there are five important areas at the wafer edge: the front straight edge and front bevel of the wafer front, the back straight edge and back bevel of the wafer back, and the vertex connecting the front and back of the wafer. During the production process, some residual particles and films may fall on the front and back of the wafer edge area, causing wafer edge defects. Wafer edge defects such as delamination, delamination, particle contamination, arcing, and micro-masking are a major cause of increased scrap rates for semiconductor products.

[0027] The wafer edge etching process can remove any type of film and residual particles in the wafer edge area, thereby overcoming wafer edge defects and is an important method to improve wafer yield. Figure 2 FIG. 1 shows an exemplary schematic diagram of a wafer edge etching process in some embodiments of the present invention. Figure 2 As shown, a wafer is placed on a bottom plate in an etcher, with the center area of ​​its front surface covered by the top plate of the etcher. A small gap exists between the top plate and the front surface of the wafer, and an inert gas such as nitrogen (N2), argon (Ar), or helium (He) is filled in the gap to prevent plasma gas from entering the center area of ​​the front surface of the wafer. It is understood that, apart from the center area shielded by the top and bottom plates, only the edge area of ​​the wafer is exposed to the plasma gas, thereby etching the front, back, and apex of the edge area, removing thin films, residual particles, and other impurities in the edge area of ​​the wafer. In some embodiments, the plasma gas is ionized from chlorine (Cl2), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), hydrogen bromide (HBr), or fluorine (F2).

[0028] It is understandable that the distance between the top plate and the wafer (which can be the distance from any plane of the top plate's upper and lower surfaces to the front or back side of the wafer) affects the wafer area that can be etched by the plasma gas. Figure 3 FIG2 is an exemplary schematic diagram showing the relationship between the distance between the top plate and the wafer and the etching area in some embodiments of the present invention. Figure 3 As shown in sub-figure (a), under the standard process, the distance between the top plate and the wafer is the standard distance D std, at this time, the plasma gas is used to etch the complete edge area of ​​the wafer, that is, the edge area of ​​the front side of the wafer, the edge area of ​​the back side of the wafer, and the vertices in the edge area. Figure 3 As shown in sub-figure (b) in the figure, when the distance between the top plate and the wafer is greater than the standard distance, the plasma gas can diffuse from the edge of the wafer to the center of the wafer, thereby etching more of the front area; because more plasma gas is used to etch the front of the wafer, the front of the wafer is over-etched, damaging the center area of ​​the wafer; at the same time, the plasma gas used to etch the back of the wafer is reduced, resulting in under-etching of the back of the wafer. Figure 3 As shown in sub-figure (c) in the figure, when the distance between the top plate and the wafer is less than the standard distance, the front area that can be etched by the plasma gas is reduced, thereby etching more back area; since more plasma gas is used to etch the back side of the wafer, the back side of the wafer is over-etched and the front side of the wafer is under-etched.

[0029] It is understandable that in the wafer edge etching process, whether it is the front or back of the wafer, once over-etching or under-etching occurs, the yield of semiconductor products will be reduced; therefore, the distance between the top plate and the wafer affects the precision of the edge etching process and the yield of semiconductor products. In the prior art, the edge etching process usually sets the distance from the top plate to the wafer of the etching machine to a standard height, and then performs edge etching on the wafer; however, due to the lack of an abnormality detection mechanism, it can only be determined whether the etching machine is abnormal by monitoring the crystal surface etching rate, and the average monitoring time of the crystal surface etching rate is about 2-7 days. When the distance between the top plate and the wafer in the etching machine is abnormal, multiple batches of wafers will have the problem of poor edge etching quality. In view of this, the present invention discloses a method for controlling etching, so as to timely identify the distance error between the top plate and the wafer in the edge etching process and improve the yield of semiconductor products.

[0030] Figure 4 An exemplary flow chart of a method for controlling etching in some embodiments of the present invention is shown. Figure 4 As shown, the method includes: step 401, detecting the width of the back etch mark of the etched wafer; step 402, adjusting the distance between the component controlling the etching of the wafer in the etching machine and the wafer according to the width of the back etch mark.

[0031] It is understood that the etching described in step 401 includes edge etching of the edge area of ​​the wafer; after the edge etching of the wafer using the etching machine, a back etch mark can be observed from the back of the wafer, and the back etch mark shows the etched area on the back side of the edge etching process. In some embodiments, the width of the back etch mark under the standard process is defined as the standard width value W std , that is, when the width of the back etching mark is W stdWhen the distance between the upper electrode assembly of the etching machine and the wafer (the distance between the upper electrode assembly and the wafer can be defined as the shortest distance between the two) is the standard distance D std In this case, during the edge etching process, the plasma gas can only etch the complete wafer edge area. After the edge etching of the wafer is completed, if the width of the etching mark on the back of the wafer is not equal to W std , the distance between the upper electrode assembly and the wafer can be adjusted to D std , thereby restoring the edge etching process to the standard process, that is, accurately etching the entire wafer edge area.

[0032] Regarding the “component in the etcher that controls the etching of the wafer”, it can be as follows Figure 2 Shown is a top plate positioned above a wafer during an edge etching process; as will be described later, in some embodiments, the top plate is an upper electrode assembly of an etcher, which can be moved by the etcher to adjust the distance between the upper electrode assembly and the wafer.

[0033] Generally speaking, the semiconductor manufacturing process can include eight steps: wafer processing, oxidation treatment, photolithography, etching, thin film deposition, interconnection (i.e., connecting individual transistors and circuit elements through metal wiring), testing, and packaging. Edge etching is a process within the etching step that can remove impurities such as residual particles and thin films introduced to the wafer edge by steps before (including) etching. Step 401 in the embodiment of the present invention may include: immediately after completing edge etching of a wafer, testing the width of the backside etch mark on the wafer; or, after completing thin film deposition or interconnection on the wafer, testing the width of the backside etch mark on the wafer; or, testing the width of the backside etch mark on the wafer during the testing phase. It is understandable that, since the edge etching process etches both the front and back sides of the wafer at the same time, after the edge etching is completed on a wafer, there will be etching marks on both the front and back sides of its edge region; therefore, if the detection is performed after the edge etching of a wafer is completed, not only can the etching area targeted by the edge etching process be identified by detecting the width of the etching mark on the back side of the wafer, but also the etching area targeted by the edge etching process can be identified by detecting the width of the etching mark on the front side of the wafer edge region; and since the thin film deposition and interconnection steps will cause the etching mark on the front side of the wafer edge region to be covered, then, if the detection is performed after the thin film deposition or interconnection of a wafer is completed, or during the test phase, the etching area targeted by the edge etching process can only be identified by detecting the width of the etching mark on the back side. In the present invention, it is preferred to detect the width of the etching mark on the back side of the wafer during the test phase, thereby introducing the method for controlling etching proposed by the present invention by making minor changes to the semiconductor manufacturing process, and at the same time, the etching mark on the back side of the wafer is easier to observe, thereby improving the accuracy of the etching area detection result.

[0034] It can be understood that the method for controlling etching disclosed in the present invention can accurately identify the etching area error in the edge etching process by detecting the width of the etching mark on the back of the wafer; after adjusting the distance between the component controlling the etching of the wafer and the wafer in the etching machine according to the width of the back etching mark, the wafer etching process can be controlled to return to the standard process. Furthermore, after completing the edge etching operation on a small number of wafers, the method can immediately detect the width of the etching mark on the back of the wafer, and adjust the distance between the component controlling the etching of the wafer and the wafer in the etching machine by the automatic process controller of the etching machine, thereby improving the precision of the edge etching process and the yield rate of semiconductor products through an immediate feedback mechanism.

[0035] In some embodiments, detecting the width of the backside etch mark of the etched wafer includes: detecting an extension length of the backside etch mark from the wafer edge toward the wafer center; and using the extension length as the width of the backside etch mark.

[0036] Figure 5 Schematic diagrams of exemplary etching marks on the back side of a wafer in some embodiments of the present invention are shown. Figure 5 As shown in the figure, after edge etching of the wafer, a circular back-etch mark can be observed from the back of the wafer. The outer circumference of the etch mark ring is the outer edge of the wafer, and the inner circumference of the etch mark ring is the back-etch mark boundary. Ideally, the back-etch mark boundary is the center of the wafer. The extension length of the back-etch mark from the wafer edge to the center of the wafer, i.e., the ring width, is the width of the back-etch mark.

[0037] In some embodiments, adjusting the distance between a component controlling the etching of the wafer and the wafer in the etcher according to the width of the back etch mark includes: increasing the distance between the component and the wafer in response to the width of the back etch mark being greater than a width threshold; and decreasing the distance between the component and the wafer in response to the width of the back etch mark being less than the width threshold.

[0038] In these embodiments, the width threshold may be set to the width standard value W described above. std , when the width of the back etching mark is W std When the height adjustment component corresponding to the top plate in the etching machine is the standard height H std , during the edge etching process, the plasma gas can only etch the complete wafer edge area. Figure 3 It can be understood that when the width of the back etching mark is greater than W std When the height adjustment component is less than H std At this time, you need to raise the height adjustment component to H std ; When the width of the back etching mark is less than W stdWhen the height adjustment component is greater than H std , at this time, you need to lower the height adjustment component to H std .

[0039] In some embodiments, the method for controlling etching further includes: a component in the etcher for controlling etching of the wafer includes an upper electrode assembly for defining an etching area.

[0040] Figure 6 Schematic diagrams of exemplary structures of etching machines in some embodiments of the present invention are shown. It is understood that the etching machine generally has an axisymmetric shape. For the sake of simplicity, Figure 6 Only half of the etching machine is shown; Figure 6 The etching machine shown in the figure only shows the components related to this embodiment. It is obvious to those skilled in the art that the etching machine may also include common components different from the components shown in the figure, including but not limited to the etching machine gate, etching machine support, actuator, RF power source, etching machine controller, etc. Figure 6 As shown, the etcher primarily consists of an upper electrode assembly and a lower electrode assembly, with the wafer placed between them. The upper electrode assembly includes an upper electrode, an upper plasma-exclusion zone (PEZ) ring, and a central ceramic dielectric plate. The lower electrode assembly includes a lower electrode, a lower isolation ring, a lower PEZ, and a lower electrode plate. In some embodiments, the upper electrode assembly is connected to the etcher's support, which is connected to an actuator that drives the upper electrode assembly and adjusts its height.

[0041] Figure 7 Shown Figure 6 The local enlarged view of the area A corresponding to the dotted box is as follows: Figure 7 As shown, the reaction gas is injected into the area between the upper electrode and the lower electrode through the gap between the upper electrode and the upper PEZ ring. The upper and lower electrodes are provided with radio frequency power by a radio frequency power source. When the radio frequency power is applied to the reaction gas, the reaction gas is ionized to form plasma gas. The upper PEZ ring and the lower PEZ ring are used to prevent the plasma gas from etching the central area of ​​the wafer. In some embodiments, the central ceramic dielectric plate is provided with air holes for releasing inert gas, thereby further preventing the plasma gas from etching the central area of ​​the wafer. It can be understood that Figure 6 The upper electrode assembly is equivalent to Figure 2 The top plate, Figure 6 The lower electrode assembly is equivalent to Figure 2 The bottom plate in the bottom plate can change the distance between the upper electrode assembly and the wafer by adjusting the height of the upper electrode assembly, thereby changing the etching area.

[0042] In some embodiments, the upper PEZ and the central ceramic dielectric plate form a first integral body, which can be controlled and moved by the etcher. By adjusting the height of the first integral body, the distance between the etcher's upper electrode assembly and the wafer can be adjusted. In these embodiments, the first integral body is the "component in the etcher that controls etching of the wafer" described in step 402. In other embodiments, the upper electrode assembly can be controlled and moved by the etcher. By adjusting the height of the upper electrode assembly, the distance between the upper electrode assembly and the wafer can be adjusted. In these embodiments, the upper electrode assembly is the "component in the etcher that controls etching of the wafer" described in step 402.

[0043] It is understood that the distance between the upper electrode assembly and the wafer can be achieved by raising the upper electrode assembly or the lower electrode assembly. In some embodiments, increasing the distance between the assembly and the wafer includes raising the upper electrode assembly; decreasing the distance between the assembly and the wafer includes lowering the upper electrode assembly.

[0044] In some embodiments, the method for controlling etching further includes: setting a width threshold according to a target etching area.

[0045] Generally speaking, the target etching area in the edge etching process refers to the edge area of ​​the wafer. It is understandable that in order to overcome the wafer edge defects, it is necessary to achieve covering etching of the wafer edge area, that is, to complete the etching of the front, back and vertex of the wafer, while ensuring that the center area of ​​the wafer is not etched; in some embodiments, the width of the etching mark on the back of the wafer when the covering etching of the edge area is completed can be observed, and the etching mark width at this time can be used as the width threshold. In some embodiments, the width threshold is set to mm.

[0046] With the development of other semiconductor-related industries such as the automotive electronics industry, the communications industry, the artificial intelligence and big data industries, the demand for semiconductor products continues to grow, and it is becoming increasingly important to increase the production volume of semiconductor products on a single wafer. Expanding the center area of ​​the wafer and shrinking the edge area of ​​the wafer is an important way to increase the production volume of semiconductor products on a single wafer. Therefore, the edge area of ​​the wafer will also change with the development of semiconductor-related industries. According to an embodiment of the present invention, the width threshold can be adaptively adjusted according to the size of the wafer edge area, and the target etching area of ​​the edge etching process can be controlled, thereby helping semiconductor manufacturers to flexibly respond to changing production needs.

[0047] In some embodiments, adjusting the distance between the component controlling the etching of the wafer and the wafer in the etching machine according to the width of the backside etching mark includes: Calculate the distance adjustment amount; adjust the distance between the component and the wafer according to the distance adjustment amount; where y is the distance adjustment amount; A is the adjustment coefficient, and when the unit of y is meter (m) and the unit of x is millimeter (mm), A can be 0.001; when the units of x and y are both millimeter or meter, A can be 1; x is the detection width of the back etch mark; z is a constant; in some embodiments, z represents the width threshold of the back etch mark, for example: when z= mm, when A=1, if x=2mm, then y=0, which means there is no need to adjust the distance between the component that controls the etching of the wafer in the etcher and the wafer.

[0048] In these embodiments, a dedicated control program can be set in the automatic process control (APC) of the etcher. The program takes the width of the back-side etch mark detected on the edge-etched wafer as input. When the program detects that the width of the back-side etch mark is too small, the program controls the reduction of the distance between the component that controls the etching of the wafer in the etcher and the wafer. The value of the distance reduction is based on the above formula Calculation; On the contrary, when the program detects that the width of the back etching mark is too large, it controls to increase the distance between the etching component of the etcher and the wafer. The value of the distance increase is based on the above formula calculate.

[0049] In some other embodiments, association data (the association data can be in the form of a table, dictionary, or array) between a preset distance adjustment amount (i.e., the aforementioned y) and the backside etch mark width (i.e., the aforementioned x) is preset and stored in the automatic process controller of the etcher. After the actual detected width of the backside etch mark is obtained for the wafer that has completed edge etching, the distance adjustment amount corresponding to the actual detected width is queried in the association data, and the distance between the component controlling the etching of the wafer in the etcher and the wafer is adjusted according to the distance adjustment amount obtained in the query. Table 1 shows the association data between the distance adjustment amount and the backside etch mark in some embodiments of the present invention, where a negative distance adjustment amount indicates that the distance between the component controlling the etching of the wafer in the etcher and the wafer needs to be reduced according to the distance adjustment amount; a positive distance adjustment amount indicates that the distance between the component controlling the etching of the wafer in the etcher and the wafer needs to be increased according to the distance adjustment amount. It can be understood that Table 1 exemplarily gives some detection widths of back etch marks and their corresponding distance adjustment values. As the table continues to expand, more back etch mark detection widths can be covered. In actual use, you can first query from the table: the detection width value of the back etch mark that is closest to the actual detection width of the back etch mark (denoted as x1), and adjust the distance between the component that controls the etching of the wafer in the etcher and the wafer according to the distance adjustment amount corresponding to x1.

[0050] Table 1

[0051]

[0052] Figure 8 An exemplary schematic diagram of a method for controlling etching in some embodiments of the present invention is shown, Figure 8 As shown, in these embodiments, after the back-side etching marks are detected on the wafer, the adjustment method of the distance between the component controlling the etching of the wafer in the etcher and the wafer can be fed back to the etcher machine according to the set calculation formula or related data in the APC. After the etcher machine is adjusted, the product production continues, thereby forming a closed loop of real-time monitoring and real-time adjustment, thereby improving the precision of the wafer edge etching process and the yield of semiconductor products.

[0053] Furthermore, the present invention discloses a device for controlling etching, comprising: a processor configured to execute program instructions; and a memory configured to store program instructions, so that when the program instructions are loaded and executed by the processor, the device executes the method described in the previous embodiments of the present invention.

[0054] Figure 9 FIG. 9 is a block diagram showing a hardware configuration of an apparatus 900 that can implement an embodiment of the present invention. Figure 9As shown, the apparatus 900 may include a processor 901 and a memory 902. The processor is configured to execute program instructions, and the memory is configured to store program instructions. When the program instructions are loaded and executed by the processor, the apparatus executes the method for controlling etching according to any one of the above embodiments. Figure 9 In the device 900, only the components related to this embodiment are shown. Therefore, it is obvious to those skilled in the art that the device 900 may also include Figure 9 The specific functions implemented by the memory 902 and the processor 901 of the device 900 provided in the embodiment of this specification can be explained in comparison with the aforementioned implementations in this specification, and can achieve the technical effects of the aforementioned implementations, so they will not be repeated here.

[0055] The apparatus 900 may correspond to a computing device having various processing functions. For example, the apparatus 900 may be implemented as various types of devices, such as a personal computer (PC), a server device, a mobile device, and the like.

[0056] The processor 901 can control the operation of the device 900. For example, the processor 901 can be implemented by a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), an artificial intelligence processor chip (IPU), etc. provided in the device 900. However, the present invention is not limited to this. In this embodiment, the processor 901 can be implemented in any appropriate manner. For example, the processor 901 can take the form of a microprocessor or a processor and a computer-readable medium storing computer-readable program code (such as software or firmware) that can be executed by the (micro)processor, a logic gate, a switch, an application-specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller, etc.

[0057] Memory 902 can be used to store various data and instructions processed by device 900. For example, memory 902 can store processed data and data to be processed by device 900. Memory 902 can also store data processed or to be processed by processor 901, such as data on the width of etch marks detected on the backside of a wafer. Furthermore, memory 902 can store applications and driver programs to be driven by device 900. For example, memory 902 can store various programs related to methods for controlling etching to be executed by processor 901. Memory 902 can be DRAM, but the present invention is not limited thereto. Memory 902 can include at least one of volatile memory and non-volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), and the like. The volatile memory may include dynamic RAM (DRAM), static RAM (SRAM), synchronous DRAM (SDRAM), PRAM, MRAM, RRAM, ferroelectric RAM (FeRAM), etc. In some embodiments, the memory 902 may include at least one of a hard disk drive (HDD), a solid-state drive (SSD), a high-density flash memory (CF), a secure digital (SD) card, a micro secure digital (Micro-SD) card, a mini secure digital (Mini-SD) card, an extreme digital (xD) card, caches, or a memory stick.

[0058] Furthermore, the present invention discloses a computer-readable storage medium storing program instructions, wherein the program instructions are suitable for being loaded by a processor and executing the methods described in the above embodiments of the present invention.

[0059] Furthermore, the present invention discloses an etching system, comprising: an etching mark detection device, configured to: detect the width of the etch mark on the back side of the etched wafer; an etching machine, configured to: etch the wafer; and adjust the distance between the component in the etching machine that controls the etching of the wafer and the wafer according to the width of the etch mark on the back side detected by the etch mark detection device.

[0060] In summary, the specific functions implemented by the device for controlling etching, computer-readable storage medium, and etching system provided in the embodiments of this specification can be interpreted in comparison with the aforementioned embodiments in this specification, and can achieve the technical effects of the aforementioned embodiments, so they will not be repeated here.

[0061] It should be noted that, for the purpose of simplicity, the present invention describes some methods and embodiments thereof as a series of actions and combinations thereof, but those skilled in the art will understand that the scheme of the present invention is not limited by the order of the described actions. Therefore, based on the disclosure or teachings of the present invention, those skilled in the art will understand that some of the steps therein can be performed in other orders or simultaneously. Further, those skilled in the art will understand that the embodiments described in the present invention can be regarded as optional embodiments, that is, the actions or modules involved therein are not necessarily necessary for the implementation of one or more schemes of the present invention. In addition, depending on the different schemes, the present invention also has different emphases on the description of some embodiments. In view of this, those skilled in the art will understand that the parts that are not described in detail in a certain embodiment of the present invention may also refer to the relevant descriptions of other embodiments.

Claims

1. A method for controlling edge etching, characterized in that include: Detecting the width of etch marks on the backside of etched wafers; Adjusting the distance between a component controlling etching of the wafer and the wafer in the etcher according to the width of the backside etching mark; The components of the etcher that control the etching of the wafer include an upper electrode assembly for defining the etching area; Adjusting the distance between a component controlling etching of the wafer in the etcher and the wafer according to the width of the backside etch mark includes: In response to a width of the backside etch mark being greater than a width threshold, increasing a distance between the component and the wafer; In response to the width of the backside etch mark being less than a width threshold, the distance between the component and the wafer is reduced.

2. The method according to claim 1, characterized in that Inspecting the width of etch marks on the backside of etched wafers includes: Detect the extension length of the backside etching mark from the edge of the wafer to the center of the wafer; The extended length is taken as the width of the backside etch mark.

3. The method according to claim 1, characterized in that Increasing the distance between the component and the wafer includes: raising the upper electrode assembly; Reducing the distance between the component and the wafer includes lowering the upper electrode assembly.

4. The method according to claim 1, wherein Further including: The width threshold is set according to a target etching area.

5. The method according to claim 1, wherein Adjusting the distance between a component controlling etching of the wafer in the etcher and the wafer according to the width of the backside etch mark includes: pass Calculate the distance adjustment amount; adjusting the distance between the component and the wafer according to the distance adjustment amount; Where y is the distance adjustment amount; A is the adjustment coefficient; x is the detection width of the backside etching mark; and z is a constant.

6. A device for controlling edge etching, characterized in that include: a processor configured to execute program instructions; as well as A memory configured to store the program instructions, which, when loaded and executed by the processor, causes the apparatus to perform the method according to any one of claims 1 to 5.

7. A computer-readable storage medium, characterized in that Program instructions are stored, and the program instructions are suitable for being loaded by a processor and executing the method according to any one of claims 1-5.

8. An edge etching system, characterized in that: include: An etch mark detection device is configured to: detect the width of an etch mark on the back side of an etched wafer; Etching machines configured to: Etching the wafer; as well as Adjusting the distance between a component controlling etching of the wafer and the wafer in the etcher according to the width of the backside etching mark detected by the etching mark detection device; The components of the etcher that control the etching of the wafer include an upper electrode assembly for defining the etching area; Adjusting the distance between a component controlling etching of the wafer in the etcher and the wafer according to the width of the backside etch mark includes: In response to a width of the backside etch mark being greater than a width threshold, increasing a distance between the component and the wafer; In response to the width of the backside etch mark being less than a width threshold, the distance between the component and the wafer is reduced.

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