Device electric leakage analysis method
By setting the efuse structure on the common gate of the CMOS device and fuse the polysilicon, the problem of difficulty in accurately positioning the leakage position of the CMOS device structure in the prior art is solved, and efficient leakage testing and positioning is achieved.
Patent Information
- Application Number
- CN202311742902.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-15
- Publication Date
- 2025-06-20
AI Technical Summary
It is difficult for the prior art to accurately locate the leakage failure position in the CMOS device structure, especially when the leakage current is very small, the accuracy of the test data is not high, and common methods such as PFA workload and low efficiency in detection.
By setting an efuse structure on the common gate between the PMOS device and the NMOS device, fuse the polysilicon in the common gate, and applying voltage or current through the efuse structure, the PMOS device or NMOS device is tested respectively to find the leakage position.
It improves the efficiency of leakage testing of CMOS device structure, can accurately locate the leakage failure position, and reduces the workload and test time.
Smart Images
Figure CN120184138A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of semiconductors, and particularly relates to a method for analyzing device leakage current. Background Art
[0002] The CMOS inverter structure includes an NMOS and a PMOS. The inverter is the core of all digital designs. With the development of semiconductor manufacturing processes, the size of the CMOS device structure has been reduced, and it is necessary to reduce the leakage current of the CMOS device structure in the off state. Detecting the leakage position of the CMOS device structure and measuring the leakage data are very important.
[0003] Conventional methods for testing the leakage current of the CMOS device structure include WAT (Wafer acceptance test). The corresponding test keys are tested by WAT, including separately testing the NMOS or PMOS, testing the metal silicide resistance, and testing parameters such as CT resistance / leakage current. However, when the leakage current in the CMOS device structure is very small, the WAT test method cannot accurately determine the leakage position, and the accuracy rate of the test data is not high. Other methods that can be used for the leakage failure analysis of the CMOS device structure include EFA (Electrical Failure Analysis) and PFA (Physical Failure Analysis). For example, the leakage failure position is located by EFA, and then whether there are bright voltage contrast defects in the transistor structure is detected by PFA. However, when the leakage current in the CMOS device structure is too small, PFA may not be able to determine the leakage source. If PFA is used to check whether there are abnormalities in the MOS region, the workload is very large, which will greatly reduce the work efficiency.
[0004] Therefore, it is necessary to provide an efficient analysis method that can accurately locate the leakage failure position. Summary of the Invention
[0005] The purpose of the present invention is to provide a method for analyzing device leakage current, which can improve the efficiency of leakage current testing of the CMOS device structure.
[0006] To achieve the above object, the present invention provides a method for analyzing device leakage current, which includes the following steps: providing a CMOS device structure to be tested; the CMOS device structure includes a PMOS device and an NMOS device formed on the same substrate, and the PMOS device and the NMOS device are connected through a common gate; an efuse structure is provided on the common gate; fusing the polysilicon in the common gate; performing a wafer acceptance test on the PMOS device and / or the NMOS device. The conditions for the fusing process include: the fusing voltage is 1 - 5V; or the fusing current is 1 - 20mA.
[0007] Optionally, the fusing voltage or current is input through an external via hole in the efuse structure.
[0008] Optionally, the polysilicon is fused by metal M1 disposed on the polysilicon.
[0009] Optionally, the metal M1 is copper and / or aluminum.
[0010] Optionally, the leakage current in the CMOS device structure is 0.01 - 1 nA.
[0011] Optionally, the method further includes: when the wafer undergoes testing, determining whether there is leakage based on whether there is current in the test circuit when the PMOS or the NMOS is turned off.
[0012] Optionally, the fuse in the efuse structure includes a fuse body and a pad connected to the fuse body, and the pad includes a cathode and an anode.
[0013] Optionally, the resistance value of the fuse before fusing is less than 500 Ω; and / or the resistance value of the fuse after fusing is 1×10 6 Ω or greater.
[0014] Optionally, one end of the efuse structure is connected to the gate of the PMOS device, and the other end is connected to the gate of the NMOS device.
[0015] Through the above technical solution, the present invention provides an efuse structure on the common gate between the PMOS device and the NMOS device, fuses the polysilicon in the common gate, and applies a voltage or current through the efuse structure to respectively test the PMOS device or the NMOS device to find the leakage location, thereby improving the testing efficiency.
[0016] Other features and advantages of the present invention will be described in detail in the subsequent specific implementation section. Brief Description of the Drawings
[0017] The drawings are used to provide a further understanding of the present invention, and constitute a part of the specification. Together with the following specific implementation, they are used to explain the present invention, but do not constitute a limitation to the present invention. In the drawings:
[0018] Figure 1 is a schematic structural diagram when the method provided by the present invention fuses the common gate through M1.
[0019] Figure 2 is a schematic diagram of the system of the leakage analysis method provided by the present invention. Detailed Description of the Invention
[0020] The following is a detailed description of the specific embodiments of the present invention. It should be understood that the specific embodiments described herein are only for explaining and illustrating the present invention, and are not used to limit the present invention.
[0021] The leakage failure analysis of the CMOS device structure is very important. Since the leakage current of a single device is very small, it is impossible to accurately locate the leakage position. If the metal is removed layer by layer to find the leakage position, the workload will be greatly increased.
[0022] The purpose of wafer acceptance test (WAT) is to detect the process conditions of each wafer product and evaluate the quality and stability of the semiconductor manufacturing process by testing the electrical parameters of specific test structures on the wafer. The test parameters of MOS transistors tested by the WAT test method include the threshold voltage V t , saturation current I dsat , source-drain breakdown voltage BVD, leakage current I off and substrate current I sub .
[0023] The inventor found that when using the WAT test unit to perform leakage failure analysis on the CMOS structure, when the leakage current level of the MOS transistor is very small, only testing the unassembled PMOS transistor or NMOS transistor cannot accurately determine whether the CMOS device structure leaks. When testing a CMOS device integrating multiple MOS transistors, since it is impossible to know whether it is the PMOS or the NMOS that leaks, it will take more time to test each MOS transistor one by one. For the foregoing reasons, the present invention proposes a device leakage analysis method.
[0024] In the present invention, the device leakage method mainly performs leakage failure analysis on the CMOS device structure.
[0025] As Figure 1 shown, the present invention provides a CMOS device structure, which includes a STI (shallow trench isolation) structure formed on a substrate 100 and well active regions located between the STI structures. The active regions include an n-well 221 and a p-well 222. Specifically, the CMOS device structure includes an NMOS transistor and a PMOS transistor located on the active region. Among them, the NMOS transistor is located on the p-well, and the PMOS transistor is located on the n-well.
[0026] The NMOS transistor and the PMOS transistor each independently include a source region, a drain region and a gate structure. Among them, the gate structure includes a gate electrode and a gate dielectric layer. A gate dielectric layer is provided between the gate electrode and the substrate, a protective layer is provided on the surface of the gate electrode, and sidewalls are provided on both sides of the gate dielectric layer, the gate electrode and the protective layer.
[0027] AsFigure 1 In the structure shown, the CMOS device structure includes a first STI structure 211, a second STI structure 212, and a third STI structure 213. A p-well 222 is formed between the first STI structure 211 and the second STI structure 212, and an n-well 221 is formed between the second STI structure 212 and the third STI structure 213. Figure 1 In the structure shown, the gate structure includes a first gate structure 311 disposed in the PMOS region, a second gate structure 312 disposed in the NMOS region, and a common gate 313 disposed between the PMOS region and the NMOS region. Both ends of the common gate 313 are respectively connected to the first gate structure 311 and the second gate structure 312, and the gate structure is integrally provided.
[0028] The present invention provides a method for analyzing device leakage current, and the method includes the following steps:
[0029] S1. Provide a CMOS device structure to be tested; the CMOS device structure includes a PMOS device and an NMOS device formed on the same substrate, and the PMOS device and the NMOS device are connected through a common gate; an efuse structure is provided on the common gate.
[0030] S2. Fuse the polysilicon in the common gate.
[0031] S3. Perform a wafer acceptance test (WAT test) on the PMOS device and / or the NMOS device.
[0032] Through the above technical solution, the present invention sets an efuse structure on the common gate between the PMOS device and the NMOS device to respectively measure the leakage current in the PMOS device or the leakage current in the NMOS device, so as to find out the leakage position.
[0033] An efuse (or electronic fuse) is an integrated circuit that can replace large conventional fuses or other protection devices, such as self - recovering polymer fuses. They are packaged in small plastics (such as DFN and flip - chip packages), integrate a control circuit and a power switch with low on - resistance, and connect the input port and the load.
[0034] The efuse structure belongs to a one - time programmable memory (OTP). The efuse technology stores information according to the electron migration theory by whether the fuse is blown by current or not. In traditional efuse structures, the fuses are mostly polysilicon. With the development of high - k materials, there are more choices for fuses, such as metal. The fuse is blown under continuous large current, and the resistance after blowing becomes infinite, and the blown state of the fuse can be permanently maintained.
[0035] Such as Figure 2As shown, the drains of the NMOS and PMOS are connected together to form a common output (Out) terminal. The source of the PMOS is connected to the power supply, and the source of the NMOS is connected to the ground wire. The input (In) terminal is the gate voltage of the two transistors.
[0036] The CMOS inverter is used for the conversion of "1→0" or "0→1". When a 1 (high voltage) is applied to the input terminal, the PMOS is cut off and the NMOS is turned on. At this time, the voltage on the ground wire (low voltage; 0) is output from the source S to the drain D of the NMOS, and the output is 0 (low voltage). When a 0 (low voltage) is applied to the input terminal, the PMOS is turned on and the NMOS is cut off. At this time, the voltage on the power supply (high voltage; VDD) is output from the source S to the drain D of the PMOS, and the output is 1 (high voltage).
[0037] It should be noted that the hardware devices involved in the WAT test in the embodiments of the present invention, such as test machines, etc. are existing devices.
[0038] Specifically, during the WAT test, the current parameters to be tested are the leakage current of the PMOS device and the leakage current of the NMOS device.
[0039] Among them, the leakage current of the PMOS device includes the current at the source of the PMOS device, the current at the drain of the PMOS device, the current at the first gate structure, and the leakage current at the body region end contact region of the PMOS device; and / or the leakage current of the NMOS device includes the current at the source of the NMOS device, the current at the drain of the NMOS device, the current at the second gate structure, and the leakage current at the body region end contact region of the NMOS device.
[0040] Among them, the above test method further includes the step of: obtaining the total width of the MOS transistors in the CMOS device structure to obtain the leakage current per unit width.
[0041] Among them, the measurement method includes: applying 1.1 times the maximum voltage to the drain, and respectively measuring and obtaining the total leakage current of the unit to be tested, the leakage current of the PMOS device, and the leakage current of the NMOS device.
[0042] In the present invention, the polysilicon structure in the common gate is subjected to a fusing process to measure the leakage current of the PMOS device or the leakage current of the NMOS device. Since the PMOS device and the NMOS device are connected through the common gate, before testing the CMOS device, it is not clear whether it is the PMOS device or the NMOS device that is leaking. After fusing the polysilicon in the common gate structure, the leakage tests can be respectively carried out on the PMOS device or the NMOS device. Specifically, the leakage test can be a test related to the CMOS leakage current in the WAT test.
[0043] Among them, the conditions for the fusing process include: fusing the polysilicon structure by using metal M1 disposed on the polysilicon. That is, a current is applied across the efuse through the metal. In some specific embodiments of the present invention, the conditions for the fusing process include: inputting 1 - 5V or inputting 1 - 20mA current into the efuse structure to fuse the polysilicon.
[0044] The polysilicon layer in the gate structure is fused through the M1 structure to respectively test the parameters of PMOS or NMOS devices, facilitating the analysis of the leakage current source, and thus analyzing and determining the leakage position. For example, the polysilicon between the first gate structure 311 and the common gate 313 can be fused through the first M1 structure 410, and the polysilicon between the second gate structure 312 and the common gate 313 can be fused through the second M1 structure 420.
[0045] In the present invention, "M1" refers to metal. In some specific embodiments, the metal is copper or aluminum, which is selected according to the specific applicable scenario.
[0046] In some embodiments of the present invention, during the WAT test, it is determined whether there is leakage according to whether there is current in the test circuit when the PMOS or the NMOS is turned off. For example, when the PMOS device is turned on and the NMOS device is turned off, in the theoretical state, the voltage output at the NMOS device should be 0. If there is a leakage current, the voltage output at the NMOS device will not immediately become 0, but is between 1 and 0, indicating that there is a leakage current in the NMOS device. Then, the NMOS device is analyzed for leakage according to the WAT test method.
[0047] By changing the voltage input to the efuse, the above method can be used to analyze the leakage of PMOS devices.
[0048] Specifically, the fusing voltage or fusing current is input through an external via in the efuse structure. The efuse structure includes a fuse, and the fuse includes a fuse body and a pad connected to the fuse body. Specifically, the pad includes a cathode and an anode. It should be noted that in the present invention, the connection between the cathode and anode of the efuse and the CMOS device is not specifically set, and it can be realized by being set on the common gate. For example, one end of the efuse is connected to the gate of the PMOS, and the other end is connected to the gate of the NMOS.
[0049] When testing the PMOS or the NMOS, the physical structure of the fuse with the fusing resistance is changed by electromigration or thermal fracture in the efuse structure, changing from a low impedance when not programmed to a high impedance. Specifically, the resistance value of the fuse before fusing is less than 500Ω; the resistance value of the fuse after fusing is 1×10 6 Ω or greater.
[0050] Among them, the leakage current in the CMOS device structure is 0.01 - 1 nA.
[0051] In a specific embodiment of the present invention, the method for analyzing the leakage of a CMOS device structure includes:
[0052] (1) Provide a CMOS device structure to be tested; the CMOS device structure includes a PMOS device and an NMOS device formed on the same substrate, and the PMOS device and the NMOS device are connected through a common gate; an efuse structure is provided on the common gate; the polysilicon in the common gate is blown.
[0053] (2) Input a current, control the PMOS device to turn on through the efuse structure, and turn off the NMOS device, and determine whether there is leakage according to the voltage output by the NMOS device; if there is leakage, measure the leakage current of the NMOS device; use the same method to determine whether the PMOS device leaks, and if there is leakage, measure the leakage current of the PMOS device.
[0054] Specifically, the method for measuring the leakage current of the PMOS device or the NMOS device may be:
[0055] To measure the leakage current of the NMOS device, first set to apply 1.1 times the maximum voltage, and measure the current at the source of the NMOS device, the current at the drain of the NMOS device, the current at the second gate structure, and the leakage current at the body region end contact area of the NMOS device; or to measure the leakage current of the PMOS device, first set to apply 1.1 times the maximum voltage, and measure the current at the source of the PMOS device, the current at the drain of the PMOS device, the current at the first gate structure, and the leakage current at the body region end contact area of the PMOS device.
[0056] The above method further includes: obtaining the total width value of all MOS transistors, and then obtaining the leakage current of a single MOS transistor.
[0057] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solutions of the present invention, and these simple modifications all belong to the protection scope of the present invention.
[0058] In addition, it should be noted that, in the case of no contradiction, the various specific technical features described in the above specific embodiments can be combined in any suitable manner. To avoid unnecessary repetition, the present invention will not separately describe various possible combination methods.
[0059] In addition, any combination can be made among various different embodiments of the present invention, as long as it does not violate the idea of the present invention, and it should equally be regarded as the content disclosed by the present invention.
Claims
1. A method for analyzing device leakage, characterized in that, The method includes the following steps: Providing a CMOS device structure to be tested; the CMOS device structure includes a PMOS device and an NMOS device formed on the same substrate, the PMOS device and the NMOS device are connected through a common gate; an efuse structure is provided on the common gate; Fusing the polysilicon in the common gate; Performing a wafer acceptance test on the PMOS device and / or the NMOS device.
2. The method according to claim 1, wherein, The conditions for the fusing process include: The fusing voltage is 1 - 5V; or The fusing current is 1 - 20mA.
3. The method according to claim 2, wherein, The fusing voltage or fusing current is input through an external via in the efuse structure.
4. The method according to claim 1, wherein, Fusing the polysilicon through a metal M1 provided on the polysilicon.
5. The method according to claim 4, wherein, The metal M1 is copper and / or aluminum.
6. The method according to claim 1, wherein, The leakage current in the CMOS device structure is 0.01 - 1nA.
7. The method according to claim 1, wherein, The method further includes: when performing the wafer acceptance test, judging whether there is leakage according to whether there is current in the test circuit when the PMOS or the NMOS is turned off.
8. The method according to claim 1, wherein, The fuse in the efuse structure includes a fuse body and a pad connected to the fuse body, and the pad includes a cathode and an anode.
9. The method according to claim 8, wherein, The resistance value of the fuse before fusing is less than 500 Ω; and / or the resistance value of the fuse after fusing is 1×10 6 Ω or greater.
10. The method according to claim 1, wherein, One end of the efuse structure is connected to the gate of the PMOS device, and the other end is connected to the gate of the NMOS device.