Quasi-closed-loop control method for DC-DC converter

Abstract

The invention discloses a quasi-closed-loop control method for a DC-DC converter in the technical field of power electronics, the main body is switching between voltage and current closed-loop control and open-loop control, and an optimized open-loop algorithm, so that when the load of the converter fluctuates, the closed loop obtains the control right and then can make a smoother and faster response. When the converter is in a relatively stable on-load condition, the converter keeps voltage open-loop operation, and when the load change causes that the output voltage exceeds a set range or is over-current, the controller enters closed-loop regulation to stabilize the output voltage. According to the invention, duty ratio jitter introduced by links such as a load, feedback loop noise, a digital controller and the like is reduced, and the operation efficiency of the DC-DC converter can be improved; the voltage closed loop of the controller obtains the control right only in the transient state, the current closed loop of the controller obtains the control right only in the overcurrent state, and the calculation load of the digital controller is obviously reduced.

Description

Technical Field

[0001] The present invention relates to a quasi-closed-loop control method for a DC-DC converter in the field of power electronics technology. Background Art

[0002] With the global emphasis on renewable energy and the accelerating energy transition, energy storage systems, as an effective way of energy storage and utilization, have been widely applied in the power field. The DC-DC converter can achieve efficient conversion and flow of electric energy, providing key technical support for the stable operation and optimal control of energy storage systems.

[0003] Currently, DC-DC converters usually adopt digital control methods, that is, they sense voltage or current through analog-to-digital conversion (ADC) and achieve feedback control in a digital manner. Noise will be introduced in links such as the converter load, feedback / sampling loop, and digital controller, resulting in duty cycle jitter. When the duty cycle jitters, unknown low-frequency disturbances are introduced, causing the duty cycle of the switching device to be unstable under steady state, increasing the switching loss and passive device loss. Especially when the jitter causes frequent switching transitions, the switching loss may increase significantly, thereby reducing the overall efficiency of the converter. Duty cycle jitter also leads to instability of the output current and voltage, thus interfering with the stability of the control loop, making it difficult for the feedback system to accurately adjust the output, which will also increase the power consumption of the system. Summary of the Invention

[0004] The purpose of the present invention is to provide a quasi-closed-loop control method for a DC-DC converter.

[0005] To achieve the above purpose, the present invention provides a quasi-closed-loop control method for a DC-DC converter, including the following steps:

[0006] S1. Sample the voltage and current output by the DC-DC converter, and preset the voltage range [-α, +α] that can operate in open loop according to the application scenario, and the maximum current I max ;

[0007] S2. Calculate the error e v [n] of the output voltage and the error e i [n] of the output current;

[0008] S3. Perform operations through the voltage controller in the digital signal processor to obtain the alternative voltage duty ratio d v [n] and the alternative duty ratio d i [n];

[0009] S4. Compare d v [n] and d i [n] and take the minimum value as the duty ratio for controlling the switch.

[0010] Compared with the prior art, the beneficial effects of the present invention are as follows. When the DC-DC converter is under relatively stable load conditions, the DC-DC converter operates with voltage open-loop. When the load changes cause the output voltage to exceed the set range or overcurrent occurs, the controller enters closed-loop regulation to stabilize the output voltage. The duty cycle jitter introduced by links such as the load, feedback loop noise, and digital controller is reduced, and the operating efficiency of the DC-DC converter can be improved; the voltage closed-loop loop of the controller only obtains control rights during transient states, and the computational load of the digital controller is significantly reduced.

[0011] As a further improvement of the present invention, in S2, the error e v [n] is specifically as follows.

[0012] After the voltage value output by the DC-DC converter is divided by a resistor, it becomes a voltage sampling signal V with an amplitude of 0 to 3.3V. This is compared with the voltage reference value V ref to obtain the error e v [n], e v [n] = V ref -V;

[0013] The current output by the DC-DC converter is sampled. The current signal variable I converted into a digital quantity is compared with the current reference value I max to obtain the error e i [n], e i [n] = I max -I.

[0014] In this way, the error values of the sampled voltage and sampled current can be obtained respectively, which are used for logical judgment in subsequent steps.

[0015] As a further improvement of the present invention, in S3, when the voltage output error e v [n] is outside the voltage range of open-loop operation, a PI controller with two zeros and three poles is used, and its s-domain expression is as follows.

[0016]

[0017] Calculate d v [n], and update d v [n - 3] to d v [n - 2], d v [n - 2] to d v [n - 1], d v [n - 1] to d v [n] and d i [n - 1], e v [n - 1] to ev [n - 2], e v [n] is updated to e v [n - 1];

[0018] where s is the Laplace operator, d v [n] is the current alternative voltage duty cycle, d v [n - 1] is the previous alternative voltage duty cycle, d v [n - 2] is the alternative voltage duty cycle of the previous two times, d v [n - 3] is the alternative voltage duty cycle of the previous three times, e v [n] is the current alternative voltage error, e v [n - 1] is the previous alternative voltage error, e v [n - 2] is the alternative voltage error of the previous two times; C v (s) is a double - zero triple - pole PI controller, K v is the gain of the voltage transfer function, ω z1 、ω z2 is the zero - point angular frequency of the controller, ω p1 、ω p2 is the pole - point angular frequency of the controller.

[0019] When the PWM duty cycle d v [n] is outside the voltage range of open - loop operation for the voltage output error e v [n], it is used to compare with d i [n].

[0020] As a further improvement of the present invention, in S3, when the error e v [n] is within the voltage error range of open - loop operation, and when e v [n] is greater than 0, update the duty cycle d v [n - 1] of the previous sampling period to d v [n], d v [n - 3] and d i [n - 1], update - d v [n - 1] to d v [n - 2], update e v [n] to e v [n - 1], update - e v [n] to e v [n - 2];

[0021] where d v [n] is the alternative voltage duty cycle, d v [n - 1] is the previous alternative voltage duty cycle, d v[n - 2] is the voltage duty cycle of the previous two times, e v [n] is the current alternative voltage error, e v [n - 1] is the alternative voltage error of the previous time, e v [n - 2] is the alternative voltage error of the previous two times.

[0022] In this way, when the error e v [n] is within the voltage range of open - loop operation, the PWM duty cycle d v when [n] is greater than 0 is calculated, and d v [n] and d i [n] are compared.

[0023] As a further improvement of the present invention, in S3, when the error e v [n] is within the voltage range of open - loop operation, when e v [n] is less than 0, the duty cycle d v [n - 1] of the previous sampling period is updated to d v [n], d v [n - 2] and d i [n - 1], - d v [n - 1] is updated to d v [n - 3], e v [n] is updated to e v [n - 2], - e v the value of [n] is updated to e v [n - 1];

[0024] Among them, d v [n] is the alternative voltage duty cycle, d v [n - 1] is the alternative voltage duty cycle of the previous time, d v [n - 2] is the alternative voltage duty cycle of the previous two times, d v [n - 3] is the alternative voltage duty cycle of the previous three times, e v [n] is the current alternative voltage error, e v [n - 1] is the alternative voltage error of the previous time, e v [n - 2] is the alternative voltage error of the previous two times.

[0025] In this way, when the error e v [n] is within the voltage range of open - loop operation, the PWM duty cycle d v when [n] is less than 0 is calculated, and d v [n] is used to compare with d i [n].

[0026] As a further improvement of the present invention, in S3, through a single-zero double-pole PI controller, its s-domain expression is as follows:

[0027]

[0028] Calculate the current PWM duty cycle d i [n], update d i [n - 2] to d i [n - 1], update d i [n - 1] to d i [n], e i [n] to e i [n - 1].

[0029] Among them, s is the Laplace operator, d i [n] is the current alternative current duty cycle, d i [n - 1] is the previous alternative current duty cycle, d i [n - 2] is the alternative current duty cycle of the previous two times, e i [n] is the current alternative current error, e v [n - 1] is the previous alternative current error; C i (s) is a single-zero double-pole PI controller, K i is the gain of the transfer function of the current, ω z is the zero angular frequency of the controller, ω p is the pole angular frequency of the controller.

[0030] In this way, a new PWM duty cycle d i [n] can be calculated, and compared with d v [n] Description of the Drawings

[0031] Figure 1 is the control flow chart of the present invention.

[0032] Figure 2 is the circuit schematic diagram of the boost DC-DC converter of the present invention.

[0033] Figure 3 is the circuit schematic diagram of the phase-shifted full-bridge DC-DC converter of the present invention.

[0034] Figure 4 is the circuit schematic diagram of the voltage and current sampling of the present invention.

[0035] Figure 5 is the circuit schematic diagram of the control circuit of the present invention.

[0036] Figure 6Add the response comparison before and after assignment for the open-loop operation of the present invention (voltage open-loop / closed-loop control switching).

[0037] Figure 7 Add the response comparison before and after assignment for the open-loop operation of the present invention (voltage / current control switching).

[0038] Figure 8 Small-scale load shedding for the present invention.

[0039] Figure 9 Heavy load switching for the present invention.

[0040] Figure 10 Light load switching for the present invention.

[0041] Figure 11 Short circuit occurrence for the present invention.

[0042] Figure 12 Short circuit recovery for the present invention. Detailed implementation manners

[0043] The present invention will be further described below with reference to the accompanying drawings:

[0044] As Figure 1-11 shown, a quasi-closed-loop control method for a DC-DC converter includes the following steps;

[0045] S1. Sample the voltage and current output by the DC-DC converter, and preset the voltage range [-α, +α] that can operate in open-loop according to the application scenario, and the maximum current I max ;

[0046] S2. Calculate the error e v [n] of the output voltage and the error e i [n] of the output current;

[0047] After the voltage value output by the DC-DC converter is divided by a resistor, it becomes a voltage sampling signal V with an amplitude of 0 to 3.3V. Compare it with the voltage reference value V ref to obtain the error e v [n] of the output voltage, e v [n] = V ref -V;

[0048] Sample the current output by the DC-DC converter, and compare the converted digital current signal variable I with the current reference value I max to obtain the error e i [n] of the output current, e i [n] = I max -I.

[0049] S3. Calculate the alternative voltage duty ratio d through the operation of the voltage controller in the digital signal processor. v [n] and the alternative duty ratio d i [n];

[0050] When the voltage output error e v [n] is outside the voltage range of open-loop operation, a PI controller with two zeros and three poles is used, and its s-domain expression is as follows.

[0051]

[0052] Calculate d v [n], and update d v [n - 3] to d v [n - 2], d v [n - 2] is updated to d v [n - 1], d v [n - 1] is updated to d v [n] and d i [n - 1], e v [n - 1] is updated to e v [n - 2], e v [n] is updated to e v [n - 1];

[0053] Among them, s is the Laplace operator, d v [n] is the current alternative voltage duty ratio, d v [n - 1] is the previous alternative voltage duty ratio, d v [n - 2] is the alternative voltage duty ratio of the previous two times, d v [n - 3] is the alternative voltage duty ratio of the previous three times, e v [n] is the current alternative voltage error, e v [n - 1] is the previous alternative voltage error, e v [n - 2] is the alternative voltage error of the previous two times; C v (s) is a PI controller with two zeros and three poles, K v is the gain of the transfer function of the voltage, ω z1 、ω z2 is the zero angular frequency of the controller, ω p1 、ω p2 is the pole angular frequency of the controller.

[0054] When the error e v [n] is within the voltage error range of open-loop operation, when e v [n] is greater than 0, update the duty ratio d v [n - 1] of the previous sampling period to dv [n], d v [n - 3] and d i [n - 1], -d v [n - 1] updated to d v [n - 2], e v [n] updated to e v [n - 1], -e v [n] updated to e v [n - 2];

[0055] Among them, d v [n] is the current alternative voltage duty cycle, d v [n - 1] is the previous alternative voltage duty cycle, d v [n - 2] is the voltage duty cycle of the previous two times, e v [n] is the current alternative voltage error, e v [n - 1] is the previous alternative voltage error, e v [n - 2] is the alternative voltage error of the previous two times.

[0056] When the error e v [n] is within the voltage range of open - loop operation, in the case where e v [n] is less than 0, the duty cycle d v [n - 1] of the previous sampling period is updated to d v [n], d v [n - 2] and d i [n - 1], -d v [n - 1] updated to d v [n - 3], e v [n] updated to e v [n - 2], -e v [n] value is updated to e v [n - 1];

[0057] Among them, d v [n] is the current alternative voltage duty cycle, d v [n - 1] is the previous alternative voltage duty cycle, d v [n - 2] is the alternative voltage duty cycle of the previous two times, d v [n - 3] is the alternative voltage duty cycle of the previous three times, e v [n] is the current alternative voltage error, e v [n - 1] is the previous alternative voltage error, e v [n - 2] is the alternative voltage error of the previous two times.

[0058] Through a single - zero double - pole PI controller, its s - domain expression is as follows:

[0059]

[0060] Calculate the current PWM duty cycle d i [n], and update d i [n - 2] to d i [n - 1], and update d i [n - 1] to d i [n], e i [n] to e i [n - 1].

[0061] Where s is the Laplace operator, d i [] is the current alternative current duty cycle, d i [n - 1] is the previous alternative current duty cycle, d i [n - 2] is the alternative current duty cycle of the previous two times, e i [n] is the current alternative current error, e v [n - 1] is the previous alternative current error; C i (s) is a single-zero double-pole PI controller, K i is the gain of the transfer function of the current, ω z is the zero angular frequency of the controller, ω p is the pole angular frequency of the controller.

[0062] S4. Compare d v [n] and d i [n], and take the minimum value as the duty cycle for controlling the switch.

[0063] In the present invention, the implementation carrier adopted includes a main circuit, a sampling circuit, a driving circuit, and a control circuit.

[0064] The main circuit, i.e., the DC-DC converter, includes an input DC power supply, an input inductor, a half-bridge circuit, an output capacitor, and a filter capacitor.

[0065] The sampling circuit includes a voltage sampling circuit and a current sampling circuit. The voltage sampling circuit includes two voltage-dividing resistors, and the current sampling circuit includes a current sampling chip and its peripheral circuits.

[0066] The driving circuit includes a driving chip, an isolation transformer, and a push-pull circuit.

[0067] The control circuit includes a digital signal processor, and the digital signal processor controls the output voltage and output current of the DC-DC converter.

[0068] Taking the non-isolated DC-DC converter as an example for specific illustration, such as Figure 2 , where V inis the input power supply, L is the input inductor, T is the power switch transistor, D is the diode, r is the equivalent impedance of the capacitor, C is the output capacitor, and R is the load.

[0069] The sampling circuit is as Figure 4 shown. The voltage sampling circuit includes a voltage-dividing circuit composed of resistor R1 and resistor R3, filtering capacitor C2, and filtering capacitor C4 connected in parallel across R3. The input terminal LOAD of the voltage sampling circuit is connected to the positive electrode of the load, and the output terminal A8 C11 of the voltage sampling circuit is connected to the digital signal processor. The current sampling circuit is connected in series with inductor L. The current sampling circuit includes a current sampling chip ACS712-30A. The current of inductor L flows into pins 1 and 2 of the current sampling chip ACS712-30A and flows out of pins 3 and 4, and is output at pin 7 and sent to the analog-to-digital conversion port of the digital signal processor.

[0070] As Figure 5 , the input terminals of the digital signal processor are respectively connected to the voltage sampling circuit and the current sampling circuit, and the output terminal of the digital signal processor is connected to the drive circuit, and the drive circuit is connected to the power transistor.

[0071] During operation, when the voltage output error e v [n] is within the open-loop operating voltage range, when e v [n] is greater than 0, update the duty cycle d v [n-1] of the previous sampling period to d v [n], d v [n-3] and d i [n-1], update -d v [n-1] to d v [n-2], update e v [n] to e v [n-1], update -e v [n] to e v [n-2]; when e v [n] is less than 0, update the duty cycle d v [n-1] of the previous sampling period to d v [n], d v [n-2] and d i [n-1], update -d v [n-1] to d v [n-3], update e v [n] to e v [n-2], update the value of -e v [n] to e v [n-1].

[0072] When the voltage output error ev When [n] is outside the open-loop operating voltage range, a digital PI controller with two zeros and three poles is used:

[0073]

[0074] Calculate d v [n], and update d v [n - 3] to d v [n - 2], d v Update d v [n - 2] to d v [n - 1], d v Update d i [n - 1] to d v [n], e v Update e v [n - 1] to e v [n - 1].

[0075] At the same time, sample the input current, and compare the current signal variable converted into a digital quantity with the current reference value I max Find the error through a digital PI controller with one zero and two poles:

[0076]

[0077] Calculate the new PWM duty cycle d i [n], and update d i [n - 2] to d i [n - 1], and update d i [n - 1] to d i [n], e i Update e i [n - 1]. Compare d v [n] and d i [n] obtained from the voltage and current control logics, and take the minimum value as the duty cycle for controlling the switch.

[0078] When the current is within the maximum value range I max , the control circuit performs closed-loop voltage control to regulate the converter voltage output within the target range, and then switches to open-loop control to maximize the operating efficiency of the converter; when increasing or decreasing the load, if the voltage exceeds the open-loop operating range, the voltage controller intervenes to generate the corresponding duty cycle until the voltage enters the open-loop operating range; when the load is too large and exceeds the current maximum limit I max , current closed-loop regulation naturally accesses, and the converter enters the current limiting I max operating state.

[0079] For the above strategy, when the voltage closed-loop is not involved, the intermediate registers for the operation of the pre-updated digital controller, such as d v [n - 2], e v [n - 1], etc., are updated so that after the operating state deviates from the voltage preset range, the digital controller can respond to the change requirement of the duty cycle in the first time, and quickly adjust the voltage back to the preset range and enter the open-loop operation again. Since the intermediate registers for the operation of the digital controller are updated only once before entering the closed-loop, the register values updated in the open-loop state do not affect the frequency-domain characteristics of the digital controller and have no impact on the stability of the DC-DC converter.

[0080] In the simulation, when the voltage open-loop control is switched to the voltage closed-loop control, the waveforms comparison of d v [n] and e v [n] without and with assignment are as follows Figure 6 , after the assignment as in Figure 1 , the regulation time of the voltage closed-loop control is significantly shortened; when the voltage control is switched to the current closed-loop control in the simulation, the waveforms comparison of d i [n] and e i [n] without and with assignment are as follows Figure 7 , after Figure 1 the assignment, the response speed is significantly accelerated, and the inductor current can be controlled to reach the target value more quickly. The duty cycle jitter introduced by links such as load, feedback loop noise, and digital controller is effectively reduced, and the operation efficiency of the DC-DC converter can be improved; the voltage closed-loop of the controller only obtains the control right during the transient state, and the calculation load of the digital controller is significantly reduced.

[0081] Verified by experiments, as Figures 8 to 12 , for the experimental waveforms, from top to bottom are the output voltage, input voltage, inductor current, and closed-loop intervention flag (high level represents open-loop control, low level represents closed-loop control intervention). Figure 8 For the waveforms when the load is switched within a small range, at this time the output voltage fluctuation does not exceed the set value range, and the controller maintains the open-loop control operation state; Figure 9 For the waveforms when the load increases, the process is the same as when the load decreases, and the duty cycle output by the controller also switches from voltage open-loop to voltage closed-loop and finally switches back to voltage open-loop; Figure 10 For the waveforms when the load decreases, at this time the inductor current decreases, and the output voltage increases to exceed the set value range, and the voltage closed-loop intervenes to adjust. When the voltage returns to the set value range, the voltage closed-loop control is switched; Figure 11 For the waveforms when the load is too large and enters overload, at this time the inductor current increases beyond the upper limit of the inductor current, the voltage closed-loop value gradually saturates upward, the current closed-loop value exits saturation, and the current closed-loop intervenes to control to maintain the inductor current at the upper limit value of the inductor current; Figure 12It is the waveform when the load exits the overload state. At this time, the current closed-loop value gradually increases to the upward saturation, the voltage closed-loop value exits saturation, and the voltage closed-loop intervenes in the control until the output voltage reaches the set value range, and then switches to the voltage open-loop control.

[0082] To expand the application scope of the present invention, the present invention is applicable to various DC-DC converters and power ranges. For example, the phase-shifted full-bridge DC-DC converter is also applicable (such as Figure 3 ). When the converter is under relatively stable load-carrying conditions, the converter keeps the phase-shift angle unchanged (open-loop). When the load changes cause the output voltage to exceed the set range or overcurrent occurs, the controller enters the phase-shift angle adjustment (closed-loop) to stabilize the output voltage.

[0083] The present invention is not limited to the above embodiments. Based on the technical solutions disclosed in the present disclosure, those skilled in the art can make some substitutions and deformations to some of the technical features without creative labor according to the disclosed technical content, and these substitutions and deformations are all within the protection scope of the present invention.

Claims

1. A quasi-closed-loop control method for a DC-DC converter, characterized in that: The steps include: S1. Sample the voltage and current output by the DC-DC converter, and preset the voltage range [-α, +α] for open-loop operation and the maximum current I according to the application scenario. max ; S2. Calculate the output voltage error e v [n] and the error e of the output current i [n]; S3, the voltage controller in the digital signal processor performs calculation to obtain the alternative voltage control ratio d v [n] and the alternative duty cycle d i [n]; S4, d v [n] and d i [n] compare and take the minimum value as the duty cycle to control the switch.

2. A quasi-closed-loop control method for a DC-DC converter according to claim 1, characterized in that: In S2, calculate the output voltage error e v [n] The specific content is as follows: the voltage value output by the DC-DC converter is converted into a voltage sampling signal V with an amplitude of 0 to 3.3V after being divided by resistors. ref Compare the output voltage error e v [n],e v [n] = V ref -V; The output current of the DC-DC converter is sampled and the current signal variable I converted into a digital quantity is compared with the current reference value I max Compare and find the output current error e i [n],e i [n]=I max -I.

3. A quasi-closed-loop control method for a DC-DC converter according to claim 2, characterized in that: In S3, when the voltage output error e v When [n] is outside the voltage range of open-loop operation, a double-zero three-pole PI controller is used, and its s-domain expression is as follows: Calculate d v [n], and put d v [n-3] Update to d v [n-2], d v [n-2] Update to d v [n-1], d v [n-1] Update to d v [n] and d i [n-1], e v [n-1] Update to e v [n-2], e v [n] Update to e v [n-1]; Among them, s is the Laplace operator, d v [n] is the current alternative voltage duty cycle, d v [n-1] is the last selected voltage duty cycle, d v [n-2] is the duty cycle of the last two alternative voltages, d v [n-3] is the duty cycle of the last three alternative voltages, e v [n] is the current alternative voltage error, e v [n-1] is the last alternative voltage error, e v [n-2] is the alternative voltage error of the last two times; C v (s) is a double-zero three-pole PI controller, K v is the gain of the voltage transfer function, ω z1 ,ω z2 is the zero angular frequency of the controller, ω p1 ,ω p2 is the pole angular frequency of the controller.

4. A quasi-closed-loop control method for a DC-DC converter according to claim 3, characterized in that: In S3, when the error e v [n] is within the voltage error range of open-loop operation. v When [n] is greater than 0, the duty cycle d of the previous sampling period is v [n-1] Update to d v [n], d v [n-3] and d i [n-1], put -d v [n-1] Update to d v [n-2], put e v [n] Update to e v [n-1], put -e v [n] Update to e v [n-2]; Among them, d v [n] is the current alternative voltage duty cycle, d v [n-1] is the last selected voltage duty cycle, d v [n-2] is the voltage duty cycle of the last two times, e v [n] is the current alternative voltage error, e v [n-1] is the last alternative voltage error, e v [n-2] is the alternative voltage error of the last two times.

5. A quasi-closed-loop control method for a DC-DC converter according to claim 4, characterized in that: In S3, when the error e v [n] is within the voltage range of open-loop operation, at e v When [n] is less than 0, the duty cycle d of the previous sampling period is v [n-1] Update to d v [n], d v [n-2] and d i [n-1], put -d v [n-1] Update to d v [n-3], put e v [n] Update to e v [n-2], put -e v The value of [n] is updated to e v [n-1]; Among them, d v [n] is the current alternative voltage duty cycle, d v [n-1] is the last selected voltage duty cycle, d v [n-2] is the duty cycle of the last two alternative voltages, d v [n-3] is the duty cycle of the last three alternative voltages, e v [n] is the current alternative voltage error, e v [n-1] is the last alternative voltage error, e v [n-2] is the alternative voltage error of the last two times.

6. A quasi-closed-loop control method for a DC-DC converter according to claim 5, characterized in that: In S3, the PI controller with a single zero and two poles has the following s-domain expression: Calculate the current PWM duty cycle d i [n], put d i [n-2] Update to d i [n-1], put d i [n-1] Update to d i [n],e i [n] Update to e i [n-1]. Among them, s is the Laplace operator, d i [n] is the current alternative current duty cycle, d i [n-1] is the last alternative current duty cycle, d i [n-2] is the last two alternative current duty cycles, e i [n] is the current alternative current error, e v [n-1] is the last alternative current error; C i (s) is a single-zero double-pole PI controller, K i is the gain of the current transfer function, ω z is the zero angular frequency of the controller, ω p is the pole angular frequency of the controller.

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