Accurate edge time sequence control circuit
By adopting precise edge control circuits in high-speed systems and using tap circuits and edge pool circuits to generate time-accurate pulses, the low operating frequency problem caused by timing violations in the prior art is solved, and the stability and user experience of the circuit are improved.
Patent Information
- Application Number
- CN202311757487.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-20
- Publication Date
- 2025-06-20
AI Technical Summary
The prior art in high-speed systems has low operating frequency due to timing violations, and glitches may occur after rapid switching of coarse clocks, affecting the normal operation of the second-level flip-flop.
The precise edge control circuit is used to delay the digital configuration information through the beat circuit, and the advance, current and lag beat information that delays the clock cycle in turn, and pulses of the drive edge and return edge with precise time controlled time are generated through the edge pool circuit.
It improves the operating frequency and stability of edge control circuits, increases the time margin of EG circuits, improves the quality of coarse clocks, and optimizes the user data input method, improving the user experience.
Smart Images
Figure CN120185588A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of circuit technology and the field of chip testing technology, and relates to an accurate edge timing control circuit. Background Art
[0002] In recent years, a large number of digital chips have been produced on the market, and the operating frequencies of digital chips have been increasing day by day. The integrated circuit test equipment (ATE) can automatically and efficiently test chips, which brings great convenience to the production of chips. Among them, in order to test the digital pins or digital functions of chips, it is a very efficient method to use the digital waveform generator of the digital circuit test module of ATE, which can meet the needs of large-scale testing in factories. At the same time, as the operating frequency of digital chips becomes faster and faster, the working clock basically operates above 100 MHz, belonging to a high-speed system. In a high-speed system, the setup time and hold time that the chip pins can normally work will also become an important issue.
[0003] The digital waveform generator of the digital circuit test module of the current ATE automatic test machine on the market has two functions: First, it can generate 0 to 1 drive edge and 0 to 1 return edge at the user-specified moment within one system clock cycle according to the user's requirements. In this way, a high-speed waveform pattern is generated as an excitation signal and input into the device under test for testing. Second, it can sample the output signal of the device under test at the specified moment within one system clock cycle according to the user's requirements, and compare it with the user's expected result to inform the user of the error location.
[0004] For example, for the test of a D flip-flop, as shown in the appendix Figure 1 ... It is necessary to input a clock and an input data to the flip-flop and collect an output data. First, judge whether the flip-flop can work normally (function verification) by giving reasonable timing. Give a rising edge to the clock and a stable input data for a long time, and collect whether there is a correct output result. Next, according to the rising edge of the clock, adjust the moment when the input data changes. Before the rising edge of the clock arrives, the input data changes at a certain moment. When the time interval between this moment and the rising edge of the clock can just make the flip-flop output the correct result, it is considered that this time interval is the minimum data setup time. Similarly, change the data at a certain moment after the rising edge of the clock so that the flip-flop can just output the correct result, and this time interval is the minimum hold time.
[0005] Currently, in the existing circuit that can accurately control the edge position, as shown in the appendix Figure 2 ... It can be seen that in the figure (a) edge control circuit (Edge Generator, abbreviated as EG), when the upper en iWhen = 1, it will cause the flip - flop 1 to reverse at the rising edge of clk, thus generating an edge signal. At the same time, the selector below selects a multi - phase clock (6 - φ clock) for the coarse - tuning of the delay time. After passing through the PDL (programmable delay chain), precise delay information is generated. Finally, the flip - flop samples the edge signal of the upper flip - flop at a determined moment, so that ultimately an edge signal with an accurate delay time can be output at w i Output an edge signal with an accurate delay time. As can be seen in Fig. (b), by combining multiple EGs into an EG Pool and finally combining multiple edge signals through an exclusive - OR gate, a complete output signal is generated.
[0006] Currently, in the existing technical solutions, since the circuit selects multiple multi - phase clocks in the data from the first flip - flop to the second flip - flop, timing violations are very likely to occur (the setup time and hold - time margins are compressed), resulting in a low operating frequency of the circuit. In order to solve the problem of the low operating frequency of the circuit, the existing technology uses multiple EG circuits to work, so as to achieve a faster generation of Patterns (digital waveform patterns). In addition, when the coarse - tuned multi - phase clock switches rapidly and after passing through the PDL, a glitch may be generated at the clock input of the second - stage flip - flop, or the signal quality is poor, thus affecting the normal operation of the second - stage flip - flop. Summary of the Invention
[0007] In view of the above analysis, the present invention aims to disclose an accurate edge timing control circuit to improve the operating frequency and stability of the edge control circuit.
[0008] The present invention discloses an accurate edge control circuit, including a clock - ticking circuit and an edge - pool circuit;
[0009] The clock - ticking circuit is used to perform delay - ticking processing on the input digital configuration information and output early - tick, current - tick, and late - tick information with clock cycles delayed in sequence;
[0010] The front and rear half - part data of the digital configuration information are used to configure the driving edge and the returning edge of the output pulse;
[0011] The edge - pool circuit is used to generate a pulse corresponding to the digital configuration information, including a driving edge and a returning edge with precise time control, according to the information output by the clock - ticking circuit;
[0012] In the edge - pool circuit, the input current - tick and early - tick information are combined as the control information for generating the edge in the first half - cycle, and the input late - tick and current - tick information are combined as the control information for generating the edge in the second half - cycle. The driving edge and the returning edge located in the first and second half - cycles are generated respectively, and then after edge synthesis, a pulse with precise edge - time control is output.
[0013] Further, in the digital configuration information for configuring the drive edge and return edge of the output pulse for each frame, the first half of the data includes the fine delay adjustment, coarse delay adjustment, and edge setting data of the drive edge and return edge, and the second half of the data includes the fine delay adjustment, coarse delay adjustment, and edge setting data of the return edge.
[0014] Further, the digital configuration information further includes control word information for setting whether the drive edge and return edge are to send waveforms to the device under test or capture data from the device under test, and a comparison value for setting the data captured from the device under test.
[0015] Further, in the beat circuit, compared with the information before the beat, the output of the early beat after the beat is delayed by half a system clock cycle, the current beat is delayed by one system clock cycle, and the late beat is delayed by two system clock cycles.
[0016] Further, the beat circuit includes: a first flip-flop, a second flip-flop, and a third flip-flop;
[0017] Among them, the first flip-flop and the second flip-flop are rising edge flip-flops, and the third flip-flop is a falling edge flip-flop;
[0018] The clock input terminals of the first, second, and third flip-flops are connected to the system clock;
[0019] The data input terminals of the first and third flip-flops are connected to the serial data of the digital configuration information; the data input terminal of the second flip-flop is connected to the output terminal of the first flip-flop;
[0020] The output terminal of the first flip-flop outputs data as the current beat information;
[0021] The output terminal of the second flip-flop outputs data as the late beat information;
[0022] The output terminal of the third flip-flop outputs data as the early beat information.
[0023] Further, the edge pool circuit includes a negative clock cycle working group circuit, a positive clock cycle working group circuit, and an edge combination circuit;
[0024] The input signals of the negative clock cycle working group circuit include the current beat and early beat information, and the system negative clock; the system negative clock is opposite in phase to the clock signal of the system clock;
[0025] According to the edge setting data in the current beat and early beat information, under the drive of the system negative clock, edge generation enabling is performed, and under the adjustment of the coarse delay and fine delay, the drive edge and return edge of the first half cycle of the next system cycle are generated;
[0026] The input signals of the positive clock cycle working group circuit include the current beat and the lag beat information, as well as the system positive clock; the system positive clock is in phase with the clock signal of the system clock;
[0027] According to the edge setting data in the current beat and the lag beat information, under the drive of the system positive clock, edge generation enabling is performed, and under the adjustment of delay coarse tuning and delay fine tuning, the drive edge and the return edge of the second half cycle of the current system cycle are generated;
[0028] The edge combination circuit combines the output edges of the negative clock cycle working group circuit and the positive clock cycle working group circuit, and then performs edge synthesis to output a pulse with precise edge time control.
[0029] Further, the negative clock cycle working group circuit includes a first EG circuit; the first EG circuit is a negative clock working group drive edge generation circuit; it includes a first exclusive-OR gate, a fourth flip-flop, a first inverter, a fifth flip-flop, a first clock coarse delay generation module, a first selector, and a first delay line;
[0030] The first exclusive-OR gate is a two-input exclusive-OR gate, and the two input terminals of the first exclusive-OR gate are respectively connected to the edge setting data of the return edge of the current beat and the edge setting data of the drive edge of the previous beat; the output terminal of the first exclusive-OR gate is connected to the data input terminal of the fourth flip-flop;
[0031] A monostable circuit is formed by connecting the data input terminal and the data output terminal of the fifth flip-flop in reverse through the first inverter;
[0032] The clock input terminal of the fourth flip-flop is connected to the system negative clock; the data output terminal is connected to the enable terminal of the fifth flip-flop to enable control of the monostable circuit;
[0033] After the first clock coarse delay generation module and the first selector are connected, the output terminal of the first selector is connected to the clock input terminal of the fifth flip-flop to output a clock signal to the monostable circuit;
[0034] The output terminal of the fifth flip-flop is connected to the input terminal of the first delay line, and the output terminal of the first delay line is used as the output terminal of the first EG circuit;
[0035] Among them, the first clock coarse delay generation module is used to generate multiple clock signals with the same frequency as the system clock and with a phase difference between each path; the multiple clock signals are input in parallel to each input terminal of the first selector;
[0036] The selection control terminal of the first selector is connected to the delay coarse tuning data of the drive edge of the previous beat; under the control of the delay coarse tuning data, 1 path of clock signal is selected from the input multiple clock signals and output from the output terminal of the first selector;
[0037] The delay control terminal of the first delay line is connected to the fine delay setting of the driving edge of the early shot for the delay control of the first delay line.
[0038] Further, the negative clock cycle working group circuit includes a second EG circuit; the second EG circuit is a circuit for generating the return edge of the negative clock working group; it includes a second exclusive-OR gate, a sixth flip-flop, a second inverter, a seventh flip-flop, a second clock coarse delay generation module, a second selector, and a second delay line;
[0039] The second exclusive-OR gate is a two-input exclusive-OR gate, and the two input terminals of the second exclusive-OR gate are respectively connected to the edge setting data of the driving edge of the early shot and the edge setting data of the return edge of the early shot; the output terminal of the second exclusive-OR gate is connected to the data input terminal of the sixth flip-flop;
[0040] A monostable circuit is formed by connecting the data input terminal and the data output terminal of the seventh flip-flop in reverse through the second inverter;
[0041] The clock input terminal of the sixth flip-flop is connected to the system negative clock; the data output terminal is connected to the enable terminal of the seventh flip-flop to enable the monostable circuit;
[0042] After the second clock coarse delay generation module and the second selector are connected, the output terminal of the second selector is connected to the clock input terminal of the seventh flip-flop to output a clock signal to the monostable circuit;
[0043] The output terminal of the seventh flip-flop is connected to the input terminal of the second delay line, and the output terminal of the second delay line is used as the output terminal of the second EG circuit;
[0044] Among them, the second clock coarse delay generation module is used to generate multiple clock signals with the same frequency as the system clock and with a phase difference between each path; the multiple clock signals are input in parallel to the input terminals of the second selector;
[0045] The selection control terminal of the second selector is connected to the coarse delay data of the return edge of the early shot; under the control of the coarse delay data, 1 path of clock signal is selected from the input multiple clock signals and output from the output terminal of the second selector;
[0046] The delay control terminal of the second delay line is connected to the fine delay setting of the return edge of the early shot for the delay control of the second delay line.
[0047] Further, the positive clock cycle working group circuit includes a third EG circuit; the third EG circuit is a circuit for generating the driving edge of the positive clock working group; it includes a third exclusive-OR gate, an eighth flip-flop, a third inverter, a ninth flip-flop, a third clock coarse delay generation module, a third selector, and a third delay line;
[0048] The third exclusive-OR gate is a two-input exclusive-OR gate. The two input terminals of the third exclusive-OR gate are respectively connected to the edge setting data of the return edge of the lagging beat and the edge setting data of the driving edge of the current beat. The output terminal of the third exclusive-OR gate is connected to the data input terminal of the eighth flip-flop.
[0049] A monostable circuit is formed by connecting the data input terminal and the data output terminal of the ninth flip-flop in reverse through the third inverter.
[0050] The clock input terminal of the eighth flip-flop is connected to the system positive clock. The data output terminal is connected to the enable terminal of the ninth flip-flop to enable and control the monostable circuit.
[0051] After the third clock coarse delay generation module and the third selector are connected, the output terminal of the third selector is connected to the clock input terminal of the ninth flip-flop to output a clock signal to the monostable circuit.
[0052] The output terminal of the ninth flip-flop is connected to the input terminal of the third delay line, and the output terminal of the third delay line serves as the output terminal of the third EG circuit.
[0053] Among them, the third clock coarse delay generation module is used to generate multiple clock signals that are of the same frequency as the system clock and have a phase difference between each path. The multiple clock signals are input in parallel to the input terminals of the third selector.
[0054] The selection control terminal of the third selector is connected to the delay coarse adjustment data of the driving edge of the current beat. Under the control of the delay coarse adjustment data, 1 path of clock signal is selected from the input multiple clock signals and output from the output terminal of the third selector.
[0055] The delay control terminal of the third delay line is connected to the delay fine adjustment setting of the driving edge of the current beat to perform the delay control of the third delay line.
[0056] Further, the positive clock cycle working group circuit includes a fourth EG circuit. The fourth EG circuit is a positive clock working group return edge generation circuit, including a fourth exclusive-OR gate, a tenth flip-flop, a fourth inverter, an eleventh flip-flop, a fourth clock coarse delay generation module, a fourth selector, and a fourth delay line.
[0057] The fourth exclusive-OR gate is a two-input exclusive-OR gate. The two input terminals of the fourth exclusive-OR gate are respectively connected to the edge setting data of the return edge of the current beat and the edge setting data of the driving edge of the current beat. The output terminal of the fourth exclusive-OR gate is connected to the data input terminal of the tenth flip-flop.
[0058] A monostable circuit is formed by connecting the data input terminal and the data output terminal of the eleventh flip-flop in reverse through the fourth inverter.
[0059] The clock input terminal of the tenth flip-flop is connected to the system positive clock; the data output terminal is connected to the enable terminal of the eleventh flip-flop; the monostable circuit is enabled and controlled;
[0060] After the fourth clock coarse delay generation module and the fourth selector are connected, the output terminal of the fourth selector is connected to the clock input terminal of the eleventh flip-flop to output a clock signal to the monostable circuit;
[0061] The output terminal of the eleventh flip-flop is connected to the input terminal of the fourth delay line, and the output terminal of the fourth delay line serves as the output terminal of the fourth EG circuit;
[0062] Among them, the fourth clock coarse delay generation module is used to generate multiple clock signals with the same frequency as the system clock and with a phase difference between each path; the multiple clock signals are input in parallel to each input terminal of the fourth selector;
[0063] The selection control terminal of the fourth selector accesses the delay coarse adjustment data of the return edge of the current beat; under the control of the delay coarse adjustment data, 1 clock signal is selected from the input multiple clock signals and output from the output terminal of the fourth selector;
[0064] The delay control terminal of the fourth delay line accesses the delay fine adjustment setting of the return edge of the current beat to perform the delay control of the fourth delay line.
[0065] Further, the edge combination circuit performs an exclusive OR operation on the output edges of the negative clock cycle working group circuit and the positive clock cycle working group circuit and then outputs a pulse with precise edge time control.
[0066] One of the beneficial effects that the present invention can achieve is as follows:
[0067] The precise edge control circuit disclosed by the present invention adopts an alternating working mode of positive and negative clocks. By dividing different delay information according to the phases of the multi-phase clocks, after the division, the time margin left for the EG circuit will increase. At the same time, moving the PDL to the rear of the second-stage flip-flop will be able to improve the quality of the coarse-adjusted clock, and leave a delay time of one PDL for the time margin. The above two aspects effectively improve the working frequency of the circuit. Using the edge change enable signal (Edge_chage_en) generated by the exclusive OR comparison of the Return edge and the Edge edge greatly facilitates the input mode of user data. Compared with the existing solution where there is only whether an edge is generated, this circuit allows the user to set it to high / low, optimizing the user experience. BRIEF DESCRIPTION OF THE DRAWINGS
[0068] The drawings are only for the purpose of showing specific embodiments and are not considered to be a limitation of the present invention. Throughout the drawings, the same reference signs denote the same components;
[0069] Figure 1 It is a test waveform diagram of a D flip-flop;
[0070] Figure 2 It is a circuit structure diagram of the existing one that can precisely control the edge position;
[0071] Figure 3 It is a block diagram of the precise edge control circuit in the embodiment of the present invention;
[0072] Figure 4 It is a schematic diagram of the data configuration information format in the embodiment of the present invention;
[0073] Figure 5 It is a schematic diagram of the connection composition of the pipelining circuit in the embodiment of the present invention;
[0074] Figure 6 It is a waveform diagram after pipelining in the embodiment of the present invention;
[0075] Figure 7 It is a schematic diagram of the connection composition of the edge pool circuit in the embodiment of the present invention;
[0076] Figure 8 It is a schematic diagram of the connection composition of the first EG circuit in the embodiment of the present invention;
[0077] Figure 9 It is a schematic diagram of the connection composition of the second EG circuit in the embodiment of the present invention;
[0078] Figure 10 It is a schematic diagram of the connection composition of the third EG circuit in the embodiment of the present invention;
[0079] Figure 11 It is a schematic diagram of the connection composition of the fourth EG circuit in the embodiment of the present invention. Specific Embodiment
[0080] Next, the preferred embodiments of the present invention will be specifically described in conjunction with the accompanying drawings, where the accompanying drawings form a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention.
[0081] An embodiment of the present invention discloses a precise edge control circuit, as Figure 3 shown, including: a pipelining circuit and an edge pool circuit;
[0082] The pipelining circuit is used to perform delayed pipelining processing on the input digital configuration information (Data_Set) and output the early beat (Next_Set), current beat (Current_Set), and late beat information (Before_Set) with the clock cycles being successively delayed;
[0083] The front and rear half - part data of the digital configuration information are used to configure the driving edge and return edge of the output pulse;
[0084] An edge pool circuit, configured to generate a pulse with a driving edge and a return edge including precise time control corresponding to digital configuration information according to the information output by the clocking circuit.
[0085] In the edge pool circuit, the input current beat and early beat information are combined as the control information for generating the edge within the first half cycle, and the input late beat and current beat information are combined as the control information for generating the edge within the second half cycle, so as to generate the driving edge and the return edge respectively within the first and second half cycles, and then perform edge synthesis to output a pulse with precise edge time control.
[0086] Specifically, in the digital configuration information for configuring the driving edge or the return edge of the output pulse for each frame, the first half of the data includes the delay fine tuning, delay coarse tuning, and edge setting data of the driving edge and the return edge, and the second half of the data includes the delay fine tuning, delay coarse tuning, and edge setting data of the return edge.
[0087] The digital configuration information further includes control word information for setting whether the driving edge and the return edge are used to send waveforms to the device under test or capture data from the device under test, and a comparison value for setting the data captured from the device under test.
[0088] As Figure 4 shown, a specific example of digital configuration information is given; the format content of the data configuration information (Data_Set) in the example includes:
[0089] One frame of Data_Set data has a total of 32 bits, including the Drive edge setting information (DrvieEdgeSet) 101 of the high 16 bits and the Return edge setting information (ReturnEdgeSet) 102 of the low 16 bits; the data format of one edge has a total of 16 bits, which are respectively:
[0090] Edge setting - Edge SET bit, 104 in the figure: the 15th bit, used to set whether the waveform of this edge is 0 or 1;
[0091] Coarse delay setting - Coarse Delay bit, 107 in the figure: the 11th - 9th bits, used to set the coarse delay of this edge;
[0092] Delay fine tuning setting - Delay line bit, 108 in the figure: the 8th - 0th bits, used to set the fine delay of this edge.
[0093] In the application and test scenarios,
[0094] In the figure, 105, the 14th bit: Recv Or Send bit, used to set whether this edge is used to send waveforms to the device under test or capture data from the device under test;
[0095] In Figure 106, bits 13 - 12: Recv Res bit, used to set the comparison value for capturing data from the device under test.
[0096] Specifically, in the beating circuit, compared with the information before beating, the output of the early beat after beating is delayed by half a system clock cycle, the current beat is delayed by one system clock cycle, and the late beat is delayed by two system clock cycles.
[0097] As Figure 5 shown, the beating circuit includes: a first flip - flop 109, a second flip - flop 110, and a third flip - flop 111;
[0098] Among them, the first flip - flop 109 and the second flip - flop 110 are rising - edge flip - flops, and the third flip - flop 111 is a falling - edge flip - flop;
[0099] The clock input terminals of the first, second, and third flip - flops are connected to the system clock Sys_Clk;
[0100] The data input terminals of the first and third flip - flops are connected to the serial data of the digital configuration information (Data_Set); the data input terminal of the second flip - flop is connected to the output terminal of the first flip - flop;
[0101] The output terminal of the first flip - flop 109 outputs data as the current beat information;
[0102] The output terminal of the second flip - flop 110 outputs data as the late beat information;
[0103] The output terminal of the third flip - flop 111 outputs data as the early beat information.
[0104] Connect Data_Set as an input to the third flip - flop 111, the clock Sys_Clk as the negative clock - end input of the third flip - flop 111, and the output terminal of the third flip - flop 111 outputs to Next_Set. Next_Set is delayed by half a clock cycle relative to Data_Set and changes at the negative phase (falling edge) of the clock; Connect Data_Set as an input to the first flip - flop 109, the clock Sys_Clk as the positive clock - end input of the first flip - flop 109, and the first flip - flop 109 outputs to Current_Set. Current_Set is delayed by 1 clock cycle relative to Data_Set and changes at the positive phase (rising edge) of the clock; Connect the output terminal of the first flip - flop 109 as an input to the second flip - flop 110, the clock Sys_Clk as the positive clock - end input of the second flip - flop 110, and the output terminal of the second flip - flop 110 outputs to Before_Set. Before_Set is delayed by 2 clock cycles relative to Data_Set and changes at the positive phase (rising edge) of the clock.
[0105] After the above processing, the Data_Set is used to generate the early beat (Next_Set) with a half-beat delay, the current beat (Current_Set) with a one-beat delay, and the late beat (Before_Set) information with a two-beat delay.
[0106] The data in the early beat (Next_Set) includes: the delay coarse adjustment setting (next_DriveCoarseDelay), the delay fine adjustment setting (next_DrivedelicateDelay), and the edge setting (next_DriveEdgeSet) of the early beat drive edge; the delay coarse adjustment setting (next_ReturnCoarseDelay), the delay fine adjustment setting (next_ReturndelicateDelay), and the edge setting data (next_ReturnEdgeSet) of the early beat return edge;
[0107] The data in the current beat (Current_Set) includes: the delay coarse adjustment setting (Current_DriveCoarseDelay), the delay fine adjustment setting (Current_DrivedelicateDelay), and the edge setting data (Current_DriveEdgeSet) of the current beat drive edge; the delay coarse adjustment data (Current_ReturnCoarseDelay), the delay fine adjustment setting (Current_ReturndelicateDelay), and the edge setting data (Current_ReturnEdgeSet) of the current beat return edge;
[0108] The data in the late beat (Before_Set) includes: the delay coarse adjustment setting (Before_DriveCoarseDelay), the delay fine adjustment setting (Before_DrivedelicateDelay), and the edge setting data (Before_DriveEdgeSet) of the late beat drive edge; the delay coarse adjustment setting (Before_ReturnCoarseDelay), the delay fine adjustment setting (Before_ReturndelicateDelay), and the edge setting data (Before_ReturnEdgeSet) of the late beat return edge;
[0109] Specifically, the waveform diagram after the beat is as Figure 6 shown.
[0110] The edge pool circuit includes a negative clock cycle working group circuit, a positive clock cycle working group circuit, and an edge combination circuit;
[0111] The input signals of the negative clock cycle working group circuit include the current beat and the early beat information, as well as the system negative clock; the system negative clock is the inverse of the clock signal of the system clock;
[0112] According to the edge setting data in the current beat and the early beat information, under the drive of the system negative clock, edge generation enabling is performed, and under the adjustment of the delay coarse tuning and the delay fine tuning, the drive edge and the return edge of the first half cycle of the next system cycle are generated;
[0113] The input signals of the positive clock cycle working group circuit include the current beat and the late beat information, as well as the system positive clock; the system positive clock is in phase with the clock signal of the system clock;
[0114] According to the edge setting data in the current beat and the late beat information, under the drive of the system positive clock, edge generation enabling is performed, and under the adjustment of the delay coarse tuning and the delay fine tuning, the drive edge and the return edge of the second half cycle of the current system cycle are generated;
[0115] The edge combination circuit combines the output edges of the negative clock cycle working group circuit and the positive clock cycle working group circuit, and then performs edge synthesis to output a pulse with precise edge time control.
[0116] As Figure 7 shown, the edge pool circuit (PG Pool), the negative clock cycle working group circuit (Negative clockworking group Edge Gen), and the positive clock cycle working group circuit (Positive clock working groupEdge Gen) all include two EG circuits, namely the first EG circuit 112 (Negative clock working groupDrive Edge Gen), the second EG circuit 113 (Negative clock working group Return Edge Gen), and the third EG circuit 114 (Positive clock working group Drive Edge Gen), the fourth EG circuit 115 (Positive clock working group Return Edge Gen), which can respectively generate a drive edge and a return edge within one system clock cycle.
[0117] The negative clock working group will work during the negative phase (falling edge) of the system. Corresponding to the Next Edge Generator (Nextperiod Drive / Return Edge), namely modules 112 and 113 in the figure, it will read Next_Set to control the internal circuit to work. This working group is mainly responsible for generating the drive edge and return edge for the first half cycle relative to the next system clock cycle. The Negative clock working group Drive Edge Gen (module 112) needs to input current_ReturnEdgeSet and next_DriveEdgeSet, and the module working clock Sys_Clk_n (system negative clock). The module will judge whether to generate an edge based on current_ReturnEdgeSet and next_DriveEdgeSet, and then select the coarse-adjusted clock for the first half cycle according to the data of next_DriveEdgeSet, and finally generate the Drive edge for the first half cycle of the next cycle (if the Drive edge of the next cycle is in the second half cycle, no edge will be generated).
[0118] As Figure 8 shown, the first EG circuit 112 is a drive edge generation circuit for the negative clock working group; it includes a first exclusive-OR gate 117, a fourth flip-flop 118, a first inverter, a fifth flip-flop 119, a first clock coarse delay generation module 120, a first selector 121, and a first delay line 122;
[0119] The first exclusive-OR gate 117 is a two-input exclusive-OR gate. The two input terminals of the first exclusive-OR gate are respectively connected to the edge setting data of the return edge of the current beat and the edge setting data of the drive edge of the previous beat; the output terminal of the first exclusive-OR gate 117 is connected to the data input terminal of the fourth flip-flop 118;
[0120] A monostable circuit is formed by connecting a first inverter between the data input terminal and the data output terminal of the fifth flip-flop 119 in an inverse manner;
[0121] The clock input terminal of the fourth flip-flop 118 is connected to the system negative clock; the data output terminal is connected to the enable terminal of the fifth flip-flop 119 to enable control of the monostable circuit;
[0122] After the first clock coarse delay generation module 120 and the first selector 121 are connected, the output terminal of the first selector 121 is connected to the clock input terminal of the fifth flip-flop 119 to output a clock signal to the monostable circuit;
[0123] The output terminal of the fifth flip-flop 119 is connected to the input terminal of the first delay line 122, and the output terminal of the first delay line 122 is used as the output terminal of the first EG circuit;
[0124] Among them, the first clock coarse delay generation module 120 is used to generate multiple clock signals that are of the same frequency as the system clock and have a phase difference between each path; the multiple clock signals are input in parallel to each input terminal of the first selector 121; the range of the phase difference between the multiple clock signals and the system clock is 0° to 180°;
[0125] The selection control terminal of the first selector 121 accesses the delay coarse adjustment data of the leading edge of the early beat; under the control of the delay coarse adjustment data, 1 path of clock signal is selected from the input multiple clock signals and output from the output terminal of the first selector 121;
[0126] The delay control terminal of the first delay line 122 accesses the delay fine adjustment setting of the leading edge of the early beat to perform the delay control of the first delay line 122.
[0127] In a specific embodiment, the first clock coarse delay generation module 120 generates three clock signals that are of the same frequency as the system clock and have phase differences of 0°, 60°, and 120°, and the delay coarse adjustment data of the leading edge of the early beat is 3-bit control data.
[0128] In Figure 8In the circuit connection, the current cycle's return edge setting data current_ReturnEdgeSet and the previous cycle's drive edge setting data next_DriveEdgeSet are input into the exclusive-OR gate 117. The exclusive-OR gate 117 compares the return edge of the current cycle and the drive edge of the next cycle to confirm whether to generate the drive edge of the next cycle; that is, the exclusive-OR gate 117 outputs the Edge_change_en signal. The Edge_change_en signal is used as the data input terminal of the flip-flop 118, and the module working clock CLK_n (system negative clock) is input into the flip-flop 118. The flip-flop 118 samples the Edge_change_en to stabilize the enable signal. The selector 121 selects one of the polyphase clocks from the outputs of 120 as the coarse delay of the fine tuning according to the coarse time adjustment Coarse_TimeSet of the previous cycle's drive edge (since the negative clock working group is only responsible for generating the edges in the first half cycle of the next clock cycle, there are only 3 polyphase clocks 0 to 2). The coarse tuning clock selected by the selector 121 is used as the clock of the flip-flop 119, the output triggered by the flip-flop 118 is input as the clock enable signal of the flip-flop 119, and the output of the flip-flop 119 is inverted and looped back as the data input to the data input of the flip-flop 119. If the enable signal Edge_change_en of this cycle is valid, when the rising edge of the coarse delay clock arrives, the flip-flop 119 will flip once to generate an edge signal with coarse delay information. Finally, the Program Delay Line (PDL) of the first delay line 122 performs fine delay adjustment according to the PDL_TimeSet of Next_DriveSet, and outputs an edge with complete delay information.
[0129] As Figure 9 shown, the second EG circuit 113 is a return edge generation circuit for the negative clock working group; it includes a second exclusive-OR gate 123, a sixth flip-flop 124, a second inverter, a seventh flip-flop 125, a second clock coarse delay generation module 126, a second selector 127, and a second delay line 128;
[0130] The second exclusive-OR gate 123 is a two-input exclusive-OR gate. The two input terminals of the second exclusive-OR gate 123 are respectively connected to the edge setting data of the drive edge of the previous cycle and the edge setting data of the return edge of the previous cycle; the output terminal of the second exclusive-OR gate 123 is connected to the data input terminal of the sixth flip-flop 124;
[0131] A monostable circuit is formed by connecting the second inverter in reverse between the data input terminal and the data output terminal of the seventh flip-flop 125;
[0132] The clock input terminal of the sixth flip-flop 124 is connected to the system negative clock; the data output terminal is connected to the enable terminal of the seventh flip-flop 125 to enable the control of the monostable circuit;
[0133] After the second clock coarse delay generation module 126 and the second selector 127 are connected, the output end of the second selector 127 is connected to the clock input end of the seventh flip-flop 125 to output a clock signal for the monostable circuit;
[0134] The output end of the seventh flip-flop 125 is connected to the input end of the second delay line 128, and the output end of the second delay line 128 serves as the output end of the second EG circuit 113;
[0135] Among them, the second clock coarse delay generation module 126 is used to generate multiple clock signals that are of the same frequency as the system clock and have a phase difference between each path; the multiple clock signals are input in parallel to each input end of the second selector 127; the range of the phase difference between the multiple clock signals and the system clock is 0° to 180°;
[0136] The selection control end of the second selector 127 accesses the delay coarse adjustment data of the return edge of the early beat; under the control of the delay coarse adjustment data, 1 clock signal is selected from the input multiple clock signals and output from the output end of the second selector 127;
[0137] The delay control end of the second delay line 128 accesses the delay fine adjustment setting of the return edge of the early beat to perform the delay control of the second delay line 128.
[0138] In a specific embodiment, the first clock coarse delay generation module 127 generates three clock signals that are of the same frequency as the system clock and have phase differences of 0°, 60°, and 120°, and the delay coarse adjustment data of the return edge of the early beat is 3-bit control data.
[0139] In Figure 9In the circuit connection, the pre-taken drive edge and return edge setting data next_DriveEdgeSet and next_ReturnEdgeSet are input into the 123 exclusive-OR gate. The 123 compares the Return edge of the current cycle and the Drive edge of the next cycle to confirm whether to generate the Drive edge of the next cycle, that is, the 123 outputs the Edge_change_en signal. The Edge_change_en signal is used as the data input terminal of the flip-flop 124, and the module working clock CLK_n (system negative clock) is input into the flip-flop 124. The 124 samples the Edge_change_en to stabilize the enable signal. The lower selector 127 selects a polyphase clock from the Coarse_TimeSet of the Next_ReturnSet data as the coarse delay (since the negative clock working group is only responsible for generating the edges in the first half cycle of the next clock cycle, so there are only 3 polyphase clocks 0 to 2). The coarse clock selected by the 127 selector is used as the clock of the flip-flop 125, the output triggered by the 124 is input as the clock enable signal of the flip-flop 125, and the output of the 125 is fed back as the data input to the data input of the 125 flip-flop after inversion. If the enable signal Edge_change_en of this cycle is valid, when the rising edge of the coarse delay clock arrives, the flip-flop 125 will perform a flip to generate an edge signal with coarse delay information. Finally, the Program Delay Line (PDL) of 128 performs fine delay according to the PDL_TimeSet of the Next_ReturnSet, and outputs an edge with complete delay information.
[0140] The positive clock working group will work in the positive phase (falling edge) of the system. Corresponding to modules 114 and 115 in the (Positive clock workinggroup Drive Edge Gen) and (Positive clock working group Return Edge Gen) diagrams, it will read Current_Set to control the internal circuit to work. This working group mainly generates the Drive edge and Return edge in the second half of the current system clock cycle. The Positive clock working groupDrive Edge Gen (module 114) needs to input before_ReturnEdgeSet, current_DriveEdgeSet, and the module working clock Sys_Clk_p (system positive clock). Module 114 compares before_ReturnEdgeSet and current_DriveEdgeSet to determine whether to generate an edge, selects the coarse-tuning clock in the second half according to current_DriveEdgeSet, and finally generates the Drive edge in the second half of the current cycle (if the Drive edge of the current cycle is in the previous cycle, no edge is generated). The Positive clock working group Return Edge Gen (module 115) needs to input current_DriveEdgeSet, current_ReturnEdgeSet, and the module working clock Sys_Clk_p (system positive clock). Module 115 compares current_DriveEdgeSet and current_ReturnEdgeSet to determine whether to generate an edge, selects the coarse-tuning clock in the second half according to current_ReturnEdgeSet, and finally generates the Return edge in the second half of the current cycle (if the Return edge of the current cycle is in the first half, no edge is generated).
[0141] As Figure 10 shown, the third EG circuit 114 is a positive clock working group drive edge generation circuit; it includes a third exclusive-OR gate 129, an eighth flip-flop 130, a third inverter, a ninth flip-flop 131, a third clock coarse delay generation module 132, a third selector 133, and a third delay line 134;
[0142] The third exclusive-OR gate 129 is a two-input exclusive-OR gate. The two input terminals of the third exclusive-OR gate 129 are respectively connected to the edge setting data of the return edge of the previous beat and the edge setting data of the drive edge of the current beat; the output terminal of the third exclusive-OR gate 129 is connected to the data input terminal of the eighth flip-flop 130;
[0143] The data input terminal and the data output terminal of the ninth flip-flop 131 are reversely connected with a third inverter to form a monostable circuit;
[0144] The clock input terminal of the eighth flip-flop 130 is connected to the system positive clock; the data output terminal is connected to the enable terminal of the ninth flip-flop 131 to enable and control the monostable circuit;
[0145] After the third clock coarse delay generation module 132 and the third selector 133 are connected, the output terminal of the third selector 133 is connected to the clock input terminal of the ninth flip-flop 131 to output a clock signal to the monostable circuit;
[0146] The output terminal of the ninth flip-flop 131 is connected to the input terminal of the third delay line 134, and the output terminal of the third delay line 134 is used as the output terminal of the third EG circuit 114;
[0147] Among them, the third clock coarse delay generation module 132 is used to generate multiple clock signals with the same frequency as the system clock and with phase differences between channels; the multiple clock signals are input in parallel to the respective input terminals of the third selector 133; the range of the phase difference between the multiple clock signals and the system clock is 180° to 360°;
[0148] The selection control terminal of the third selector 133 accesses the delay coarse adjustment data of the driving edge of the current beat; under the control of the delay coarse adjustment data, 1 clock signal is selected from the input multiple clock signals and output from the output terminal of the third selector 133;
[0149] The delay control terminal of the third delay line 134 accesses the delay fine adjustment setting of the driving edge of the current beat to perform the delay control of the third delay line 134.
[0150] In a specific embodiment, the third clock coarse delay generation module 132 generates three clock signals with the same frequency as the system clock and with phase differences of 180°, 240°, and 300°, and the delay coarse adjustment data of the driving edge of the current beat is 3-bit control data.
[0151] In Figure 10In the circuit connection, before_RetrunEdgeSet and current_DriveEdgeSet are input into exclusive-OR gate 129. Exclusive-OR gate 129 compares the Return edge of the current cycle and the Drive edge of the next cycle to confirm whether the Drive edge of the next cycle needs to be generated, that is, exclusive-OR gate 129 outputs the Edge_change_en signal. The Edge_change_en signal is used as the data input terminal of flip-flop 130, and the module working clock CLK_n is input into flip-flop 130. Flip-flop 130 samples Edge_change_en to stabilize the enable signal. The lower selector 133 selects a polyphase clock from the Coarse_TimeSet of the current_DriveSet data as the coarse delay (since the positive clock working group is only responsible for generating the edges in the second half cycle of the current clock cycle, there are only 3 polyphase clocks 0 to 2). The coarse clock selected by selector 133 is used as the clock of flip-flop 131. The output triggered by 130 is input as the clock enable signal of flip-flop 131. The output of 131 is fed back as the data input to the data input of flip-flop 131 after inversion. If the enable signal Edge_change_en of this cycle is valid, when the rising edge of the coarse delay clock arrives, flip-flop 131 will flip once to generate an edge signal with coarse delay information. Finally, the Program Delay Line (PDL) of 134 performs fine delay according to the PDL_TimeSet of current_DriveSet, and outputs an edge with complete delay information.
[0152] As Figure 11 shown, the fourth EG circuit 115 is a return edge generation circuit for the positive clock working group; it includes a fourth exclusive-OR gate 135, a tenth flip-flop 136, a fourth inverter, an eleventh flip-flop 137, a fourth clock coarse delay generation module 138, a fourth selector 139, and a fourth delay line 140;
[0153] The fourth exclusive-OR gate 135 is a two-input exclusive-OR gate. The two input terminals of the fourth exclusive-OR gate 135 are respectively connected to the edge setting data of the return edge of the current beat and the edge setting data of the drive edge of the current beat; the output terminal of the fourth exclusive-OR gate 135 is connected to the data input terminal of the tenth flip-flop 136;
[0154] A monostable circuit is formed by connecting the fourth inverter in reverse between the data input terminal and the data output terminal of the eleventh flip-flop 137;
[0155] The clock input terminal of the tenth flip-flop 136 is connected to the system positive clock; the data output terminal is connected to the enable terminal of the eleventh flip-flop 137 to enable control of the monostable circuit;
[0156] After the fourth clock coarse delay generation module 138 and the fourth selector 139 are connected, the output end of the fourth selector 139 is connected to the clock input end of the eleventh flip-flop 137 to output a clock signal for the monostable circuit;
[0157] The output end of the eleventh flip-flop 137 is connected to the input end of the fourth delay line 140, and the output end of the fourth delay line 140 serves as the output end of the fourth EG circuit 115;
[0158] Among them, the fourth clock coarse delay generation module 138 is used to generate multiple clock signals that are of the same frequency as the system clock and have a phase difference between each path; the multiple clock signals are input in parallel to each input end of the fourth selector 139; the range of the phase difference between the multiple clock signals and the system clock is 180° to 360°;
[0159] The selection control end of the fourth selector 139 accesses the delay coarse adjustment data of the return edge of the current beat; under the control of the delay coarse adjustment data, 1 clock signal is selected from the input multiple clock signals and output from the output end of the fourth selector 139;
[0160] The delay control end of the fourth delay line 140 accesses the delay fine adjustment setting of the return edge of the current beat to perform the delay control of the fourth delay line 140.
[0161] In a specific embodiment, the fourth clock coarse delay generation module 138 generates three clock signals that are of the same frequency as the system clock and have phase differences of 180°, 240°, and 300°, and the delay coarse adjustment data of the return edge of the current beat is 3-bit control data.
[0162] In Figure 11In the circuit connection, current_DriveEdgeSet and current_ReturnEdgeSet are input into the 135 XOR gate. The 135 XOR gate compares the Return edge of the current cycle and the Drive edge of the next cycle to confirm whether the Drive edge of the next cycle needs to be generated, that is, the 135 XOR gate outputs the Edge_change_en signal. The Edge_change_en signal is used as the data input terminal of the flip-flop 130, and the module working clock CLK_n is input into the flip-flop 136. The 136 samples the Edge_change_en to stabilize the enable signal. The lower selector 139 selects a polyphase clock from the Coarse_TimeSet of the current_DriveSet data as the coarse delay (because the positive clock working group is only responsible for generating the edges in the second half cycle of the current clock cycle, so there are only 3 polyphase clocks 0 to 2). The coarse clock selected by the 133 selector is used as the clock of the flip-flop 131, the output triggered by the 130 is input as the clock enable signal of the flip-flop 131, and the output of the 131 is fed back as the data input to the data input of the 131 flip-flop after inversion. If the enable signal Edge_change_en of this cycle is valid, when the rising edge of the coarse delay clock arrives, the flip-flop 131 will perform a flip to generate an edge signal with coarse delay information. Finally, the Program Delay Line (PDL) of the 134 performs fine delay according to the PDL_TimeSet of the current_DriveSet, and outputs an edge with complete delay information.
[0163] Figure 7 In it, the edge combination circuit 116 includes a fifth XOR gate, a sixth XOR gate, and a seventh XOR gate; among them,
[0164] The fifth XOR gate is a two-input XOR gate; the two input terminals of the fifth XOR gate are respectively connected to the output terminals of the first EG circuit and the second EG circuit;
[0165] The sixth XOR gate is a two-input XOR gate; the two input terminals of the sixth XOR gate are respectively connected to the output terminals of the third EG circuit and the fourth EG circuit;
[0166] The seventh XOR gate is a two-input XOR gate; the two input terminals of the seventh XOR gate are respectively connected to the output terminals of the fifth XOR gate and the sixth XOR gate; the output terminal of the seventh XOR gate is used as the output terminal of the edge control circuit.
[0167] Optionally, the edge combination circuit can also be replaced by a 4-input XOR gate; the 4 edges output by the first, second, third, and fourth EG circuits are combined into an output pulse required by the user.
[0168] In summary, the precise edge control circuit disclosed in this embodiment adopts an alternating working mode of positive and negative clocks. By dividing different delay information according to the phases of the multi-phase clock, after the division, the time margin left for the EG circuit will increase. At the same time, moving the PDL to the rear of the second-stage flip-flop can improve the quality of the coarse-tuning clock and leave a delay time of one PDL for the time margin. The above two aspects effectively improve the working frequency of the circuit. Using the edge change enable signal (Edge_chage_en) generated by the exclusive-OR comparison of the Return edge and the Edge edge greatly facilitates the input mode of user data. Compared with the existing solution where only the presence or absence of an edge is considered, this circuit allows the user to set it to high / low, optimizing the user experience.
[0169] As described above, the above are only the preferred specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.
Claims
1. An accurate edge timing control circuit, characterized in that, It includes a clocking circuit and an edge pool circuit; The clocking circuit is used to perform a delayed clocking process on the input digital configuration information and output the early beat, current beat, and late beat information with the clock cycles being successively delayed; The first half and the second half of the data of the digital configuration information are used to configure the driving edge and the return edge of the output pulse; The edge pool circuit is used to generate a pulse corresponding to the digital configuration information and including a driving edge and a return edge with precise time control according to the information output by the clocking circuit; In the edge pool circuit, the input current beat and early beat information are combined as the control information for generating the edge within the first half cycle, and the input late beat and current beat information are combined as the control information for generating the edge within the second half cycle, so as to generate the driving edge and the return edge respectively within the first half and the second half cycles, and then perform edge synthesis to output a pulse with precise edge time control.
2. The accurate edge timing control circuit according to claim 1, characterized in that, In each frame of the digital configuration information for configuring the driving edge and the return edge of the output pulse, the first half of the data includes the fine delay adjustment, coarse delay adjustment, and edge setting data of the driving edge and the return edge, and the second half of the data includes the fine delay adjustment, coarse delay adjustment, and edge setting data of the return edge.
3. The accurate edge timing control circuit according to claim 2, characterized in that, The digital configuration information further includes control word information for setting whether the driving edge and the return edge are used to send waveforms to the device under test or capture data from the device under test, and a comparison value for setting the data captured from the device under test.
4. The accurate edge timing control circuit according to claim 2 or 3, characterized in that, In the clocking circuit, compared with the information before clocking, the output early beat is delayed by half a system clock cycle, the current beat is delayed by one system clock cycle, and the late beat is delayed by two system clock cycles after clocking.
5. The accurate edge timing control circuit according to claim 4, characterized in that, The clocking circuit includes: a first flip-flop, a second flip-flop, and a third flip-flop; Among them, the first flip-flop and the second flip-flop are rising-edge flip-flops, and the third flip-flop is a falling-edge flip-flop; The clock input terminals of the first, second, and third flip-flops are connected to the system clock; The data input terminals of the first and third flip-flops are connected to the serial data of the digital configuration information; the data input terminal of the second flip-flop is connected to the output terminal of the first flip-flop; The output terminal of the first flip-flop outputs data as the current beat information; The output terminal of the second flip-flop outputs data as the late beat information; The output terminal of the third flip-flop outputs data as the early beat information.
6. The accurate edge timing control circuit according to claim 5, characterized in that, The edge pool circuit includes a negative clock cycle working group circuit, a positive clock cycle working group circuit, and an edge combination circuit; The input signals of the negative clock cycle working group circuit include the current beat and early beat information, and the system negative clock; the system negative clock is opposite in phase to the clock signal of the system clock; According to the edge setting data in the current beat and early beat information, under the drive of the system negative clock, edge generation enabling is performed, and under the adjustment of the coarse delay adjustment and the fine delay adjustment, the driving edge and the return edge of the first half cycle of the next system cycle are generated; The input signals of the positive clock cycle working group circuit include the current beat and late beat information, and the system positive clock; the system positive clock is in phase with the clock signal of the system clock; According to the edge setting data in the current beat and the lag beat information, under the drive of the system positive clock, edge generation enabling is performed. Under the adjustment of delay coarse tuning and delay fine tuning, the drive edge and the return edge of the second half cycle of the current system period are generated; The edge combination circuit combines the output edges of the negative clock cycle working group circuit and the positive clock cycle working group circuit, and then performs edge synthesis to output a pulse with precise edge time control.
7. The accurate edge timing control circuit according to claim 6, characterized in that, The negative clock cycle working group circuit includes a first EG circuit; the first EG circuit is a negative clock working group drive edge generation circuit; It includes a first exclusive-OR gate, a fourth flip-flop, a first inverter, a fifth flip-flop, a first clock coarse delay generation module, a first selector, and a first delay line; The first exclusive-OR gate is a two-input exclusive-OR gate. The two input terminals of the first exclusive-OR gate are respectively connected to the edge setting data of the return edge of the current beat and the edge setting data of the drive edge of the previous beat; the output terminal of the first exclusive-OR gate is connected to the data input terminal of the fourth flip-flop; A monostable circuit is formed by connecting a first inverter in reverse between the data input terminal and the data output terminal of the fifth flip-flop; The clock input terminal of the fourth flip-flop is connected to the system negative clock; the data output terminal is connected to the enable terminal of the fifth flip-flop; enabling control is performed on the monostable circuit; After the first clock coarse delay generation module and the first selector are connected, the output terminal of the first selector is connected to the clock input terminal of the fifth flip-flop to output a clock signal to the monostable circuit; The output terminal of the fifth flip-flop is connected to the input terminal of the first delay line, and the output terminal of the first delay line is used as the output terminal of the first EG circuit; Among them, the first clock coarse delay generation module is used to generate multiple clock signals that are of the same frequency as the system clock and have a phase difference between each path; the multiple clock signals are input in parallel to each input terminal of the first selector; The selection control terminal of the first selector is connected to the delay coarse tuning data of the drive edge of the previous beat; under the control of the delay coarse tuning data, 1 path of clock signal is selected from the input multiple clock signals and output from the output terminal of the first selector; The delay control terminal of the first delay line is connected to the delay fine tuning setting of the drive edge of the previous beat to perform the delay control of the first delay line.
8. The precise edge timing control circuit according to claim 7, wherein, The negative clock cycle working group circuit includes a second EG circuit; the second EG circuit is a negative clock working group return edge generation circuit; It includes a second exclusive-OR gate, a sixth flip-flop, a second inverter, a seventh flip-flop, a second clock coarse delay generation module, a second selector, and a second delay line; The second exclusive-OR gate is a two-input exclusive-OR gate. The two input terminals of the second exclusive-OR gate are respectively connected to the edge setting data of the drive edge of the previous beat and the edge setting data of the return edge of the previous beat; the output terminal of the second exclusive-OR gate is connected to the data input terminal of the sixth flip-flop; A monostable circuit is formed by connecting a second inverter in reverse between the data input terminal and the data output terminal of the seventh flip-flop; The clock input terminal of the sixth flip-flop is connected to the system negative clock; the data output terminal is connected to the enable terminal of the seventh flip-flop; enabling control is performed on the monostable circuit; After the second clock coarse delay generation module and the second selector are connected, the output terminal of the second selector is connected to the clock input terminal of the seventh flip-flop to output a clock signal to the monostable circuit; The output terminal of the seventh trigger is connected to the input terminal of the second delay line, and the output terminal of the second delay line serves as the output terminal of the second EG circuit; Among them, the second clock coarse delay generation module is used to generate multiple clock signals that are of the same frequency as the system clock and have a phase difference between each path; the multiple clock signals are input in parallel to each input terminal of the second selector; The selection control terminal of the second selector accesses the delay coarse adjustment data of the return edge of the early beat; under the control of the delay coarse adjustment data, 1 clock signal is selected from the input multiple clock signals and output from the output terminal of the second selector; The delay control terminal of the second delay line accesses the delay fine adjustment setting of the return edge of the early beat to perform the delay control of the second delay line.
9. The precise edge timing control circuit according to claim 8, wherein, The positive clock cycle working group circuit includes a third EG circuit; the third EG circuit is a positive clock working group driving edge generation circuit; It includes a third exclusive-OR gate, an eighth trigger, a third inverter, a ninth trigger, a third clock coarse delay generation module, a third selector, and a third delay line; The third exclusive-OR gate is a two-input exclusive-OR gate. The two input terminals of the third exclusive-OR gate are respectively connected to the edge setting data of the return edge of the lagging beat and the edge setting data of the driving edge of the current beat; the output terminal of the third exclusive-OR gate is connected to the data input terminal of the eighth trigger; A monostable circuit is formed by connecting a third inverter in reverse between the data input terminal and the data output terminal of the ninth trigger; The clock input terminal of the eighth trigger is connected to the system positive clock; the data output terminal is connected to the enable terminal of the ninth trigger to enable the monostable circuit; After the third clock coarse delay generation module and the third selector are connected, the output terminal of the third selector is connected to the clock input terminal of the ninth trigger to output a clock signal to the monostable circuit; The output terminal of the ninth trigger is connected to the input terminal of the third delay line, and the output terminal of the third delay line serves as the output terminal of the third EG circuit; Among them, the third clock coarse delay generation module is used to generate multiple clock signals that are of the same frequency as the system clock and have a phase difference between each path; the multiple clock signals are input in parallel to each input terminal of the third selector; The selection control terminal of the third selector accesses the delay coarse adjustment data of the driving edge of the current beat; under the control of the delay coarse adjustment data, 1 clock signal is selected from the input multiple clock signals and output from the output terminal of the third selector; The delay control terminal of the third delay line accesses the delay fine adjustment setting of the driving edge of the current beat to perform the delay control of the third delay line.
10. The precise edge timing control circuit according to claim 9, wherein, The positive clock cycle working group circuit includes a fourth EG circuit; the fourth EG circuit is a positive clock working group return edge generation circuit; It includes a fourth exclusive-OR gate, a tenth trigger, a fourth inverter, an eleventh trigger, a fourth clock coarse delay generation module, a fourth selector, and a fourth delay line; The fourth exclusive-OR gate is a two-input exclusive-OR gate. The two input terminals of the fourth exclusive-OR gate are respectively connected to the edge setting data of the return edge of the current beat and the edge setting data of the driving edge of the current beat; the output terminal of the fourth exclusive-OR gate is connected to the data input terminal of the tenth trigger; A monostable circuit is formed by connecting a fourth inverter in reverse between the data input terminal and the data output terminal of the eleventh trigger; The clock input terminal of the tenth flip-flop is connected to the system positive clock; the data output terminal is connected to the enable terminal of the eleventh flip-flop; the monostable circuit is enabled and controlled. After the fourth clock coarse delay generation module and the fourth selector are connected, the output terminal of the fourth selector is connected to the clock input terminal of the eleventh flip-flop, and the clock signal is output to the monostable circuit. The output terminal of the eleventh flip-flop is connected to the input terminal of the fourth delay line, and the output terminal of the fourth delay line is used as the output terminal of the fourth EG circuit. Among them, the fourth clock coarse delay generation module is used to generate multiple clock signals that are of the same frequency as the system clock and have a phase difference between each path; the multiple clock signals are input in parallel to each input terminal of the fourth selector. The selection control terminal of the fourth selector accesses the coarse delay adjustment data of the return edge of the current beat. Under the control of the coarse delay adjustment data, 1 path of clock signal is selected from the input multiple clock signals and output from the output terminal of the fourth selector. The delay control terminal of the fourth delay line accesses the fine delay setting of the return edge of the current beat to perform the delay control of the fourth delay line.
11. The precise edge timing control circuit according to claim 6, wherein, The edge combination circuit performs an exclusive OR operation on the output edges of the negative clock cycle working group circuit and the positive clock cycle working group circuit and outputs a pulse with precise edge time control.