Phase calibration system for phase interpolation circuit

Abstract

The invention discloses a phase calibration system for a phase interpolation circuit, which relates to the technical field of integrated circuits and comprises a reference circuit and a circuit to be calibrated. The reference circuit and the to-be-calibrated circuit have the same structure; the reference circuit or the to-be-calibrated circuit comprises a current type digital-to-analog converter, a phase interpolation module and a phase combination module; the phase interpolation module comprises a PIA module and a PIB module; the current type digital-to-analog converter is connected with the phase interpolation module, and the current type digital-to-analog converter provides current for the phase interpolation module; and the phase combination module is connected with the phase interpolation module and is used for calibrating the clock phase of 45 degrees and the clock phase of integral multiples of the clock phase to a standard phase. According to the invention, a double-phase interpolator architecture is adopted, and the linearity loss of a phase interpolator is compensated through the principle of nonlinear trend complementation of clocks at intervals of pi / 4 under the input of an orthogonal reference clock.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular, to a phase calibration system for a phase interpolation circuit. Background Art

[0002] Communication is an important means for humans to communicate with each other. With the development of network technology, people's demand for the information transmission speed is becoming increasingly strict. With the rapid development of semiconductor technology, the complexity and communication rate of integrated circuits are constantly increasing. How to achieve high-speed communication is one of the important research directions in modern communication. Traditional parallel transmission technology dominates in short-distance interconnections. Although it can transmit multiple data channels simultaneously, the clock signal also needs to be synchronized. In addition, as the rate increases, crosstalk and timing offsets between transmission lines will become more serious. Compared with parallel transmission, the serial transmission scheme has taken various measures to improve problems such as crosstalk and timing offsets, such as using differential signals instead of single-ended signals to enhance the noise resistance ability; using clock recovery technology to avoid the serious problem of clock signal offset caused by transmitting the clock signal additionally while transmitting data. The serial transceiver SerDes is an abbreviation for Serializer / Deserializer, which is a communication technology that combines time-division multiplexing and point-to-point links, and is an indispensable component of many communication protocols. As the core module of the phase interpolation type clock data recovery circuit (PI-CDR), high linearity is of great significance for improving the performance of the circuit system, reducing signal distortion, and enhancing communication quality. Analyzing from the current mainstream research and product iteration directions in academia and industry, the phase interpolation circuit mainly develops towards high speed, high precision, and low power consumption.

[0003] Therefore, there is an urgent need to provide a more reliable dual-phase interpolation circuit and its phase calibration scheme. Summary of the Invention

[0004] The purpose of the present invention is to provide a phase calibration system for a phase interpolation circuit, which is used to solve the problems of linearity loss caused by the linear coding strategy of the tail current source in the current-mode phase interpolation circuit, and the problem of phase error conversion from amplitude error during the amplification process of the current-mode clock signal.

[0005] To achieve the above purpose, the present invention provides the following technical solutions:

[0006] In a first aspect, the present invention provides a phase calibration system for a phase interpolation circuit, which at least includes:

[0007] A reference circuit and a circuit to be calibrated; the reference circuit and the circuit to be calibrated have the same structure;

[0008] Both the reference circuit or the circuit to be calibrated include a current-mode digital-to-analog converter, a phase interpolation module, and a phase combination module;

[0009] The phase interpolation module includes a PIA module and a PIB module; the current-mode digital-to-analog converter is connected to the phase interpolation module, and the current-mode digital-to-analog converter provides current for the phase interpolation module;

[0010] The phase combination module is connected to the phase interpolation module and calibrates the clock phases of 45° and its integer multiples to the standard phase.

[0011] Optionally, the system further includes:

[0012] A CML2CMOS module;

[0013] The phase combination module is connected to the CML2CMOS module, and the CML2CMOS module is used to amplify the current-mode signal to a full-amplitude square-wave signal.

[0014] Optionally, the PIA module and the PIB module respectively receive 0° reference clock, 90° reference clock, 180° reference clock, and 270° reference clock as reference input clocks, and realize phase synthesis by controlling the on / off of the tail current switches of four differential pairs to generate differential interpolated clock outputs.

[0015] Optionally, the phase combination module is used to adopt a compensation method with a dual-phase interpolator architecture on the PIA module and the PIB module, and there is a 45° phase difference between the PIA and the PIB through the current-mode digital-to-analog converter.

[0016] Optionally, the system further includes:

[0017] A calibration logic module; the calibration logic module is connected to the current-mode digital-to-analog converter;

[0018] The current-mode digital-to-analog converter serves as the tail current input of the phase interpolation module and provides current for the phase interpolation module in a 9-bit control word segmented manner; the 9-bit control word segmented manner includes the high two-bit binary code and the low seven-bit full thermometer code. The high two-bit binary code is used to control the on / off of the tail current sources of four differential pairs, and the low seven-bit full thermometer code is used to control the ratio of the interpolation current to complete the ratio regulation of 127 phases within 90 degrees;

[0019] Each segment of the low seven-bit thermometer code inputs independent reference currents. The reference current includes two 4-bit adjustable current calibration branches, and the on / off of the current in the adjustable branches is controlled by the output result of the current-mode digital-to-analog converter.

[0020] Optionally, the reference circuit identifies and calibrates the worst linearity exhibited at clock phases of 45° and its integer multiples. Using the replicated phase interpolation module as a reference, it provides a reference clock phase. Within each 90° range, the 127-bit thermometer code is divided into four parts. By adjusting the input reference current magnitude of the current-mode digital-to-analog converter in a specific part and the current ratio of the I / Q two paths, a two-phase standard reference clock is obtained for calibrating the intermediate phase clock of the phase interpolation module in the circuit to be calibrated.

[0021] By selecting the initial current magnitude for generating the preset two-phase clock and the current ratio of the I / Q two paths, a two-phase standard reference clock is obtained; the preset two-phase clock is adjacent clocks separated by 45°.

[0022] Optionally, the current-mode digital-to-analog converters in both the circuit to be calibrated and the reference circuit each include two parts of current-mode digital-to-analog converters.

[0023] During the calibration process, normalization statistics are performed at control word 0; when the control word is 32, a clock representing a 22.5° phase is generated, and the 31-bit thermometer code switch of the first part of the current-mode digital-to-analog converter in the circuit to be calibrated is turned on; when the control word is 480, a 337.5° clock is generated, the 31-bit thermometer code current branch switch of the first part of the current-mode digital-to-analog converter in the circuit to be calibrated is turned off, and the thermometer codes of the other three parts are turned on; the control word 0 represents a 0° phase.

[0024] Optionally, in the phase interpolation module, the gates of the first transistor and the fourth transistor are input with a 0° clock, and the gates of the second transistor and the third transistor are input with a 180° clock. By selecting the reference clocks of the I / Q two paths, phase synthesis is achieved within a 360° range.

[0025] In the phase combination module, the gates of the first transistor and the third transistor are respectively connected to the negative pole of the input clock, and the gates of the second transistor and the fourth transistor are connected to the positive pole of the clock. The voltage signal with phase information is converted into a source-drain current signal with phase information in the differential pair and vectorially superimposed on the load resistor.

[0026] Optionally, during the power-on startup phase, the control position of the current-mode digital-to-analog converter is set to 0, the calibration control word is set to 0, the circuit is powered on, and each module in the system is initialized and a steady state is established. The current-mode digital-to-analog converter generates a reference current.

[0027] In the 0° clock phase calibration stage, the enable of the calibration logic module is set to 1, the circuit starts the calibration process, calibrates the clock phases representing 0° and its integer multiples. The input control word of the phase interpolation module to be calibrated in the circuit to be calibrated is switched to 0. The reference phase interpolation module in the reference circuit sets the first input control word to provide the first two-phase clock as a reference. The phase interpolation module to be calibrated provides a 0° clock, and the clock phase is adjusted through an adjustable current-mode digital-to-analog converter with 4-bit calibration bits until the first preset condition is met, determining that the current error exceeds the calibration range. The first preset condition means setting the done0 signal representing the completion of the 0° clock calibration to 1, or the first preset condition means that all 4-bit current-mode digital-to-analog converter control bits are opened or closed.

[0028] Optionally, in the 45° clock phase calibration stage, after the 0° clock calibration is completed, the input control word of the phase interpolation module to be calibrated is changed to the second input control word, and the second input control word represents a 45° clock. The control word of the reference phase interpolation module is changed to the third input control word to provide the second two-phase clock as a reference. The phase interpolation module to be calibrated provides a 45° clock, and the clock phase is adjusted through an adjustable current-mode digital-to-analog converter with 4-bit calibration bits until the second preset condition is met, determining that the current error exceeds the calibration range. The second preset condition means setting the done45 signal representing the completion of the 45° clock calibration to 1, or the second preset condition means that all 4-bit control bits are opened or closed.

[0029] In the calibration end stage, the control position of the calibration logic module is set to 0, the calibration control word of the current-mode digital-to-analog converter is updated, and the system switches back to the external control word input to perform the clock phase adjustment after calibration.

[0030] Compared with the prior art, the present invention provides a phase calibration system for a phase interpolation circuit, which at least includes: a reference circuit and a circuit to be calibrated; the reference circuit and the circuit to be calibrated have the same structure; both the reference circuit and the circuit to be calibrated include a current-mode digital-to-analog converter, a phase interpolation module, and a phase combination module; the phase interpolation module includes a PIA module and a PIB module; the current-mode digital-to-analog converter is connected to the phase interpolation module, and the current-mode digital-to-analog converter provides current for the phase interpolation module; the phase combination module is connected to the phase interpolation module to calibrate the clock phases of 45° and its integer multiples to the standard phase. Based on the PIA module and the PIB module in the reference circuit and the circuit to be calibrated, a dual-phase interpolator architecture is adopted, and through the principle of complementary clock non-linear trends separated by π / 4 under the input of orthogonal reference clocks, the linearity loss of the phase interpolator is compensated. The problems of linearity loss caused by the linear coding strategy of the tail current source in the current-mode phase interpolation circuit and the problem of converting amplitude error (AM) to phase error (PM) during the amplification process of the current-mode clock signal are solved. Description of the Drawings

[0031] The drawings described herein are used to provide a further understanding of the present invention, and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention, and do not constitute an improper limitation to the present invention. In the drawings:

[0032] Figure 1 It is a schematic diagram of a traditional current-mode structure phase interpolation circuit in the prior art;

[0033] Figure 2 It is a schematic diagram of the geometric model of a linear coding phase interpolation circuit in the prior art;

[0034] Figure 3 It is a structural diagram of a non-equal tail current source phase interpolation circuit provided by the prior art one;

[0035] Figure 4 It is a structural diagram of a high-order coefficient fitting phase interpolation circuit system provided by the prior art two;

[0036] Figure 5 It is a structural diagram of a phase calibration system for a phase interpolation circuit provided by the present invention;

[0037] Figure 6 It is a schematic diagram of the dual-phase interpolator structure provided by the present invention;

[0038] Figure 7 It is a schematic diagram of the phase interpolation module structure provided by the present invention;

[0039] Figure 8 It is a schematic diagram of the phase combination module structure provided by the present invention;

[0040] Figure 9 Structural diagram of the current-mode digital-to-analog converter provided by the present invention;

[0041] Figure 10 Schematic diagram of the intermediate phase error provided by the present invention;

[0042] Figure 11 Schematic diagram of the calibration process logic provided by the present invention;

[0043] Figure 12(a) is a clock signal diagram before compensation of the dual-phase interpolator structure provided by the present invention;

[0044] Figure 12(b) is a clock signal diagram after compensation of the dual-phase interpolator structure provided by the present invention;

[0045] Figure 13(a) is a schematic diagram of eight clock signals before calibration of the present invention;

[0046] Figure 13(b) is a schematic diagram of eight clock signals after calibration of the present invention;

[0047] Figure 14 Schematic diagram of differential non-linearity statistics;

[0048] Figure 15 Schematic diagram of the clock phase range during calibration of the present invention;

[0049] Figure 16 Schematic diagram of the INL comparison between the phase interpolation module and the traditional phase interpolation module provided by the present invention.

[0050] Reference numerals:

[0051] 1 - reference circuit, 2 - circuit to be calibrated, 3 - CML2CMOS module, 4 - calibration logic module, 101 - current-mode digital-to-analog converter, 102 - phase interpolation module, 103 - phase combination module. Detailed implementation manners

[0052] For the convenience of clearly describing the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, terms such as "first" and "second" are used to distinguish identical or similar items with basically the same functions and effects. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and do not limit their sequence. Those skilled in the art can understand that terms such as "first" and "second" do not limit the quantity and execution order, and "first" and "second" do not necessarily mean different.

[0053] It should be noted that in the present invention, words such as "exemplary" or "for example" are used to represent examples, illustrations or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the present invention should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0054] In the present invention, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after. "At least one (item)" or its similar expression refers to any combination of these items, including any combination of single item (item) or plural items (items). For example, at least one (item) of a, b or c can represent: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b and c can be single or multiple.

[0055] First, the definitions of the abbreviations, English and key terms that appear in the embodiments of this specification are described:

[0056] 1. SerDes: Serializer / Deserializer, serializer / deserializer

[0057] 2. RX: Receiver

[0058] 3. CDR: Clock Data Recovery Circuit

[0059] 4. CML: Current Mode

[0060] 5. CMOS: Full Swing Level Signal

[0061] 6. LSB: Least Significant Bit

[0062] 7. INI: Integral Nonlinearity

[0063] 8. DNL: Differential Nonlinearity

[0064] 9. AM-PM: Amplitude-to-Phase

[0065] 10. Dual-PI: Dual Phase Interpolator

[0066] 11. IDAC: Current Digital-to-Analog Converter

[0067] 12. PVT: Process Voltage Temperature

[0068] 13. I / Q: Orthogonal.

[0069] At present, the phase interpolation circuit structure applied to high-speed circuits is generally as Figure 1 shown: Figure 1 It shows the basic structure of traditional current-mode circuit interpolation. The principle of phase interpolation is analyzed and deduced by the following formula:

[0070] Pa = A1sin(ω in t) (1)

[0071]

[0072] In the above formulas (1)-(3), Pa and Pb are input reference clocks, A1 and A2 are amplitude coefficients of the two initial clocks, ω in is the input reference clock frequency, is the initial phase difference between the two input reference clocks. In formula (3):

[0073] Formulas (1)-(5) represent the basic principle of phase interpolation, that is, the synthesis formula of trigonometric functions. When the initial angles of the reference clocks are fixed, by adjusting the coefficient weights of the two phases A1 and A2, any phase clock between the two reference clocks can be obtained. However, in circuit design, implementing the coefficients is not an easy task. A more commonly used solution is to adopt a linear coding strategy of |A1| + |A2| = 1 to achieve the change of the phase weight coefficient. The linear substitution strategy is easy to implement in circuit design, but it also brings the problem of serious deterioration of the linearity of the output clock signal. Figure 2 It shows the mathematical geometric model of linear coding and phase interpolation under ideal conditions. It can be seen that geometrically, linear coding is equivalent to approximately replacing a circle with a square, and the linearity deteriorates most severely at 45° and its integer multiples of angles.

[0074] To address this problem, in the prior art one, a non-equal tail current source coding method is adopted. From the above analysis, it can be known that linear weight coding will cause the increment of the phase to show a sine change trend. Then, by inverse-solving the expression of θ, the change ratio of the input weight is obtained under the condition that the output phase changes approximately linearly. A weight coding method that fits the sine is used to offset the linearity error, thereby improving the linearity of the output clock, and thus achieving the improvement of the problem of the trade-off between circuit complexity and linearity in the traditional interpolation circuit. Figure 3The structural diagram of a phase interpolation circuit based on a non-equal-value tail current source is shown. The gates of differential pairs M1, M2 and M3, M4 are respectively connected to the reference clock signal. Binary encoding is performed on the tail current arrays of the two differential pairs. The more encoding bits there are, the finer the current weight control will be, and the trend of the weight change will be closer to a sine wave, so that the output clock linearity will be better.

[0075] However, although the non-equal-value tail current source interpolation scheme can improve the linearity loss of the circuit to a certain extent, there are still some deficiencies. First, the cost of designing a high-precision binary current-type digital-to-analog converter is relatively high. Second, for low-speed circuits with low requirements for phase resolution, this scheme can meet the need for linearity compensation. However, for high-speed and high-precision design requirements, the circuit has high requirements for the linearity of the clock signal. If a non-linear fitting method is still adopted, it will greatly increase the implementation cost of the circuit. At the same time, for the change of PVT, the designed weights are likely to fluctuate, deviating from the initial designed ratio, thus deteriorating the linearity.

[0076] Another solution is to perform trigonometric function fitting on the high-order current coefficients, which essentially also adjusts the proportion weight of the current source, so as to improve the problem of non-linear response. Figure 4 The left figure is the composition structure of this phase interpolator, which mainly includes a coefficient encoding circuit, a current mirror array and a phase synthesis circuit. Figure 4 The right figure is the structural block diagram. The main idea of this scheme is to set the current mirror array sub-circuit to generate a current corresponding to the approximate coefficient of the control word of this row according to the first weight, the second weight, the third weight, the fourth weight and the corresponding row control word; among them, the first weight is the weight of the preset bias current, and the second weight, the third weight and the fourth weight are the weights corresponding to the first-order coefficient, the second-order coefficient and the third-order coefficient in the control word of this row respectively. Compared with the first-order coefficient directly linearly regulated, the amplitude error after the third-order combination can be reduced to 6.5%.

[0077] However, the essence of the high-order current coefficient fitting method is also to refine the current weight, and the problem of circuit complexity still exists under high resolution. In addition, although the amplitude error of the third-order coefficient fitting is reduced to 6.5%, this value is only measured under the current-mode signal. As the clock signal sampled in the CDR circuit, it still needs to be amplified to the rail-to-rail clock through the CML2CMOS module. During this process, the linearity will deteriorate further, that is, the amplitude error (AM) is converted into the phase error (PM).

[0078] In view of the defects existing in the prior art, the present invention provides a phase calibration system for a phase interpolation circuit. Next, the solution provided by the embodiments of this specification will be described in conjunction with the accompanying drawings:

[0079] As Figure 5As shown, the system may include:

[0080] a reference circuit 1 and a circuit 2 to be calibrated; the reference circuit 1 and the circuit 2 to be calibrated have the same structure;

[0081] Either the reference circuit 1 or the circuit 2 to be calibrated includes a current-mode digital-to-analog converter 101, a phase interpolation module 102, and a phase combination module 103;

[0082] The phase interpolation module 102 includes a PIA module and a PIB module; the current-mode digital-to-analog converter 101 is connected to the phase interpolation module 102, and the current-mode digital-to-analog converter 101 provides current for the phase interpolation module 102;

[0083] The phase combination module 103 is connected to the phase interpolation module 102 to calibrate the clock phases of 45° and its integer multiples to the standard phase.

[0084] The system may further include:

[0085] a CML2CMOS module 3;

[0086] The phase combination module 103 is connected to the CML2CMOS module 3, and the CML2CMOS module 3 is used to amplify the current-mode signal to a full-amplitude square-wave signal;

[0087] a calibration logic module 4; the calibration logic module 4 is connected to the current-mode digital-to-analog converter 101.

[0088] Among them, the current-mode digital-to-analog converter 101 (Current Digital-to-Analog Converter), abbreviated as IDAC, generates an analog voltage by changing the current flowing through a resistor, thereby realizing digital-to-analog conversion.

[0089] The phase interpolation module 102 PI (Phase Interpolator) plays an important role in high-speed digital-analog hybrid circuits (such as phase-locked loop PLL circuits, clock data recovery CDR circuits, serial link transceivers, etc.).

[0090] The phase combination module 103 (Phase Combiner) combines multiple signals with different phases to generate an output signal with a specific phase relationship.

[0091] Figure 5In the system, the reference circuit 1 and the circuit to be calibrated 2 are set; the reference circuit 1 and the circuit to be calibrated 2 have the same structure; either the reference circuit 1 or the circuit to be calibrated 2 includes a current-mode digital-to-analog converter 101, a phase interpolation module 102, and a phase combination module 103; the phase interpolation module 102 includes a PIA module and a PIB module; the current-mode digital-to-analog converter 101 is connected to the phase interpolation module 102, and the current-mode digital-to-analog converter 101 provides current for the phase interpolation module 102; the phase combination module 103 is connected to the phase interpolation module 102 to calibrate the clock phases of 45° and its integer multiples to the standard phase. Based on the PIA module and the PIB module in the reference circuit 1 and the circuit to be calibrated 2, a dual-phase interpolator architecture is adopted. Through the principle of complementary clock non-linear trends separated by π / 4 under the orthogonal reference clock input, the linearity loss of the phase interpolator is compensated. The problems of linearity loss caused by the linear coding strategy of the tail current source in the current-mode phase interpolation circuit and the problem of amplitude error (AM) converted to phase error (PM) in the process of current-mode clock signal amplification are solved.

[0092] Based on Figure 5 For the system, the embodiments of this specification also provide some specific structures and specific implementation solutions of the system, which will be described below.

[0093] For Figure 5 the phase interpolation module 102 in, a dual-phase interpolator (Dual-PI) architecture is adopted. The dual-phase interpolator (Dual-PI) architecture is as Figure 6 shown. Through the principle of complementary clock non-linear trends separated by π / 4 under the orthogonal reference clock input, the linearity loss of the phase interpolator is compensated. Figure 6 In, the PIA module is connected to the first part of the IDAC, and the PIB module is connected to the second part of the IDAC. The two parts of the IDAC provide current for the PIA module and the PIB module. The circuit structure of the phase interpolation module 102 is as Figure 7 shown. The phase interpolation module 102 mainly includes eight transistors (M1-M8) and two load resistors (R1, R2).

[0094] Among them, as Figure 5 shown, the PIA module and the PIB module respectively input four reference clocks of 0°, 90°, 180°, and 270° as the reference input clocks.

[0095] The circuit realizes phase synthesis within 360° by selecting the reference clocks for the I / Q two paths; in the phase combination module 103, the gates of the first transistor and the third transistor are respectively connected to the negative pole of the input clock, the gates of the second transistor and the fourth transistor are connected to the positive pole of the clock, and the voltage signal with phase information is converted into a source-drain current signal with phase information in the differential pair and vectorially superimposed on the load resistor.

[0096] More specifically, the reference clocks for the I / Q two paths are selected by controlling the on / off of the tail current switches of the four differential pairs, such as 0° and 90°; 90° and 180°; 180° and 270°; 270° and 0°, so as to achieve the purpose of phase synthesis within 360°. The current-mode signal with phase information is vectorially superimposed on the load resistors R1 and R2 and converted into a synthesized vector voltage signal, generating the differential interpolated clocks CKN and CKP for output.

[0097] For Figure 5 the phase combination module 103 in Figure 8 as shown, PIA and PIB adopt the Dual-PI compensation method. Among them, the two IDACs that respectively supply current to PIA and PIB have a control word difference of 64 steps, that is, there is always a 45° phase difference between their phases. Through their complementary non-linear trends, the linearity loss caused by the linear interpolation weight control strategy is compensated. The clock signals separated by 45° are vectorially synthesized on the phase combination module 103. The gates of M1 and M3 are respectively connected to the negative pole of the input clock, and the gates of M2 and M4 are connected to the positive pole of the clock. The voltage signal with phase information is converted into a source-drain current signal with phase information in the differential pair and vectorially superimposed on the load resistors R1 and R2.

[0098] For Figure 5 the current-mode digital-to-analog converter 101 (IDAC) in

[0099] Specifically, Figure 5 the current-mode digital-to-analog converter 101 in Figure 9 is shown asFigure 9 The IDAC serves as the tail current input of the phase interpolation module 102 and adopts a 9-bit control word segmented design. Among them, the high two bits use binary codes to control the on / off of the tail current sources of four differential pairs and select the reference clock phase connected to the circuit; the low seven bits use a full thermometer code design as the control bits of the phase weights to control the ratio of the interpolation current, thereby realizing the proportional regulation of 127 phases within 90 degrees, which can effectively reduce the conversion error and improve the linearity and switching noise.

[0100] The 7-bit controls 127 thermometer code outputs, which are divided into four segments of 31, 32, 32, and 32. Each segment inputs independent reference currents. The reference current includes two 4-bit adjustable current calibration branches, and the current on / off of the adjustable branches is controlled by the output result of the calibration logic. Among them, the 4-bit control word has 16 levels to finely fit the non-linear response of the output clock within the range of 22.5°, compensating for the loss of linearity. The circuit system is a quarter-rate architecture, and four phase interpolators are used to simultaneously generate eight clock signals CLK<7:0> with an interval of 45°.

[0101] Figure 12(a) is the clock signal diagram before compensation of the dual-phase interpolator structure provided by the present invention; Figure 12(b) is the clock signal diagram after compensation of the dual-phase interpolator structure provided by the present invention, showing the amplitude error of the phase interpolation clock separated by 45° after compensation. The proportion of the amplitude error in the output swing (ΔVerr / Vpp) drops from 32.2% to 3.6%. After passing through the CML2CMOS module 3, the current-mode signal is amplified to a full-amplitude square-wave signal. In this process, due to the AM-PM problem, there will still be a linearity loss of up to 9.3 LSB. At this time, the present invention is based on Figure 5 the structure, and is further optimized by adopting a global linearity calibration technology based on the worst-phase optimization:

[0102] The linear coding strategy will show the worst linearity at the "45°" phase. However, this phase is not an absolute value but a relative value, depending on where the intersection point of the approximate equivalent rhombus and the standard circle is. The point 45° different from the intersection phase is the worst-phase point. From the coding characteristics of the thermometer code, we know that within each sub-segment of 90°, the tail current controlling the phase change always shows a linear increasing and decreasing trend, and each current change amount is always the same. Although the middle-phase clock within this sub-segment is very different from the standard clock, the phase clocks on both sides of the middle phase still follow a uniform distribution. The middle-phase error is jointly caused by the non-linear response brought by the linear coding and the AM-PM conversion. The clock phase representing 45° is not in the middle of the clocks representing 0° and 90°, but is fixed and shifted towards the 0° clock side, as Figure 10As shown above, based on the above analysis, if we can calibrate the clock phases of "45°" and its integer multiples to the standard phase, then the clock phases evenly distributed on both sides will naturally return to the correct phase. The only remaining problem is how to obtain an accurate reference standard. In the system of the present invention, an accurately replicated phase interpolation circuit is introduced as a reference to provide an accurate reference clock phase. The specific implementation logic is analyzed as follows:

[0103] The current-mode digital-to-analog converters 101 in the circuit 2 to be calibrated and the reference circuit 1 each include two parts of current-mode digital-to-analog converters 101;

[0104] During the calibration process, normalization statistics are performed at the control word 0; when the control word is 32, a clock representing a 22.5° phase is generated, and the 31-bit thermometer code switches of the first part of the current-mode digital-to-analog converter 101 in the circuit 2 to be calibrated are turned on; when the control word is 480, a 337.5° clock is generated, and the 31-bit thermometer code current branch switches of the first part of the current-mode digital-to-analog converter 101 in the circuit 2 to be calibrated are turned off, and the other three parts of the thermometer codes are turned on; the control word 0 represents a 0° phase.

[0105] More specifically, within each 90° range, the 127-bit thermometer code is divided into four parts, that is, every 31 or 32 thermometer code current branch switches control the step adjustment within a 22.5° phase range. Normalization statistics are performed at the control word 0, and the control word 0 represents a 0° phase. Then, when the control word is 32, a clock representing a 22.5° phase is generated, and only the 31-bit thermometer code switches of the first part of the IDAC are turned on to provide a reference current, and the IDAC switches of the other three parts are closed. This means that adjusting the input reference current magnitudes of these three parts of the IDAC will not have any impact on the linearity of this 22.5° clock. Similarly, when the input control word is 480, the generated 337.5° clock is the same, except that the 31-bit thermometer code current branch switches of the first part are turned off, and the remaining three parts of the thermometer codes are turned on. As long as the initial current magnitudes for generating these two-phase clocks and the current ratio of the I / Q two paths are carefully selected, we can obtain two-phase standard reference clocks. The system structure is as Figure 5 shown, where PI represents the replicated phase interpolation module 102 (PIA and PIB). Three-phase clocks are taken from the PI clock output as the input clocks for calibration, such as Figure 5 CLK<0>, CLK<1>, CLK<2> in. Among them, CLK<1> and CLK<2> come from the reference standard PI and are adjacent clocks separated by 45°. The third phase CLK<0> is taken from the PI to be calibrated, and CLK<0> is the intermediate phase clock between CLK<1> and CLK<2>, and is 32 steps, that is, 22.5° different from each of the two reference clocks.

[0106] Based on Figure 5 the circuit structure in Figure 11 as shown below, a brief analysis of this process is as follows:

[0107] In the power-on startup phase, set the control position of the current-mode digital-to-analog converter 101 to 0, set the calibration control word to 0, power on the circuit, initialize each module in the system and establish a steady state, and the current-mode digital-to-analog converter 101 generates a reference current;

[0108] In the 0° clock phase calibration phase, enable the calibration logic module 4 by setting it to 1, start the calibration process of the circuit, calibrate the clock phases representing 0° and its integer multiples. The input control word of the phase interpolation module 102 to be calibrated in the circuit to be calibrated 2 is switched to 0. The reference phase interpolation module 102 in the reference circuit 1 sets the first input control word to provide the first two-phase clock as a reference. The phase interpolation module 102 to be calibrated provides a 0° clock, and adjusts the clock phase through the adjustable current-mode digital-to-analog converter 101 with 4-bit calibration bits until the first preset condition is met, and it is determined that the current error exceeds the calibration range. The first preset condition means setting the done0 signal representing the completion of the 0° clock calibration to 1, or the first preset condition means that all 4-bit control bits of the current-mode digital-to-analog converter 101 are opened or closed.

[0109] In the 45° clock phase calibration phase, after the 0° clock calibration is completed, change the input control word input of the phase interpolation module 102 to be calibrated to the second input control word, where the second input control word represents a 45° clock. Change the control word of the reference phase interpolation module 102 to the third input control word to provide the second two-phase clock as a reference. The phase interpolation module 102 to be calibrated provides a 45° clock, and adjusts the clock phase through the adjustable current-mode digital-to-analog converter 101 with 4-bit calibration bits until the second preset condition is met, and it is determined that the current error exceeds the calibration range. The second preset condition means setting the done45 signal representing the completion of the 45° clock calibration to 1, or the second preset condition means that all 4-bit control bits are opened or closed;

[0110] In the calibration end phase, set the control position of the calibration logic module 4 to 0, update the calibration control word of the current-mode digital-to-analog converter 101, and the system switches back to the external control word input to perform clock phase adjustment after calibration.

[0111] More specifically, in the calibration logic process, the first stage is the power-on startup stage. In this stage, the calibration logic control bit (en_cal) is set to 0, the IDAC calibration control word is set to 0, the circuit is powered on, each module is initialized and a steady state is established. The IDAC generates a reference current, and the circuit normally generates 8 uncalibrated phases of the clock. In the second stage, the calibration logic enable (en_cal) is set to 1, and the circuit starts the calibration process. First, the clock phases representing 0° and its integer multiples are calibrated. The input control word of the calibrated PI is switched to 0, the reference PI setting input control word is 480, providing two-phase clocks of 337.5° and 22.5°. The calibrated PI provides a 0° clock. At this time, these two-phase clocks are taken as references to correct the 0° clock. The adjustable IDAC with 4-bit calibration bits opens a one-bit current reference selection switch under the control of the logic circuit to adjust the clock phase. Then, this process is repeated. If the logic circuit sets the done0 signal representing the completion of the 0° clock calibration to 1, the 0° clock calibration is completed; if all 4-bit IDAC control bits are opened or closed, it indicates that the current error exceeds the calibration range. After the 0° clock calibration is completed, in the third stage, the clock phases of 45° and its integer multiples are calibrated. The input control word input of the calibrated PI is changed to 64, representing the 45-degree clock, and the reference PI control word is changed to 32, providing 22.5° and 62.5° clocks. At this time, these two-phase clocks are taken as references to correct the 45° clock. The adjustable IDAC with 4-bit calibration bits opens a one-bit current reference selection switch under the control of the logic circuit to adjust the clock phase. Then, this process is repeated. If the logic circuit sets the done45 signal representing the completion of the 45° clock calibration to 1, the 45° clock calibration is completed; if all 4-bit control bits are opened or closed, it indicates that the current error exceeds the calibration range. In the last stage, the done0 signal and the done45 signal are processed by the logic circuit to determine the end of the system calibration. Then, the calibration logic control bit (en_cal) is set to 0, the IDAC calibration control word is updated, and the system is switched back to the external control word input for clock phase adjustment after calibration.

[0112] The present invention verifies the effectiveness by simulating and building an actual circuit. Figure 13(a) is a schematic diagram of the first eight clock signals before calibration of the present invention; Figure 13(b) is a schematic diagram of the first eight clock signals after calibration of the present invention. Figure 14 For the differential nonlinearity (DNL) normalization statistics of the first eight clocks before and after calibration, as shown in Figure 13(a), Figure 13(b), and Figure 14 It can be seen that for the eight-phase clock, it is 0LSB, 0.29LSB, 0.68LSB, 0.65LSB, -0.09LSB, 0.17LSB, 0.77LSB, 0.69LSB. Among them, the maximum value drops from -9.37LSB to 0.77LSB.

[0113] The calibration range is as Figure 15As shown, calibration with a step size of 0.4° can be provided within a range of 6.336°.

[0114] Figure 16 It is the statistical result of the integral nonlinearity (INL) simulation of 512 phases. Compared with the traditional PI without calibration, the proposed scheme of the present invention can limit the overall INL to less than 2.1 LSB. Generally speaking, the present invention can achieve very high-precision phase linearity calibration, and adopts a fully digital method, which has good process portability. At the same time, it also has a certain resistance to PVT fluctuations and can achieve an excellent phase interpolator linearity level at a small cost. Among them, INL (Integral Nonlinearity) is integral nonlinearity, which is an important static performance parameter of an analog-to-digital converter (ADC). INL represents the error value at the point with the largest error between the analog value and the true value corresponding to all numerical points of the ADC, that is, the maximum distance by which the output value deviates from linearity. The unit of INL is LSB (Least Significant Bit), that is, the least significant bit. LSB represents the last bit in the digital stream and also represents the smallest unit that makes up the full-scale input range.

[0115] Through the scheme of the foregoing embodiments, the present invention proposes a global linearity calibration technique and implementation scheme based on worst-case phase optimization on the basis of a traditional current-mode phase interpolation circuit to solve the problems of linearity loss caused by the linear coding strategy of the tail current source in the current-mode phase interpolation circuit and the problem of amplitude error (AM) converted to phase error (PM) during the amplification process of the current-mode clock signal. It provides an effective solution to the problem that in the design of a traditional current-mode phase interpolation circuit, the linear weight control strategy causes AM-PM errors in the output signal and serious loss of system linearity. Using the scheme designed by this invention, very good linearity calibration of the phase interpolation circuit can be achieved. The innovative phase calibration idea and calibration logic design are the innovative points protected by the present invention.

[0116] Although the present invention has been described in connection with various embodiments herein, however, in the process of implementing the claimed invention, those skilled in the art can understand and realize other variations of the disclosed embodiments by viewing the drawings, the disclosed content, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions recited in the claims. Certain measures are recited in mutually different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0117] Although the present invention has been described in connection with specific features and their embodiments, it will be apparent that various modifications and combinations can be made without departing from the spirit and scope of the invention. Accordingly, the present specification and drawings are merely exemplary illustrations of the invention defined by the appended claims and are considered to cover any and all modifications, variations, combinations or equivalents within the scope of the invention. Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these changes and modifications.

Claims

1. A phase calibration system for a phase interpolation circuit, characterized in that: The system shall at least include: A reference circuit and a circuit to be calibrated; the reference circuit and the circuit to be calibrated have the same structure; The reference circuit or the circuit to be calibrated includes a current-type digital-to-analog converter, a phase interpolation module and a phase combination module; The phase interpolation module includes a PIA module and a PIB module; the current-type digital-to-analog converter is connected to the phase interpolation module, and the current-type digital-to-analog converter provides current for the phase interpolation module; The phase combination module is connected to the phase interpolation module to calibrate the clock phase of 45° and its integer multiples to the standard phase.

2. A phase calibration system for a phase interpolation circuit according to claim 1, characterized in that: The system further comprises: CML2CMOS module; The phase combination module is connected to the CML2CMOS module, and the CML2CMOS module is used to amplify the current mode signal to a full-scale square wave signal.

3. A phase calibration system for a phase interpolation circuit according to claim 1, characterized in that: The PIA module and the PIB module receive a 0° reference clock, a 90° reference clock, a 180° reference clock and a 270° reference clock as reference input clocks respectively, and realize phase synthesis by controlling the on and off of the tail current switches of the four differential pairs to generate a differential interpolation clock output.

4. A phase calibration system for a phase interpolation circuit according to claim 3, characterized in that: The phase combination module is used to respectively adopt a compensation method of a dual-phase interpolator architecture on the PIA module and the PIB module, and to make a phase difference of 45° between the PIA and the PIB through the current-type digital-to-analog converter.

5. A phase calibration system for a phase interpolation circuit according to claim 1, characterized in that: The system further comprises: A calibration logic module; the calibration logic module is connected to the current-type digital-to-analog converter; The current-type digital-to-analog converter serves as the tail current input of the phase interpolation module, and adopts a 9-bit control word segmented method to provide current for the phase interpolation module; the 9-bit control word segmented method includes two high-order binary codes and seven low-order full-thermometer codes, the two high-order binary codes are used to control the on-off of the tail current sources of the four differential pairs, and the seven low-order full-thermometer codes are used to control the ratio of the interpolation current, completing the ratio control of 127 phases within a 90-degree range; Each input of the lower seven-bit thermometer code is an independent reference current. The reference current includes two 4-bit adjustable current calibration branches. The output result of the current-type digital-to-analog converter is used to control the current on and off of the adjustable branch.

6. A phase calibration system for a phase interpolation circuit according to claim 1, characterized in that: The reference circuit identifies and calibrates the worst linearity exhibited at the clock phase of 45° and its integer multiples, provides a reference clock phase by using a replicated phase interpolation module as a reference, and divides the 127-bit thermometer code into four parts within each 90° range, and obtains a two-phase standard reference clock by adjusting the input reference current magnitude of the current-type digital-to-analog converter of a specific part and the current ratio of the I / Q paths, which is used to calibrate the intermediate phase clock of the phase interpolation module in the circuit to be calibrated; By selecting the initial current size and the current ratio of the I / Q paths for generating a preset two-phase clock, a two-phase standard reference clock is obtained; the preset two-phase clock is an adjacent clock separated by 45°.

7. A phase calibration system for a phase interpolation circuit according to claim 1, characterized in that: The current-type digital-to-analog converters in the circuit to be calibrated and in the reference circuit each include two parts of current-type digital-to-analog converters; During the calibration process, normalized statistics are performed at control word 0; when the control word is 32, a clock representing a phase of 22.5° is generated, and the 31-bit thermometer code switch of the first part of the current-type digital-to-analog converter in the circuit to be calibrated is turned on; When the control word is 480, a 337.5° clock is generated, the 31-bit thermometer code current branch switch of the first part of the current-type digital-to-analog converter in the circuit to be calibrated is closed, and the other three parts of the thermometer code are opened; the control word 0 represents a 0° phase.

8. A phase calibration system for a phase interpolation circuit according to claim 1, characterized in that: The gates of the first transistor and the fourth transistor in the phase interpolation module input 0° clocks, and the gates of the second transistor and the third transistor input 180° clocks, and phase synthesis is achieved within a 360° range by selecting I / Q reference clocks; In the phase combination module, the gates of the first transistor and the third transistor are respectively connected to the negative pole of the input clock, and the gates of the second transistor and the fourth transistor are connected to the positive pole of the clock. The voltage signal with phase information is converted into a source-drain current signal with phase information in the differential pair, and vector superposition is performed on the load resistor.

9. The phase calibration system for a phase interpolation circuit according to claim 5, characterized in that: In the power-on startup phase, the control bit of the current-mode digital-to-analog converter is set to 0, the calibration control word is set to 0, the circuit is powered on, each module in the system is initialized and establishes a steady state, and the current-mode digital-to-analog converter generates a reference current; In the 0° clock phase calibration stage, the calibration logic module is enabled and set to 1, the circuit starts the calibration process, and the clock phase representing 0° and its integer multiples is calibrated. The input control word of the phase interpolation module to be calibrated in the circuit to be calibrated is switched to 0, and the reference phase interpolation module in the reference circuit sets the first input control word to provide a first two-phase clock as a reference. The phase interpolation module to be calibrated provides a 0° clock, and the clock phase is adjusted through an adjustable current-type digital-to-analog converter containing a 4-bit calibration bit until the first preset condition is met, and it is determined that the current error exceeds the calibration range; the first preset condition indicates that the done0 signal representing the completion of the 0° clock calibration is set to 1, or the first preset condition indicates that all the 4-bit current-type digital-to-analog converter control bits are turned on or off.

10. A phase calibration system for a phase interpolation circuit according to claim 9, characterized in that: In the 45° clock phase calibration stage, when the 0° clock calibration is completed, the input control word input of the phase interpolation module to be calibrated is changed to the second input control word, the second input control word represents the 45° clock, the reference phase interpolation module control word is changed to the third input control word, a second two-phase clock is provided as a reference, the phase interpolation module to be calibrated provides a 45° clock, and the clock phase is adjusted by an adjustable current-type digital-to-analog converter containing a 4-bit calibration bit until the second preset condition is met, and it is determined that the current error exceeds the calibration range; the second preset condition indicates that the done45 signal representing the completion of the 45° clock calibration is set to 1, or the second preset condition indicates that all 4-bit control bits are turned on or off; In the calibration end stage, the calibration logic module control position is set to 0, the current-mode digital-to-analog converter calibration control word is updated, and the system is switched back to the external control word input to perform the calibrated clock phase adjustment.

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