Memory and forming method thereof
By introducing a buffer layer with a density higher than the isolation layer into a semiconductor structure that only selects the memory, filling the depressions of the isolation layer and covering the conductive layer, the problem of insufficient flatness of the conductive layer is solved, and the quality of the memory cell and memory performance are improved.
Patent Information
- Application Number
- CN202510345351.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-24
- Publication Date
- 2025-06-20
AI Technical Summary
In the manufacturing process of selecting memory only (SOM), the surface flatness of the plane where the conductive layer between the adjacent two memory cells is located is insufficient, affecting the quality of subsequent memory cells and the performance of the memory.
By introducing a buffer layer into the semiconductor structure, the buffer layer is filled in the depression of the isolation layer and covers the first conductive layer and the isolation layer, the density of the buffer layer is greater than the density of the isolation layer to provide uniform abrasion resistance, reduce the grinding rate, and reduce local depressions.
The flatness of the plane in which the first conductive layer is located is effectively improved, the quality of the stacked memory cells is improved, and the performance of selecting only memory is improved.
Smart Images
Figure CN120187035A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor-related technologies, and particularly to a memory and a method for forming the same. Background Art
[0002] Selector only memory (SOM) is an emerging non-volatile storage technology. Its storage structure only includes a selection layer and does not require a phase change layer formed by a phase change material. Compared with three-dimensional phase change memories, selector only memory (SOM) has advantages such as a simple structure, high scalability, fast read / write speed, and strong durability, showing broad application prospects in fields such as Compute Express Link (CXL) and High Bandwidth Memory (HBM).
[0003] In the manufacturing process of selector only memory (SOM), in order to improve storage density and performance, a two-layer or multi-layer storage cell stacking method needs to be adopted.
[0004] However, since the storage structure of selector only memory (SOM) does not include a phase change layer and the storage structure is only composed of an electrode layer and a selection layer, during the manufacturing process, the surface flatness of the plane where the conductive layer is located between two adjacent storage cells directly affects the quality of subsequent storage cells and the performance of selector only memory. Summary of the Invention
[0005] This application provides a memory and a method for forming the same, aiming to improve the flatness of the plane of the conductive layer between adjacent storage structures.
[0006] To achieve the above object, on the one hand, this application discloses a method for forming a memory, including:
[0007] Providing a semiconductor structure, the semiconductor structure includes a first storage structure, a plurality of mutually discrete first conductive layers, and an isolation layer; the first storage structure includes a plurality of storage cells arranged in an array, the plurality of mutually discrete first conductive layers are located on the same side of the plurality of storage cells, and the isolation layer is located between two adjacent storage cells, between two adjacent first conductive layers, and on the side of the first conductive layer facing away from the storage cells;
[0008] Performing a first planarization process on the isolation layer until the first conductive layer is exposed; at this time, the surface of the isolation layer between two adjacent first conductive layers is lower than the surface of the side of the first conductive layer facing away from the storage cells, and a first depression is formed;
[0009] Form a buffer layer covering the first conductive layer and the isolation layer; a surface of the buffer layer facing away from the storage unit extends beyond a surface of the first conductive layer facing away from the storage unit;
[0010] Perform a second planarization process on the buffer layer until the first conductive layer is exposed, and retain the buffer layer within the first recess.
[0011] Optionally, the material composition of the buffer layer is the same as that of the isolation layer, and the density of the buffer layer is greater than that of the isolation layer.
[0012] Optionally, forming the buffer layer covering the first conductive layer and the isolation layer includes:
[0013] Form the buffer layer by an atomic layer deposition process, and the temperature range of the atomic layer deposition process is 200 - 250 °C.
[0014] Optionally, after forming the buffer layer and before performing the second planarization process on the buffer layer, the method for forming the memory further includes:
[0015] Form a sacrificial layer on the buffer layer;
[0016] When performing the second planarization process, first perform the second planarization process on the sacrificial layer, and then perform the second planarization process on the buffer layer.
[0017] Optionally, forming the sacrificial layer on the buffer layer includes:
[0018] Form the sacrificial layer by a chemical vapor deposition process, and the chemical vapor deposition process uses tetraethyl orthosilicate as a raw material.
[0019] Optionally, the material composition of the buffer layer is the same as that of the sacrificial layer, and the density of the buffer layer is greater than that of the sacrificial layer.
[0020] Optionally, the thickness range of the buffer layer is [200, 250] angstroms; the thickness range of the sacrificial layer is [1000, 2000] angstroms.
[0021] Optionally, the method for forming the memory further includes:
[0022] After the second planarization process, form a metal film on a surface of the first conductive layer facing away from the storage structure;
[0023] Form a second storage structure on a surface of the metal film facing away from the first conductive layer.
[0024] On the other hand, the present application discloses a memory device, which is prepared by using the method for forming a memory device described in any one of the above disclosures. The memory device includes:
[0025] A semiconductor structure, the semiconductor structure includes a first storage structure, a plurality of mutually discrete first conductive layers, and an isolation layer. The first storage structure includes a plurality of memory cells arranged in an array. The plurality of mutually discrete first conductive layers are located on the same side of the plurality of memory cells. The isolation layer is located between adjacent two memory cells and between adjacent two first conductive layers;
[0026] Wherein, the surface of the isolation layer between adjacent two first conductive layers is lower than the surface of the first conductive layer facing away from the memory cell, having a first recess, and the first recess is filled with a buffer layer.
[0027] Optionally, the material composition of the buffer layer is the same as that of the isolation layer, and the density of the buffer layer is greater than that of the isolation layer.
[0028] Through the above technical solution, after the first planarization treatment of the isolation layer, a first recess is formed on the isolation layer between adjacent two first conductive layers. The present application introduces a buffer layer above the first conductive layer and the isolation layer. The buffer layer fills the first recess and covers the first conductive layer and the isolation layer. The density of the buffer layer is greater than that of the isolation layer. During the subsequent second planarization treatment when the first conductive layer is exposed again, the buffer layer can provide uniform grinding resistance, reduce the grinding rate, effectively reduce local depression, improve the flatness of the plane where the first conductive layer is located, improve the quality of the stacked memory cells, and enhance the performance of the selected memory device only. After the subsequent second planarization treatment, the buffer layer located in the first groove is retained, which also improves the flatness of the plane where the first conductive layer is located.
[0029] Other features and advantages of the present application will be described in detail in the subsequent specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0031] Figure 1 It is a schematic flowchart of a method for forming a memory device provided by an embodiment of the present application;
[0032] Figures 2 to 8 It is a cross-sectional view of the memory device provided by an embodiment of the present application during the formation process.
[0033] The main reference numerals in the accompanying drawings of this application specification are described as follows:
[0034] 11. First storage structure; 12. Second storage structure;
[0035] 21. Storage unit; 211. First electrode; 212. Strobe layer; 213. Second electrode; 22. First conductive layer; 23. Mask structure; 24. First depression; 25. Second conductive layer;
[0036] 30. Isolation layer;
[0037] 40. Buffer layer; 41. Sacrificial layer;
[0038] 50. Metal film. Detailed implementation manners
[0039] Next, the technical solutions in the embodiments of this application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of this application.
[0040] It should be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. For example, the first component may be referred to as the second component, and similarly, the second component may be referred to as the first component, without departing from the scope of this application.
[0041] It should be understood that when a component is said to be "on" another component or "connected" to another component, it may be directly on the other component or connected to the other component, or there may also be intervening components. Other words used to describe the relationship between components should be interpreted in a similar manner.
[0042] As used herein, the term "layer" refers to a portion of a material that includes a region having a thickness. The layer may extend over the entire underlying or overlying structure, or may have a scope smaller than the scope of the underlying or overlying structure. In addition, the layer may be a region of a uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any set of horizontal planes at the top and bottom surfaces. The layer may extend horizontally, vertically, and / or along a tapered surface. The substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. The layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers and one or more dielectric layers.
[0043] It should be noted that the illustrations provided in the embodiments of the present application are only used to illustrate the basic concept of the present application in a schematic manner. Although the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.
[0044] As mentioned in the background art, the memory cell of the select-only memory (SOM) does not contain a phase change layer, and the memory cell is composed only of an electrode layer and a gate layer. Therefore, during the manufacturing process, in the stacking direction of the memory structure, the surface flatness of the plane where the conductive layer between two adjacent memory structures is located directly affects the quality of the subsequent memory cells and the performance of the select-only memory.
[0045] In some embodiments, the memory includes a first storage structure, a plurality of mutually independent first conductive layers, and an isolation layer. The first storage structure includes a plurality of storage cells arranged in an array. The plurality of mutually independent first conductive layers are located on the same side of the plurality of storage cells, and the isolation layer is located between two adjacent storage cells, between two adjacent first conductive layers, and on the side of the first conductive layer away from the storage cell. When stacking the second storage structure on the first storage structure, the isolation layer needs to be planarized to expose the surface of the first conductive layer away from the storage cell, so as to provide a process plane for forming the second storage structure. However, when the isolation layer is planarized, a grinding speed that is too fast may cause a depression in the isolation layer between two adjacent first conductive layers, resulting in an uneven plane on the side of the first conductive layer away from the storage cell. In addition, in some embodiments, the surface of the first conductive layer facing away from the storage unit has a mask structure. When the isolation layer is planarized, the mask structure on the surface of the first conductive layer also needs to be planarized. The two have different densities and removal speeds. The isolation layer may be removed faster than the mask structure, which may cause a depression in the isolation layer between two adjacent first conductive layers. The depth of the depression is between 70 and 100 angstroms, resulting in an uneven plane on the side of the first conductive layer facing away from the storage unit.
[0046] If the surface flatness of the plane where the conductive layer between two adjacent memory cells is located is low and the depression is serious, it may cause the thickness of the gate layer of the memory cell formed by the subsequent stacking to be uneven, thus affecting the quality of the memory cell; in addition, the depression of the surface of two adjacent conductive layers may cause the distance between adjacent conductive layers to be too close, increasing the risk of short circuit and affecting the normal operation of the select-only memory. At the same time, the uneven surface of the conductive layer may also cause stress imbalance, causing the conductive layer to bend and deform, thereby affecting the stability of the signal transmission of the select-only memory (SOM).
[0047] Therefore, in order to improve the flatness of the plane where the first conductive layer is located between adjacent memory cells, so as to improve the quality of subsequent memory cells and the performance of the selected memory only. An embodiment of the present application provides a method for forming a memory.
[0048] Referring to Figure 1 , Figure 1 is a schematic flowchart of a method for forming a memory provided by an embodiment of the present application. As Figure 1 shown, an embodiment of the present application provides a method for forming a memory, which includes:
[0049] Step S100, providing a semiconductor structure, the semiconductor structure includes a first memory structure, a plurality of mutually discrete first conductive layers, and an isolation layer; the first memory structure includes a plurality of memory cells arranged in an array, the plurality of mutually discrete first conductive layers are located on the same side of the plurality of memory cells, and the isolation layer is located between adjacent two memory cells, between adjacent two first conductive layers, and on the side of the first conductive layer facing away from the memory cells;
[0050] Step S200, performing a first planarization process on the isolation layer until the first conductive layer is exposed; at this time, the surface of the isolation layer between adjacent two first conductive layers is lower than the surface of the side of the first conductive layer facing away from the memory cells, and a first depression is formed;
[0051] Step S300, forming a buffer layer covering the first conductive layer and the isolation layer; the surface of the buffer layer facing away from the memory cells extends beyond the surface of the side of the first conductive layer facing away from the memory cells;
[0052] Step S400, performing a second planarization process on the buffer layer until the first conductive layer is exposed, and retaining the buffer layer located in the first depression.
[0053] Referring to Figures 2 to 8 , Figures 2 to 8 is a cross-sectional view of the memory provided by an embodiment of the present application during the formation process. Next, the formation process of the memory provided by an embodiment of the present application will be described in detail with reference to Figure 1 and Figures 2 to 8 , and the formation process of the memory provided by an embodiment of the present application will be described in detail.
[0054] Before describing in detail the formation process of the memory provided by an embodiment of the present application, the directions that may be involved in the embodiment of the present application are defined first. The direction in which the memory cells 21 in the memory are arranged at intervals is defined as the intersecting first direction and second direction, and the stacking direction of the first memory structure 11 and the second memory structure 12 in the memory is defined as the third direction. Here, any two of the first direction, the second direction, and the third direction intersect. In some embodiments, any two of the first direction, the second direction, and the third direction are perpendicular to each other. The following will be described by taking any two of the first direction, the second direction, and the third direction being perpendicular to each other as an example.
[0055] Please refer to Figure 2 , in step S100 of the embodiment of the present application, a semiconductor structure is provided. The semiconductor structure includes a first storage structure 11, a plurality of mutually discrete first conductive layers 22, and an isolation layer 30. In some embodiments, the first storage structure 11 includes a plurality of memory cells 21 arranged in an array. The plurality of mutually discrete first conductive layers 22 are located on the same side of the plurality of memory cells 21. The isolation layer 30 is located between two adjacent memory cells 21, between two adjacent first conductive layers 22, and on the side of the first conductive layer 22 facing away from the memory cells 21. In other embodiments, the first storage structure 11 provided in step S100 is formed on a substrate. And based on the above embodiments, the semiconductor structure provided in step S100 further includes a mask structure 23. The mask structure 23 is located on the surface of the first conductive layer 22 facing away from the memory cells 21, and the isolation layer 30 covers the surface of the mask structure 23. The mask structure 23 serves as a patterned mask for etching to form the first conductive layer 22.
[0056] In some embodiments, the mask structure 23 may include, but is not limited to, a silicon nitride hard mask (Hard Mask SiN); the material of the isolation layer 30 may include, but is not limited to, a spin-on dielectric (SOD).
[0057] In some embodiments, the sidewalls of the memory cells 21 are further covered with sidewall protection layers. The sidewall protection layers are used to protect the memory cells 21. The material of the sidewall protection layers may include, but is not limited to, silicon nitride, silicon oxide, etc. The formation process of the sidewall protection layers includes, but is not limited to, a pulsed plasma process. In some other embodiments, the sidewall protection layers also cover the sidewalls of the first conductive layers 22 and the mask structure 23.
[0058] In some embodiments, the memory cells 21 are arranged in an array along a first direction and a second direction. The first direction and the second direction are parallel to the surface of the substrate, and the first direction and the second direction are different. The first conductive layer 22 is parallel to the first direction (in other words, the first conductive layer 22 extends along the first direction), is arranged at intervals along the second direction, and the first conductive layer 22 is connected to the plurality of memory cells 21 arranged along the first direction.
[0059] In some embodiments, the semiconductor structure provided in step S100 further includes a second conductive layer 25. The second conductive layer 25 is formed on the substrate, parallel to the second direction (in other words, the second conductive layer 25 extends along the second direction), arranged at intervals along the first direction. The storage unit 21 is located on the surface of the second conductive layer 25 facing away from the substrate (in other words, the first conductive layer 22 and the second conductive layer 25 are respectively located on both sides of the storage unit 21 in the third direction, and the third direction is perpendicular to the surface of the substrate). The second conductive layer 25 can be connected to a plurality of storage units 21 arranged along the second direction. It should be noted that the first conductive layer 22 can also be referred to as a word line, and the second conductive layer 25 can also be referred to as a bit line.
[0060] In some embodiments, the storage unit 21 includes, but is not limited to, a memory for forming a select-only memory. When the storage unit 21 is used to form a select-only memory, the storage unit 21 includes a first electrode 211, a select layer 212, and a second electrode 213 stacked along the third direction. The first electrode 211 and the second electrode 213 can be used to transmit electrical signals, and the materials of the first electrode 211 and the second electrode 213 include, but are not limited to, carbon electrodes. The select layer 212 can include a threshold switching material, such as a bidirectional threshold switching (Ovonic Threshold Switching, OTS) material. The OTS material can be a chalcogenide material, such as GeSeAs, GeTeAs, GeSeTeSe, GeSe, SeAs, GeTe, SiTe, etc. The bidirectional threshold switch uses an electrical signal to control the switching of the select device. When the applied electrical signal is higher than the threshold voltage, the OTS material changes from a high-resistance state to a low-resistance state, and at this time, the OTS is in an on state; when the electrical signal is removed, the OTS material changes from a low-resistance state to a high-resistance state, and at this time, the OTS is in an off state.
[0061] Please refer to Figure 3 and Figure 4 , in step S200, a first planarization process is performed on the isolation layer 30 until the first conductive layer 22 is exposed; at this time, the surface of the isolation layer 30 between two adjacent first conductive layers 22 is lower than the surface of the first conductive layer 22 facing away from the storage unit 21, and a first depression 24 is formed. The isolation layer 30 between two adjacent first conductive layers 22 and two adjacent storage units 21 can play a role in electrical isolation and structural support.
[0062] The first planarization process on the semiconductor structure with the mask structure 23 includes: first, performing a planarization process on the isolation layer 30 covering the mask structure 23 until the mask structure 23 is exposed (as Figure 3 shown); then, simultaneously performing a planarization process on the mask structure 23 and the isolation layer 30 until the first conductive layer 22 is exposed (asFigure 4 as shown
[0063] Due to the different removal rates of the mask structure 23 and the isolation layer 30 during the first planarization process, the removal rate of the isolation layer 30 is greater than that of the mask structure 23. After the first planarization process is completed, the surface of the isolation layer 30 between two adjacent first conductive layers 22 is lower than the surface of the first conductive layer 22 on the side away from the storage unit 21, forming a first depression 24.
[0064] Please refer to Figure 5 , in step S300, a buffer layer 40 covering the first conductive layer 22 and the isolation layer 30 is formed, and the surface of the buffer layer 40 away from the storage unit 21 extends beyond the surface of the first conductive layer 22 on the side away from the storage unit 21.
[0065] The buffer layer 40 can be filled in the first depression 24 to provide uniform polishing resistance for the subsequent second planarization process.
[0066] The material of the buffer layer 40 can include but is not limited to silicon oxide material. In some embodiments, the material of the buffer layer 40 is silicon oxide.
[0067] In some embodiments, the materials of the buffer layer 40 and the isolation layer 30 can be the same or different, and the density of the buffer layer 40 is greater than that of the isolation layer 30. The polishing rate of the buffer layer 40 is lower than that of the isolation layer 30.
[0068] The process of the buffer layer 40 includes chemical vapor deposition process, physical vapor deposition process, atomic layer deposition process, etc. In this embodiment, the forming process of the buffer layer 40 is atomic layer deposition process, and the atomic layer deposition process includes: the temperature range is 200 - 250 °C, including the temperatures at both ends, that is, including 200 °C and 250 °C.
[0069] In this embodiment, the temperature of the atomic layer deposition process is 250 °C, and the thickness of the buffer layer 40 is 250 Å.
[0070] Compared with forming the buffer layer 40 by atomic layer deposition process at a low temperature (50 °C - 75 °C), the buffer layer 40 formed by atomic layer deposition process at a high temperature (above 200 °C) can better fill the first depression 24, and the formed buffer layer 40 has a higher density, and the density of the formed buffer layer 40 is also greater than that of the isolation layer 30, and can provide uniform polishing resistance in the subsequent second planarization process.
[0071] In some embodiments, please refer to Figure 6 , a sacrificial layer 41 is formed on the surface of the buffer layer 40.
[0072] The sacrificial layer 41 can enhance the stability of the subsequent second planarization process and appropriately extend the grinding time of the subsequent second planarization process to optimize the endpoint control of the subsequent second planarization process.
[0073] The thickness range of the sacrificial layer 41 is 1000 - 2000 angstroms. The formation process of the sacrificial layer 41 includes but is not limited to Chemical Vapor Deposition (CVD) process and Physical Vapor Deposition process. In this embodiment, tetraethoxysilane (TEOS) is used as the raw material, and the sacrificial layer 41 is formed by chemical vapor deposition at a temperature of 300 °C, and the thickness of the sacrificial layer 41 is 1700 angstroms.
[0074] In some embodiments, the buffer layer 40 and the sacrificial layer 41 are made of the same material, which is silicon dioxide. In this embodiment, the buffer layer 40 is formed by atomic layer deposition process, and the sacrificial layer 41 is formed by chemical vapor deposition process, which can make both the buffer layer 40 and the sacrificial layer 41 made of silicon dioxide. When the buffer layer 40 and the sacrificial layer 41 are made of the same material, the interaction between the abrasive and the material is more consistent, and the endpoint can be more precisely controlled during the subsequent second planarization process, improving the surface flatness of the first conductive layer 22 and reducing the non-uniformity caused by different materials.
[0075] In this embodiment, forming the buffer layer 40 and the sacrificial layer 41 by different processes can also make the density of the buffer layer 40 greater than that of the sacrificial layer 41. The density of the buffer layer 40 being greater than that of the sacrificial layer 41 means that the grinding rate of the sacrificial layer 41 is relatively high. During the subsequent second planarization process, the sacrificial layer 41 can be quickly removed to achieve preliminary planarization and ensure process efficiency. When the grinding approaches the buffer layer 40, the grinding rate gradually decreases, entering a more refined polishing stage, making the endpoint control more precise, ultimately effectively improving the surface flatness of the first conductive layer 22, and at the same time optimizing the stability and operability of the entire second planarization process.
[0076] Please refer to Figure 7 , in step S400, the second planarization process is performed on the buffer layer 40 until the surface of the first conductive layer 22 facing away from the storage unit 21 is exposed, and the buffer layer 40 located in the first recess 24 is retained.
[0077] After the second planarization process, the buffer layer 40 remains in the first recess 24, which not only effectively improves the flatness of the surface where the first conductive layer 22 faces away from the storage unit 21, but also can provide support for the first recess 24, reducing the stress concentration phenomenon of the first conductive layer 22.
[0078] The high density of the buffer layer 40 can reduce the polishing rate during the second planarization process, making the material removal process more controllable, thereby improving polishing uniformity, reducing uneven polishing caused by excessive rate in local areas, and further optimizing the surface flatness. In addition, after the polishing rate is reduced, the endpoint control of the second planarization process is more accurate, making the polishing depth more stable, thereby effectively improving the flatness of the surface on the side of the first conductive layer 22 facing away from the storage unit 21.
[0079] When the surface of the buffer layer 40 is covered with a sacrificial layer 41, the second planarization process needs to first planarize the sacrificial layer 41 and then planarize the buffer layer 40. During the second planarization process, the sacrificial layer 41 is first planarized, and then the buffer layer 40 is gradually planarized, avoiding the sudden change in the polishing rate caused by directly polishing the high-density buffer layer 40 and improving the controllability of the second planarization process.
[0080] In some embodiments, please refer to Figure 8 , after completing step S400, the method for forming a memory further includes: forming a metal film 50 on the surface of the first conductive layer 22 on the side facing away from the storage unit 21; forming a second storage structure 12 on the side of the metal film 50 facing away from the first conductive layer 22.
[0081] After the second storage structure 12 is formed, a first conductive layer 22 or a second conductive layer 25 is formed on the surface of the second storage structure 12 on the side facing away from the first storage structure 11.
[0082] Refer to Figure 8 , the metal films 50 covering different first conductive layers 22 are separated from each other, and the metal film 50 can be tungsten.
[0083] It is worth mentioning that in this application, after the first planarization process, a buffer layer 40 is formed on the first conductive layer 22 and the isolation layer 30, and the second planarization process is introduced to expose the surface of the first conductive layer 22 again, effectively improving the flatness of the surface on the side of the first conductive layer 22 facing away from the storage unit 21. By filling the first depression 24 with the buffer layer 40, after the second planarization process, the depression phenomenon on the surface of the first conductive layer 22 on the side facing away from the storage unit 21 is reduced by about 80%. In some embodiments, a second depression may be formed on the buffer layer 40 located in the first depression 24 after the second planarization process of the buffer layer 40, but the depth of the second depression can be controlled within 15 angstroms, significantly improving the flatness of the surface on the side of the first conductive layer 22 facing away from the storage unit 21.
[0084] The embodiments of the present application also disclose a memory, which is prepared by using the method for forming a memory disclosed above. Refer to Figure 7, the memory includes a semiconductor structure, and the semiconductor structure includes a first storage structure 11, a plurality of mutually discrete first conductive layers 22, and an isolation layer 30. The first storage structure 11 includes a plurality of memory cells 21 arranged in an array. The plurality of mutually discrete first conductive layers 22 are located on the same side of the plurality of memory cells 21. The isolation layer 30 is located between two adjacent memory cells 21 and between two adjacent first conductive layers 22. Among them, the surface of the isolation layer 30 located between two adjacent first conductive layers 22 is lower than the surface of the first conductive layer 22 facing away from the memory cell 21, and a first recess 24 is formed, and the first recess 24 is filled with the isolation layer 30.
[0085] In some embodiments, the material of the buffer layer 40 is the same as that of the isolation layer 30, and the density of the buffer layer 40 is greater than that of the isolation layer 30.
[0086] In some embodiments, with reference to Figure 8 , a metal film 50 also covers the surface of the first conductive layer 22 facing away from the memory cell 21, and a second storage structure 12 is provided on the surface of the metal film 50 facing away from the first conductive layer 22.
[0087] It should be noted that the specific structures of the first storage structure 11 and the second storage structure 12 have been described in detail in the method for forming the memory, and will not be elaborated here.
[0088] In the description of this specification, specific features, structures, materials, or characteristics may be combined in a suitable manner in any one or more embodiments or examples.
[0089] As mentioned above, the above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims. In addition, specific examples are used in the specification to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application, and the content of this specification should not be construed as a limitation to the present application.
Claims
1. A method for forming a memory, characterized in that: include: Providing a semiconductor structure, the semiconductor structure comprising a first storage structure, a plurality of mutually separate first conductive layers and an isolation layer; The first storage structure comprises a plurality of storage units arranged in an array, the plurality of mutually independent first conductive layers are located on the same side of the plurality of storage units, and the isolation layer is located between two adjacent storage units, between two adjacent first conductive layers, and on a side of the first conductive layer away from the storage unit; Performing a first planarization process on the isolation layer until the first conductive layer is exposed; at this time, the surface of the isolation layer between two adjacent first conductive layers is lower than the surface of the first conductive layer on one side away from the storage unit, forming a first recess; forming a buffer layer covering the first conductive layer and the isolation layer; The surface of the buffer layer facing away from the memory cell exceeds the surface of one side of the first conductive layer facing away from the memory cell; The buffer layer is subjected to a second planarization process until the first conductive layer is exposed, and the buffer layer in the first recess is retained.
2. The method for forming a memory according to claim 1, wherein: The material composition of the buffer layer is the same as that of the isolation layer, and the density of the buffer layer is greater than that of the isolation layer.
3. The method for forming a memory according to claim 1, wherein: The forming of a buffer layer covering the first conductive layer and the isolation layer comprises: The buffer layer is formed by an atomic layer deposition process, and the temperature range of the atomic layer deposition process is 200-250°C.
4. The method for forming a memory according to claim 1, wherein: After forming the buffer layer and before performing a second planarization process on the buffer layer, the method for forming the memory further includes: forming a sacrificial layer on the buffer layer; When performing the second planarization treatment, the sacrificial layer is firstly subjected to the second planarization treatment, and then the buffer layer is subjected to the second planarization treatment.
5. The method for forming a memory according to claim 4, characterized in that: The forming of a sacrificial layer on the buffer layer comprises: The sacrificial layer is formed by a chemical vapor deposition process using tetraethylsiloxane as a raw material.
6. The method for forming a memory according to claim 4, characterized in that: The material composition of the buffer layer is the same as that of the sacrificial layer, and the density of the buffer layer is greater than the density of the sacrificial layer.
7. The method for forming a memory according to claim 4, characterized in that: The thickness of the buffer layer is in the range of [200, 250] angstroms; the thickness of the sacrificial layer is in the range of [1000, 2000] angstroms.
8. The method for forming a memory according to claim 1, characterized in that: The method for forming the memory further includes: After the second planarization process, forming a metal film on a surface of the first conductive layer that is away from the storage unit; A second storage structure is formed on a surface of the metal film on a side away from the first conductive layer.
9. A memory, characterized in that: Prepared by the method for forming a memory according to any one of claims 1 to 8, the memory comprising: A semiconductor structure, the semiconductor structure comprising a first storage structure, a plurality of mutually independent first conductive layers and an isolation layer, the first storage structure comprising a plurality of storage cells arranged in an array, the plurality of mutually independent first conductive layers being located on the same side of the plurality of storage cells, and the isolation layer being located between two adjacent storage cells and between two adjacent first conductive layers; The isolation layer between two adjacent first conductive layers has a surface lower than a surface of the first conductive layer facing away from the storage unit and has a first recess filled with a buffer layer.
10. The memory according to claim 9, characterized in that: The material composition of the buffer layer is the same as that of the isolation layer, and the density of the buffer layer is greater than that of the isolation layer.