CMOS with mixed contact

Abstract

A MOSFET transistor structure includes: a well region having a first dopant polarity; a source region; a drain region; a channel region; a gate structure over the channel region; a mixed contact implant having a second dopant polarity in the source region or the drain region; and a respective metal contact on or within each of the source region, the gate structure, and the drain region. The mixed contact implant combines with the metal contact on or within the source region or the drain region, respectively, to form a mixed contact defining first, second, and third electrical junctions. The first electrical junction is a Schottky junction vertically formed between the source metal contact or the drain metal contact and the well region, respectively. The second electrical junction is an ohmic junction formed laterally between the source metal contact or the drain metal contact and the mixed contact implant, respectively. The third electrical junction is a rectification PN junction between the mixed contact implant and the channel region.

Description

[0001] This application is a divisional application of Chinese Patent Application (Application No.: 202080077330.4, Application Date: November 5, 2020, Invention Title: Apparatus and Method for LDMOS and Other MOS Transistors with Hybrid Contacts).

[0002] Cross - reference to Related Applications

[0003] For the United States, this application is a continuation application of U.S. Non - Provisional Patent Application No. 16 / 845,666, filed on April 10, 2020, and claims the priority of the 16 / 845,666 application under 35 U.S.C. § 120. The entire content of the 16 / 845,666 application is incorporated herein by reference. The 16 / 845,666 application is a non - provisional patent application of U.S. Provisional Patent Application No. 62 / 931,535, filed on November 6, 2019, and claims the priority of the U.S. provisional patent application under 35 U.S.C.§ 119(e). The entire content of the U.S. provisional patent application is incorporated herein by reference. And, for the United States, this application is a non - provisional patent application of U.S. Provisional Patent Application No. 62 / 931,535, filed on November 6, 2019, and claims the priority of the U.S. provisional patent application under 35 U.S.C.§ 119(e). The entire content of the U.S. provisional patent application is incorporated herein by reference.

[0004] Copyright Notice

[0005] All materials in this patent document are protected by copyright laws of the United States and other countries. The copyright owner does not object to anyone faxing and reproducing the patent document or patent disclosure that appears in the patent file or records of the Patent and Trademark Office, but reserves all copyrights in all other cases. Technical Field

[0006] This disclosure generally relates to the structure of metal - oxide - semiconductor field - effect transistors (MOSFETs) and corresponding design methods. More particularly, it relates to forming hybrid contacts during the fabrication of source regions in LDMOS and sources and / or drains in other MOSFETs, which contain Schottky, ohmic, and rectifying PN junctions. Background Art

[0007] For decades, semiconductor reliability and robustness have been a major concern in the industry. One such factor of reliability and robustness is related to the Electrical Safe Operating Area (E-SOA). Although the E-SOA can be affected by various factors, one phenomenon that can significantly affect the E-SOA is the bipolar-induced snapback associated with the parasitic bipolar junction transistor (BJT) in MOSFETs. For illustrative purposes, Figure 1A FIG. 18 is a cross-sectional view of an exemplary LDMOS device 10 showing the parasitic BJT 40. The LDMOS device 10 has a p-type substrate 21, a p-type body 20, an n-type well 13, a body tap 18 (formed by p-type diffusion), a shallow trench isolation 11, a gate structure 16 (polysilicon on gate oxide) and a gate sidewall spacer structure 15, a source region 14 (formed by n-type diffusion), a drain region 12 (formed by n-type diffusion), and ohmic contacts 22, 23, 24 formed at the source, gate, and drain adjacent to the body tap, respectively, by silicide placement. A conventional "ohmic contact" has an ohmic connection between the silicide and the n+ diffusion and a rectifying PN junction between the n+ diffusion and the underlying body / well. Figure 1A The device 10 in FIG. 19 includes an inherent parasitic bipolar junction transistor (BJT) 40 formed between the source 14, the body 20, and the n-type well (drift region) 13 of the device 10. These three regions form the bipolar emitter (source 14), base (body 20), and collector (drift region 13) of the parasitic BJT 40, respectively. When a high voltage is applied to the drain 12, the parasitic BJT 40 can be turned on at the trigger voltage (V t1 ), which generates an alternative current path (I h1 ) 42 between the drain 12 and the source 14 of the device 10. As the gate voltage increases, the drain voltage that triggers the BJT becomes even lower, thereby reducing the E-SOA of the LDMOS device 10. When the parasitic BJT 40 dominates the operation of the device 10, the local current causes extremely high temperatures and eventually leads to the destruction of the device. This is typically shown in Figure 1B FIG. 20, which is a graphical illustration of the bipolar triggering and device destruction phases.

[0008] A conventional method of mitigating the parasitic BJT of an LDMOS device is to use a highly doped buried body (well) region directly below the n-type diffusion 14. The effect of this use is to reduce the bulk resistance (Rbulk) 49. With a lower Rbulk 49, in response to the hole current from the drain-body junction breakdown, a smaller base-emitter voltage can be generated across this resistance. With a lower base-emitter voltage, the triggering of the bipolar is suppressed.

[0009] The parasitic BJT problem also exists in complementary MOS (CMOS) devices. In this regard, Figure 1C FIG. 3 is a cross-sectional view of exemplary n-channel and p-channel CMOS devices, which shows parasitic BJTs 70, 80 combined to form a parasitic silicon controlled rectifier (SCR) structure. More specifically, Figure 1C FIG. 3 shows complementary NMOS and PMOS devices, which include a p-type substrate 321, a p-type well 31, an n-type well 51, a p-type well body tap 18 (formed by p-type diffusion), an n-type well body tap 58 (formed by n-type diffusion), an NMOS gate structure (n-type polysilicon on a gate oxide) 16, a PMOS gate structure (p-type polysilicon on a gate oxide) 56, a gate sidewall spacer structure 15, an NMOS source region 14 (formed by n-type diffusion), an NMOS drain region 12 (formed by n-type diffusion), a PMOS source region 54 (formed by p-type diffusion), a PMOS drain region 55 (formed by p-type diffusion), and ohmic contacts 22, 23, 24, 25 formed at the source, gate, drain, and body tap regions respectively by silicide placement. The triggering of the parasitic SCR induces latch-up, inadvertently creating a low-impedance path through electrostatic discharge (ESD), electrical overstress (EOS), or an ionizing radiation event, thereby triggering the parasitic SCR and causing a continuous current in the SCR structure, which can lead to permanent damage to the CMOS device.

[0010] Alternative methods have also been utilized, where instead of focusing on the body / well below the source diffusion, the design of the source that forms the emitter of the parasitic bipolar is modified by using a Schottky junction. Replacing the PN source with a Schottky source helps the E-SOA in two ways. First, the shallower source gives the hole current from the drain-body breakdown a direct path to the body tap. Therefore, the resistance experienced by these hole currents is lower than that of a deeper diffused source, and thus a lower effective Rbulk 49, 79, 89 is obtained. Second, the Schottky junction has an electron injection barrier, while the PN junction does not. This means that when the Schottky junction is forward-biased, the injection of electrons from the emitter to the base region is greatly reduced, and thus the bipolar cannot be triggered. The combination of the two factors enables the suppression of the parasitic bipolar and the extension of the electrical SOA compared to conventional LDMOS devices. For CMOS devices, reducing the bipolar gain of the parasitic SCR eliminates latch-up.

[0011] Various solutions involving Schottky junctions or contacts have been explored in some MOSFET devices to address a variety of issues including extending E-SOA, which are defined as metal (or metal with interfacial dopants) to well / bulk source and / or drain junctions. However, as further detailed below, each solution is insufficient to provide a complete solution across MOS devices.

[0012] For example, U.S. Patent No. 9,947,787 to Dolny et al. ("Dolny") discloses a power MOSFET (LDMOS) having a portion referred to as a "Schottky" or "Schottky-like" source. For such devices, Dolny teaches replacing the highly doped source / drain regions with Schottky or Schottky-like contacts. These Schottky contacts form a Schottky barrier between the source and / or drain regions of the device and the body or well. Due to the nature of the LDMOS design, spacers are used between the gate and the source / drain regions. Notably, Dolny also teaches "after (gate) spacer formation... after p+ body contact implant and anneal, form the Schottky or Schottky-like contact", which ensures a significant barrier height is maintained between the silicide and the silicon even when dopant segregation is used to modify the barrier height of the Schottky junction. This restricts electron conduction between the source and the channel region, thereby reducing the drive current and increasing the on-resistance of the transistor.

[0013] A series of short-channel Schottky barrier MOSFET device and manufacturing patents by inventor John P. Snyder also describe MOSFET devices that use Schottky barrier contacts for source and / or drain contact fabrication in the context of a MOSFET device structure to eliminate the need for halo / pocket implants and shallow source / drain extensions, thereby controlling short-channel effects. These patents include U.S. Patent Nos. 8,058,167, 8,154,025, 7,221,019, 6,744,103, 6,495,882, and 6,303,479.

[0014] In one example, U.S. Patent No. 6,495,882 to Snyder (the "Snyder") defines a short-channel MOSFET device having Schottky or Schottky-like source and / or drain regions with a channel length less than 100 nm. For such devices, Snyder teaches replacing the highly doped source / drain regions 14, 12, 54, 55; the lightly doped source / drain extensions 33, 53 (often referred to as the "LDD" regions) and the pocket / halo implants 32, 52 with metal silicides such as platinum silicide, palladium silicide, and iridium silicide. These Schottky contacts form a Schottky barrier between the source region of the device and the well or body. Benefits of this approach to MOSFET design include: reduced manufacturing complexity due to the avoidance of the need for LDD implants 33, 53 and thus pocket / halo implants 32, 52; reduced capacitance in the absence of pocket / halo implants 32, 52; and elimination of parasitic bipolar gain and associated latch-up. However, the Snyder design is limited by the channel length and the channel dopant concentration.

[0015] In both Dolny and Snyder, no dopant is located under the spacer. As mentioned above, a significant barrier height is maintained between the silicide and the silicon, which limits electron conduction between the source and / or drain and the channel region, reducing the drive current and increasing the on-resistance of the transistor.

[0016] M. Nishisaka envisioned a "Schottky SOI MOSFET with lightly doped extensions". Since Nishisaka's device is a SOI MOSFET, the current leakage described above is not a problem. The metal-semiconductor Schottky junction exists only laterally between the deep (200 nm) silicide placed on the SOI and the adjacent body region. Vertically, Nishisaka's source / drain silicide has an oxide termination as compared to the case shown by Snyder and Dolny.

[0017] Currently, the Schottky contacts in Snyder and Dolny eliminate the parasitic BJTs 40, 70, 80 in their MOSFET devices, thus allowing a larger drain voltage. However, in all designs having a vertical Schottky junction between the silicide metal and the body, no dopant / implant is present under the spacer region for the purpose of providing a low-ohmic path to the channel. For a square E-SOA, an ideal Schottky source contact with the least amount of dopant is needed to minimize electron injection and suppress BJT triggering under ESD events. Therefore, there is a need to be able to minimize the triggering of parasitic BJTs in MOSFET devices, thereby improving the E-SOA and maintaining a high MOSFET channel current while maintaining low junction leakage using a simple and cost-effective manufacturing process. SUMMARY OF THE INVENTION

[0018] Some exemplary embodiments of the present invention may overcome one or more of the above disadvantages and other disadvantages not described above, but the present invention is not required to overcome any specific disadvantage described above, and some exemplary embodiments of the present invention may not overcome any of the disadvantages described above.

[0019] The present invention includes many aspects and features. In addition, although many aspects and features are related to LDMOS devices and are described in the context of LDMOS devices, the present invention is not limited to being used only in LDMOS devices, as will become apparent from the following overview and detailed description of the aspects, features, and one or more specific examples of the present invention.

[0020] Broadly defined, aspects of one or more specific examples of the present invention relate to a lateral DMOS transistor structure, which includes: a substrate having a first dopant polarity; a body region having a first dopant polarity; a source region on or within the body region; a drift region having a second dopant polarity; a drain region on or within the drift region; a channel region between the source region and the drift region; a gate structure above the channel region; a hybrid contact implant having a second dopant polarity in the source region; and respective metal contacts on or within each of the source region, the gate structure, and the drain region; wherein the hybrid contact implant combines with the metal contact on or within the source region to form a hybrid contact that defines first, second, and third electrical junctions, wherein the first electrical junction is a Schottky junction vertically formed between the source metal contact and the body, wherein the second electrical junction is an ohmic junction laterally formed between the source metal contact and the hybrid contact implant, and wherein the third electrical junction is a rectifying PN junction between the hybrid contact implant and the channel region.

[0021] In a feature of this aspect, the hybrid contact implant is aligned with the gate structure.

[0022] In another feature of this aspect, the hybrid contact implant has an implanted depth that defines a first depth, the metal contact of the hybrid contact has a second depth, and the first depth is less than the depth of the second depth.

[0023] In another feature of this aspect, the hybrid contact implant has a doping concentration greater than 1e19 atoms / cm³.

[0024] In another feature of this aspect, an interfacial dopant layer is disposed between the metal contact and the body region, thereby modulating the barrier height and turn-on voltage of the first electrical junction.

[0025] In another feature of this aspect, the first electrical contact has a turn-on voltage in the range of 0.1 V to 0.5 V.

[0026] In another feature of this aspect, the parasitic bipolar junction transistor is formed by the drain-body-source region, and the parasitic bipolar junction transistor formed by the drain-body-source region has a bipolar gain less than 1.

[0027] In another feature of this aspect, the gate structure has a source region side and a drain region side, wherein the gate sidewall spacer structure is disposed along the gate structure on its source region side, and wherein the hybrid contact implant is disposed directly below the gate sidewall spacer structure. In other features, the metal contact on or in the source region is aligned with the gate sidewall spacer structure; and / or a first portion of the hybrid contact implant is disposed below the gate sidewall spacer structure, and a second portion of the hybrid contact implant is exposed adjacent to the gate sidewall spacer structure, a second electrical contact is formed laterally between the source metal contact and the first portion of the hybrid contact implant, and the third electrical contact is a rectifying PN junction between the first portion of the hybrid contact implant and the channel region.

[0028] In another feature of this aspect, each of the respective metal contacts on or in each of the source region, the gate structure, and the drain region is a silicide.

[0029] Broadly defined, another aspect of one or more specific examples of the present invention is directed to a method of fabricating a power transistor structure, the method comprising the steps of: providing a substrate having a first dopant polarity, wherein the substrate includes a body region also having the first dopant polarity; forming a drift region having a second dopant polarity on or within the substrate; forming a gate structure over a portion of the body region and a portion of the drift region by oxide growth, polysilicon deposition, and polysilicon etching; implanting a dopant having a second dopant polarity into the body region, the dopant being aligned with the gate structure, the implanted dopant defining a hybrid contact implant having a first depth; forming a gate sidewall spacer structure such that a first portion of the hybrid contact implant is disposed beneath the gate sidewall spacer structure and a second portion of the hybrid contact implant is exposed adjacent to the gate sidewall spacer structure; diffusing a dopant having a first dopant polarity into the body region to form a body tap; coating a photoresist layer over the body region including the body tap adjacent to the gate structure, but exposing the gate structure and the drift region; diffusing a dopant having a second dopant polarity into the gate structure and the drift region to form a drain region; depositing a blanket layer of metal; annealing the metal of the blanket layer to react with the body tap, the drain region, the gate structure, and the exposed silicon / polysilicon on the second portion of the hybrid contact implant to form silicides, wherein the silicide formed on the second portion of the hybrid contact implant has a second depth, and wherein the second depth is greater than the first depth; and removing the unreacted portion of the blanket layer of metal, thereby creating metal contacts to the body tap, the drain region, the gate structure, and the hybrid contact implant; whereby the silicide, the first portion of the hybrid contact implant, and the second portion of the hybrid contact implant together form a hybrid contact that constitutes a source region, and wherein a channel region is established between the source region and the drift region; and whereby the resulting hybrid contact defines first, second, and third electrical interfaces, wherein the first electrical interface is a Schottky interface formed vertically between the silicide and the substrate, wherein the second electrical interface is an ohmic interface formed laterally between the silicide and the first portion of the hybrid contact implant, and wherein the third electrical interface is a rectifying PN interface between the first portion of the hybrid contact implant and the channel region.

[0030] In another feature of this aspect, the method further comprises the step of coating a first photoresist layer over the drift region and a portion of the body region prior to the implant step, and wherein the implant step is performed using the first photoresist layer and a portion of the gate structure as a mask.

[0031] In another feature of this aspect, the source region does not include the diffusion of a dopant having a second dopant polarity into the body region.

[0032] In another feature of this aspect, depositing metal on the second exposed portion of the hybrid contact implant and annealing the deposited metal causes an interfacial dopant layer to form between the silicide and the body region.

[0033] Broadly defined, another aspect of one or more specific examples of the present invention is directed to a method of fabricating a power transistor structure, which includes the steps of: providing a substrate having a first dopant polarity, wherein the substrate includes a body region also having the first dopant polarity; forming a drift region having a second dopant polarity on or within the substrate; forming a gate structure over a portion of the body region and a portion of the drift region by oxide growth, polysilicon deposition, and polysilicon etching; coating a first photoresist layer over the drift region and a portion of the body region; using the first photoresist layer and a portion of the gate structure as a mask to implant a dopant having a second dopant polarity into the body region, the implanted dopant defining a hybrid contact implant having a first depth; forming a gate sidewall spacer structure such that a first portion of the hybrid contact implant is disposed beneath the gate sidewall spacer structure and a second portion of the hybrid contact implant is exposed adjacent to the gate sidewall spacer structure; diffusing a dopant having a first dopant polarity into the body region to form a body tap; coating a second photoresist layer over the body region including the body tap adjacent to the gate structure, but exposing the gate structure and the drift region; diffusing a dopant having a second dopant polarity into the gate structure and the drift region to form a drain region; depositing a blanket layer of metal; annealing the metal of the blanket layer to react with the body tap, the drain region, the gate structure, and the exposed silicon / polysilicon on the second portion of the hybrid contact implant to form silicide, wherein the silicide formed on the second portion of the hybrid contact implant has a second depth and wherein the second depth is greater than the first depth; and removing the unreacted portion of the blanket layer of metal, thereby creating metal contacts to the body tap, the drain region, the gate structure, and the hybrid contact implant; whereby the silicide, the first portion of the hybrid contact implant, and the second portion of the hybrid contact implant together form a hybrid contact that constitutes a source region, and wherein a channel region is established between the source region and the drift region; and whereby the resulting hybrid contact defines first, second, and third electrical interfaces, wherein the first electrical interface is a Schottky interface formed vertically between the silicide and the substrate, wherein the second electrical interface is an ohmic interface formed laterally between the silicide and the first portion of the hybrid contact implant, and wherein the third electrical interface is a rectifying PN interface between the first portion of the hybrid contact implant and the channel region.

[0034] Other applications of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating preferred specific examples of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Other features, specific examples, and advantages of the present invention will become apparent from the following detailed description with reference to the drawings, in which:

[0036] Figure 1A is a cross-sectional view of an exemplary LDMOS device showing a parasitic BJT;

[0037] Figure 1B is a graphical illustration of the bipolar triggering and device destruction phases;

[0038] Figure 1C is a cross-sectional view of exemplary n-channel and p-channel CMOS devices showing a parasitic BJT;

[0039] Figure 2 is a cross-sectional view of an exemplary hybrid contact LDMOS device according to one or more preferred specific examples of the present invention;

[0040] Figure 3A is for Figure 2 an enlarged cross-sectional view of an exemplary hybrid contact of an LDMOS device;

[0041] Figure 3B is for Figure 2 a cross-sectional view of an exemplary hybrid contact LDMOS device showing a mask formed by a combination of a photoresist coating and a gate structure (polysilicon on gate oxide) for hybrid contact implants;

[0042] Figure 3C is for Figure 3A a band diagram of the n-type interface dopant layer vertical Schottky junction (A-A') region of a MOS device, where the metal energy level is close to the mid-gap on a p-type substrate;

[0043] Figure 3D is for Figure 3A a band diagram of the lateral ohmic connection of the channel (B-B') region of a hybrid contact, where the metal energy level is close to the mid-gap on n-type silicon;

[0044] Figure 3E is for Figure 3A an Energy Dispersive X-ray Spectroscopy (EDS) image of a hybrid contact;

[0045] Figure 4A is an enlarged cross-sectional view of an exemplary hybrid contact for use in a MOS device according to one or more other preferred specific examples of the present invention;

[0046] Figure 4B is forFigure 4A Energy band diagram of the vertical classical Schottky energy band in the A-A' region of the hybrid contact, where the metal energy level is close to the middle band gap on the p-type substrate;

[0047] Figure 5A is Figure 1A Cross-sectional view of the source contact region of

[0048] Figure 5B is Figure 5A Circuit schematic diagram of the source contact region of , where the corresponding MOS device is in the off state;

[0049] Figure 6A Cross-sectional view of the Schottky-only source contact region using the conventional spacer width;

[0050] Figure 6B is Figure 6A Circuit schematic diagram of the source contact region of , where the corresponding MOS device is in the off state;

[0051] Figure 7A is Figure 3A Cross-sectional view of the source contact region featuring a hybrid contact, which illustrates the Schottky and PN diodes and the resistor;

[0052] Figure 7B is Figure 7A Circuit schematic diagram of the source contact region featuring a hybrid contact, where the corresponding MOS device is in the off state;

[0053] Figure 8A Graph showing the arsenic migration during the experimental fabrication process after silicide formation;

[0054] Figure 8B Graph showing the arsenic migration after the second annealing when the wafer is completed;

[0055] Figure 9 is to compare Figure 2 Lateral BJT gain of the hybrid contact on the source of the LDMOS device of with the lateral BJT gain of the conventional source in the LDMOS device similar to Figure 1A device;

[0056] Figure 10 is Figure 1A conventional LDMOS with a PN source ( Figure 2 ),

[0057] Figure 11ACross-sectional view of an n-channel CMOS device with hybrid contacts according to one or more other preferred embodiments of the present invention;

[0058] Figure 11B Cross-sectional view of a p-channel CMOS device with hybrid contacts according to one or more other preferred embodiments of the present invention;

[0059] Figures 12A to 12E Cross-sectional view illustrating various steps in a method of manufacturing a hybrid-contact LDMOS device in one or more preferred embodiments of the present invention; and

[0060] Figure 13 Illustrating Figures 12A to 12E Flowchart of the steps of a hybrid-contact LDMOS device manufacturing process. Detailed Description

[0061] As a preliminary matter, those of ordinary skill in the art (the "person of ordinary skill") will readily appreciate that the present invention has broad utility and applicability. In addition, any specific embodiments discussed and identified as "preferred" are considered to be part of the best mode contemplated for carrying out the present invention. Other specific embodiments may also be discussed for additional illustrative purposes to provide a complete and enabling disclosure of the present invention. In addition, many specific embodiments such as adaptations, variations, modifications, and equivalent configurations are implicitly disclosed by the specific embodiments described herein and fall within the scope of the present invention.

[0062] Accordingly, while the present invention is described in detail herein with respect to one or more specific embodiments, it is to be understood that this disclosure illustrates and exemplifies the present invention and is made only for the purpose of providing a complete and enabling disclosure of the present invention. The detailed disclosure of one or more specific embodiments herein is neither intended nor to be construed as limiting the scope of the patent protection provided by the present invention, which will be defined by the claims and their equivalents. The scope of the patent protection provided by the present invention is not intended to be defined by limitations found herein that are not expressly present in the technical solution itself in any technical solution.

[0063] Thus, for example, any one or more sequences and / or temporal orders of the steps of the various procedures or methods described herein are illustrative and not restrictive. Accordingly, it is to be understood that although the steps of the various procedures or methods may be shown and described as in a sequence or temporal order, in the absence of further indication, any such steps of any such procedures or methods are not limited to being performed in any particular sequence or order. In fact, the steps in such procedures or methods can generally be performed in a variety of different sequences and orders while still falling within the scope of the present invention. Accordingly, the scope of the patent protection provided by the present invention is intended to be defined by the appended claims rather than the description set forth herein.

[0064] In addition, it is noted that each term used herein means what a person of ordinary skill in the art would understand such term to mean based on the context of the term's use herein. In the event that the meaning of a term used herein as understood by a person of ordinary skill in the art based on the context of the term's use differs in any way from any specific dictionary definition of such term, the meaning of the term as understood by the person of ordinary skill in the art is intended to prevail.

[0065] Further, it is noted that as used herein, "a / an" each generally indicates "at least one", but does not exclude a plurality, unless the context of use otherwise dictates. Thus, a reference to "a picnic basket having an apple" describes "a picnic basket having at least one apple" as well as "a picnic basket having a plurality of apples". In contrast, a reference to "a picnic basket having a single apple" describes "a picnic basket having only one apple".

[0066] When used herein to introduce a list of items, "or" indicates "at least one of the items", but does not exclude a plurality of items in the list. Thus, a reference to "a picnic basket having cheese or crackers" describes "a picnic basket having cheese and not having crackers", "a picnic basket having crackers and not having cheese", and "a picnic basket having both cheese and crackers". Finally, when used herein to introduce a list of items, "and" indicates "all of the items in the list". Thus, a reference to "a picnic basket having cheese and crackers" describes "a picnic basket having cheese, wherein the picnic basket further has crackers" and describes "a picnic basket having crackers, wherein the picnic basket further has cheese".

[0067] Referring now to the drawings, in which like numerals represent like components throughout several views, preferred specific examples of the present invention will now be described. The following description of the preferred specific examples is exemplary in nature only and is in no way intended to limit the invention, its application, or uses.

[0068] Figure 2 FIG. is a cross-sectional view of an exemplary hybrid contact LDMOS device 100 in accordance with one or more preferred specific examples of the present invention. As with Figure 1A the exemplary LDMOS device 10, Figure 2 the LDMOS device 100 has a p-type substrate 121, a p-type body 120, an n-type well 113, a body tap 118, shallow trench isolation 111, a gate structure 116 (polysilicon on gate oxide) and a gate sidewall spacer structure 115, a drain region 112, and ohmic contacts 123, 124 formed by silicidation at the gate and drain, respectively. In at least some specific examples, these elements all have the same as Figure 1AThose configurations of the exemplary prior art LDMOS device 10 therein are generally similar configurations. However, notably, the n-type diffusion 14 in the source region no longer exists. In addition, a hybrid contact 110 formed by the placement of a hybrid contact implant 114 and subsequent silicidation of the metal 122 replaces the original PN rectifying junction of the n-type diffusion to the underlying p-type body. As described below, an interfacial dopant layer 117 can be formed on or in the silicide 122.

[0069] Figure 3A For Figure 2 An enlarged cross-sectional view of the exemplary hybrid contact 110 of the LDMOS device 100. Notably, although described in the context of the Figure 2 LDMOS device 100, it should be understood that in various preferred embodiments of the present invention, the hybrid contact 110 is also applicable to other MOS devices. The hybrid contact 110 includes a hybrid contact implant 114 placed in the p-type body 120 and a silicide metal 122 adjacent to the hybrid contact implant 114. Notably, as Figure 3A may be best shown in and as mentioned above, Figure 1A the n-type diffusion in the source region 14 of the LDMOS device 10 in Figure 12C does not exist. The fact is that the hybrid contact implant 114 having a first part and a second part is aligned with the gate structure 116 before the placement of the gate sidewall spacer structure 115 (which covers the first part, as Figure 3B For Figure 2 A cross-sectional view of the exemplary hybrid contact LDMOS device 100 in Figure 12C which shows the use of a mask formed by a combination of a photoresist coating 170 and a gate structure 116 (polysilicon on gate oxide) for the hybrid contact implant. The n-type diffusion 14 in the source region of the exemplary LDMOS device 10 forms a PN source-body junction. In the hybrid contact 110, the n-type diffusion in the source region has been omitted, leaving the silicide metal 122 on the p-type body region 120, including the interfacial dopant layer 117, thereby forming a vertical metal-to-p-type Schottky junction 130 (A-A'), the barrier height of which has been modified by the second part of the hybrid contact implant 114. The interfacial dopant layer 117 is generated by the displacement of the second part of the hybrid contact implant 114 ( Figure 12C the part not covered by the gate sidewall spacer structure) during silicidation. The first part of the hybrid contact implant 114 ultimately results in as Figure 3AThe ohmic coupling region 132 (B-B') shown therein. When the device is in operation, the vertical rectifying Schottky junction 130 (A-A') ensures minimal electron injection into the body when the source-body junction is forward-biased. Laterally, the silicide metal interfaces with the lightly doped n-type semiconductive region to form an ohmic connection 132 (B-B') to the channel, which enables electrons to tunnel between the metal and the semiconductor to achieve high current and low resistance.

[0070] The combination of the Schottky junction in a single contact and the ohmic connection to the channel together forms a first preferred embodiment of the hybrid contact 110. Figure 3C For Figure 3A the n-type interface dopant layer vertical Schottky junction 130 (A-A') region of the hybrid contact 110, where the metal energy level is close to the mid-gap on the p-type substrate, while Figure 3D For Figure 3A the energy band diagram of the lateral ohmic connection 132 (B-B') region of the hybrid contact 110 to the channel region, where the metal energy level is close to the mid-gap on the n-type silicon.

[0071] Figure 3E For Figure 3A the energy dispersive X-ray spectrometer (EDS) image of the hybrid contact 110. This EDS image shows the location of the shallowly implanted arsenic adjacent to the source silicide, resulting in a high concentration of arsenic under the gate sidewall spacer structure. Some arsenic from the second portion of the hybrid contact implant 114 is visible on the top and inside of the cobalt silicide, while the arsenic in the interface dopant layer at the bottom of the silicide is below the detection limit of this instrument. The presence of the "activated" interface dopant has been confirmed by the change in electrical characteristics, which is an increase in the source junction turn-on voltage due to the increased barrier height.

[0072] Notably, although Figure 3A the interface dopant layer 117 shown therein can be advantageously used to modulate the barrier height and turn-on voltage of the Schottky junction, resulting in a range of turn-on voltages from 0.1 V to 0.5 V. In some embodiments, the interface dopant layer can be omitted or fully incorporated into the metal silicide. In this regard, Figure 4A is an enlarged cross-sectional view of an exemplary hybrid contact for use in a MOS device according to one or more other preferred embodiments of the present invention. Similar to Figure 3A the hybrid contact 110, the hybrid contact 210 includes a hybrid contact implant 214 placed in the p-type body 220 and a silicide metal 222 adjacent to the hybrid contact implant 214. Notably, as in the device 100 described above, Figure 1A the n-type diffusion in the source region 14 of the LDMOS device 10 inFigure 4A As shown, the hybrid contact implant 214 is aligned with the gate structure 216 before the placement of the gate sidewall spacer structure 215. The n-type diffusion 14 in the source region of the exemplary LDMOS device 10 forms a PN source-body junction. In the hybrid contact 210, the deep n-type diffusion in the source region has been omitted, leaving the silicide metal 222 directly above the p-type body region 220, thereby forming a vertical metal-to-p-type Schottky junction 230 (A-A'), the fixed barrier height of which is effectively determined by the selected metal. The hybrid contact implant 214 also forms an ohmic coupling region 232 (B to B') as shown in Figure 4A When the device is in operation, the vertical rectifying Schottky junction 230 (A-A') ensures minimal electron injection into the body when the source-body junction is forward biased. Laterally, the silicide metal interfaces with the lightly doped n-type semiconductor region to form an ohmic connection 232 (B-B') to the channel, which allows electrons to tunnel between the metal and the semiconductor to achieve high current and low resistance.

[0073] The combination of the Schottky junction and the ohmic connection to the channel in a single contact together form another preferred embodiment of the hybrid contact 210. Figure 4B For Figure 4A is a band diagram of the vertical classical Schottky energy band for the A-A' region of the hybrid contact 210 for Figure 4A and the band diagram of the lateral ohmic contact B-B' region of the hybrid contact for Figure 3D remains generally similar to the band diagram of

[0074] Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A and Figure 7B depict cross-sectional views and circuit diagrams for each of three source contact region scenarios, where the source contact regions 1114, 1214, 1314 of each MOS device are in the off state. More specifically, Figure 5A is a cross-sectional view of the source contact region for Figure 1A and Figure 5B is a circuit diagram of the source contact region 1114 for Figure 5A where the corresponding MOS device is in the off state; Figure 6A is a cross-sectional view of a Schottky-only source contact region using a conventional spacer width, and Figure 6B is a circuit diagram of the source contact region 1214 for Figure 6A where the corresponding MOS device is in the off state; and Figure 7A is for Figure 3Ais a cross-sectional view of a source contact region 1314 of a hybrid contact 110, illustrating a Schottky and PN diodes and a resistor, and Figure 7B is Figure 7A a schematic circuit diagram of a source contact region 1314 of a hybrid contact 110, where the corresponding MOS device is in an off state.

[0075] In Figure 5A 、 Figure 6A and Figure 7A each of Figure 5A and Figure 5B the junctions formed in the respective source contact regions 1114, 1214, 1314 and their relative portions are schematically illustrated. Figure 5A and Figure 5B depict a conventional source contact region 1114 of Figure 1A without a Schottky junction. Figure 6A and Figure 6B illustrate a Schottky-only source contact region 1214 using a conventional spacer width, resulting in little or no connection to the MOS channel 1260. Figure 7A and 7B illustrate Figure 3A an equivalent circuit of a preferred embodiment of Figure 3A where the source contact region 1314 is characterized by a hybrid contact formed of a silicide directly adjacent to a hybrid contact implant and defining first, second, and third electrical junctions, where the first junction (Schottky junction) is formed vertically between the silicide and the substrate, where the second junction is an ohmic junction formed laterally from the silicide to the hybrid contact implant region under the spacer, and where the third junction is a rectifying PN junction between the hybrid contact implant region and the channel region 1360. These three junctions at these defined locations constitute the hybrid contact 110, where the combination of the Schottky and PN diodes and the resistor results in unique behavior. The vertical Schottky junction enables a trade-off between device leakage and BJT suppression. The PN diode from the hybrid contact implant to the channel 1360 provides a normal rectifying connection between the lightly doped region and the channel, and the hybrid contact implant is a lightly doped n-type region in one preferred embodiment. The lateral ohmic connection observed when the device is in the on state provides evidence that the Schottky barrier height has been overcome, enabling high current drive. Comparing Figure 5B 、 Figure 6B and Figure 7B in the equivalent circuits, it can be seen that Figure 7B the hybrid contact source circuit of Figure 5B differs from the conventional source circuit ( Figure 5B )and the Schottky-only source circuit ( Figure 6BBoth. When the MOS device is in the on state, coupling the source contact region 1314 to the lateral region of the hybrid contact below the gate sidewall spacer structure 115 of the channel 1360 enables high current drive, which is not the case for the Schottky source contact region 1214 alone.

[0076] Notably, although Figure 6A and Figure 7A each of the Schottky junctions in contains an interfacial dopant layer that modifies the barrier height, the junction can alternatively be formed by a metal-to-semiconductor junction with a fixed barrier height.

[0077] Historically, implants have been customized by selecting species, dose, and energy to achieve specific connections and electrical effects within semiconductor devices. For MOSFETs, one goal is to form low-resistance contact regions at the source and drain terminals coupled to degenerated or highly doped P-type or n-type implants, which are typically metals or silicides. In one example, for scaled CMOS devices, the well-known lightly doped drain (LDD) extension implant is aligned with the polysilicon gate edge. LDD is often mainly used in low-power CMOS devices to reduce short-channel effects (SCEs) such as punch-through and mitigate the hot carrier injection (HCI) effect on the drain. In another example, by engineering an appropriate spacer width structure, the highly doped deep source / drain regions are placed further away from the channel. Since CMOS devices operate symmetrically, LDD extensions are typically placed on both the source and drain regions to provide electrical connectivity between the deep source / drain regions and the device channel. Its main purpose on the drain side is to cause the SCEs mentioned above when the drain-to-source voltage (VDS) is large. LDD implants are typically performed in combination with deep source / drain implants but usually use separate masks and implant conditions. Notably, the implants in these two regions are customized for specific purposes and implanted separately. Generally, multiple implants of different species can be used for both deep source / drain and LDD implants to finely tune the SCE behavior of the MOSFET. In contrast, in the case of hybrid contacts, a single implant and a single mask are used to achieve two different specific electrical connections in the same device: (1) a tuned Schottky junction between the source or drain contact and the body or well, and (2) an ohmic connection between the source or drain contact and the channel.

[0078] The implanted dopant will have a vertical Gaussian distribution. To form an interfacial dopant layer at the bottom of the silicide that can be used to adjust the junction between the Schottky and PN characteristics, the "shallow" depth of the implant is preferably from zero < the implanted Gaussian peak < the silicide depth, where zero is the original silicon surface and the silicide depth is determined after silicidation annealing. In a preferred embodiment, the silicide depth is about 30 nm.

[0079] In Figure 3A the hybrid contact 110 and Figure 4A in the case of 210, the hybrid contact implant (lightly doped region) is placed on the source side of the LDMOS device 100 before the gate sidewall spacer structure and is not combined with the deep diffusion 14 (source implant) depicted in Figure 1A . The hybrid contact implant is an arsenic implant in at least some embodiments. In Figure 3A embodiments, a single implant and a single mask 170 can be used to form the hybrid contact implant 114. As shown in Figure 3B , the hybrid contact implant region extends from the edge of the photoresist 171 to the left edge of the gate structure 116. The implant energy is low enough to avoid penetrating the polysilicon gate. After forming the gate sidewall spacers, contact silicide is deposited. In a preferred embodiment, a metal is sputtered over the silicon wafer. When annealed, silicide forms in the region where this metal contacts silicon. No silicide forms in the region where the metal lands on the oxide. During silicidation, the silicide grows into the silicon, and the second portion of the hybrid contact implant below the contact silicide is pushed (or snowplowed) ahead of the deep silicide to form an interfacial dopant layer. The first portion of the hybrid contact implant below the spacer has a doping concentration high enough, preferably greater than 1e19 atoms / cm³, to ensure an ohmic junction with the newly grown silicide. A single hybrid contact implant forms both the vertical Schottky barrier junction at the bottom of the silicide and the lateral ohmic connection to the channel below the spacer, as shown in the hybrid contact 110.

[0080] As shown in Figure 4A in the embodiment of the hybrid contact, the source region is lightly doped such that the interfacial dopant layer can have a low enough concentration to produce a hybrid contact 210 that has a minimal or no effect on the electrical behavior of the Schottky junction. In other embodiments of the hybrid contact, multiple masks or a more refined annealing schedule can be used to form the hybrid contact implant to produce regions with lower dopant concentrations or no dopants in regions outside the spacer.

[0081] The formation of hybrid contacts 110, 210 in the LDMOS device 100 affects at least three different characteristics of the device behavior: device leakage, ESD behavior, and DC performance. As Figure 3A and Figure 4A shown, the hybrid contact implants below the spacers form ohmic connections 132, 232 (B-B') to the channel, which achieve high drive current. It is believed that the optimal condition for suppressing the parasitic bipolar junction transistor (BJT) to improve ESD performance is when the Schottky junctions 130, 230 (A-A') are metal-to-semiconductor junctions (fixed barrier height without dopants) as in Figure 4A , and the interfacial dopant layer can be formed by the snowplow effect ( Figure 3A ) to modulate the barrier height of the Schottky junction and reduce the electron injection efficiency. In the case of having an interfacial dopant layer, modifying fabrication process variables such as hybrid contact implant energy and / or dose and silicide annealing conditions enables a trade-off between ESD performance and leakage / drive current.

[0082] Recent work on the formation of vertical Schottky junctions has provided a better understanding of how it is formed, especially in the presence of implanted arsenic. In at least some specific examples, its formation is a function of at least three steps.

[0083] First, a shallow implant is used, the protrusion depth of which is less than the protrusion depth of the silicide depth (about 30 nm in at least some specific examples). Arsenic is an excellent choice for this implant because it is a heavy ion that does not penetrate deeply into silicon and thus has an implant energy that can be easily achieved for a shallow implant. In other specific examples, similar heavy ions can be used and placed slightly deeper or shallower in silicon, allowing a range of Schottky barrier heights and ohmic connections to the channel.

[0084] Second, the arsenic is plowed in front of the growing silicide. The solid solubility of arsenic in cobalt silicide is quite low, less than 10e18 / cubic centimeter. When the silicide is formed, it cannot absorb the implanted arsenic, and thus, this arsenic is pushed in front of the silicide, which is called the "snowplow" effect. This creates a high concentration of arsenic at the silicide-to-silicon interface. The difference in solid solubility between cobalt silicide and silicon dictates this behavior.

[0085] Third, the plowed arsenic diffuses into the silicide. Fick's law dictates that the dopant should diffuse from a high-concentration region to a lower-concentration region. In the case of having a sufficient thermal budget, this is what happens to the high-concentration plowed arsenic described herein. The main thermal budget for this case may be the transformation annealing of the silicide.

[0086] The second and third steps have been observed experimentally using Secondary Ion Mass Spectroscopy (SIMS). In this regard, Figure 8A and Figure 8B are graphs illustrating the migration of arsenic during a preferred manufacturing process in which a metal is placed on silicon and a two-step annealing process is performed. Figure 8A Illustrates arsenic migration during an experimental manufacturing process after silicide formation in which a metal is placed on silicon and a first annealing is performed, where the graph shows the accumulation of arsenic (from plowing) beneath the silicide. Figure 8B Shows arsenic migration after a second annealing at the end of wafer completion. (In this process, the second annealing changes the phase of the silicide to reduce its resistance.) At the end of the experimental manufacturing process, some arsenic has diffused into the silicide, leaving a shallow abrupt junction of activated arsenic at the silicon / silicide interface. The reason for this is the high diffusivity of arsenic in cobalt silicide. The diffusion of arsenic in cobalt silicide can be about sixty times faster than in silicon. Notably, Figure 8A and Figure 8B reflect the experimental results. To some extent, the actual results will depend on other manufacturing process factors, and the curves of these experimental steps can be significantly different from those shown in these figures.

[0087] Using hybrid contacts such as Figure 3A and Figure 4A for the hybrid contacts 110, 210 of the LDMOS device 100 provides various useful electrical characteristics. These include, for example, a significant improvement in Transmission Line Pulsing (TLP) characteristics, especially for very fast pulses (1 ns and 2.5 ns). Also, a "square E-SOA" can be achieved, whereby at higher gate voltages, the trigger voltage does not decrease. This helps to maintain a large ESD design window for the designer.

[0088] Combined with the hybrid contact at the source, combining a highly doped body / well such as is traditionally used to suppress the parasitic BJT forms a non snapback LDMOS device 100. This feature can be exploited by the customer to optimize their ESD clamp design, thereby reducing the chip area. However, if the manufacturing cost is related to the chip area, the hybrid contact can be used instead of the highly doped well to save the cost of additional implants.

[0089] Figure 9 To compare Figure 2 the lateral BJT gain of the hybrid contact 110 on the source of the LDMOS device 100 with that similar to Figure 1AGraph of the lateral BJT gain of a conventional source in an LDMOS device of the device. This gain is obtained from a dedicated test structure with a separate source body. In this structure, the source / body junction is forward biased and all terminal currents are measured. The bipolar gain is defined as the collector current (drain current) divided by the base (body) current. A bipolar gain less than one will significantly reduce the turn-on of the parasitic BJT. As Figure 9 seen, the gain at the Schottky junction 130 of the hybrid contact on the source region of the LDMOS 100 is tens of times lower, indicating that the BJT has been suppressed. In this situation, in the absence of bipolar snapback, the TLP results should be improved.

[0090] Figure 10 For a conventional LDMOS with a PN source ( Figure 1A ), and Figure 2 ), a graph comparison of the 2.5 ns TLP results between the hybrid contact LDMOS (

[0091] In some embodiments, the present invention is not limited to LDMOS devices, but is applicable to various other MOS devices. In this regard, Figure 11A and Figure 11B are cross-sectional views of an n-channel (NMOS) CMOS device 300 and a p-channel (PMOS) CMOS device 500 respectively having hybrid contacts 310, 510 according to another preferred embodiment of the present invention. Notably, although the NMOS device 300 and the PMOS device 500 are defined for a dual-well fabrication process, those of ordinary skill in the art should understand that various embodiments can be implemented in a single-well fabrication process.

[0092] Figure 11AThe NMOS device 300 has a p-type substrate 321, a p-type well 331, a gate structure 316, a gate sidewall spacer structure 315, unspecified source and drain regions, and an ohmic contact 323 formed by silicide placement at the gate. In this device 300, in both the source and drain regions, a hybrid contact 310 replaces the ohmic contact that would conventionally be utilized. In the hybrid contact 310, the n-type diffusion in the source and drain regions has been omitted, leaving a silicide metal 322 on the p-type well 331, including an interfacial dopant layer 317, thereby forming a vertical metal-to-p-type Schottky junction 330 (A-A') region, the barrier height of which has been modified by a hybrid contact implant 314. The interfacial dopant layer 317 is created by the displacement of the hybrid contact implant 314 during silicide growth. In at least some preferred embodiments, the hybrid contact implant 314 is a shallow arsenic implant. The hybrid contact implant 314 also forms an ohmic coupling 332 (B-B') region. When the device is in operation, the vertical rectifying Schottky junction 330 (A-A') ensures minimal electron injection when the source / drain to p-type well junction is forward biased. Laterally, the silicide metal interfaces with a shallowly doped n-type semiconducting region to form an ohmic connection 332 (B-B') to the channel, which enables electrons to tunnel between the metal and the semiconductor to achieve high current and low resistance.

[0093] Figure 11B The PMOS device 500 has a p-type substrate 321, an n-type well 551, a gate structure 516, a gate sidewall spacer structure 515, unspecified source and drain regions, and an ohmic contact 523 formed by silicide placement at the gate. In this device 500, in both the source and drain regions, a hybrid contact 510 replaces the ohmic contact that would conventionally be utilized. In the hybrid contact 510, the p-type diffusion in the source region has been omitted, leaving a silicide metal 522 on the n-type well 551, including an interfacial dopant layer 517, thereby forming a vertical metal-to-n-type Schottky junction 530 (A-A') region, the barrier height of which has been modified by a hybrid contact implant 514. The interfacial dopant layer 517 is created by the displacement of the hybrid contact implant 514 during silicide growth. In one preferred embodiment, the hybrid contact implant 514 is a shallow boron implant. The hybrid contact implant 514 also forms an ohmic coupling 532 (B-B') region. When the device is in operation, the vertical rectifying Schottky junction 530 (A-A') ensures minimal hole injection when the source / drain to n-type well junction is forward biased. Laterally, the silicide metal interfaces with a shallowly doped p-type semiconducting region to form an ohmic connection 532 (B-B') to the channel, which enables electrons to tunnel between the metal and the semiconductor to achieve high current and low resistance.

[0094] Those of ordinary skill in the art will understand that the various specific examples can be implemented in substrate wafer materials commonly used in the semiconductor industry, including bulk silicon (n-type and p-type), partially depleted (PD) SOI, epitaxial silicon, and the like. The goal is to be able to construct a vertical Schottky junction between the silicide of the hybrid contact and the body / well region and a lateral ohmic connection between the silicide of the hybrid contact at the source and / or drain regions and the MOS channel formed by the gate. In some preferred specific examples, arsenic and boron are used, but other n-type and p-type implants with similar weights and diffusivities relative to the selected silicide can also be used. Ultimately, it should be understood that although cobalt silicide is used, other silicides can also be used.

[0095] Throughout the discussion herein, examples of reference rectifying Schottky barrier junctions are provided. The present invention does not recognize any limitations on what types of Schottky interfaces can be used, and more specifically, it is expected that such types of junctions can be formed by any form of conductive material. Additionally, while traditional Schottky junctions are abrupt, specifically, the present invention anticipates that in some cases, an interfacial layer can be utilized between the silicon substrate and the actual conductive material. Furthermore, the interfacial layer can include materials having conductive, semi-conductive, and / or insulator-like properties. Preferred specific examples use dopant segregation techniques to form an interfacial dopant layer between the silicon substrate and the silicide.

[0096] Figures 12A to 12E Cross-sectional views for illustrating the various steps in a method of manufacturing a hybrid contact LDMOS device in one or more preferred specific examples of the present invention, and Figure 13 For illustration Figures 12A to 12E of the steps of the hybrid contact LDMOS device manufacturing process 3000. More specifically, Figure 12A is a cross-sectional view for illustrating the polysilicon deposition and polysilicon etching for manufacturing a gate structure (shown at step or fabrication process 3100 in Figure 13 ). Figure 12B is a cross-sectional view for illustrating a shallow arsenic implant (shown at step or fabrication process 3200 in Figure 13 ). The mask for the shallow arsenic implant is described above with respect to Figure 3B . Figure 12C is a cross-sectional view for illustrating the steps or fabrication process 3300 for forming a gate sidewall spacer structure (shown at step or fabrication process 3300 in Figure 13 ), where this structure covers a first portion of the implant but exposes a second portion. Referring to Figure 12D , this is then followed by a p-type diffusion into the body region to form a body tap (at Figure 13The steps or fabrication processes (shown at 3400) and applying a photoresist coating (mask) to the body region / tap (at Figure 13 the steps or fabrication processes shown at 3500) to prepare for n-type diffusion into the gate structure to improve conductivity and n-type diffusion into the drift region to form the drain region (at Figure 13 the steps or fabrication processes shown at 3600). Finally, Figure 12E is a cross-sectional view illustrating the formation of a hybrid contact at the source and ohmic contacts at the body tap, gate structure, and drain region during the fabrication of a hybrid contact LDMOS. As explained in detail above, the silicidation fabrication process preferably involves laying down a blanket layer of metal (at Figure 13 the steps or fabrication processes shown at 3700), which can be followed by sputtering and silicidation (shown at fabrication process step 3800). In at least some embodiments, this can involve: a first anneal to form a silicide on the regions where the metal contacts silicon; removing the unreacted metal; and a second anneal to transform the silicide to a low-ohmic phase. For example, these fabrication process steps can be used to fabricate Figure 2 the hybrid contact LDMOS device 100.

[0097] Variations of the fabrication processes described with respect to Figures 12A to 12E can also be utilized without departing from the scope of the present invention. For example, for the specific example of the hybrid contact shown in Figure 4A , the fabrication process mask for the arsenic implant only extends under the gate sidewall spacer structure, and little or no shallow arsenic is placed outside the spacer structure. In this specific example, a pure metal Schottky junction with a fixed barrier height is formed, the height of which is determined by the selected metal.

[0098] Figure 13The flowchart in illustrates the steps of the hybrid contact LDMOS device manufacturing process 3000 in more detail. First, at step 3100, polysilicon is deposited on the gate oxide and the polysilicon is etched to form a gate structure. Next, at step 3200, a shallow p-type dopant is implanted into the body region, which is aligned with the gate structure. Then, at step 3300, a gate sidewall spacer structure is formed, and at step 3400, the p-type dopant is diffused into the body region to form a body tap. At step 3500, a photoresist coating is then applied to the body region including the body tap, but the gate structure and the drift region are exposed, and at step 3600, an n-type dopant is diffused into both the gate structure and the drift region. The photoresist coating in step 3500 preferably covers all of the body region / tap near the gate structure and extends at least to a point or line consistent with the edge of the gate structure, and may extend slightly beyond the edge of the gate structure to ensure coverage of the body region / tap such that the gate structure and the drift region are completely or almost completely exposed. At step 3700, a blanket layer of metal is deposited on the surface of the wafer. This can be done without any pre-patterning. Finally, at step 3800, silicidation of the metal is performed to form ohmic contacts to the body tap, the gate structure, and the drain region along with a hybrid contact as the source region to the channel.

[0099] In some specific examples, the corresponding manufacturing process is applicable to various other MOS devices, including those in which the dopant in step 3400 is an n-type dopant.

[0100] It should be noted that the description and the drawings only illustrate the basic principles of the proposed method and system. Therefore, it should be understood that those of ordinary skill in the art will be able to design various configurations that, although not explicitly described or shown herein, embody the principles of the present invention and are included within its spirit and scope. In addition, all the examples described herein are mainly explicitly intended for educational purposes only to assist the reader in understanding the principles of the proposed method and system and the concepts contributed by the inventors to the art, and all the examples should be considered as not limited to these specifically described examples and conditions. Furthermore, all statements of the principles, aspects, and specific examples of the present invention described herein, as well as the specific examples thereof, are intended to cover their equivalents.

[0101] Based on the foregoing information, it is readily understood by those of ordinary skill in the art that the present invention is susceptible to a wide range of utilities and applications. In addition to those specifically described herein, many specific examples and adaptations of the present invention, as well as many variations, modifications, and equivalent configurations, will be apparent from or reasonably suggested by the present invention and its foregoing description without departing from the essence or scope of the present invention.

[0102] Accordingly, while the present invention has been described in detail herein with reference to its preferred specific examples, it is to be understood that the disclosure is only illustrative and exemplary of the invention and is made for the purpose of providing a complete and enabling disclosure thereof. The foregoing disclosure is not intended to be construed as limiting the invention or otherwise excluding any such other specific examples, adaptations, variations, modifications or equivalent configurations; the invention is limited only by the appended claims and their equivalents. Although specific terms are used herein, they are used in a general and descriptive sense only and not for purposes of limitation.

Claims

1. A MOSFET transistor structure, comprising: (a) A well region having a first dopant polarity; (b) A source region on or within the well region; (c) A drain region on or within the well region; (d) A channel region between the source region and the drain region; (e) A gate structure above the channel region; (f) A hybrid contact implant having a second dopant polarity in the source region or the drain region; and (g) Individual metal contacts on or within each of the source region, the gate structure, and the drain region; (h) Wherein the hybrid contact implant and the metal contact on or within the source region or the drain region are respectively combined to form a hybrid contact defining first, second, and third electrical interfaces, wherein the first electrical interface is a Schottky interface respectively formed vertically between the source metal contact or the drain metal contact and the well region, wherein the second electrical interface is an ohmic interface respectively formed laterally between the source metal contact or the drain metal contact and the hybrid contact implant, and wherein the third electrical interface is a rectifying PN interface between the hybrid contact implant and the channel region.

2. The transistor structure of claim 1, further comprising a substrate below the well region.

3. The transistor structure of claim 1, wherein the hybrid contact implant is aligned with the gate structure.

4. The transistor structure of claim 1, wherein the hybrid contact implant has an implanted depth defining a first depth, wherein the metal contact of the hybrid contact has a second depth, and wherein the first depth is less than the second depth.

5. The transistor structure of claim 1, wherein the hybrid contact implant has a doping concentration greater than 1e19 atoms / cm³.

6. The transistor structure of claim 1, wherein an interfacial dopant layer is disposed between the metal contact and the well region, thereby modulating the barrier height and turn-on voltage of the first electrical interface.

7. The transistor structure of claim 1, wherein the first electrical interface has a turn-on voltage in the range of 0.1 V to 0.5 V.

8. The transistor structure of claim 1, wherein a parasitic bipolar junction transistor is formed by the drain-well-source region, and wherein the parasitic bipolar junction transistor formed by the drain-well-source region has a bipolar gain less than 1.

9. The transistor structure of claim 1, wherein the gate structure has a source region side and a drain region side, wherein the gate sidewall spacer structure is disposed along the gate structure on its source region side and its drain region side, and wherein the hybrid contact implant is disposed directly below the gate sidewall spacer structure on the source region side or the drain region side of the gate structure, respectively.

10. The transistor structure of claim 9, wherein the metal contact on or in the source region and the drain region is aligned with the gate sidewall spacer structure.

11. The transistor structure of claim 9, wherein a first portion of the hybrid contact implant is disposed below the gate sidewall spacer structure and a second portion of the hybrid contact implant is exposed adjacent to the gate sidewall spacer structure, wherein the second electrical contact is formed laterally between the source metal contact or the drain metal contact and the first portion of the hybrid contact implant, respectively, and wherein the third electrical contact is a rectifying PN junction between the first portion of the hybrid contact implant and the channel region.

12. The transistor structure of claim 11, wherein: (j)The hybrid contact implant is a first hybrid contact implant and is in the source region; (k)The transistor structure further includes a second hybrid contact implant having a second dopant polarity in the drain region; (l)The second hybrid contact implant and the metal contact on or in the drain region are combined to form a second hybrid contact defining fourth, fifth, and sixth electrical interfaces, wherein the fourth electrical interface is a Schottky interface vertically formed between the drain metal contact and the well region, wherein the fifth electrical interface is an ohmic interface laterally formed between the drain metal contact and the second hybrid contact implant, and wherein the sixth electrical interface is a rectifying PN interface between the second hybrid contact implant and the channel region; and (m)The second hybrid contact implant has an implanted depth defining a third depth, wherein the metal contact of the second hybrid contact has a fourth depth, and wherein the third depth is less than the depth of the fourth depth.

13. The transistor structure of claim 1, wherein each of the respective metal contacts on or in each of the source region, the gate structure, and the drain region is a silicide.

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