Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the following steps: providing a substrate; the base comprises a substrate and a shallow trench isolation structure; wherein the substrate comprises a first region defined by the shallow trench isolation structure; etching the substrate to form a groove located in the first region; wherein the plane where the bottom of the groove is located and the side walls, facing each other, of the adjacent shallow trench isolation structures form a target area; a substrate etching residual part formed in the substrate etching process is arranged in the target region; and converting the material of the etching residual part of the substrate so as to manufacture and obtain a first gate oxide layer in the target area. By converting the material of the etching residual part of the substrate, the substrate material residue of the target area after the first gate oxide layer is manufactured and formed can be reduced, and the reliability of the first gate oxide layer is improved.

Description

Technical Field

[0001] The embodiments in the present application relate to the technical field of semiconductor manufacturing processes, and particularly to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] With the continuous development of integrated circuits, in order to improve the performance of chips such as switching characteristics and power consumption, it is usually necessary to integrate power devices with different operating voltages and logic control circuits on a single chip. For MOS devices with a relatively high operating voltage, their gate oxide layers need to have a certain thickness to meet the requirements of high breakdown voltage.

[0003] In related technologies, when preparing a relatively thick gate oxide layer, a dry etching process is usually adopted to etch a groove with a certain depth on the substrate surface between adjacent shallow trench isolation (STI) structures, and then a gate oxide layer is formed in the groove. In this way, a relatively thick gate oxide layer can be prepared, and its surface height can be basically kept consistent with that of a relatively thin gate oxide layer.

[0004] However, due to the inherent upper-wide and lower-narrow structural characteristics of STI and the anisotropic characteristics of dry etching, there are residues of substrate materials on the sidewalls of the STI on both sides of the groove etched on the substrate surface, which easily leads to current tunneling, thereby reducing the reliability of the gate oxide layer formed in the groove. Summary of the Invention

[0005] In view of this, multiple embodiments of the present application are dedicated to providing a semiconductor structure and a method for manufacturing the same, which can reduce the residue of substrate materials and improve the reliability of the gate oxide layer.

[0006] An embodiment of the present application provides a method for manufacturing a semiconductor structure, including: providing a substrate; the substrate includes a substrate and shallow trench isolation structures; wherein, the substrate includes a first region defined by the shallow trench isolation structures; etching the substrate to form a groove in the first region; wherein, the plane where the bottom of the groove is located and the sidewalls facing each other of adjacent shallow trench isolation structures form a target region; the target region has a substrate etching residue formed during the process of etching the substrate; converting the material of the substrate etching residue to fabricate a first gate oxide layer in the target region.

[0007] Optionally, a patterned mask layer defining the first region is further formed on the substrate; the step of converting the material of the etched residue of the substrate to fabricate a first gate oxide layer in the target region includes: converting the material of the etched residue of the substrate to the same material as the patterned mask layer; removing the patterned mask layer; wherein, the etched residue of the substrate in the target region is removed together; forming a first gate oxide layer in the target region.

[0008] Optionally, the material of the substrate is silicon; the material of the patterned mask layer is silicon nitride; the step of converting the material of the etched residue of the substrate to the same material as the patterned mask layer includes: performing a decoupled plasma nitridation deposition process on the etched residue of the silicon substrate to form an etched residue of the substrate made of silicon nitride.

[0009] Optionally, during the decoupled plasma nitridation deposition process, N2 is used as the ion source, and the deposition rate of silicon nitride falls within the range of 5 um / cm2 to 20 um / cm2.

[0010] Optionally, the step of converting the material of the etched residue of the substrate to fabricate a first gate oxide layer in the target region includes: converting the material of the etched residue of the substrate to the same material as the first gate oxide layer.

[0011] Optionally, the material of the substrate is silicon; the material of the first gate oxide layer is silicon dioxide; the step of converting the material of the etched residue of the substrate to the same material as the first gate oxide layer includes: oxidizing the etched residue of the silicon substrate with oxygen under low temperature and high pressure conditions to form an etched residue of the substrate made of silicon dioxide.

[0012] Optionally, during the process of oxidizing the etched residue of the silicon substrate with oxygen under low temperature and high pressure conditions, both the etched residue of the substrate and the bottom of the groove are subjected to the oxygen pressure; wherein, the oxygen pressure acting on the etched residue of the substrate is greater than the oxygen pressure acting on the bottom of the groove.

[0013] Optionally, a transition gate oxide part made of silicon dioxide is formed at the bottom of the groove; after converting the material of the etched residue of the substrate to the same material as the first gate oxide layer, the step of converting the material of the etched residue of the substrate to fabricate a first gate oxide layer in the target region further includes: performing an ion implantation process on the substrate with the transition gate oxide part and the etched residue of the substrate made of silicon dioxide as the mask layer; removing at least part of the mask layer consumed in the ion implantation process; the remaining mask layer serves as part of the first gate oxide layer.

[0014] Optionally, the substrate further includes a second region defined by the shallow trench isolation structure; the substrate further includes an oxide layer on the surface of the substrate; correspondingly, in the step of etching the substrate to form a groove in the first region, the oxide layer in the first region is removed; the remaining oxide layer in the second region serves as a second gate oxide layer; wherein, the thickness of the second gate oxide layer is less than the thickness of the first gate oxide layer.

[0015] An embodiment of the present application provides a semiconductor structure, which is prepared by using the preparation method of the semiconductor structure described in the foregoing embodiment.

[0016] For multiple embodiments provided by the present application, the unexpected effect is that in the process of preparing a thick gate oxide layer, for the substrate etching residue in the target region formed during the etching of the substrate in the first region, after converting the material of the substrate etching residue, and then fabricating the first gate oxide layer, it is possible to reduce the substrate material residue in the target region after forming the first gate oxide layer and improve the reliability of the first gate oxide layer. Description of the Drawings

[0017] Figure 1 It is a schematic diagram of substrate material residue during the preparation of a relatively thick gate oxide layer in the related art.

[0018] Figure 2 It is a schematic diagram of the preparation method of the semiconductor structure provided by an embodiment of the present application.

[0019] Figure 3 It is a schematic diagram of providing a substrate in the preparation method of the semiconductor structure provided by an embodiment of the present application.

[0020] Figure 4 and Figure 5 It is a schematic diagram of etching to form a groove in the preparation method of the semiconductor structure provided by an embodiment of the present application.

[0021] Figure 6 It is a schematic diagram of converting the material of the substrate etching residue in the preparation method of the semiconductor structure provided by an embodiment of the present application.

[0022] Figure 7 It is a schematic diagram of removing the patterned mask layer in the preparation method of the semiconductor structure provided by an embodiment of the present application.

[0023] Figure 8 It is a schematic diagram of converting the material of the substrate etching residue in the preparation method of the semiconductor structure provided by another embodiment of the present application.

[0024] Figure 9Schematic diagram of forming a first gate oxide layer in the method for preparing a semiconductor structure provided by another embodiment of the present application.

[0025] Description of reference numerals: 101, thick gate oxide region; 102, shallow trench isolation; 103, thin gate oxide layer; 104, patterned mask layer; 105, etched groove; 106, residual substrate material; 10, substrate; 11, substrate; 111, first region; 112, second region; 12, shallow trench isolation structure; 13, oxide layer; 14, mask layer; 15, groove; 16, target region; 17, substrate etching residue; 171, sacrificial residue; 172, oxidation residue; 141, patterned mask layer; 18, transition gate oxide part; 19, masking layer; 131, second gate oxide layer. Detailed implementation manners

[0026] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments.

[0027] In the present application, the accompanying drawings are not necessarily drawn to scale, and local features can be enlarged or reduced to more clearly show the details of the local features.

[0028] Unless otherwise specified, all the technical and scientific terms used in the present application have the same meanings as those commonly understood by those skilled in the technical field of the present application. The terms used in the present application are only for the purpose of describing specific embodiments, and are not intended to limit the scope of the present application. The term "and / or" used in the embodiments of the present application and the appended claims includes any and all combinations of one or more of the related listed items. The singular forms "a", "above-mentioned", and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0029] In the description of the present application, it should be understood that the terms "first" and "second" are only used for descriptive purposes, and cannot be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of the described features. In the description of the embodiments of the present application, "a plurality of" means two or more, unless otherwise specifically defined.

[0030] In the description of the present application, the orientation or positional relationship indicated by terms such as "center", "longitudinal", "transverse", "length", "width", "thickness", "height", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of the simplified description of the present application, rather than indicating that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, that is, it cannot be understood as a limitation to the present application.

[0031] In the description of the present application, unless otherwise clearly defined, terms such as "installation", "connection", "connection", "fixation", "setting", etc. should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can also be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0032] Please refer to Figure 1 . In the related art, preparing a relatively thick gate oxide layer usually may include the following steps: S1: Provide a substrate; the substrate includes a substrate and shallow trench isolation; wherein, the substrate includes a thick gate oxide region defined by the shallow trench isolation; an oxide layer is formed on the surface of the substrate; a mask layer is provided on the surfaces of the oxide layer and the shallow trench isolation.

[0033] S2: Use a dry etching process to etch the mask layer, the oxide layer, and the substrate in sequence to form an etching groove located in the thick gate oxide region.

[0034] S3: Form a thick gate oxide layer in the groove.

[0035] Among them, the etching groove formed by the dry etching process in step S2 can be as Figure 1 shown. Figure 1 In, 101 is the thick gate oxide region, 102 is the shallow trench isolation, 103 and 104 are respectively the thin gate oxide layer and the patterned mask layer formed by the remaining oxide layer and the mask layer after etching, and 105 is the etching groove formed by step S2.

[0036] However, since the width of the shallow trench isolation 102 gradually decreases from its surface to the bottom, that is, it has a structure with a wider top and a narrower bottom, and dry etching has anisotropic characteristics, there is residual substrate material 106 on the sidewalls of the shallow trench isolation 102 that has not been etched away. At this time, if a thick gate oxide layer is directly formed in the etching groove 105, this part of the residual substrate material 106 can easily cause current tunneling, reducing the reliability of the thick gate oxide layer and even possibly causing the subsequent fabricated semiconductor device to fail directly. If the isotropic etching method is used to etch or remove this part of the residual substrate material 106, it will aggravate the damage to the shallow trench isolation 102, and the surface of the thick gate oxide region 101 will have a large arc, still affecting the reliability of the fabricated thick gate oxide layer.

[0037] Therefore, it is necessary to provide a method for fabricating a semiconductor structure, which can reduce the residual substrate material during the process of fabricating a relatively thick gate oxide layer and improve the reliability.

[0038] Please refer to Figures 2 - 9 This application provides a method for fabricating a semiconductor structure in one embodiment. The method for fabricating the semiconductor structure may include the following steps.

[0039] S110: Provide a substrate.

[0040] In this embodiment, as shown in Figure 3 the substrate 10 may include a substrate 11, a shallow trench isolation structure 12, an oxide layer 13 on the surface of the substrate 11, and a mask layer 14 covering the surfaces of the shallow trench isolation structure 12 and the oxide layer 13.

[0041] In this embodiment, the substrate 11 can be used as the basic structure of the semiconductor structure, which not only provides mechanical support, but also can affect the electrical properties of the semiconductor structure, such as the working voltage and carrier mobility, by doping ions. Specifically, the substrate 11 can be made of silicon (Si), or can be made of other semiconductor materials according to requirements, such as silicon carbide (SiC) or gallium nitride (GaN), etc.

[0042] In this embodiment, the shallow trench isolation structure 12 (Shallow Trench Isolation, STI) is used to form effective electrical isolation between different device regions by etching shallow trenches in the substrate 11 and filling them with insulating materials, such as silicon dioxide, thereby reducing parasitic capacitance and leakage current and improving the performance and reliability of the semiconductor structure. For example, the shallow trench isolation structure 12 can form isolation between devices with different working voltages, such as power devices and logic devices.

[0043] In this embodiment, the oxide layer 13 can be used to form a thinner gate oxide layer on the low-voltage device region during subsequent processes. Specifically, in the etching process, a part of the oxide layer 13 on other regions can be removed, and the remaining oxide layer 13 serves as the thinner gate oxide layer. Specifically, the material of the oxide layer 13 can be silicon dioxide.

[0044] It should be noted that, in some embodiments, the substrate 10 may also only include the substrate 11 and the shallow trench isolation structure 12. The mask layer 14 can be set during the etching process, and the oxide layer 13 can also be fabricated separately later.

[0045] In this embodiment, the substrate 11 includes a first region 111 and a second region 112 defined by the shallow trench isolation structure 12. Among them, the first region 111 is the position region between adjacent shallow trench isolation structures 12. In this embodiment, the working voltage requirements of the first region 111 and the second region 112 are different. Specifically, the first region 111 can be a high-voltage device region with higher working voltage requirements, such as a power device, and a relatively thick gate oxide layer needs to be fabricated in this region. The second region 112 can be a low-voltage device region with lower working voltage requirements, and a relatively thin gate oxide layer needs to be fabricated in this region. It should be noted that the so-called high and low voltage requirements in this application are relative, that is, the first region 111 is higher than the second region 112, and it does not necessarily correspond to the voltage values of high voltage and low voltage in actual applications such as circuit design.

[0046] S120: Etch the substrate to form a groove in the first region.

[0047] In this embodiment, as Figure 4 and Figure 5 shown, the photolithography and etching processes can be used to perform etching with the narrowest spacing between adjacent shallow trench isolation structures 12 as the position reference. After removing a part of the mask layer, oxide layer, and substrate in the first region 111, a patterned mask layer 141, a second gate oxide layer 131, and a groove 15 are formed. The patterned mask layer 141 is located on the substrate 11 and defines the first region 111, which can be removed in subsequent steps. It can be understood that the groove 15 is located in the first region 111.

[0048] In this embodiment, referring to Figure 5 , the plane where the bottom of the groove 15 is located (as Figure 5 shown by the dotted line) and the mutually facing sidewalls of the adjacent shallow trench isolation structures 12 can form a target region 16. The target region 16 can be used as the position region where the subsequently fabricated first gate oxide layer is located. Since in Figure 5In this case, there are a mask layer, an oxide layer, and substrate material remaining on the sidewalls of the shallow trench isolation structure 12 facing the groove 15 in the target region. Therefore, to clearly illustrate the position of the target region 16, please also refer to Figure 7 . Specifically, the target region 16 has a boundary formed by the plane where the bottom of the groove 15 is located and the sidewalls of adjacent shallow trench isolation structures 12 facing each other. Among them, the part of the plane where the bottom of the groove 15 is located defined by the adjacent shallow trench isolation structures 12 can be used as the bottom boundary of the target region 16, and the part of the sidewalls of the adjacent shallow trench isolation structures 12 above the bottom boundary can be used as the two side boundaries of the target region 16.

[0049] In this embodiment, there is a substrate etching residue portion 17 formed during the etching of the substrate 11 in the target region 16. The substrate etching residue portion 17 is located on the sidewall of the shallow trench isolation structure 12 facing the groove 15. Among them, the substrate etching residue portion 17 has a side surface in contact with the shallow trench isolation structure 12, and the other side surface can be used as the sidewall of the groove 15. The bottom surface of the substrate etching residue portion 17 is located on the plane where the bottom of the groove 15 is located, and the bottom surface of the substrate etching residue portion 17 and the bottom surface of the groove 15 can jointly form the bottom boundary of the target region 16.

[0050] It should be noted that in the related art, due to the presence of the substrate etching residue portion 17 in the target region 16, there will be substrate material residue between the subsequently formed first gate oxide layer and the shallow trench isolation structure 12, thereby affecting the reliability of the first gate oxide layer.

[0051] In this embodiment, there are also partial oxide residues and partial mask layer residues formed during the etching of the substrate 11 in the target region 16. Among them, the partial mask layer residues can be removed together when the mask is removed subsequently.

[0052] In this embodiment, since the oxide layer in the first region 111 is removed, the remaining oxide layer in the second region 112 can be used as the second gate oxide layer 131, that is, as the thinner gate oxide layer in the low-voltage device region.

[0053] S130: Convert the material of the substrate etching residue portion to form a first gate oxide layer in the target region.

[0054] In this embodiment, the material properties of the substrate etching residue 17 can be changed or new compounds can be formed through specific processes such as plasma bombardment and wet chemical treatment to achieve the conversion of the material of the substrate etching residue 17. Specifically, the material of the substrate etching residue 17 can be converted into a non-conductive material to avoid current tunneling in the subsequently fabricated first gate oxide layer, which affects reliability. In some embodiments, the material of the substrate etching residue 17 can also be converted into a material that is easy to remove, and it can be removed separately before fabricating the first gate oxide layer, and then the first gate oxide layer is formed in the target region 16, which can also solve the problem of substrate material residue in the target region 16.

[0055] In some embodiments, the step of converting the material of the substrate etching residue to fabricate the first gate oxide layer in the target region may include: converting the material of the substrate etching residue into the same material as the patterned mask layer; removing the patterned mask layer; wherein, the substrate etching residue in the target region is removed together; and fabricating the first gate oxide layer in the target region.

[0056] Specifically, as Figure 6 shown, since the patterned mask layer 141 formed during the etching process needs to be removed after the groove 15 is formed, converting the material of the substrate etching residue 17 into the same material as the patterned mask layer 141 can remove the substrate etching residue 17 together in the step of removing the patterned mask layer 141, without an additional cleaning step, which not only simplifies the process steps, but also reduces the damage to the surfaces of the shallow trench isolation structure 12 and the substrate 11 based on the high selectivity of the material of the patterned mask layer 141 relative to the materials of the shallow trench isolation structure 12 and the substrate 11 when removing the substrate etching residue 17.

[0057] In some embodiments, the material of the substrate can be silicon; the material of the patterned mask layer can be silicon nitride; the step of converting the material of the substrate etching residue into the same material as the patterned mask layer may include: performing a decoupled plasma nitridation (DPN) deposition process on the silicon-based substrate etching residue to form a silicon nitride-based substrate etching residue. Specifically, referring to Figure 6 , during the process of performing the decoupled plasma nitridation process on the substrate etching residue 17, N2 can be used as the ion source. Among them, the deposition rate of silicon nitride on the substrate etching residue 17 falls within the range of 5 um / cm 2 ~20um / cm 2 . When the material of the substrate etching residue 17 is completely converted into silicon nitride, the plasma bombardment is stopped to form a sacrificial residue 171 made of silicon nitride.

[0058] Of course, as Figure 6 shown, during the decoupled plasma nitridation process, a certain thickness of silicon nitride will also be formed at the bottom of the groove 15, and it can also be removed when the patterned mask layer 141 is removed.

[0059] In some embodiments, when the material of the first gate oxide layer to be prepared is different from that of the second gate oxide layer 131, it is also necessary to remove some of the oxide layer residues in the target region 16, so as to form a structure as Figure 7 shown. Of course, when the material of the first gate oxide layer to be prepared is the same as that of the second gate oxide layer 131, such as both being made of silicon dioxide, it is not necessary to remove some of the oxide layer residues in the target region 16, and it can be directly used as part of the second gate oxide layer for subsequent fabrication.

[0060] It can be understood that at this time, the target region 16 is completely opened, and then the first gate oxide layer can be fabricated in the target region 16. Among them, the height of the surface of the first gate oxide layer can be flush with the surface of the second gate oxide layer 131, or can be higher than the surface of the second gate oxide layer 131.

[0061] In some embodiments, the step of converting the material of the substrate etching residue to fabricate the first gate oxide layer in the target region may include: converting the material of the substrate etching residue to the same material as the first gate oxide layer.

[0062] In some embodiments, the material of the substrate etching residue 17 can be directly converted to the same material as the first gate oxide layer. When fabricating the first gate oxide layer subsequently, the substrate etching residue 17 after the material conversion can be directly used as part of the first gate oxide layer, which can also reduce the residue of the substrate material.

[0063] In some embodiments, the material of the substrate can be silicon; the material of the first gate oxide layer can be silicon dioxide; the step of converting the material of the substrate etching residue to the same material as the first gate oxide layer includes: oxidizing the silicon-based substrate etching residue under low temperature and high pressure conditions using oxygen to form a silicon dioxide-based substrate etching residue.

[0064] In some embodiments, please refer to Figure 5 and Figure 8 together. Under low temperature and high pressure conditions, the silicon-based substrate etching residue 17 can be rapidly oxidized by passing oxygen to convert it into a silicon dioxide-based material to form an oxidized residue 172. Similarly, some silicon dioxide will also grow at the bottom of the groove 15 to form a transition gate oxide portion 18. As Figure 8 shown, Figure 8The part of silicon dioxide between the two dashed lines is the transition gate oxide part 18, and the parts of silicon dioxide on both sides are the oxidation residue parts 172.

[0065] In some embodiments, under low-temperature and high-pressure conditions, during the process of etching the substrate etching residue part 17 made of silicon with oxygen, both the substrate etching residue part 17 and the bottom of the groove 15 are affected by the oxygen pressure; among them, the oxygen pressure acting on the substrate etching residue part 17 is greater than the oxygen pressure acting on the bottom of the groove 15. In this way, the silicon oxidation rate of the substrate etching residue part 17 can be accelerated, and the consumption of the silicon material at the bottom of the groove 15 is less. After the substrate etching residue part 17 on the sidewall of the shallow trench isolation structure 12 is completely oxidized, the oxidized silicon material at the bottom of the groove 15 is less, thereby reducing the thickness of the transition gate oxide part 18 and facilitating subsequent processing.

[0066] In some embodiments, after converting the material of the substrate etching residue part into the same material as the first gate oxide layer, the step of converting the material of the substrate etching residue part to form the first gate oxide layer in the target area may further include: using the transition gate oxide part and the substrate etching residue part as a masking layer to perform an ion implantation process on the substrate; removing at least part of the masking layer consumed in the ion implantation process; and using the remaining masking layer as part of the first gate oxide layer.

[0067] In some embodiments, as Figure 9 shown, the patterned mask layer 141 can be removed first, and then ion implantation is performed on the substrate 11 to form a well region. When performing ion implantation, the converted oxidation residue part 172 and the transition gate oxide part 18 can just be used as the masking layer 19 for ion implantation. After the ion implantation is completed, at least part of the masking layer 19 consumed in the ion implantation process can be removed. The remaining masking layer 19 is already in the target area 16, that is, it can be used as part of the first gate oxide layer. Then, the remaining first gate oxide layer is formed in the target area 16 to complete the fabrication of the first gate oxide layer. In this way, without adding additional process steps, on the basis of the existing process steps, the residue of the substrate material in the target area 16 can be reduced, the uniformity and reliability of the first gate oxide layer in the subsequent target area 16 can be improved, and without additional cleaning steps, the damage to the shallow trench isolation structure 12 and the substrate 11 can also be effectively reduced.

[0068] It should be noted that during the ion implantation process, a relatively thin masking layer is usually required. Therefore, when oxidizing the substrate etching residue part 17, the transition gate oxide part 18 formed by controlling the oxygen pressure is also relatively thin, which is just suitable for the required thickness of the masking layer, and there is no need to separately set the masking layer additionally, realizing process simplification.

[0069] In some embodiments, the thickness of the transitional gate oxide portion 18 does not exceed 100 Å.

[0070] In some embodiments, in the step of oxidizing the substrate etching residue portion made of silicon with oxygen to form a substrate etching residue portion made of silicon dioxide, the ratio of the oxygen pressure acting on the substrate etching residue portion to the oxygen pressure acting on the bottom of the groove may fall within the range of 2 to 10. In this way, the thickness of the formed transitional gate oxide portion 18 is more matched with the thickness requirement of the ion implantation masking layer.

[0071] In this embodiment, the first gate oxide layer formed in the first region 111 and the second gate oxide layer 131 on the second region 112 may jointly form a double gate oxide layer, wherein the thickness of the second gate oxide layer 131 is less than the thickness of the first gate oxide layer.

[0072] In this embodiment, the unexpected effect is that in the process of preparing the thick gate oxide layer, for the substrate etching residue portion 17 located in the target region 16 formed during the etching process of the substrate in the first region 111, after converting the material of the substrate etching residue portion 17 and then fabricating the first gate oxide layer, the residual substrate material in the target region 16 after forming the first gate oxide layer can be reduced, and the reliability of the first gate oxide layer can be improved.

[0073] An embodiment of the present application provides a semiconductor structure, and the semiconductor structure is prepared by using the preparation method of the semiconductor structure described in any of the foregoing embodiments.

[0074] It can be understood that the specific examples herein are only for helping those skilled in the art better understand the embodiments of the present application, rather than limiting the scope of the present invention.

[0075] It can be understood that in various embodiments of the present application, the magnitudes of the serial numbers of the various processes do not mean the sequence of execution, and the execution sequence of each process should be determined according to its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0076] It can be understood that the various embodiments described in the present application can be implemented alone or in combination, and the embodiments of the present application do not limit this.

[0077] Unless otherwise defined, all technical and scientific terms used in the embodiments of this application have the same meanings as commonly understood by one of ordinary skill in the technical field of this application. The terms used in this application are for the purpose of describing particular embodiments only and are not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a", "the above" and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly dictates otherwise.

[0078] As described above, the foregoing are only specific embodiments of this application, but the protection scope of the present invention is not limited thereto. Any person skilled in the technical field can easily conceive of changes or substitutions within the technical scope disclosed in this application, and all such changes or substitutions should be covered by the protection scope of this application. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; The base comprises a substrate and a shallow trench isolation structure; wherein the substrate comprises a first region defined by the shallow trench isolation structure; Etching the substrate to form a groove located in the first area; wherein the plane where the bottom of the groove is located and the sidewalls of the adjacent shallow trench isolation structure facing each other form a target area; and the target area has a substrate etching residue formed in the process of etching the substrate; The material of the etching residue of the substrate is transformed to obtain a first gate oxide layer in the target area.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: A patterned mask layer defining the first region is also formed on the substrate; the step of transforming the material of the etching residue of the substrate to form a first gate oxide layer in the target region includes: Converting the material of the substrate etching residue into the same material as the patterned mask layer; Removing the patterned mask layer; wherein the substrate etching residue in the target area is also removed; A first gate oxide layer is formed in the target area.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The material of the substrate is silicon; the material of the patterned mask layer is silicon nitride; and the step of converting the material of the etching residue of the substrate into the same material as the patterned mask layer comprises: A decoupled plasma nitridation deposition process is performed on a substrate etching residue portion made of silicon material to form a substrate etching residue portion made of silicon nitride material.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that: In the decoupled plasma nitridation deposition process, N2 is used as the ion source and the deposition rate of silicon nitride falls within 5 um / cm 2 ~20um / cm 2 within the range.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that: The step of transforming the material of the etching residue of the substrate to form a first gate oxide layer in the target area includes: The material of the substrate etching residue is converted into the same material as the first gate oxide layer.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that: The material of the substrate is silicon; the material of the first gate oxide layer is silicon dioxide; and the step of converting the material of the etching residue of the substrate into the same material as the first gate oxide layer comprises: Under low temperature and high pressure conditions, oxygen is used to oxidize the substrate etching residue of silicon material to form the substrate etching residue of silicon dioxide material.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that: Under low temperature and high pressure conditions, in the process of oxidizing the substrate etching residue of silicon material using oxygen, the substrate etching residue and the bottom of the groove are both affected by oxygen pressure; wherein the oxygen pressure acting on the substrate etching residue is greater than the oxygen pressure acting on the bottom of the groove.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that: A transition gate oxide portion made of silicon dioxide is formed at the bottom of the groove; after the material of the substrate etching residue is converted into the same material as the first gate oxide layer, the material of the substrate etching residue is converted to form a first gate oxide layer in the target area, and the step also includes: Using the transition gate oxide portion and the substrate etching residue portion of the silicon dioxide material as a masking layer, an ion implantation process is performed on the substrate; At least a portion of the masking layer consumed in the ion implantation process is removed; and the remaining masking layer serves as a portion of the first gate oxide layer.

9. The method for preparing a semiconductor structure according to any one of claims 1 to 8, characterized in that: The substrate also includes a second area defined by the shallow trench isolation structure; the base also includes an oxide layer located on the surface of the substrate; accordingly, in the step of etching the substrate to form a groove located in the first area, the oxide layer located in the first area is removed; the remaining oxide layer located in the second area serves as a second gate oxide layer; wherein the thickness of the second gate oxide layer is less than the thickness of the first gate oxide layer.

10. A semiconductor structure, characterized in that: The semiconductor structure is prepared by the method for preparing a semiconductor structure according to any one of claims 1 to 9.

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