Array substrate, preparation method thereof and display panel

Abstract

The invention discloses an array substrate, a preparation method thereof and a display panel. The array substrate comprises a substrate, a first electrode layer, a first metal layer, a gate insulation layer, an active layer, a pixel electrode layer and a second metal layer, the pixel electrode layer is located on one side of the active layer away from the substrate; the second metal layer is located on the side, away from the substrate, of the pixel electrode layer and comprises a source electrode and a drain electrode which are arranged at intervals; the array substrate further comprises a contact hole penetrating through the gate insulation layer, and the second wire in the second metal layer is electrically connected with the first wire in the first metal layer through the contact hole. The second metal layer and the pixel electrode can be patterned through one photomask, and the active layer and the contact hole penetrating through the gate insulation layer can be patterned through one photomask, so that only three photomasks are needed for preparation of the column substrate, the manufacturing process is simplified, the manufacturing time is shortened, the manufacturing cost is reduced, and the yield in the production process is greatly improved.

Description

Technical Field

[0001] The present invention relates to the field of displays, and particularly to an array substrate, a preparation method thereof, and a display panel. Background Art

[0002] Currently, array substrates mainly reduce costs, improve efficiency and yield by reducing the number of photomasks and exposure times. However, the preparation of traditional array substrates requires at least four processes, including a common electrode layer and M1 (the first metal layer), an active layer and M2 (the second metal layer), vias of PV (organic layer), and pixel electrodes, resulting in relatively high costs. Therefore, reducing the number of processes has become an urgent technical problem to be solved for current array substrates. Summary of the Invention

[0003] Embodiments of the present invention provide an array substrate, a preparation method thereof, and a display panel, which can solve the technical problem that the preparation of existing array substrates requires at least four processes, resulting in relatively high costs.

[0004] Embodiments of the present invention provide an array substrate, including:

[0005] A substrate;

[0006] A first electrode layer located on one side of the substrate;

[0007] A first metal layer located on the side of the first electrode layer away from the substrate, the first metal layer including a gate and a first trace arranged at intervals;

[0008] A gate insulating layer covering the side of the first metal layer away from the substrate;

[0009] An active layer located on the side of the gate insulating layer away from the substrate;

[0010] A second electrode layer located on the side of the active layer away from the substrate; and

[0011] A second metal layer directly overlapping with the side of the second electrode layer away from the substrate, the second metal layer including a source electrode, a drain electrode, and a second trace arranged at intervals;

[0012] The array substrate further includes a contact hole penetrating the gate insulating layer, and the second trace is connected to the first trace through the contact hole.

[0013] According to the array substrate provided by the embodiments of the present invention, the orthographic projection of the first metal layer on the substrate is located within the orthographic projection of the first electrode layer on the substrate;

[0014] The orthographic projection of the second metal layer on the substrate is located within the orthographic projection of the second electrode layer on the substrate; and

[0015] The positive projection of the active layer on the substrate is located within the positive projection of the gate insulating layer on the substrate.

[0016] For the array substrate provided by an embodiment of the present invention, the second electrode layer includes an opening, the opening is correspondingly arranged in the region between the source electrode and the drain electrode, and the part of the active layer exposed by the opening forms a channel;

[0017] The second electrode layer includes a first electrode part and a second electrode part respectively located on both sides of the opening, the drain electrode is located on the side of the first electrode part away from the substrate, and the source electrode is located on the side of the second electrode part away from the substrate;

[0018] Wherein, the edge of the drain electrode close to the opening is flush with the edge of the first electrode part close to the opening, and the edge of the source electrode close to the opening is flush with the edge of the second electrode part close to the opening.

[0019] For the array substrate provided by an embodiment of the present invention, the first electrode layer includes a third electrode part and a fourth electrode part arranged at intervals, the third electrode part is arranged opposite to the first electrode part, and the gate is located on the side of the fourth electrode part away from the substrate; wherein, the positive projection of the gate on the substrate is located within the positive projection of the fourth electrode part on the substrate.

[0020] For the array substrate provided by an embodiment of the present invention, the first electrode layer further includes a fifth electrode part arranged at intervals with the third electrode part, and a first trace is located on the side of the fifth electrode part away from the substrate;

[0021] Wherein, the second electrode layer further includes a connection electrode arranged at intervals with the first electrode part, a second trace is located on the side of the connection electrode away from the substrate, and the second trace is electrically connected to the first trace through the connection electrode and the contact hole.

[0022] An embodiment of the present invention provides a display panel, including the above-mentioned array substrate.

[0023] An embodiment of the present invention provides a method for manufacturing an array substrate, including the following steps:

[0024] Provide a substrate;

[0025] Use a first photomask to form a patterned first electrode layer and a patterned first metal layer on the substrate, the first metal layer is formed on the side of the first electrode layer away from the substrate, and the first metal layer includes a gate and a first trace arranged at intervals;

[0026] A patterned gate insulating layer, contact holes penetrating the gate insulating layer, and a patterned active layer are formed using a second photomask. The gate insulating layer covers a side of the first metal layer away from the substrate, and the active layer is located on a side of the gate insulating layer away from the substrate; and

[0027] A patterned second electrode layer and a patterned second metal layer are formed using a third photomask. The second electrode layer is located on a side of the active layer away from the substrate, and the second metal layer is located on a side of the second electrode layer away from the substrate. The second metal layer includes a source electrode, a drain electrode, and a second trace that are spaced apart. The second trace is connected to the first trace through the contact hole.

[0028] According to the method for manufacturing an array substrate provided by an embodiment of the present invention, the first photomask is a first halftone photomask, and the first halftone photomask includes a first light-transmitting region, a first semi-light-transmitting region, and a first light-blocking region;

[0029] The first light-transmitting region corresponds to a portion where the first electrode layer and the first metal layer are to be simultaneously removed. The first semi-light-transmitting region corresponds to a portion of the first electrode layer where the third electrode portion of the first electrode layer is to be formed. The first light-blocking region corresponds to a portion of the first metal layer where the gate and the first trace are to be formed.

[0030] According to the method for manufacturing an array substrate provided by an embodiment of the present invention, the second photomask is a second halftone photomask, and the second halftone photomask includes a second light-transmitting region, a second semi-light-transmitting region, and a second light-blocking region;

[0031] The second light-transmitting region corresponds to a portion where the contact hole is to be formed in the gate insulating layer. The second semi-light-transmitting region corresponds to a portion where the active layer is removed while the gate insulating layer is not removed. The third light-blocking region corresponds to a portion where the active layer is not removed.

[0032] According to the method for manufacturing an array substrate provided by an embodiment of the present invention, the third photomask is a third halftone photomask, and the third halftone photomask includes a third light-transmitting region, a third semi-light-transmitting region, and a third light-blocking region;

[0033] The third light-transmitting region corresponds to a portion where the channel is to be formed in the active layer. The third semi-light-transmitting region corresponds to a portion where the second electrode layer is not removed. The third light-blocking region corresponds to a portion where the source electrode, the drain electrode, and the second trace are to be formed in the second metal layer.

[0034] Beneficial effects: In the array substrate, its manufacturing method, and the display panel provided by the embodiments of the present invention, by disposing the second electrode layer on the side of the active layer away from the substrate, and the second metal layer is located on the side of the first pixel electrode away from the substrate and directly overlaps with the pixel electrode, without forming an insulating layer and a via hole penetrating the insulating layer to electrically connect the pixel electrode and the second metal layer therebetween, thus eliminating the photomask for preparing the via hole; moreover, the second metal layer and the pixel electrode can be patterned through one photomask, and the contact hole of the active layer and the gate insulating layer can be patterned through one photomask. Compared with the prior art, the array substrate of the present invention only requires three photomasks, simplifies the manufacturing process, reduces the manufacturing time, lowers the manufacturing cost, and greatly improves the yield during the production process. Description of the Drawings

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0036] Figure 1 It is a schematic cross-sectional structure diagram of the first type of the array substrate provided by the embodiment of the present invention;

[0037] Figure 2 It is a schematic plan cross-sectional structure diagram of the pixel electrode of the array substrate provided by the embodiment of the present invention;

[0038] Figure 3 It is a schematic cross-sectional structure diagram of the second type of the array substrate provided by the embodiment of the present invention;

[0039] Figure 4 It is a flowchart of the manufacturing method of the array substrate provided by the embodiment of the present invention;

[0040] Figures 5A - 5G It is a schematic structural diagram of the process of the manufacturing method of the array substrate provided by the embodiment of the present invention.

[0041] Description of the Reference Numerals:

[0042] 10. Substrate; 11. First electrode layer; 111. Third electrode portion; 112. Fourth electrode portion; 113. Fifth electrode portion; 12. First metal layer; 121. Gate; 122. First trace; 123. Scan line; 13. Gate insulating layer; 131. Contact hole; 14. Active layer; 15. Second electrode layer; 151. First electrode portion; 152. Second electrode portion; 153. Connection electrode; 154. Opening; 16. Second metal layer; 161. Source; 162. Drain; 163. Second trace; 164. Data line;

[0043] 21. First photomask; 211. First light-transmitting region; 212. First semi-light-transmitting region; 213. First light-impermeable region; 22. Second photomask; 221. Second light-transmitting region; 222. Second semi-light-transmitting region; 223. Second light-impermeable region; 23. Third photomask; 231. Third light-transmitting region; 232. Third semi-light-transmitting region; 233. Third light-impermeable region; 31. First photoresist layer; 32. Second photoresist layer; 33. Third photoresist layer. Detailed implementation mode

[0044] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts belong to the protection scope of the present invention.

[0045] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "length", "width", "thickness", "upper", "lower", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention. In the description of the present invention, "a plurality of" means two or more unless otherwise specifically defined.

[0046] In the present invention, unless otherwise clearly defined and limited, the first feature being "above" or "below" the second feature may include direct contact between the first and second features, or may include the situation where the first and second features are not in direct contact but are in contact through other features therebetween.

[0047] The embodiments of the present invention provide an array substrate, a preparation method thereof, and a display panel. The following will be described in detail respectively. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments.

[0048] In view of the technical problem that the preparation of an array substrate in the related art requires at least four manufacturing processes, resulting in high costs, in the present invention, the second electrode layer is disposed on the side of the active layer away from the substrate, and the second metal layer is located on the side of the first pixel electrode away from the substrate and is directly overlapped with the pixel electrode, without forming an insulating layer and a via hole penetrating the insulating layer to electrically connect the pixel electrode and the second metal layer therebetween, thus eliminating the photomask for preparing the via hole; moreover, the second metal layer and the pixel electrode can be patterned through one photomask, and the contact hole penetrating the gate insulating layer of the active layer can be patterned through one photomask. Compared with the prior art, the array substrate of the present invention only requires three photomasks, simplifies the manufacturing process, reduces the manufacturing time, reduces the manufacturing cost, and greatly improves the yield during the production process.

[0049] Please refer to Figure 1 and Figure 2 As shown in FIGS. and, the array substrate provided by the embodiment of the present invention includes a substrate 10, a first electrode layer 11, a first metal layer 12, a gate insulating layer 13, an active layer 14, a second electrode layer 15, and a second metal layer 16. The first electrode layer 11 is located on one side of the substrate 10; the first metal layer 12 is located on the side of the first electrode layer 11 away from the substrate 10, and the first metal layer 12 includes a gate 121 and a first trace 122 arranged at intervals; the gate insulating layer 13 covers the side of the first metal layer 12 away from the substrate 10; the active layer 14 is located on the side of the gate insulating layer 13 away from the substrate 10; the second electrode layer 15 is located on the side of the active layer 14 away from the substrate 10; the second metal layer 16 is located on the side of the second electrode layer 15 away from the substrate 10, and the second metal layer 16 includes a source electrode 161, a drain electrode 162, and a second trace 163 arranged at intervals. The array substrate further includes a contact hole 131 that penetrates the gate insulating layer 13, and the second trace 163 is electrically connected to the first trace 122 through the contact hole 131.

[0050] It can be understood that in the embodiment of the present invention, only three photomasks are required to prepare the array substrate, specifically: the two film layers of the first electrode layer 11 and the first metal layer 12 are jointly prepared using the same photomask; the active layer 14 is prepared using one photomask; the second electrode layer 15 and the second metal layer 16 are jointly prepared using the same photomask, and the contact hole 131 penetrating the gate insulating layer 13 of the active layer 14 can be patterned through one photomask. Compared with the prior art where at least four photomasks are required to prepare the array substrate, it is beneficial to simplify the manufacturing process, reduce the manufacturing time, reduce the manufacturing cost, and greatly improve the yield during the production process.

[0051] Specifically, the substrate 10 can be a rigid substrate 10 or a flexible substrate 10. The second electrode layer 15 and the first electrode layer 11 are made of a light-transmitting material, and the two can be made of the same material. For example, the second electrode layer 15 and the first electrode layer 11 are made of indium tin oxide (ITO) material. The gate insulating layer 13 is made of an inorganic insulating material, such as one or a combination of silicon nitride, silicon oxide, or silicon oxynitride.

[0052] In the present invention, referring to Figure 2 , the orthographic projection of the first metal layer 12 on the substrate 10 is located within the orthographic projection of the first electrode layer 11 on the substrate 10; the orthographic projection of the second metal layer 16 on the substrate 10 is located within the orthographic projection of the second electrode layer 15 on the substrate 10; the orthographic projection of the active layer 14 on the substrate 10 is located within the orthographic projection of the gate insulating layer 13 on the substrate 10.

[0053] Since the first metal layer 12 and the first electrode layer 11 are prepared using the same photomask, and the stacking order of the two in the film thickness direction is that the first electrode layer 11 is located below the first metal layer 12, according to the characteristics of the yellow light process, the actually formed pixel structure is: there must be the first electrode layer 11 below the first metal layer 12, and there may not be the second metal layer 16 above the first electrode layer 11. Similarly, since the gate insulating layer 13 and the active layer 14 are prepared using the same photomask, and the stacking order of the two in the film thickness direction is that the gate insulating layer 13 is located below the active layer 14, according to the characteristics of the yellow light process, the actually formed pixel structure is: there must be the gate insulating layer 13 below the active layer 14, and there may not be the active layer 14 above the gate insulating layer 13. Similarly, since the second electrode layer 15 and the second metal layer 16 are prepared using the same photomask, and the stacking order of the two in the film thickness direction is that the second electrode layer 15 is located below the second metal layer 16, according to the characteristics of the yellow light process, the actually formed pixel structure is: there must be the second electrode layer 15 below the second metal layer 16, and there may not be the second metal layer 16 above the second electrode layer 15.

[0054] In the present invention, the second electrode layer 15 includes an opening 154 which is correspondingly disposed in the region between the source electrode 161 and the drain electrode 162. The portion of the active layer 14 exposed by the opening 154 forms a channel. The second electrode layer 15 includes a first electrode portion 151 and a second electrode portion 152 respectively located on both sides of the opening 154. The drain electrode 162 is located on the side of the first electrode portion 151 away from the substrate 10, and the source electrode 161 is located on the side of the second electrode portion 152 away from the substrate 10. Wherein, the edge of the drain electrode 162 close to the opening 154 is flush with the edge of the first electrode portion 151 close to the opening 154, and the edge of the source electrode 161 close to the opening 154 is flush with the edge of the second electrode portion 152 close to the opening 154. The reason for such a setting is that, according to the above analysis, since the second electrode layer 15 must exist below the second metal layer 16, in order to make the region between the source electrode 161 and the drain electrode 162 correspond to the portion of the active layer 14 exposed by the opening 154, so as to increase the width of the formed channel.

[0055] Specifically, the gate electrode 121, the active layer 14, the source electrode 161 and the drain electrode 162 constitute a thin film transistor, and the thin film transistor can be located in the display area to drive the pixel to emit light; the thin film transistor can also be located in the scan driving circuit area (GOA). In this embodiment of the present invention, the case where the thin film transistor is located in the display area is taken as an example for illustration.

[0056] Specifically, in the present invention, the first electrode layer 11 includes a third electrode portion 111 and a fourth electrode portion 112 which are spaced apart. The third electrode portion 111 is disposed opposite to the first electrode portion 151, and the gate electrode 121 is located on the side of the fourth electrode portion 112 away from the substrate 10. Wherein, the orthographic projection of the gate electrode 121 on the substrate 10 is located within the orthographic projection of the fourth electrode portion 112 on the substrate 10. Specifically, a storage capacitor is formed between the third electrode portion 111 and the first electrode portion 151.

[0057] Specifically, the first metal layer 12 and the second metal layer 16 may include multiple signal traces. For example, the first metal layer 12 includes a scan line 123 disposed horizontally, and the second metal layer 16 includes a data line 164 disposed vertically. The scan line 123 and the data line 164 are cross - arranged to define a plurality of sub - pixel units, and the thin film transistor and the first electrode portion 151 are located within the region defined by the scan line 123 and the data line 164.

[0058] In the present invention, the array substrate further includes a contact hole 131 penetrating through the gate insulating layer 13. The first metal layer 12 further includes a first trace 122 spaced apart from the gate 121. The first electrode layer 11 further includes a fifth electrode portion 113 spaced apart from the third electrode portion 111. The first trace 122 is located on a side of the fifth electrode portion 113 away from the substrate 10. Wherein, the second electrode layer 15 further includes a connection electrode 153 spaced apart from the first electrode portion 151. The connection electrode 153 is electrically connected to the first trace 122 through the contact hole 131. It can be understood that the contact hole 131 on the gate insulating layer 13 can be fabricated using the same photomask as the active layer 14 without adding a manufacturing process.

[0059] In the present invention, the second trace 163 is located on a side of the connection electrode 153 away from the substrate 10. The second trace 163 is electrically connected to the first trace 122 through the connection electrode 153 and the contact hole 131.

[0060] It should be noted that, in one embodiment, the connection electrode 153 can also be used to connect two traces arranged in different layers. For example, the connection electrode 153 can be used to connect the first trace 122 and the second trace 163 arranged in different layers. Specifically, the connection electrode 153 is connected to the first trace 122 through the contact hole 131. Also, since the connection electrode 153 is directly overlapped with the second trace 163, the connection between the first trace 122 and the second trace 163 can be achieved.

[0061] Exemplarily, the first trace 122 and the second trace 163 are GOA area wirings. Since the GOA area is relatively small, the wirings in this area can be routed by changing the lines to make full use of the space. For example, the first trace 122 and the second trace 163 can be initial signal lines with a line-changing design, and the initial signal lines are connected to the scan line 123. Or, the first trace 122 and the second trace 163 can also be double-layer fan-out wirings for transmitting fan-out signals to make full use of the fan-out area space, and the double-layer fan-out wirings are connected to the data line 164.

[0062] In another embodiment, as Figure 3 shown, the connection electrode 153 can be used as a bridging electrode to connect two of the first traces 122. At this time, two contact holes 131 can be provided, and the two first traces 122 are bridged through the connection electrode 153. At this time, the second trace 163 can be cancelled on a side of the connection electrode 153 away from the substrate 10.

[0063] Specifically, the first electrode layer 11 is a common electrode layer, and the second electrode layer 15 is a pixel electrode layer.

[0064] Please refer to Figure 4 and Figures 5A - 5G , an embodiment of the present invention further provides a method for manufacturing an array substrate, including the following steps:

[0065] Step S10: Provide a substrate 10.

[0066] Specifically, as Figure 5A shown, the substrate 10 can be a rigid substrate 10 or a flexible substrate 10. The rigid substrate 10 can be a glass substrate 10, and the flexible substrate 10 can be a polyimide substrate 10.

[0067] Step S20: Use a first photomask 21 to form a patterned first electrode layer 11 and a patterned first metal layer 12 on the substrate 10. The first metal layer 12 is formed on a side of the first electrode layer 11 away from the substrate 10. The first metal layer 12 includes a gate 121 and a first trace 122 that are spaced apart.

[0068] Specifically, the step S20 includes the following steps: As Figure 5B shown, coat the first electrode layer 11, the first metal layer 12, and a first photoresist layer 31 on the substrate 10 in sequence over the entire surface; as Figure 5C shown, use the first photomask 21 to expose the first photoresist layer 31, and then develop the first photoresist layer 31 to form the patterned first photoresist layer 31; use the patterned first photoresist layer 31 as a mask to etch the first electrode layer 11 and the first metal layer 12 in sequence to form a third electrode portion 111, a fourth electrode portion 112, a gate 121, and a first trace 122; then, remove the remaining first photoresist layer 31.

[0069] Specifically, the first photomask 21 is a first halftone photomask. The first halftone photomask includes a first light-transmitting area 211, a first semi-light-transmitting area 212, and a first light-impermeable area 213. The first light-transmitting area 211 corresponds to a portion of the first electrode layer 11 and the first metal layer 12 to be removed simultaneously. The first semi-light-transmitting area 212 corresponds to a portion of the first electrode layer 11 where the third electrode portion 111 of the first electrode layer 11 is to be formed. The first light-impermeable area 213 corresponds to a portion of the first metal layer 12 where the gate 121 and the first trace 122 are to be formed.

[0070] Step S30: A patterned gate insulating layer 13 and a patterned active layer 14 are formed using a second photomask 22. The gate insulating layer 13 is covered on a side of the first metal layer 12 away from the substrate 10, and the active layer 14 is located on a side of the gate insulating layer 13 away from the substrate 10.

[0071] Specifically, step S30 includes the following steps: As Figure 5D shown, the gate insulating layer 13, the active layer 14, and a second photoresist layer 32 are coated over the entire surface of the second metal layer 16 in sequence; as Figure 5E shown, the second photoresist layer 32 is exposed using the second photomask 22, and then the second photoresist layer 32 is developed to form the patterned second photoresist layer 32; the gate insulating layer 13 and the active layer 14 are etched in sequence using the patterned second photoresist layer 32 as a mask to form contact holes 131 and a patterned active layer 14; thereafter, the remaining second photoresist layer 32 is removed.

[0072] Specifically, the second photomask 22 is a second halftone photomask, and the second halftone photomask includes a second light-transmitting region 221, a second semi-light-transmitting region 222, and a second light-impermeable region 223; the second light-transmitting region 221 corresponds to a portion of the gate insulating layer 13 where the contact holes 131 are to be formed, the second semi-light-transmitting region 222 corresponds to a portion where the active layer 14 is removed and the gate insulating layer 13 is not removed, and the third light-impermeable region 233 corresponds to a portion where the active layer 14 is not removed.

[0073] Step S40: A patterned second electrode layer 15 and a patterned second metal layer 16 are formed using a third photomask 23. The second electrode layer 15 is located on a side of the active layer 14 away from the substrate 10, the second metal layer 16 is located on a side of the second electrode layer 15 away from the substrate 10, and the second metal layer 16 includes a source electrode 161, a drain electrode 162, and a second trace 163 that are arranged at intervals; wherein, the second trace 163 is connected to the first trace 122 through the contact holes 131.

[0074] Specifically, as Figure 5F shown, step S40 includes the following steps: The second electrode layer 15, the second metal layer 16, and a third photoresist layer 33 are coated over the entire surface of the active layer 14 in sequence; as Figure 5GAs shown, the third photoresist layer 33 is exposed using the third photomask 23, and then the third photoresist layer 33 is developed to form the patterned third photoresist layer 33. Using the patterned third photoresist layer 33 as a mask, the second electrode layer 15 and the second metal layer 16 are etched in sequence to form the contact holes 131 and the patterned active layer 14. After that, the remaining third photoresist layer 33 is removed.

[0075] Specifically, the third photomask 23 is a third halftone photomask, and the third halftone photomask includes a third light-transmitting region 231, a third semi-light-transmitting region 232, and a third light-impermeable region 233. The third light-transmitting region 231 corresponds to the part of the active layer 14 where the channel is to be formed. The third semi-light-transmitting region 232 corresponds to the part of the second electrode layer 15 that is not to be removed. The third light-impermeable region 233 corresponds to the parts of the second metal layer 16 where the source electrode 161 and the drain electrode 162 are to be formed.

[0076] It should be noted that for the above-mentioned first halftone photomask, the second halftone photomask, and the third halftone photomask, the light-transmitting region refers to the region with a light transmittance of 100%. The semi-light-transmitting region only refers to the region with a light transmittance less than 100%. The light-impermeable region refers to the region with a light transmittance of 0.

[0077] It can be understood that by using the manufacturing method provided by the embodiments of the present invention, only three photomasks are required, which simplifies the manufacturing process, reduces the manufacturing time, reduces the manufacturing cost, and greatly improves the yield during the production process.

[0078] Correspondingly, an embodiment of the present invention further provides a display panel. The display panel includes the above-mentioned array substrate. The display panel has all the beneficial effects of the above-mentioned array substrate. The display panel can be one of a liquid crystal display panel and an organic light-emitting diode display panel. The above embodiments have described the array substrate in detail. Therefore, in the embodiments of the present invention, the array substrate will not be described in detail.

[0079] Beneficial effects: In the array substrate, its manufacturing method, and the display panel provided by the embodiments of the present invention, by disposing the second electrode layer on the side of the active layer away from the substrate, and the second metal layer is located on the side of the second electrode layer away from the substrate and is directly lapped with the second electrode layer, without forming an insulating layer and a via hole penetrating the insulating layer to electrically connect the second electrode layer and the second metal layer between them, thus eliminating the photomask for preparing the via hole. Moreover, the second metal layer and the second electrode layer can be patterned through one photomask, and the contact holes of the active layer and the gate insulating layer can be patterned through one photomask. Compared with the prior art, the array substrate of the present invention only requires three photomasks, which simplifies the manufacturing process, reduces the manufacturing time, reduces the manufacturing cost, and greatly improves the yield during the production process.

[0080] In the above embodiments, the descriptions of the respective embodiments have their own focuses. For the parts not described in detail in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0081] The above has introduced in detail an array substrate, a method for preparing the same, and a display panel provided by an embodiment of the present invention. Specific examples are used herein to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the technical solution and its core idea of the present invention; those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An array substrate, characterized in that, Comprising: Substrate; A first electrode layer located on one side of the substrate; A first metal layer located on the side of the first electrode layer away from the substrate, the first metal layer including a gate and a first trace arranged at intervals; A gate insulating layer covering the side of the first metal layer away from the substrate; An active layer located on the side of the gate insulating layer away from the substrate; A second electrode layer located on the side of the active layer away from the substrate; And A second metal layer directly overlapping with the side of the second electrode layer away from the substrate, the second metal layer including a source electrode, a drain electrode and a second trace arranged at intervals; The array substrate further includes a contact hole penetrating the gate insulating layer, and the second trace is connected to the first trace through the contact hole.

2. The array substrate according to claim 1, characterized in that, The orthographic projection of the first metal layer on the substrate is located within the orthographic projection of the first electrode layer on the substrate; The orthographic projection of the second metal layer on the substrate is located within the orthographic projection of the second electrode layer on the substrate; And The orthographic projection of the active layer on the substrate is located within the orthographic projection of the gate insulating layer on the substrate.

3. The array substrate according to claim 2, characterized in that, The second electrode layer includes an opening corresponding to the region between the source electrode and the drain electrode, and the portion of the active layer exposed by the opening forms a channel; The second electrode layer includes a first electrode portion and a second electrode portion respectively located on both sides of the opening, the drain electrode is located on the side of the first electrode portion away from the substrate, and the source electrode is located on the side of the second electrode portion away from the substrate; Wherein, the edge of the drain electrode close to the opening is flush with the edge of the first electrode portion close to the opening, and the edge of the source electrode close to the opening is flush with the edge of the second electrode portion close to the opening.

4. The array substrate according to claim 3, characterized in that, The first electrode layer includes a third electrode portion and a fourth electrode portion arranged at intervals, the third electrode portion is arranged opposite to the first electrode portion, and the gate is located on the side of the fourth electrode portion away from the substrate; wherein, the orthographic projection of the gate on the substrate is located within the orthographic projection of the fourth electrode portion on the substrate.

5. The array substrate according to claim 4, characterized in that, The first electrode layer further includes a fifth electrode portion arranged at intervals with the third electrode portion, and the first trace is located on the side of the fifth electrode portion away from the substrate; Wherein, the second electrode layer further includes a connection electrode arranged at intervals with the first electrode portion, the second trace is located on the side of the connection electrode away from the substrate, and the second trace is electrically connected to the first trace through the connection electrode and the contact hole.

6. A display panel, characterized in that, An array substrate according to any one of claims 1-5.

7. A method for manufacturing an array substrate, characterized in that, Comprising the following steps: Providing a substrate; Forming a patterned first electrode layer and a patterned first metal layer on the substrate by using a first photomask, the first metal layer being formed on the side of the first electrode layer away from the substrate, the first metal layer including a gate and a first trace arranged at intervals; A patterned gate insulating layer, contact holes penetrating the gate insulating layer, and a patterned active layer are formed using a second photomask. The gate insulating layer covers a side of the first metal layer away from the substrate, and the active layer is located on a side of the gate insulating layer away from the substrate; and A patterned second electrode layer and a patterned second metal layer are formed using a third photomask. The second electrode layer is located on a side of the active layer away from the substrate, and the second metal layer is located on a side of the second electrode layer away from the substrate. The second metal layer includes a source electrode, a drain electrode, and a second trace arranged at intervals; wherein, the second trace is connected to the first trace through the contact hole.

8. The method for manufacturing an array substrate according to claim 7, characterized in that, The first photomask is a first halftone photomask, and the first halftone photomask includes a first light-transmitting region, a first semi-light-transmitting region, and a first light-impermeable region; The first light-transmitting region corresponds to a portion where the first electrode layer and the first metal layer are to be simultaneously removed. The first semi-light-transmitting region corresponds to a portion of the first electrode layer where the third electrode portion of the first electrode layer is to be formed. The first light-impermeable region corresponds to a portion of the first metal layer where the gate and the first trace are to be formed.

9. The method for manufacturing an array substrate according to claim 7, characterized in that, The second photomask is a second halftone photomask, and the second halftone photomask includes a second light-transmitting region, a second semi-light-transmitting region, and a second light-impermeable region; The second light-transmitting region corresponds to a portion of the gate insulating layer where the contact holes are to be formed. The second semi-light-transmitting region corresponds to a portion where the active layer is removed while the gate insulating layer is not removed. The third light-impermeable region corresponds to a portion where the active layer is not removed.

10. The method for manufacturing an array substrate according to claim 7, characterized in that,The third photomask is a third halftone photomask, and the third halftone photomask includes a third light-transmitting region, a third semi-light-transmitting region, and a third light-impermeable region; The third light-transmitting region corresponds to a portion of the active layer where the channel is to be formed. The third semi-light-transmitting region corresponds to a portion where the second electrode layer is not removed. The third light-impermeable region corresponds to a portion of the second metal layer where the source electrode, the drain electrode, and the second trace are to be formed.

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