Programmable temperature sensing circuit suitable for in-chip temperature measurement

Abstract

The invention relates to a programmable temperature sensing circuit suitable for in-chip temperature measurement. The band-gap reference circuit comprises a band-gap reference which is used for generating reference voltage and reference current with zero temperature excursion; the V-I conversion circuit is used for receiving reference voltage generated by the band-gap reference and converting the reference voltage into positive temperature drift current changing along with the temperature, so that the temperature state of a chip where the V-I conversion circuit is located is represented by the positive temperature drift current; and the current operation unit is used for receiving the positive temperature drift current generated by the V-I conversion circuit and the reference current generated by the band-gap reference, and carrying out temperature calibration on the positive temperature drift current based on the digital control code and the reference current so as to generate a positive temperature drift calibration voltage corresponding to the current chip temperature after temperature calibration. The chip temperature sensing device is suitable for being integrated in a chip, can effectively sense the temperature in the chip, and improves the precision of temperature sensing in the chip and the adaptability of temperature sensing.

Description

Technical Field

[0001] The present invention relates to a temperature sensing circuit, and in particular to a programmable temperature sensing circuit suitable for on-chip temperature measurement. Background Art

[0002] For some digital circuits, the power consumption increases as the temperature rises, and the increased power consumption further raises the internal temperature of the circuit, which may cause thermal runaway and damage to the chip. Therefore, it is necessary to detect the temperature change in real time to adjust the power consumption. On the other hand, most analog circuits are sensitive to temperature and also require real-time detection of temperature changes.

[0003] In order to obtain the temperature inside the chip, a temperature sensing circuit is generally set inside the chip. It can be seen from this that the temperature sensing circuit inside the chip is mainly used to sense the change of the ambient temperature inside the chip where it is located and output a corresponding voltage change. Thereafter, the output voltage change can also be decoded by an analog-to-digital converter at the back end to obtain a temperature reading.

[0004] Currently, most common temperature sensing circuits form a bandgap reference circuit based on the temperature characteristics of transistors. Specifically, the temperature is sensed by using the difference between the base voltages of two transistors, that is, a voltage with a positive temperature coefficient proportional to the absolute temperature (PTAT, proportional to absolute temperature) can be obtained. After obtaining the PTAT voltage, the absolute temperature T can be converted into a Celsius voltage and output through a signal conditioning circuit.

[0005] Although the common temperature sensing circuit can realize the detection of the temperature inside the chip, it has the following deficiencies: it is greatly affected by the process, power supply voltage, and external environment (except temperature), and has poor compatibility with digital circuits. If a problem is found in the temperature detection during the test, it is difficult to correct.

[0006] Furthermore, for the deficiencies of the common temperature sensing circuit, although it can be adjusted by improving the signal conditioning circuit, the signal conditioning circuit itself is also affected by temperature, and this will greatly increase the circuit area. Therefore, the improvement effect through the signal conditioning circuit is limited. Summary of the Invention

[0007] The object of the present invention is to overcome the deficiencies existing in the prior art and provide a programmable temperature sensing circuit suitable for on-chip temperature measurement, which is suitable for integration in a chip and can effectively realize the sensing of the on-chip temperature, improve the accuracy of on-chip temperature sensing and the adaptability of temperature sensing.

[0008] According to the technical solution provided by the present invention, a programmable temperature sensing circuit suitable for on-chip temperature measurement, the programmable temperature sensing circuit includes:

[0009] Bandgap reference, used to generate a reference voltage and a reference current with zero temperature drift;

[0010] V-I conversion circuit, receiving the reference voltage generated by the bandgap reference and converting the reference voltage into a positive temperature drift current that varies with temperature, so as to characterize the temperature state of the chip where the V-I conversion circuit is located by using the positive temperature drift current;

[0011] Current operation unit, receiving the positive temperature drift current generated by the V-I conversion circuit and the reference current generated by the bandgap reference, and performing temperature calibration on the positive temperature drift current based on the digital control code and the reference current, so as to generate a positive temperature drift calibration voltage that corresponds exactly to the current chip temperature after temperature calibration.

[0012] The V-I conversion circuit includes a negative feedback amplifier circuit and a temperature current generation unit that is adaptively connected to the negative feedback amplifier circuit, where,

[0013] The negative feedback amplifier circuit receives the reference voltage generated by the bandgap reference and stabilizes the operating voltage of the temperature current generation unit at the reference voltage, so that the temperature current generation unit generates a positive temperature drift current that varies with temperature under a stable operating voltage.

[0014] The negative feedback amplifier circuit includes an operational amplifier A1 and a PMOS transistor MP100 that is adaptively connected to the operational amplifier A1, where,

[0015] The inverting terminal of the operational amplifier A1 is connected to the reference voltage, the output terminal of the operational amplifier A1 is connected to the gate terminal of the PMOS transistor MP100, and the source terminal of the PMOS transistor MP100 is connected to the power supply VDD;

[0016] The non-inverting terminal of the operational amplifier A1 and the drain terminal of the PMOS transistor MP100 are both connected to the first end of a temperature resistor R1 in the temperature current generation unit. The second end of the temperature resistor R1 is connected to the collector terminal and the base terminal of an NPN transistor Q1, and the emitter terminal of the NPN transistor Q1 is grounded;

[0017] A positive temperature drift current is loaded into the current operation unit through the gate terminal of the PMOS transistor MP100.

[0018] It further includes a frequency compensation unit for loop frequency compensation, where,

[0019] The frequency compensation unit at least includes a Miller compensation capacitor C1. One end of the Miller compensation capacitor C1 is connected to the output terminal of the operational amplifier A1 and the gate terminal of the PMOS transistor MP100, and the other end of the Miller compensation capacitor C100 is connected to the drain terminal of the PMOS transistor MP100, the non-inverting terminal of the operational amplifier A1, and the first end of the temperature resistor R1.

[0020] The current operation unit includes a temperature calibration unit for calibrating the temperature of the positive temperature drift current and a current-voltage conversion unit adaptively connected to the temperature calibration unit. Among them,

[0021] When calibrating the temperature of the positive temperature drift current, at least the reference current and the positive temperature drift current are linearly added by using the digital control code to generate a positive temperature drift calibration current after the linear addition;

[0022] The current-voltage conversion unit performs current-voltage conversion on the positive temperature drift calibration current to generate a positive temperature drift calibration voltage after the current-voltage conversion.

[0023] The temperature calibration unit includes a first group of current mirrors, a second group of current mirrors, a third group of current mirrors, and a fourth group of current mirrors.

[0024] The digital control code includes a first digital control signal and a second digital control signal. Among them,

[0025] The first group of current mirrors, the second group of current mirrors, and the third group of current mirrors are adaptively connected to form a temperature calibration node;

[0026] The first group of current mirrors is adaptively connected to the V-I conversion circuit and receives the first digital control signal. The first group of current mirrors is configured by the first digital control signal to convert the received positive temperature drift current into a temperature-sensing reference current. Among them, the temperature-sensing reference current and the positive temperature drift current are in a first ratio, and the temperature coefficient of the temperature-sensing reference current is different from that of the positive temperature drift current;

[0027] The fourth group of current mirrors is adaptively connected to the bandgap reference to respectively transmit the reference current generated by the bandgap reference to the second group of current mirrors and the third group of current mirrors;

[0028] The second group of current mirrors receives the second digital control signal and converts the reference current into a zero-temperature coefficient positive current based on the second digital control signal. Among them, the zero-temperature coefficient positive current and the reference current are in a second ratio;

[0029] The third group of current mirrors receives the first digital control signal and converts the reference current into a zero-temperature coefficient negative current based on the first digital control signal. Among them, the zero-temperature coefficient negative current and the reference current are in a third ratio;

[0030] When calibrating the temperature of the positive temperature drift current, the temperature-sensing reference current and the zero-temperature coefficient positive current are subjected to an accumulation operation, and the accumulated value obtained from the accumulation operation is subtracted from the zero-temperature coefficient negative current. After that, the result value of the subtraction operation is configured as the positive temperature drift calibration current;

[0031] The temperature calibration unit transmits the positive temperature drift calibration current to the current-voltage conversion unit through the temperature calibration node.

[0032] The first group of current mirrors includes a first group of first sub-current mirrors and a first group of second sub-current mirrors, where,

[0033] The first group of first sub-current mirrors includes a first PMOS transistor group of the first sub-current mirror and a second PMOS transistor group of the first sub-current mirror. The number of PMOS transistors in the first PMOS transistor group of the first sub-current mirror is consistent with the number of PMOS transistors in the second PMOS transistor group of the first sub-current mirror, and the number of PMOS transistors in the second PMOS transistor group of the first sub-current mirror is not less than the data bit width of the first digital control signal;

[0034] The PMOS transistors in the first PMOS transistor group of the first sub-current mirror are connected to the PMOS transistors in the second PMOS transistor group of the first sub-current mirror in a one-to-one correspondence. Among them, the source terminals of each PMOS transistor in the first PMOS transistor group of the first sub-current mirror are all connected to the power supply VDD, and the drain terminal of each PMOS transistor in the first PMOS transistor group of the first sub-current mirror is connected to the source terminal of the corresponding PMOS transistor in the second PMOS transistor group of the first sub-current mirror,

[0035] The drain terminals of all PMOS transistors in the second PMOS transistor group of the first sub-current mirror are all connected to the temperature calibration node, and the gate terminal of each PMOS transistor in the second PMOS transistor of the first sub-current mirror receives one digital control bit in the first digital control signal;

[0036] The first group of second sub-current mirrors includes a first PMOS transistor group of the second sub-current mirror and a second PMOS transistor group of the second sub-current mirror. The number of PMOS transistors in the first PMOS transistor group of the second sub-current mirror is consistent with the number of PMOS transistors in the second PMOS transistor group of the second sub-current mirror;

[0037] The PMOS transistors in the first PMOS transistor group of the second sub-current mirror are connected to the PMOS transistors in the second PMOS transistor group of the second sub-current mirror in a one-to-one correspondence. Among them, the source terminals of each PMOS transistor in the first PMOS transistor group of the second sub-current mirror are all connected to the power supply VDD, and the drain terminal of each PMOS transistor in the first PMOS transistor group of the second sub-current mirror is connected to the source terminal of the corresponding PMOS transistor in the second PMOS transistor group of the second sub-current mirror,

[0038] The drain terminals of all PMOS transistors in the second PMOS transistor group of the second sub-current mirror are all connected to the temperature calibration node, and all PMOS transistors in the second PMOS transistor group of the second sub-current mirror are configured to be in a conducting state;

[0039] The gate terminals of all PMOS transistors in the first PMOS transistor group of the first sub-current mirror and the gate terminals of all PMOS transistors in the first PMOS transistor group of the second sub-current mirror are adaptively connected to the V-I conversion circuit to receive the positive temperature drift current generated by the V-I conversion circuit;

[0040] When converting the received positive temperature drift current into a temperature-sensing reference current, the following equation holds:

[0041] I_TC = (TC1 + m) * I1

[0042] Wherein, I_TC is the temperature-sensing reference current, TC1 is the number of digital control bits with a value of 0 in the first digital control signal, m is the number of PMOS transistors in the first PMOS transistor group of the second sub-current mirror, and I1 is the positive temperature drift current;

[0043] When calibrating the temperature of the positive temperature drift current, the induced reference current flows into the temperature calibration node.

[0044] The third group of current mirrors includes a first NMOS transistor group of the third current mirror and a second NMOS transistor group of the third current mirror, wherein,

[0045] The number of NMOS transistors in the first NMOS transistor group of the third current mirror is the same as the number of NMOS transistors in the second NMOS transistor group of the third current mirror, and the number of NMOS transistors in the first NMOS transistor group of the third current mirror is not less than the data bit width of the first digital control signal. One digital control bit of the first digital control signal is loaded to the gate terminal of one NMOS transistor in the first NMOS transistor group of the third current mirror;

[0046] The drain terminal of each NMOS transistor in the first NMOS transistor group of the third current mirror is connected to the temperature calibration node, and the source terminal of each NMOS transistor in the first NMOS transistor of the third current mirror is connected to the drain terminal of the corresponding NMOS transistor in the second NMOS transistor group of the third current mirror;

[0047] The source terminal of each NMOS transistor in the second NMOS transistor group of the third current mirror is grounded, and the gate terminal of each NMOS transistor in the second NMOS transistor group of the third current mirror is adaptively connected to the fourth group of current mirrors to receive the reference current loaded by the fourth group of current mirrors;

[0048] When converting the received reference current into a zero temperature coefficient negative current, the following equation holds:

[0049] I_CA2 = CA2 * IREF

[0050] Wherein, I_CA2 is the zero temperature coefficient negative current, CA2 is the number of digital control bits with a value of 1 in the first digital control signal, and IREF is the reference current;

[0051] When calibrating the temperature of the positive temperature drift current, the zero temperature coefficient negative current flows out of the temperature calibration node.

[0052] The second group of current mirrors includes a first PMOS transistor group of the second current mirror and a second PMOS transistor group of the second current mirror, wherein,

[0053] The number of PMOS transistors in the first PMOS transistor group of the second current mirror is consistent with the number of PMOS transistors in the second PMOS transistor group of the second current mirror, and the number of PMOS transistors in the second PMOS transistor group of the second current mirror is not less than the data bit width of the second digital control signal. One digital control bit of the second digital control signal is loaded to the gate terminal of one PMOS transistor in the second PMOS transistor group of the second current mirror;

[0054] The PMOS transistors in the first PMOS transistor group of the second current mirror are connected to the PMOS transistors in the second PMOS transistor group of the second current mirror in a one-to-one correspondence. Among them, the source terminal of each PMOS transistor in the first PMOS transistor group of the second current mirror is connected to the power supply VDD, and the drain terminal of each PMOS transistor in the first PMOS transistor group of the second current mirror is connected to the source terminal of the corresponding PMOS transistor in the second PMOS transistor group of the second current mirror,

[0055] The gate terminal of each PMOS transistor in the first PMOS transistor group of the second current mirror is adaptively connected to the fourth group of current mirrors to receive the reference current loaded by the fourth group of current mirrors;

[0056] The source terminal of each PMOS transistor in the second PMOS transistor group of the second current mirror is connected to the temperature calibration node;

[0057] When converting the received reference current into a zero-temperature-coefficient forward current, there is:

[0058] I_CA1 = CA1 * IREF

[0059] Among them, I_CA1 is the zero-temperature-coefficient forward current, CA1 is the number of digital control bits with a value of 0 in the second digital control signal, and IREF is the reference current;

[0060] When calibrating the positive temperature drift current, the zero-temperature-coefficient forward current flows into the temperature calibration node.

[0061] The fourth group of current mirrors includes a fourth group of first sub-current mirrors, a low-voltage cascode current mirror, a fourth group of second sub-current mirrors, and a fourth group of third sub-current mirrors. Among them,

[0062] The fourth group of first sub-current mirrors is connected to the bandgap reference to mirror the reference current generated by the bandgap reference to the low-voltage cascode current mirror,

[0063] The low-voltage cascode current mirror loads the reference current to the third group of current mirrors, and transmits it to the fourth group of third sub-current mirrors through the fourth group of second sub-current mirrors, and loads the reference current to the second group of current mirrors through the fourth group of third sub-current mirrors;

[0064] The low-voltage cascode current mirror includes a current mirror resistor, a first NMOS transistor of the cascode current mirror, and a second NMOS transistor of the cascode current mirror. Among them,

[0065] The first end of the current mirror resistor is connected to the gate terminals of the first sub-current mirror of the fourth group and the first NMOS transistor of the cascode current mirror.

[0066] The second end of the current mirror resistor is connected to the drain terminal of the first NMOS transistor of the cascode current mirror and the gate terminal of the second NMOS transistor of the cascode.

[0067] The source terminal of the first NMOS transistor of the cascode current mirror is connected to the drain terminal of the second NMOS transistor of the cascode current mirror, and the source terminal of the second NMOS transistor of the cascode current mirror is grounded.

[0068] The gate terminal of the second NMOS transistor of the cascode current mirror is adaptively connected to the current mirror of the third group and the second sub-current mirror of the fourth group, and the gate terminal of the first NMOS transistor of the cascode current mirror is adaptively connected to the second sub-current mirror of the fourth group.

[0069] Advantages of the present invention: A reference voltage and a reference current with zero temperature drift are generated by using a bandgap reference. The negative feedback amplifier circuit in the V-I conversion circuit can stabilize the operating voltage of the temperature current generation unit at the reference voltage. Thereafter, a positive temperature drift current can be generated by using the temperature current generation unit. The generated positive temperature current is less affected by process, power supply voltage, and external environment (except temperature), improving the accuracy and stability of generating the positive temperature drift current.

[0070] The positive temperature drift current can be temperature-calibrated through the current operation unit. During temperature calibration, the reference current and the positive temperature drift current are linearly added by using a digital control code to adjust the curve of the positive temperature drift current - temperature generated by the V-I conversion circuit, further reducing the influence of process, power supply voltage, and external environment (except temperature).

[0071] It can be integrated in a chip through CMOS process. The state of linearly adding the reference current and the positive temperature drift current is configured through a digital control code, so as to adapt to the temperature calibration of different chips and the temperature calibration of the same chip under different working scenarios; improving the accuracy of on-chip temperature sensing and the adaptability of temperature sensing. Description of the Drawings

[0072] Figure 1 It is a structural block diagram of an embodiment of the programmable temperature sensing circuit of the present invention.

[0073] Figure 2 It is a circuit schematic diagram of an embodiment of the V-I conversion circuit of the present invention.

[0074] Figure 3This is a schematic circuit diagram of an embodiment of the current operation unit of the present invention. Detailed implementation mode

[0075] The present invention will be further described below in conjunction with specific drawings and embodiments.

[0076] In order to effectively realize the induction of the on-chip temperature, improve the accuracy of on-chip temperature induction and the adaptability of temperature induction, the present invention provides a programmable temperature sensing circuit suitable for on-chip temperature measurement. Specifically, the programmable temperature sensing circuit includes:

[0077] A bandgap reference for generating a reference voltage and a reference current with zero temperature drift;

[0078] A V-I conversion circuit that receives the reference voltage generated by the bandgap reference and converts the reference voltage into a positive temperature drift current that changes with temperature, so as to use the positive temperature drift current to characterize the temperature state of the chip where the V-I conversion circuit is located;

[0079] A current operation unit that receives the positive temperature drift current generated by the V-I conversion circuit and the reference current generated by the bandgap reference, and performs temperature calibration on the positive temperature drift current based on a digital control code and the reference current, so as to generate a positive temperature drift calibration voltage corresponding to the current chip temperature after temperature calibration.

[0080] It should be noted that the programmable temperature sensing circuit should be integrated in the chip so as to measure the temperature of the integrated chip. Figure 1 An embodiment of the programmable temperature sensing circuit of the present invention is shown in. It can be seen from the figure that the programmable temperature sensing circuit should include a bandgap reference. Among them, a reference voltage and a reference current with zero temperature drift can be generated by using the bandgap reference. That is, the reference voltage and reference current generated by the bandgap reference do not change with temperature. Therefore, Figure 1 The zero temperature drift voltage in is the reference voltage, and the zero temperature drift current is the reference current. The bandgap reference can adopt the existing common form, specifically based on being able to generate a reference voltage and a reference current with zero temperature drift.

[0081] Figure 1 In, the bandgap reference is connected to the V-I conversion circuit. The V-I conversion circuit can convert the reference voltage generated by the bandgap reference into a positive temperature drift current that changes with temperature. Since the V-I conversion circuit is integrated in the chip, the positive temperature drift current can characterize the temperature state of the chip where the V-I conversion circuit is located, that is, the on-chip temperature induction of the located chip is realized. It can be understood that when the on-chip temperature is higher, the current value of the positive temperature drift current will be larger. The following is an example of the method and process of the V-I conversion circuit converting the reference voltage into a positive temperature drift current.

[0082] In an embodiment of the present invention, the V-I conversion circuit includes a negative feedback amplifier circuit and a temperature current generation unit adaptively connected to the negative feedback amplifier circuit, where,

[0083] The negative feedback amplifier circuit receives the reference voltage generated by the bandgap reference and stabilizes the operating voltage of the temperature current generation unit at the reference voltage, so that the temperature current generation unit generates a positive temperature drift current that changes with temperature under the stable operating voltage.

[0084] Specifically, by connecting the reference voltage through the negative feedback amplifier circuit and stabilizing the operating voltage of the temperature current generation unit at the reference voltage, that is, making the temperature current generation unit operate under the reference voltage. Thereafter, the temperature current generation unit can generate a positive temperature drift current that changes with temperature.

[0085] In an embodiment of the present invention, the negative feedback amplifier circuit includes an operational amplifier A1 and a PMOS transistor MP100 adaptively connected to the operational amplifier A1, where,

[0086] The inverting terminal of the operational amplifier A1 is connected to the reference voltage, the output terminal of the operational amplifier A1 is connected to the gate terminal of the PMOS transistor MP100, and the source terminal of the PMOS transistor MP100 is connected to the power supply VDD;

[0087] The non-inverting terminal of the operational amplifier A1 and the drain terminal of the PMOS transistor MP100 are both connected to the first end of the temperature resistor R1 in the temperature current generation unit. The second end of the temperature resistor R1 is connected to the collector terminal and the base terminal of the NPN transistor Q1, and the emitter terminal of the NPN transistor Q1 is grounded;

[0088] A positive temperature drift current is loaded into the current operation unit through the gate terminal of the PMOS transistor MP100.

[0089] Figure 2 An embodiment of the V-I conversion circuit is shown. Specifically, the operational amplifier A1 detects the collector voltage of the NPN transistor Q1 and compares the collector voltage of the NPN transistor Q1 with the reference voltage from the bandgap reference. When the voltage at the collector of the NPN transistor Q1 is lower than the reference voltage, the output of the operational amplifier A1 decreases. At this time, the voltage at the drain of the PMOS transistor MP100 increases, forming a negative feedback loop, and finally stabilizing the collector voltage of the NPN transistor Q1 at the reference voltage.

[0090] The principle of the temperature current generation unit generating a positive temperature drift current is explained below. Specifically:

[0091] When the temperature current generation unit uses the NPN transistor Q1, based on the V-I characteristics corresponding to the NPN transistor Q1, it can be known that:

[0092]

[0093] Wherein, I c is the current at the collector of the NPN transistor Q1, I0 is the reverse saturation current of the NPN transistor, k is the Boltzmann constant, T is the temperature, q is the unit charge amount, and V BE is the base-emitter voltage of the NPN transistor Q1.

[0094] Based on the V-I characteristic of the above NPN transistor Q1, when generating a positive temperature drift current, there is:

[0095]

[0096] Wherein, V T is the thermoelectric potential, VREF is the reference voltage, and R1 is the resistance value of the temperature resistor R1. It can be understood that the positive temperature drift current I zwp is the current I flowing through the collector of the NPN transistor Q1 c .

[0097] As can be seen from the above description, the V-I conversion circuit receives the reference voltage generated by the bandgap reference, which is not affected by process, power supply voltage, and external environment. Thereafter, the NPN transistor Q1 and the temperature resistor R1 generate a current that linearly changes with temperature under the working voltage, which can greatly reduce the influence of the output current on the process, power supply voltage, and external environment (except temperature), that is, a positive temperature drift current that effectively characterizes the chip temperature can be obtained.

[0098] In an embodiment of the present invention, it further includes a frequency compensation unit for loop frequency compensation, wherein,

[0099] the frequency compensation unit at least includes a Miller compensation capacitor C1. One end of the Miller compensation capacitor C1 is connected to the output end of the operational amplifier A1 and the gate terminal of the PMOS transistor MP100, and the other end of the Miller compensation capacitor C100 is connected to the drain terminal of the PMOS transistor MP100, the non-inverting input terminal of the operational amplifier A1, and the first end of the temperature resistor R1.

[0100] During specific implementation, in order to increase the stability of the V-I conversion circuit, it is also necessary to use the frequency compensation unit for frequency compensation. Figure 2 FIG. shows an embodiment of the frequency compensation unit. In the figure, the frequency compensation unit includes a Miller compensation capacitor C1, that is, frequency compensation can be achieved through the Miller compensation capacitor C1 to improve the stability of the V-I conversion circuit.

[0101] It can be understood that when the chip is working, the current curve of the chip changing linearly with temperature can be obtained through the V-I conversion circuit. However, in practice, due to the deviation of the chip manufacturing process, the current-temperature curves of the same type of chips will also be different. Therefore, it is necessary to calibrate the positive temperature drift current generated by the V-I conversion circuit. During specific implementation, the current operation unit performs temperature calibration on the positive temperature drift current to adjust the slope and intercept of the I-T curve generated by the V-I conversion circuit after temperature calibration, so as to reduce the process deviation and make the output temperature value of each chip consistent with the actual temperature value.

[0102] As Figure 1 can be seen, when performing temperature calibration using the current operation unit, the current operation unit also receives a reference current and a digital control code. Generally, the digital control code can be emitted by other components within the chip. The current operation unit can perform temperature calibration on the positive temperature drift current based on the digital control code and the reference current to generate a positive temperature drift calibration voltage corresponding to the current chip temperature after temperature calibration, where the current chip is the chip where the programmable temperature sensing circuit integration of the present invention is located.

[0103] In an embodiment of the present invention, the current operation unit includes a temperature calibration unit for performing temperature calibration on the positive temperature drift current and a current-voltage conversion unit adaptively connected to the temperature calibration unit, where

[0104] when performing temperature calibration on the positive temperature drift current, at least the reference current and the positive temperature drift current are configured by the digital control code to be linearly added to generate a positive temperature drift calibration current after linear addition;

[0105] The current-voltage conversion unit performs current-voltage conversion on the positive temperature drift calibration current to generate a positive temperature drift calibration voltage after current-voltage conversion.

[0106] Specifically, the current operation unit may include a temperature calibration unit and a current-voltage conversion unit. The temperature calibration unit can be used to perform temperature calibration on the positive temperature drift current. When performing temperature calibration on the positive temperature drift current, at least the reference current and the positive temperature drift current are configured by the digital control code to be linearly added to generate a positive temperature drift calibration current after linear addition. Thereafter, the current-voltage conversion unit can be used to perform current-voltage conversion, thereby generating a positive temperature drift calibration voltage.

[0107] It can be understood that the generated positive temperature drift calibration voltage can correspond to the on-chip temperature of the current chip, that is, it can accurately represent the on-chip temperature of the chip. Figure 1Among them, the positive temperature drift voltage is the positive temperature drift calibration voltage. The positive temperature drift calibration voltage is output to the digital circuit through the A / D conversion circuit to utilize the digital circuit for temperature control or display output. Specifically, the A / D conversion circuit can adopt the existing common form, and the processing of the positive temperature drift calibration voltage after A / D conversion by the digital circuit can be selected according to needs, which will not be elaborated here.

[0108] In an embodiment of the present invention, the temperature calibration unit includes a first group of current mirrors, a second group of current mirrors, a third group of current mirrors, and a fourth group of current mirrors.

[0109] The digital control code includes a first digital control signal and a second digital control signal, where

[0110] The first group of current mirrors, the second group of current mirrors, and the third group of current mirrors are adaptively connected to form a temperature calibration node;

[0111] The first group of current mirrors is adaptively connected to the V-I conversion circuit and receives the first digital control signal. The first group of current mirrors is configured by the first digital control signal to convert the received positive temperature drift current into a temperature-sensing reference current. Among them, the temperature-sensing reference current and the positive temperature drift current are in a first ratio, and the temperature coefficient of the temperature-sensing reference current is different from that of the positive temperature drift current;

[0112] The fourth group of current mirrors is adaptively connected to the bandgap reference to respectively transmit the reference current generated by the bandgap reference to the second group of current mirrors and the third group of current mirrors;

[0113] The second group of current mirrors receives the second digital control signal and converts the reference current into a zero-temperature-coefficient positive current based on the second digital control signal. Among them, the zero-temperature-coefficient positive current and the reference current are in a second ratio;

[0114] The third group of current mirrors receives the first digital control signal and converts the reference current into a zero-temperature-coefficient negative current based on the first digital control signal. Among them, the zero-temperature-coefficient negative current and the reference current are in a third ratio;

[0115] When calibrating the temperature of the positive temperature drift current, the temperature-sensing reference current and the zero-temperature-coefficient positive current are subjected to an addition operation, and the addition value obtained from the addition operation is subtracted from the zero-temperature-coefficient negative current. After that, the result value of the subtraction operation is configured as the positive temperature drift calibration current;

[0116] The temperature calibration unit transmits the positive temperature drift calibration current to the current-voltage conversion unit through the temperature calibration node.

[0117] In order to achieve temperature calibration for the positive temperature drift current, the temperature calibration unit may include a first group of current mirrors, a second group of current mirrors, a third group of current mirrors, and a fourth group of current mirrors. Among them, the first group of current mirrors is used to receive the positive temperature drift current and convert the positive temperature drift current into a temperature-sensing reference current under the first digital control signal. Specifically, the temperature-sensing reference current and the positive temperature drift current are in a first ratio. At the same time, the temperature coefficient of the temperature-sensing reference current is different from that of the positive temperature drift current. The first ratio is generally greater than 1, and the magnitude of the first ratio can be configured according to the first digital control signal. The following specifically describes the situation of generating the temperature-sensing reference current.

[0118] In an embodiment of the present invention, the first group of current mirrors includes a first group of first sub-current mirrors and a first group of second sub-current mirrors, where

[0119] The first group of first sub-current mirrors includes a first sub-current mirror first PMOS transistor group and a first sub-current mirror second PMOS transistor group. The number of PMOS transistors in the first sub-current mirror first PMOS transistor group is the same as the number of PMOS transistors in the first sub-current mirror second PMOS transistor group, and the number of PMOS transistors in the first sub-current mirror second PMOS transistor group is not less than the data bit width of the first digital control signal;

[0120] The PMOS transistors in the first sub-current mirror first PMOS transistor group are connected to the PMOS transistors in the first sub-current mirror second PMOS transistor group in a one-to-one correspondence. Among them, the source terminal of each PMOS transistor in the first sub-current mirror first PMOS transistor group is connected to the power supply VDD, and the drain terminal of each PMOS transistor in the first sub-current mirror first PMOS transistor group is connected to the source terminal of the corresponding PMOS transistor in the first sub-current mirror second PMOS transistor group.

[0121] The drain terminals of all PMOS transistors in the first sub-current mirror second PMOS transistor group are connected to the temperature calibration node, and the gate terminal of each PMOS transistor in the first sub-current mirror second PMOS transistor receives a digital control bit in the first digital control signal;

[0122] The first group of second sub-current mirrors includes a second sub-current mirror first PMOS transistor group and a second sub-current mirror second PMOS transistor group. The number of PMOS transistors in the second sub-current mirror first PMOS transistor group is the same as the number of PMOS transistors in the second sub-current mirror second PMOS transistor group;

[0123] The PMOS transistors in the first PMOS transistor group of the second sub-current mirror are connected in one-to-one correspondence with the PMOS transistors in the second PMOS transistor group of the second sub-current mirror. Among them, the source terminals of each PMOS transistor in the first PMOS transistor group of the second sub-current mirror are all connected to the power supply VDD, and the drain terminal of each PMOS transistor in the first PMOS transistor group of the second sub-current mirror is connected to the source terminal of the corresponding PMOS transistor in the second PMOS transistor group of the second sub-current mirror.

[0124] The drain terminals of all PMOS transistors in the second PMOS transistor group of the second sub-current mirror are all connected to the temperature calibration node, and all PMOS transistors in the second PMOS transistor group of the second sub-current mirror are configured to remain in the conducting state.

[0125] The gate terminals of all PMOS transistors in the first PMOS transistor group of the first sub-current mirror and the gate terminals of all PMOS transistors in the first PMOS transistor group of the second sub-current mirror are adaptively connected to the V-I conversion circuit to receive the positive temperature drift current generated by the V-I conversion circuit.

[0126] When converting the received positive temperature drift current into the temperature-sensing reference current, there is:

[0127] I_TC = (TC1 + m) * I1

[0128] Wherein, I_TC is the temperature-sensing reference current, TC1 is the number of digital control bits with a value of 0 in the first digital control signal, m is the number of PMOS transistors in the first PMOS transistor group of the second sub-current mirror, and I1 is the positive temperature drift current.

[0129] When calibrating the positive temperature drift current, the induced reference current flows into the temperature calibration node.

[0130] It should be noted that the temperature-sensing reference current with an adjustable temperature coefficient can be generated by using the first group of current mirrors. Figure 3 An embodiment of the first group of current mirrors is shown in the figure. In the figure, MP1<1:63> is the first PMOS transistor group of the first sub-current mirror, and MP2<1:63> is the second PMOS transistor group of the first sub-current mirror. At this time, the first PMOS transistor group and the second PMOS transistor group of the first sub-current mirror each include 63 PMOS transistors. Of course, the corresponding PMOS transistors in the first PMOS transistor group and the second PMOS transistor group of the first sub-current mirror can also be other numbers, which can be specifically selected according to needs and refer to the corresponding descriptions here.

[0131] It should be noted that when the data bit width of the first digital control signal is 2^N - 1, the number of bits of m should be selected to be near 2^(N - 1) to maximize the output current magnitude, the positive adjustment range, and the negative adjustment range at the same time. Specifically, for example, when N can take 6, at this time, m can be near 2^5, such as Figure 3In [the above], the bit width of the first digital control signal can be 63, and m can be taken as 30. It can be understood that when calibrating the temperature, the value of TC1 can be 1 to 63.

[0132] Figure 3 In [the above], MP3<1:30> is the first PMOS transistor group of the second sub-current mirror, and MP4<1:30> is the second PMOS transistor group of the second sub-current mirror. Thus, it can be known that the number of PMOS transistors in the first PMOS transistor group of the second sub-current mirror is less than the number of PMOS transistors in the first PMOS transistor group of the first sub-current mirror. During specific implementation, for the corresponding PMOS transistors in the first PMOS transistor group of the first sub-current mirror and the first PMOS transistor group of the second sub-current mirror, they should have the same parameters as the PMOS transistor MP100 in the V-I conversion circuit. At this time, completely identical positive temperature drift currents can be obtained through the first group of the first sub-current mirror and the first group of the second sub-current mirror respectively.

[0133] Figure 3 In [the above], MP4<1:30> is the second PMOS transistor group of the second sub-current mirror. The gate terminals of the PMOS transistors in the second PMOS transistor group of the second sub-current mirror are grounded, thereby configuring the PMOS transistors in the second PMOS transistor group of the second sub-current mirror to be in a conducting state.

[0134] Figure 3 In [the above], TC<1:63> is the first digital control signal. At this time, the data bit width of the first digital control signal is 63, and the data bit width of the first digital control signal is consistent with the number of PMOS transistors in the first PMOS transistor group of the first sub-current mirror. Thus, each digital control bit in the first digital control signal can be loaded onto the gate terminal of the PMOS transistor in the second PMOS transistor group of the first sub-current mirror. It can be understood that each digital control bit in the first digital control signal is "0" or "1". When the digital control bit is "0", the corresponding PMOS transistor can be controlled to be in a conducting state. When the digital control bit is "1", the corresponding PMOS transistor can be controlled to be in an off state. That is, one digital control bit can control the on-off state of the corresponding PMOS transistor.

[0135] It can be understood that the number of PMOS transistors in the second PMOS transistor group of the first sub-current mirror can also be greater than the data bit width of the first digital control signal. At this time, the gate terminals of some PMOS transistors will be in a suspended state, that is, there is no corresponding digital control bit. Preferably, the number of PMOS transistors in the second PMOS transistor group of the first sub-current mirror is configured to be consistent with the data bit width of the first digital control signal. At this time, one digital control bit is loaded onto the gate terminal of one PMOS transistor.

[0136] Figure 3In it, the drain terminals of all PMOS transistors in the second PMOS transistor group of the first sub-current mirror and the drain terminals of all PMOS transistors in the second PMOS transistor group of the second sub-current mirror are interconnected, that is, they are all connected to the temperature calibration node. Figure 3 In it, WDJD is the temperature calibration node.

[0137] It should be noted that when the number of PMOS transistors in the first PMOS transistor group of the second sub-current mirror is 30, then the number m of PMOS transistors in the first PMOS transistor group of the second sub-current mirror should be 30. When it is other numbers, the value of m can be determined. For a determined first digital control signal, the corresponding digital control bit can be determined, and then the value of the quantity TC1 can be determined. When the first digital control signal changes, the value of the quantity TC1 may be different, so that the corresponding temperature-sensitive reference current can be determined. Among them, (TC1 + m) is the first ratio.

[0138] In an embodiment of the present invention, the third group of current mirrors includes a first NMOS transistor group of the third current mirror and a second NMOS transistor group of the third current mirror, where

[0139] the number of NMOS transistors in the first NMOS transistor group of the third current mirror is consistent with the number of NMOS transistors in the second NMOS transistor group of the third current mirror, and the number of NMOS transistors in the first NMOS transistor group of the third current mirror is not less than the data bit width of the first digital control signal. One digital control bit of the first digital control signal is loaded to the gate terminal of one NMOS transistor in the first NMOS transistor group of the third current mirror;

[0140] the drain terminal of each NMOS transistor in the first NMOS transistor group of the third current mirror is connected to the temperature calibration node, and the source terminal of each NMOS transistor in the first NMOS transistor of the third current mirror is connected to the drain terminal of the corresponding NMOS transistor in the second NMOS transistor group of the third current mirror;

[0141] the source terminal of each NMOS transistor in the second NMOS transistor group of the third current mirror is grounded, and the gate terminal of each NMOS transistor in the second NMOS transistor group of the third current mirror is adaptively connected to the fourth group of current mirrors to receive the reference current loaded by the fourth group of current mirrors;

[0142] When the received reference current is converted into a zero temperature coefficient negative current, there is:

[0143] I_CA2 = CA2 * IREF

[0144] Among them, I_CA2 is the zero temperature coefficient negative current, CA2 is the number of digital control bits with a value of 1 in the first digital control signal, and IREF is the reference current;

[0145] When calibrating the positive temperature drift current for temperature, the zero temperature coefficient negative current flows out of the temperature calibration node.

[0146] Figure 3 In [description], MN1<1:63> is the first NMOS transistor group of the third current mirror. At this time, there are 63 NMOS transistors in the first NMOS transistor group of the third current mirror, and MN2<1:63> is the second NMOS transistor group of the third current mirror. Figure 3 In [description], the digital control bits in the first digital control signal are respectively loaded to the gate terminals of the corresponding NMOS transistors in the first NMOS transistor group of the third current mirror. At this time, when the digital control bit is "1", the corresponding NMOS transistor can be controlled to be in the on state, and when the digital control bit is "0", the corresponding NMOS transistor is in the off state, that is, one digital control bit can control the on-off state of the corresponding NMOS transistor.

[0147] From the above description, it can be seen that when the first digital control signal is determined, the corresponding quantity CA2 can be determined. At this time, CA2 is the third ratio. Based on the description of the third group of current mirrors, the zero temperature coefficient negative current flows from the first NMOS transistor group - the second NMOS transistor group of the third current mirror to the ground, that is, the zero temperature coefficient negative current forms a state of flowing out of the temperature calibration node.

[0148] It should be noted that CA2 is the number of digital control bits with a value of 1 in the first digital control signal, and TC1 is the number of digital control bits with a value of 1 in the first digital control signal. Therefore, CA2 and TC1 are complementary with respect to the first digital control signal, so that during temperature calibration, the base point of temperature calibration can be maintained at the positive temperature drift current, improving the controllability of temperature calibration.

[0149] In an embodiment of the present invention, the second group of current mirrors includes a first PMOS transistor group of the second current mirror and a second PMOS transistor group of the second current mirror, where

[0150] the number of PMOS transistors in the first PMOS transistor group of the second current mirror is the same as the number of PMOS transistors in the second PMOS transistor group of the second current mirror, and the number of PMOS transistors in the second PMOS transistor group of the second current mirror is not less than the data bit width of the second digital control signal. One digital control bit of the second digital control signal is loaded to the gate terminal of one PMOS transistor in the second PMOS transistor group of the second current mirror;

[0151] The PMOS transistors in the first PMOS transistor group of the second current mirror are connected in one-to-one correspondence with the PMOS transistors in the second PMOS transistor group of the second current mirror. Among them, the source terminal of each PMOS transistor in the first PMOS transistor group of the second current mirror is connected to the power supply VDD, and the drain terminal of each PMOS transistor in the first PMOS transistor group of the second current mirror is connected to the source terminal of the corresponding PMOS transistor in the second PMOS transistor group of the second current mirror.

[0152] The gate terminal of each PMOS transistor in the first PMOS transistor group of the second current mirror is adaptively connected to the fourth group of current mirrors to receive the reference current loaded by the fourth group of current mirrors.

[0153] The source terminal of each PMOS transistor in the second PMOS transistor group of the second current mirror is connected to the temperature calibration node.

[0154] When converting the received reference current into a zero-temperature-coefficient forward current, there is:

[0155] I_CA1 = CA1 * IREF

[0156] Among them, I_CA1 is the zero-temperature-coefficient forward current, CA1 is the number of digital control bits with a value of 0 in the second digital control signal, and IREF is the reference current.

[0157] When calibrating the positive temperature drift current, the zero-temperature-coefficient forward current flows into the temperature calibration node.

[0158] Figure 3 Among them, MP5<1:63> is the first PMOS transistor group of the second current mirror, and MP6<1:63> is the second PMOS transistor group of the second current mirror. At this time, the first PMOS transistor group of the second current mirror and the first PMOS transistor group of the second current mirror each include 63 PMOS transistors. Of course, the corresponding PMOS transistors in the first PMOS transistor group of the second current mirror and the second PMOS transistor group of the second current mirror can also be other numbers, which can be specifically selected according to needs and refer to the corresponding descriptions here.

[0159] Figure 3 Among them, CA<1:63> is the second digital control signal. At this time, the second digital control signal has 63 digital control bits. The situation of the second digital control signal and the digital control bits can refer to the corresponding description of the first digital control signal above, which will not be elaborated here.

[0160] It can be understood that when the second digital control signal is determined, the quantity CA1 can be determined. Based on CA1, the zero-temperature-coefficient forward current can be determined. At this time, CA1 is the second ratio. From Figure 3 It can be seen that the current flow direction of the zero-temperature-coefficient forward current is the direction of flowing into the temperature calibration node.

[0161] It should be understood that for the above-mentioned first group of current mirrors, second group of current mirrors, and third group of current mirrors, the temperature-sensing reference current, zero-temperature-coefficient positive current, and zero-temperature-coefficient negative current can be respectively generated through the first digital control signal and the second digital control signal. Thereafter, according to the directions of the temperature-sensing reference current, zero-temperature-coefficient positive current, zero-temperature-coefficient negative current, and the temperature calibration node, linear addition can be achieved, and a positive temperature drift calibration current can be obtained.

[0162] For each chip, common technical means in the technical field can be used to determine the current on-chip temperature of the chip. Thereafter, the first digital control signal and the second digital control signal can be configured, so that the corresponding positive temperature drift calibration current can be generated by using the first digital control signal and the second digital control signal. When the generated positive temperature drift calibration current corresponds exactly to the on-chip temperature of the chip, it can be regarded that the calibration is completed. At this time, the first digital control signal and the second digital control signal can be kept fixed to perform the above temperature calibration when the chip is working normally and generate the corresponding positive temperature drift calibration current. Thus, it can be seen that the generated positive temperature drift calibration current can correspond exactly to the current temperature of the chip, so as to achieve the purpose of calibrating the output voltage change caused by the process variation between different chips.

[0163] Generally, the first digital control signal and the second digital control signal can be stored in the registers inside the chip. When the working scenario of the chip changes or the measurement of the on-chip temperature of the chip is inaccurate, the first digital control signal and the second digital control signal can be adjusted again, that is, the temperature sensing circuit can be programmed again to improve the accuracy of the chip temperature measurement and the accuracy and adaptability of the measurement of the on-chip temperature of the chip.

[0164] In an embodiment of the present invention, the fourth group of current mirrors includes a fourth group of first sub-current mirrors, a low-voltage cascode circuit current mirror, a fourth group of second sub-current mirrors, and a fourth group of third sub-current mirrors, wherein,

[0165] The fourth group of first sub-current mirrors is connected to the bandgap reference to mirror the reference current generated by the bandgap reference to the low-voltage cascode current mirror.

[0166] The low-voltage cascode current mirror loads the reference current to the third group of current mirrors, and transmits it to the fourth group of third sub-current mirrors through the fourth group of second sub-current mirrors, and loads the reference current to the second group of current mirrors through the fourth group of third sub-current mirrors;

[0167] The low-voltage cascode current mirror includes a current mirror resistor, a cascode current mirror first NMOS transistor, and a cascode current mirror second NMOS transistor, wherein,

[0168] The first end of the current mirror resistor is connected to the gate terminals of the fourth group of first sub-current mirrors and the cascode current mirror first NMOS transistor.

[0169] The second terminal of the current mirror resistor is connected to the drain terminal of the first NMOS transistor of the cascode current mirror and the gate terminal of the second NMOS transistor of the cascode.

[0170] The source terminal of the first NMOS transistor of the cascode current mirror is connected to the drain terminal of the second NMOS transistor of the cascode, and the source terminal of the second NMOS transistor of the cascode is grounded.

[0171] The gate terminal of the second NMOS transistor of the cascode current mirror is adaptively connected to the third group of current mirrors and the fourth group of second sub-current mirrors, and the gate terminal of the first NMOS transistor of the cascode current mirror is adaptively connected to the fourth group of second sub-current mirrors.

[0172] Figure 3 An embodiment of the fourth group of current mirrors in Figure 3 Among them, PMOS transistor MP11 and PMOS transistor PM12 are current mirrors that generate a reference current in the bandgap reference. The reference current can be loaded into the current calibration unit through the current mirror formed by PMOS transistor MP11 and PMOS transistor MP12.

[0173] Figure 3 Among them, PMOS transistor MP9 and PMOS transistor MP10 form the first sub-current mirror of the fourth group. Among them, the source terminal of PMOS transistor MP9 is connected to the source terminal of PMOS transistor MP11 and the power supply VDD. The gate terminal of PMOS transistor MP9 is connected to the gate terminal of PMOS transistor MP11. The drain terminal of PMOS transistor MP9 is connected to the source terminal of PMOS transistor MP10. The gate terminal of PMOS transistor MP10 is connected to the gate terminal of PMOS transistor MP12. The drain terminal of PMOS transistor MP10 is connected to the first terminal of the current mirror resistor. Figure 3 Among them, resistor R3 is the current mirror resistor.

[0174] Figure 3 Among them, NMOS transistor MN5 is the first NMOS transistor of the cascode current mirror, NMOS transistor MN7 is the second NMOS transistor of the cascode current mirror, and the gate terminal of NMOS transistor MN7 is connected to the gate terminals of all NMOS transistors in NMOS transistor MN2<1:63>.

[0175] Figure 3 Among them, the fourth group of second sub-current mirrors includes NMOS transistor MN3 and NMOS transistor MN4. Among them, the gate terminal of NMOS transistor MN3 is connected to the gate terminal of NMOS transistor MN5 and the first terminal of the current mirror resistor. The source terminal of NMOS transistor MN3 is connected to the drain terminal of NMOS transistor MN4. The gate terminal of NMOS transistor MN4 is connected to the gate terminal of NMOS transistor MN7. The source terminal of NMOS transistor MN4 is grounded.

[0176] Figure 3Among them, the third sub-current mirror of the fourth group includes PMOS transistor MP7 and PMOS transistor MP8. Among them, the source terminal of PMOS transistor MP7 is connected to power supply VDD. The gate terminal of PMOS transistor MP7 is connected to the drain electrode of NMOS transistor MN3, the drain terminal of PMOS transistor MP8, and the gate terminals of all PMOS transistors in PMOS transistor MP5<1:63>. The drain terminal of PMOS transistor MP7 is connected to the source terminal of PMOS transistor MP8. The gate terminal of PMOS transistor MP8 is grounded, that is, PMOS transistor MP8 is configured to maintain a conducting state.

[0177] In specific implementation, the reference current is copied by the first current mirror of the fourth group, and then the copied reference current is output to the low-voltage cascode current mirror to generate a voltage at the gate of NMOS transistor MN7, thereby controlling the current of the third group of current mirrors, that is, loading the reference current onto the third group of current mirrors. At the same time, the second sub-current mirror of the fourth group copies the current from the low-voltage cascode current mirror, and then outputs it to the third sub-current mirror of the fourth group, and generates a voltage at the gate of PMOS transistor MP7, thereby controlling the current of the second group of current mirrors and loading the reference current onto the second group of current mirrors.

[0178] It should be noted that when a low-voltage cascode circuit current mirror is used in the fourth group of current mirrors, the reference current is copied to the third group of current mirrors through the low-voltage cascode circuit current mirror and transmitted to the third sub-current mirror of the fourth group through the second sub-current mirror of the fourth group, and can be loaded onto the second group of current mirrors, thereby increasing the variation range of the source-drain voltage of the current mirror, and thus improving the linearity of the current-temperature curve.

[0179] The above gives an embodiment of generating a positive temperature drift calibration current. From the above description, it can be seen that after generating the positive temperature drift calibration current, it is necessary to convert the positive temperature drift calibration current into a positive temperature drift calibration voltage through a current-voltage conversion unit. Figure 3 An embodiment of the current-voltage conversion unit is also shown in Figure 3 The manner and process of converting the positive temperature drift calibration current into a positive temperature drift calibration voltage by the current-voltage conversion unit will be explained below.

[0180] Figure 3 Among them, the current-voltage conversion unit includes PMOS transistor MP13 and PMOS transistor MP15. Among them, the source terminals of PMOS transistor MP13 and PMOS transistor MP15 are both connected to power supply VDD. The gate terminal of PMOS transistor MP13 is connected to the gate terminal of PMOS transistor MP15, the drain terminal of PMOS transistor MP13, and the source terminal of PMOS transistor MP14. The gate terminal of PMOS transistor MP14 is connected to the drain terminal of PMOS transistor MP14, the drain terminal of NMOS transistor MN10, and the gate terminal of PMOS transistor MP16.

[0181] The source terminal of PMOS transistor MP16 is connected to the drain terminal of PMOS transistor MP15. The source terminal of PMOS transistor MP16 is connected to the first terminal of the voltage conversion resistor. After the source terminal of PMOS transistor MP16 and the first terminal of the voltage conversion resistor are connected to each other, a voltage conversion output terminal can be formed. That is, the positive temperature drift calibration voltage can be output through the voltage conversion output terminal. The second terminal of the voltage conversion resistor is grounded. Figure 3 In Figure 3 , resistor R2 is the voltage conversion resistor.

[0182] The gate terminal of NMOS transistor MN10 is connected to the gate terminal of NMOS transistor MN8, the drain terminal of NMOS transistor MN8, and the temperature calibration node. The source terminal of NMOS transistor MN8 is connected to the drain terminal of NMOS transistor MN9, the gate terminal of NMOS transistor MN9, and the gate terminal of NMOS transistor MN11. The source terminals of NMOS transistor MN9 and NMOS transistor MN11 are both grounded. The drain terminal of NMOS transistor MN11 is connected to the source terminal of NMOS transistor MN10.

[0183] Specifically, NMOS transistors MN8, MN9, MN10, and MN11 can form a 1:1 current mirror to transmit the positive temperature drift calibration current into the current mirror formed by PMOS transistors MP13 and MP14, and then copy it to the current mirror formed by PMOS transistors MP15 and MP16. At this time, the positive temperature drift calibration current can generate a positive temperature drift calibration voltage through the voltage conversion resistor and output the positive temperature drift calibration voltage.

[0184] Of course, the current-voltage conversion unit can also adopt other forms, which can be specifically selected according to needs. It should be understood that when the bandgap reference, V-I conversion circuit, and current transportation unit adopt the above forms, they can be integrated into the chip through CMOS process, which can improve the convenience and reliability of integration into the chip.

[0185] When the programmable temperature sensing circuit of the present invention adopts the above form, it is less affected by the process during temperature sensing. The relationship between temperature sensing and the process (mainly referring to the process corner) will be specifically described below. Specifically:

[0186] Figure 3 In , VOUT is the output voltage of the current operation unit, that is, VOUT is the positive temperature drift calibration voltage generated by the current operation unit. When the current operation unit adopts the above circuit form, there is:

[0187] Considering the process corner deviation, there is:

[0188] VOUT = (I_OUT + ΔI) * (R2 + ΔR)

[0189] Among them, I_OUT is the current flowing into the current-voltage conversion unit, ΔR is the process deviation resistance of the output resistance at different process corners relative to the process deviation resistance at the TT (Typical) process corner, which is approximately 1.15K; ΔI is the process deviation current of the output current at the same process corner relative to TT.

[0190] It can be understood that if there is no process deviation in the voltage conversion resistance, at this time, ΔR should be 0, and the output voltage VOUT will increase proportionally with the change of the process deviation current ΔI. However, in fact, compared with the deviation of the output current, the deviation of the output voltage is relatively small. For example, at a temperature T = 60°C, the current difference between the SS process corner and the FF process corner is 30uA, the current at the TT process corner is 89.8uA, and the relative error of the output current is The output voltages of the SS process corner and the FF process corner only differ by 21.68mV, the output voltage at the TT process corner is 693.1mV, and the relative error of the output voltage is It can be seen from this that the reduction of the voltage deviation is mainly because the deviation direction of the process deviation resistance ΔR is just opposite to the deviation direction of the process deviation current ΔI, offsetting the influence caused by ΔI*R2.

[0191] The process deviation current ΔI is related to the deviation between the zero-temperature-drift current output by the bandgap reference and the positive-temperature-drift current deviation output by the V-I conversion circuit. For the positive-temperature-drift current output by the V-I conversion circuit, that is, the positive-temperature-drift current and the zero-temperature-drift current are both proportional to 1 / process deviation resistance, so that they can be offset by the process deviation of the output resistance. In addition, those skilled in the art know that the resistance of the SS (Slowest) process corner is relatively large, and the corresponding current under the SS process corner is relatively small; the resistance under the FF (Fastest) process corner is relatively small, and the current under the FF process corner is relatively large, still satisfying the above cancellation relationship.

[0192] Therefore, when the programmable temperature sensing circuit of the present invention adopts the above structure, it is less affected by the process and can almost completely cancel the output error caused by the process corner, that is, high-precision temperature sensing can be realized.

[0193] The present invention uses a bandgap reference to generate a zero-temperature-drift reference voltage and reference current. The negative feedback amplifier circuit in the V-I conversion circuit can stabilize the working voltage of the temperature current generation unit at the reference voltage. Thereafter, the temperature current generation unit can be used to generate a positive-temperature-drift current. The generated positive-temperature current is less affected by the process, power supply voltage, and external environment (except temperature), improving the accuracy and stability of generating the positive-temperature-drift current.

[0194] The positive temperature drift current can be temperature calibrated by the current operation unit. During temperature calibration, the reference current and the positive temperature drift current are configured by the digital control code for linear addition to regulate the V-I conversion circuit to generate the positive temperature drift current-temperature curve, further reducing the influence of process, power supply voltage, and external environment (except temperature).

[0195] The state of linearly adding the reference current and the positive temperature drift current is configured by the digital control code to adapt to the temperature calibration of different chips and the temperature calibration of the same chip under different working scenarios.

Claims

1. A programmable temperature sensing circuit suitable for on-chip temperature measurement, characterized in that: The programmable temperature sensing circuit comprises: Bandgap reference, used to generate reference voltage and reference current with zero temperature drift; A VI conversion circuit receives a reference voltage generated by a bandgap reference and converts the reference voltage into a positive temperature drift current that changes with temperature, so as to use the positive temperature drift current to characterize the temperature state of the chip where the VI conversion circuit is located; The current calculation unit receives the positive temperature drift current generated by the VI conversion circuit and the reference current generated by the bandgap reference, and performs temperature calibration on the positive temperature drift current based on the digital control code and the reference current, so as to generate a positive temperature drift calibration voltage corresponding to the current chip temperature after the temperature calibration.

2. The programmable temperature sensing circuit suitable for on-chip temperature measurement according to claim 1, characterized in that: The VI conversion circuit includes a negative feedback amplifier circuit and a temperature current generating unit adaptively connected to the negative feedback amplifier circuit, wherein: The negative feedback amplifier circuit receives a reference voltage generated by a bandgap reference and stabilizes the operating voltage of the temperature current generating unit at the reference voltage, so that the temperature current generating unit generates a positive temperature drift current that varies with temperature under a stable operating voltage.

3. The programmable temperature sensing circuit suitable for on-chip temperature measurement according to claim 2, characterized in that: The negative feedback amplifier circuit includes an operational amplifier A1 and a PMOS tube MP100 adapted to be connected to the operational amplifier A1, wherein: The inverting terminal of the operational amplifier A1 is connected to the reference voltage, the output terminal of the operational amplifier A1 is connected to the gate terminal of the PMOS tube MP100, and the source terminal of the PMOS tube MP100 is connected to the power supply VDD; The in-phase terminal of the operational amplifier A1 and the drain terminal of the PMOS tube MP100 are both connected to the first terminal of the temperature resistor R1 in the temperature current generating unit, the second terminal of the temperature resistor R1 is connected to the collector terminal of the NPN transistor Q1 and the base terminal of the NPN transistor Q1, and the emitter terminal of the NPN transistor Q1 is grounded; The positive temperature drift current is loaded to the current calculation unit through the gate terminal of the PMOS tube MP100.

4. The programmable temperature sensing circuit suitable for on-chip temperature measurement according to claim 3, characterized in that: It also includes a frequency compensation unit for loop frequency compensation, wherein: The frequency compensation unit at least includes a Miller compensation capacitor C1, one end of which is connected to the output end of the operational amplifier A1 and the gate end of the PMOS tube MP100, and the other end of the Miller compensation capacitor C100 is connected to the drain end of the PMOS tube MP100, the in-phase end of the operational amplifier A1 and the first end of the temperature resistor R1.

5. The programmable temperature sensing circuit suitable for on-chip temperature measurement according to any one of claims 1 to 4, characterized in that: The current calculation unit includes a temperature calibration unit for performing temperature calibration on the positive temperature drift current and a current-to-voltage conversion unit adaptively connected to the temperature calibration unit, wherein: When temperature calibration is performed on the positive temperature drift current, at least a reference current and a positive temperature drift current are configured to be linearly added using a digital control code to generate a positive temperature drift calibration current after the linear addition; The current-to-voltage conversion unit performs current-to-voltage conversion on the positive temperature drift calibration current to generate a positive temperature drift calibration voltage after the current-to-voltage conversion.

6. The programmable temperature sensing circuit suitable for on-chip temperature measurement according to claim 5, characterized in that: The temperature calibration unit includes a first group of current mirrors, a second group of current mirrors, a third group of current mirrors and a fourth group of current mirrors. The digital control code includes a first digital control signal and a second digital control signal, wherein: The first group of current mirrors, the second group of current mirrors, and the third group of current mirrors are adaptively connected to form a temperature calibration node; The first group of current mirrors is adaptively connected to the VI conversion circuit and receives a first digital control signal. The first group of current mirrors is configured by the first digital control signal to convert the received positive temperature drift current into a temperature-sensitive reference current, wherein the temperature-sensitive reference current is in a first ratio to the positive temperature drift current, and the temperature coefficient of the temperature-sensitive reference current is different from the temperature coefficient of the positive temperature drift current; The fourth group of current mirrors is adaptively connected to the bandgap reference to transmit the reference current generated by the bandgap reference to the second group of current mirrors and the third group of current mirrors respectively; The second set of current mirrors receives a second digital control signal and converts the reference current into a zero temperature coefficient forward current based on the second digital control signal, wherein the zero temperature coefficient forward current is in a second ratio to the reference current; The third set of current mirrors receives the first digital control signal, and converts the reference current into a zero temperature coefficient negative current based on the first digital control signal, wherein the zero temperature coefficient negative current is in a third ratio to the reference current; When the temperature calibration is performed on the positive temperature drift current, the temperature sensing reference current and the zero temperature coefficient positive current are accumulated, and the accumulated value obtained by the accumulation operation is subtracted from the zero temperature coefficient negative current, and then the subtraction operation result value is configured as the positive temperature drift calibration current; The temperature calibration unit transmits the positive temperature drift calibration current to the current-voltage conversion unit via the temperature calibration node.

7. The programmable temperature sensing circuit suitable for on-chip temperature measurement according to claim 6, characterized in that: The first group of current mirrors includes a first group of first sub-current mirrors and a first group of second sub-current mirrors, wherein: The first group of first sub-current mirrors includes a first sub-current mirror first PMOS tube group and a first sub-current mirror second PMOS tube group, the number of PMOS tubes in the first sub-current mirror first PMOS tube group is consistent with the number of PMOS tubes in the first sub-current mirror second PMOS tube group, and the number of PMOS tubes in the first sub-current mirror second PMOS tube group is not less than the data bit width of the first digital control signal; The PMOS tubes in the first PMOS tube group of the first sub-current mirror are connected to the PMOS tubes in the second PMOS tube group of the first sub-current mirror in a one-to-one correspondence, wherein the source terminal of each PMOS tube in the first PMOS tube group of the first sub-current mirror is connected to the power supply VDD, and the drain terminal of each PMOS tube in the first PMOS tube group of the first sub-current mirror is connected to the source terminal of the corresponding PMOS tube in the second PMOS tube group of the first sub-current mirror, The drain terminals of all PMOS tubes in the second PMOS tube group of the first sub-current mirror are connected to the temperature calibration node, and the gate terminal of each PMOS tube in the second PMOS tube of the first sub-current mirror receives a digital control bit in the first digital control signal; The first group of second sub-current mirrors includes a second sub-current mirror first PMOS tube group and a second sub-current mirror second PMOS tube group, and the number of PMOS tubes in the second sub-current mirror first PMOS tube group is consistent with the number of PMOS tubes in the second sub-current mirror second PMOS tube group; The PMOS tubes in the first PMOS tube group of the second sub-current mirror are connected to the PMOS tubes in the second PMOS tube group of the second sub-current mirror in a one-to-one correspondence, wherein the source terminal of each PMOS tube in the first PMOS tube group of the second sub-current mirror is connected to the power supply VDD, and the drain terminal of each PMOS tube in the first PMOS tube group of the second sub-current mirror is connected to the source terminal of the corresponding PMOS tube in the second PMOS tube group of the second sub-current mirror, The drain terminals of all PMOS tubes in the second PMOS tube group of the second sub-current mirror are connected to the temperature calibration node, and all PMOS tubes in the second PMOS tube group of the second sub-current mirror are configured to remain in a conducting state; The gate terminals of all PMOS tubes in the first PMOS tube group of the first sub-current mirror and the gate terminals of all PMOS tubes in the first PMOS tube group of the second sub-current mirror are adaptively connected to the VI conversion circuit to receive the positive temperature drift current generated by the VI conversion circuit; When the received positive temperature drift current is converted into a temperature sensing reference current, we have: I_TC=(TC1+m)*I1 Wherein, I_TC is the temperature-sensing reference current, TC1 is the number of digital control bits in the first digital control signal that are 0, m is the number of PMOS tubes in the first PMOS tube group of the second sub-current mirror, and I1 is the positive temperature drift current; When temperature calibration is performed for the positive drift current, the sense reference current flows into the temperature calibration node.

8. The programmable temperature sensing circuit suitable for on-chip temperature measurement according to claim 7, characterized in that: The third current mirror group includes a third current mirror first NMOS tube group and a third current mirror second NMOS tube group, wherein: The number of NMOS tubes in the first NMOS tube group of the third current mirror is consistent with the number of NMOS tubes in the second NMOS tube group of the third current mirror, and the number of NMOS tubes in the first NMOS tube group of the third current mirror is not less than the data bit width of the first digital control signal, and one digital control bit of the first digital control signal is loaded to the gate terminal of one NMOS tube in the first NMOS tube group of the third current mirror; The drain terminal of each NMOS tube in the first NMOS tube group of the third current mirror is connected to the temperature calibration node, and the source terminal of each NMOS tube in the first NMOS tube of the third current mirror is connected to the drain terminal of the corresponding NMOS tube in the second NMOS tube group of the third current mirror; The source terminal of each NMOS tube in the second NMOS tube group of the third current mirror is grounded, and the gate terminal of each NMOS tube in the second NMOS tube group of the third current mirror is adaptively connected to the fourth current mirror group to receive the reference current loaded by the fourth current mirror group; Convert the received reference current into a negative current with zero temperature coefficient: I_CA2=CA2*IREF Wherein, I_CA2 is a zero temperature coefficient negative current, CA2 is the number of digital control bits that are 1 in the first digital control signal, and IREF is a reference current; When temperature calibration is performed on a positive drift current, a negative current with a zero temperature coefficient flows out of the temperature calibration node.

9. The programmable temperature sensing circuit suitable for on-chip temperature measurement according to claim 6, characterized in that: The second current mirror group includes a second current mirror first PMOS tube group and a second current mirror second PMOS tube group, wherein, The number of PMOS tubes in the first PMOS tube group of the second current mirror is consistent with the number of PMOS tubes in the second PMOS tube group of the second current mirror, and the number of PMOS tubes in the second PMOS tube group of the second current mirror is not less than the data bit width of the second digital control signal, and one digital control bit of the second digital control signal is loaded to the gate terminal of a PMOS tube in the second PMOS tube group of the second current mirror; The PMOS tubes in the first PMOS tube group of the second current mirror are connected to the PMOS tubes in the second PMOS tube group of the second current mirror in a one-to-one correspondence, wherein the source terminal of each PMOS tube in the first PMOS tube group of the second current mirror is connected to the power supply VDD, and the drain terminal of each PMOS tube in the first PMOS tube group of the second current mirror is connected to the source terminal of the corresponding PMOS tube in the second PMOS tube group of the second current mirror, The gate terminal of each PMOS tube in the first PMOS tube group of the second current mirror is adaptively connected to the fourth current mirror group to receive the reference current loaded by the fourth current mirror group; The source terminal of each PMOS tube in the second PMOS tube group of the second current mirror is connected to the temperature calibration node; When the received reference current is converted into a zero temperature coefficient forward current, we have: I_CA1=CA1*IREF Wherein, I_CA1 is the zero temperature coefficient forward current, CA1 is the number of digital control bits in the second digital control signal that are 0, and IREF is the reference current; When temperature calibration is performed on the positive drift current, a zero temperature coefficient forward current flows into the temperature calibration node.

10. The programmable temperature sensing circuit suitable for on-chip temperature measurement according to claim 6, characterized in that: The fourth group of current mirrors includes a fourth group of first sub-current mirrors, a low voltage cascode circuit current mirror, a fourth group of second sub-current mirrors and a fourth group of third sub-current mirrors, wherein: The fourth group of first sub-current mirrors is connected to the bandgap reference to mirror the reference current generated by the bandgap reference to the low-voltage common-source common-gate current mirror. The low voltage common source and common gate current mirror loads the reference current to the third group of current mirrors, transmits the reference current to the fourth group of third sub-current mirrors via the fourth group of second sub-current mirrors, and loads the reference current to the second group of current mirrors via the fourth group of third sub-current mirrors; The low voltage cascode current mirror comprises a current mirror resistor, a first NMOS transistor of the cascode current mirror and a second NMOS transistor of the cascode current mirror, wherein: The first end of the current mirror resistor is connected to the gate end of the first NMOS tube of the fourth group of first sub-current mirrors and the common-source common-gate current mirror. The second end of the current mirror resistor is connected to the drain end of the first NMOS transistor of the cascode current mirror and the gate end of the second NMOS transistor of the cascode current mirror. The source terminal of the first NMOS tube of the cascode current mirror is connected to the drain terminal of the second NMOS tube of the cascode current mirror, and the source terminal of the second NMOS tube of the cascode current mirror is grounded; The gate terminal of the second NMOS tube of the cascode current mirror is adaptively connected to the third group of current mirrors and the fourth group of second sub-current mirrors, and the gate terminal of the first NMOS tube of the cascode current mirror is adaptively connected to the fourth group of second sub-current mirrors.

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