Current-based built-in self-test of circuit components arranged in various configurations

Abstract

The invention relates to current-based built-in self-testing of circuit components arranged in various configurations. A self-test circuit may send a first test vector to a test block of a plurality of test blocks in the self-test circuit. The first test vector may correspond to a first configuration of a set of components in the test block. The self-test circuit may measure a first current drawn by the test block when the set of components is in the first configuration. The self-test circuitry may also send a second test vector to the test block, the second test vector corresponding to a second configuration of the set of components. The self-test circuit may measure a second current drawn by the test block when the set of components is in the second configuration. Based on a comparison between the first current and the second current, the self-test circuit may detect a defect in the test block.

Description

Technical Field

[0001] This specification relates to methods and systems for built-in self-test and / or support for efficient production testing of semiconductor products. Background Art

[0002] Various types of analog and digital circuits are produced by intricate semiconductor manufacturing processes. In some examples, these processes result in circuits having a very large number of very small electronic components (such as transistors, resistors, capacitors, etc.). Testing to ensure that such a large number of complex components included in these complex circuits function properly can present various challenges, especially on production lines where large quantities of products are being manufactured and thorough testing is required. External test equipment in a manufacturing facility can be used to provide input stimuli and analyze the outputs generated based on the input stimuli for each individual circuit (e.g., each die on a wafer, each chip, etc.). However, such equipment may tend to be relatively large, expensive, and slow when performing a full set of tests on each circuit produced. As a result, the testing process can significantly increase the cost, complexity, and / or time of manufacturing, and may make it difficult to meet the quantity and / or quality (e.g., test coverage) goals of products manufactured and tested in these ways. Summary of the Invention

[0003] Described herein is current-based built-in self-test for circuit components arranged in various configurations. In one general aspect, a method for current-based built-in self-test of circuit components arranged in various configurations can include the following operations. First, a first test vector can be sent to one of a plurality of test blocks in a self-test circuit, the first test vector corresponding to a first configuration of a set of components in the test block. Next, when the set of components is in the first configuration, a first current drawn by the test block can be measured. Then, the test block can be sent a second test vector, the second test vector corresponding to a second configuration of the set of components, the second configuration being different from the first configuration. When the set of components is in the second configuration, a second current drawn by the test block can be measured. Finally, a defect in the test block can be detected based on a comparison between the first current and the second current.

[0004] In some embodiments of the method, various additional elements and / or features can be employed. As an example, the method can further include determining a first setting of a set of switches within the test block based on the first test vector, the set of switches being configured to produce the first configuration of the set of components when the first setting is applied; and determining a second setting of the set of switches based on the second test vector, the set of switches being configured to produce the second configuration of the set of components when the second setting is applied.

[0005] As another example, the test block can include an enable input and can be configured to allow the set of components in the test block to be placed in a new configuration when the enable input is valid. When the enable input is invalid, the test block can be configured to not allow the set of components in the test block to be placed in the new configuration (and to change the set of components to be placed in a configuration associated with normal operation of the test block).

[0006] As another example, the method can further include sending a third test vector to an additional test block among the plurality of test blocks, the third test vector corresponding to a particular configuration of a set of additional components in the additional test block; and measuring a third current drawn by the additional test block when the set of additional components is in the particular configuration. In this example, detecting a defect in the test block can also be based on a comparison between the first current and the third current.

[0007] As another example, the method can further include sending the first test vector to an additional test block included in an additional self-test circuit and corresponding to the test block, the additional self-test circuit being fabricated on the same wafer as the self-test circuit; and measuring a third current drawn by the additional test block when a set of additional components in the additional test block is in the first configuration. In this example, detecting a defect in the test block can also be based on a comparison between the first current and the third current.

[0008] As another example, the method can further include using an analog-to-digital converter circuit to convert the first current to a first value and the second current to a second value; and storing the first value and the second value in a memory. In this example, then, the comparison between the first current and the second current can be performed by comparing the first value and the second value stored in the memory. Also in this example, comparing the first value and the second value can include determining a ratio of the first value to the second value; and detecting a defect in the test block can include determining that the ratio falls outside a predetermined range. Also in this example, comparing the first value and the second value can include determining a difference between the first value and the second value; and detecting a defect in the test block can include determining that the difference falls outside a predetermined range.

[0009] As another example, the method can include sending a third test vector to an additional test block among the plurality of test blocks, the third test vector corresponding to a particular configuration of a set of additional components in the additional test block; measuring a third current drawn by the additional test block when the set of additional components is in the particular configuration; and detecting a defect in the additional test block based on the third current without comparison with another current. In this example, detecting a defect in the additional test block can include determining that the third current indicates a short circuit condition or an open condition in the additional test block.

[0010] As another example, the set of components can include resistor components implemented as a first resistor and a second resistor, the first resistor and the second resistor being configured to be in series during operation of the test block and on separate current paths of the first configuration and the second configuration. In this example, the first current drawn by the test block can be associated with a first measurement value of the first resistor, the second current drawn by the test block can be associated with a second measurement value of the second resistor, and detecting a defect in the test block can be performed based on a comparison indicating that the difference between the first measurement value and the second measurement value is greater than a predetermined threshold.

[0011] As another example, the set of components can include a dual-input component that includes a first input and a second input. In this example, the first configuration can connect the first input and the second input to a supply voltage, the second configuration can connect the first input to the supply voltage and ground the second input, a third configuration corresponding to a third test vector on a test vector bus can ground the first input and connect the second input to the supply voltage, and a fourth configuration corresponding to a fourth test vector on the test vector bus can ground the first input and the second input. Then, detecting a defect in the test block can also be performed based on one or more comparisons involving a third current drawn by the test block when the set of components is in the third configuration and a fourth current drawn by the test block when the set of components is in the fourth configuration.

[0012] As another example, detecting a defect in the test block can be performed by a test controller integrated into the self-test circuit. Additionally or alternatively, detecting a defect in the test block can be performed by a test controller integrated into a test device separate from the self-test circuit.

[0013] In another general aspect, a self-test circuit can include a plurality of test blocks, a current measurement circuit, and a test controller electrically connected to the plurality of test blocks and the current measurement circuit. The plurality of test blocks can include a test block configured to receive a first test vector and a second test vector. The first test vector can correspond to a first configuration of a set of components in the test block, and the second test vector can correspond to a second configuration of the set of components. The current measurement circuit can be configured to measure a first current drawn by the test block when the set of components is in the first configuration. The current measurement circuit can also be configured to measure a second current drawn by the test block when the set of components is in the second configuration. The test controller can be configured to send the first test vector and the second test vector to the test block and detect a defect in the test block based on a comparison between the first current and the second current.

[0014] In some embodiments of the self-test circuit, various additional components and / or features may be employed. As an example, the self-test circuit may further include a set of switches within the test block. The set of switches may be configured to produce a first configuration of the set of components when a first setting of the set of switches is applied, the first setting being determined based on the first test vector; and to produce a second configuration of the set of components when a second setting of the set of switches is applied, the second setting being determined based on the second test vector.

[0015] As another example, the self-test circuit may include an enable input to the test block. In this example, the test block may be configured to allow the set of components in the test block to be placed in a new configuration when the enable input is active. Then, when the enable input is inactive, the test block may be configured to not allow the set of components in the test block to be placed in the new configuration (and to change the set of components to be placed in a configuration associated with normal operation of the test block).

[0016] As another example, the self-test circuit may further include an analog-to-digital converter circuit configured to convert the first current to a first value and the second current to a second value; and a memory configured to store the first value and the second value. In this example, the comparison between the first current and the second current may be performed by comparing the first value and the second value stored in the memory.

[0017] In another general aspect, a non-transitory computer-readable medium stores instructions that, when executed, cause a test controller associated with the self-test circuit to perform a process. The process may include sending a first test vector corresponding to a first configuration of a set of components in a test block to one of a plurality of test blocks in the self-test circuit. The process may further include sending a second test vector corresponding to a second configuration of the set of components, the second configuration being different from the first configuration, to the test block. The method may further include detecting a defect in the test block based on a comparison between the first current and the second current, wherein the first current is drawn by the test block when the set of components is in the first configuration, and wherein the second current is drawn by the test block when the set of components is in the second configuration.

[0018] In some embodiments of the non-transitory computer-readable medium, various additional elements and / or features may be employed. As an example, the process may further include determining a first setting of a set of switches within the test block based on the first test vector, the set of switches being configured to produce the first configuration of the set of components when the first setting is applied; and determining a second setting of the set of switches based on the second test vector, the set of switches being configured to produce the second configuration of the set of components when the second setting is applied.

[0019] Details of these and other embodiments are set forth in the accompanying drawings and the following description. Other features will be apparent from the following description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figures 1A to 1B Illustrative embodiments of a self-test circuit configured for current-based built-in self-test in accordance with the principles described herein are shown.

[0021] Figures 2 to 3 Illustrative methods for performing current-based built-in self-test on circuit components arranged in various configurations in accordance with the principles described herein are shown.

[0022] Figure 4 An illustrative current measurement circuit in accordance with the principles described herein is shown.

[0023] Figure 5 Illustrative current comparisons that can be performed to detect defects in a test block in accordance with the principles described herein are shown.

[0024] Figure 6 Multiple illustrative test blocks in accordance with the principles described herein are shown, each test block including a corresponding multiple sets of components that can be arranged in various configurations.

[0025] Figures 7A to 7F Aspects of how an illustrative set of switches within a test block can be configured with different settings to produce various configurations of a set of components within the test block in accordance with the principles described herein are shown.

[0026] Figures 8A to 8H An extended example of how certain components within an illustrative test block can be arranged in various configurations and tested using the current-based built-in self-test principles described herein is shown. DETAILED DESCRIPTION

[0027] This document describes current-based built-in self-test for circuit components arranged in various configurations. As mentioned above, various challenges are associated with testing complex circuits produced using modern semiconductor manufacturing processes. These challenges can be particularly significant for testing the analog blocks of a circuit (since digital logic circuits can be more efficiently tested using scan chains, automatically generated test patterns, etc.) and for testing manufacturer defects in the analog blocks (as opposed to performing parametric measurements of the blocks and / or other types of tests). As will be described herein, these challenges and others can be addressed efficiently and effectively by methods and systems according to the principles described herein for current-based built-in self-test of analog circuit components arranged in various configurations.

[0028] During the manufacturing process, multiple instances of a particular circuit can be produced on a single semiconductor wafer. These individual circuits can be referred to as dies, and when separated and packaged (and possibly combined with other circuits within a unified package), these packaged dies can be referred to as chips. The electronic chips themselves can be sold as end products, or can be included on a circuit board along with other discrete components (other chips, passive electronic components, power supplies, etc.), which circuit board is embedded within an electrical or electronic device that is sold as an end product itself. In any case, a single wafer can include a large number of individual circuits (dies) that need to be thoroughly tested, such that conventional test techniques involving external test equipment may be inadequate or suboptimal for testing all of the circuits on all of the wafers that can be produced by a given manufacturing facility. For example, while external test equipment can be configured to generate stimuli for each individual circuit and to measure and analyze the outputs in response to that stimulus for various tests, this test method can be inconvenient and inefficient, may take an inordinate amount of time to ensure proper test coverage, may be expensive in terms of the necessary test equipment and the floor space it consumes in a manufacturing site, and so on.

[0029] In response to the challenges described above, Built-In Self-Test (BIST) techniques have been developed. The idea behind BIST is that certain aspects of the test equipment that would otherwise be implemented external to the circuit under test can be instead integrated into the circuit itself, such that built-in circuitry on the die itself can be used to generate, measure, and analyze at least some test stimuli rather than using external test equipment. Conventional BIST techniques can be used to quickly and efficiently ensure that a circuit performs as expected when receiving typical input stimuli. However, these techniques generally do not provide thorough defect testing coverage of individual components within the circuit, since each component is only tested to the extent that it operates as part of the circuit in its connected state. Thus, especially for circuits that will be used in high-stakes situations where reliability is critical (e.g., for automotive products, etc.), it will be necessary to test each individual component within the circuit and to do so with a similar efficiency (e.g., low cost, short test time, etc.) as provided by conventional BIST methods.

[0030] To that end, this document describes current-based built-in self-test for efficiently testing circuit components arranged in various configurations. Different from (or in addition to) stimulating portions of the circuit and analyzing its outputs in its normal operating configuration, as a conventional BIST method might do, the methods and systems described herein perform current-based BIST on individual components (especially analog components) and on groups of components in configurations other than the configuration in which the components are arranged during normal operation of the circuit. More specifically, as will be described and illustrated in more detail below, a set of components within a particular test block (one of a plurality of test blocks included in a given self-test circuit) can be arranged and rearranged in a variety of different configurations, with the aim of exposing potential manufacturing defects in the various components (if such defects exist). For each different configuration, the current drawn by the test block can be measured and stored. Then, when these measured currents do not align as expected, a defect can be detected. For example, two configurations can be established such that if no defects are present, similar currents are expected to be drawn (e.g., as an example, the same resistor on a parallel branch of the test block can be tested in both configurations). If the measured currents differ too much from each other, comparing the currents drawn by the test block in the two configurations can indicate the presence of a defect.

[0031] Although designing each test block to be flexibly reconfigurable to support various configurations associated with various different tests may require some additional design effort on the front end, the total cost added to the circuit (e.g., switches and other circuitry added to make the test block reconfigurable) is minimal and can generally improve test efficiency and BIST coverage, which can be achieved by using these techniques. Specifically, once each self-test circuit is designed and fabricated, the on-die built-in test circuitry can be used to primarily or exclusively perform testing of the circuit with less or no reliance on external test equipment. Even when the test time and associated test costs are significantly reduced, this can achieve more thorough test coverage. Thus, the methods and systems for current-based built-in self-test described herein can produce various benefits, including at least: high defect coverage, short test times, reduced measurement complexity (reducing or eliminating measurements and analysis of current consumption directly on the chip and less reliant on external equipment, reducing the need for one observation point per test block, etc.), high reliability with both high-impedance and low-impedance nodes, reduced or eliminated need for dynamic part average testing (DPAT) since ratios between different measurements can be used, reduced number of desired excitation signals (e.g., using only a few digital signals, serial configuration of a possible test shift register, etc.), high potential for test parallelism due to the reduction or elimination of the reliance on specialized automated test equipment, unified test methods for various types of test blocks (e.g., different types of analog blocks with different types and arrangements of electrical components), etc.

[0032] Various embodiments will now be described in more detail with reference to the accompanying drawings. It should be understood that the specific embodiments described below are provided as non-limiting examples and can be applied in various situations. Additionally, it should be understood that other embodiments not explicitly described herein may also fall within the scope of the claims set forth below. Current-based built-in self-test for circuit components arranged in various configurations can produce any or all of the technical benefits mentioned above, as well as various additional technical benefits that will be described and / or made apparent below.

[0033] Figure 1AIllustrative embodiment 100-A of a self-test circuit 102 configured for current-based built-in self-test in accordance with the principles described herein is shown. The self-test circuit 102 may represent any unit of an electronic circuit that may serve a particular embodiment. For example, the self-test circuit 102 may correspond to a single die on a wafer, which is fabricated to include multiple like or identical dies. Thus, the self-test circuit 102 may be considered an electronic chip configured to perform various analog and / or digital functions (although some chip elements such as those related to packaged dies are not shown). In other examples, the self-test circuit 102 may correspond to a portion of a circuit on a die, a circuit of more than one die, or some other unit of an electronic circuit that may serve a particular embodiment. In some examples, the self-test circuit 102 may be implemented by a relatively simple circuit having only a few analog or digital blocks configured to perform relatively straightforward functions. In other examples, the self-test circuit 102 may be implemented by an extremely advanced or complex circuit having a large number of analog and / or digital blocks configured to perform various simple and / or complex functions.

[0034] In accordance with the principles described herein, the self-test circuit 102 may be configured to reconfigure test blocks (e.g., analog blocks) into a plurality of non-functional test modes in which an expected current consumption has been defined, or in which at least an expected ratio or difference of current consumption with respect to other test modes has been defined. For example, a pre-specified test plan for a particular self-test circuit may lay out the various tests to be performed (e.g., including test vectors to be used for each test block) and the various current ratios and / or differences between the tests to be analyzed in order to detect potential defects. The reconfiguration of these test blocks may be performed in such a way that potential defects will manifest themselves in the variation of the measured current consumption and / or in the variation of the comparison between different measured current consumptions. Based on these principles, current-based BIST techniques may be used to re-arrange circuit components into various configurations and sequentially examine all internal structures (e.g., circuit components, groups of components, etc.) as part of a BIST program.

[0035] To enable current-based BIST to take effect, an embodiment 100-A of the self-test circuit 102 is shown to include a plurality of test blocks 104 individually labeled as test blocks 104-1, 104-2, and 104-N. These test blocks 104 represent simpler circuit units with fewer functions than the self-test circuit 102 as a whole, but it should be understood that each test block 104 itself may include a set of components (e.g., analog and / or digital electronic components such as resistors, capacitors, transistors, operational amplifiers, combinational logic gates, registers, etc.) configured to operate together to perform a certain function. Specific examples of the test blocks 104 will be described and illustrated in detail below. The ellipsis before the test block 104-N is shown to indicate that any suitable number (N) of test blocks may be included in a particular self-test circuit (e.g., included on a particular die for a particular chip). For example, depending on the complexity, purpose, and design of the self-test circuit 102, some embodiments may include dozens, hundreds, or thousands of test blocks.

[0036] Along with the test blocks 104, an embodiment 100-A of the self-test circuit 102 is also shown to include a test vector bus 106 that electrically connects the plurality of test blocks 104, as well as a current measurement circuit 108 and a test controller 110. Each of these elements will be described and illustrated in more detail below.

[0037] Figure 1A It is shown that the current measurement circuit 108 can measure the current drawn or consumed by the test blocks 104 from the power supply 112, since each test block is powered by a voltage rail 114 sourced from the power supply 112 and can be monitored by the current measurement circuit 108 (e.g., to detect how much current any test block that is actively consuming current is drawing from the voltage rail 114). Figure 1A It is also shown that the test controller 110 is communicatively coupled to the current measurement circuit 108 via a communication interface 116 and communicatively coupled to the memory 118 via a communication interface 120.

[0038] As shown in the dashed box representing the connection to the memory 118 within the self-test circuit 102, the memory 118 can be used to store various types of data for various purposes related to current-based BIST. For example, as shown, the memory 118 can implement a non-transitory computer-readable medium storing a set of instructions 122 that, when executed, cause the test controller 110 to perform a process 124 that will be described in more detail below. More generally, the instructions 122 can be based on a test plan for the self-test circuit, which can incorporate various measurements, comparisons, and other test-related information to ensure proper test coverage for the self-test circuit. The memory 118 can also be used to store any number of current measurements 126 that have been made, test results 128 that have been determined (e.g., based on the current measurements 126 themselves or based on comparisons of different current measurements 126, etc.), and / or any other suitable data that can serve a particular implementation. The communication interface 120 between the test controller 110 and the memory 118 is understood to represent the movement of data between the test controller 110 and the memory 118. For example, the communication interface 120 can be used to load the instructions 122 of the process 124, store the current measurements 126 that have been measured by the current measurement circuit 108, load the current measurements 126 for analysis by the test controller 110, store the test results 128 that have been determined, etc.

[0039] Similar to the communication interface 120, the communication interface 116 between the test controller 110 and the current measurement circuit 108 can act as an interface for data transfer between these components. The test controller 110 can use the communication interface 116 to trigger the current measurement circuit 108 to make certain current measurements at certain times (e.g., when certain test vectors are driven by the test controller 110 onto the test vector bus 106, when certain test blocks are valid in a particular configuration to draw current from the voltage rail 114, etc.). The test controller 110 can also use the communication interface 116 to receive current measurements from the current measurement circuit 108, and then the test controller 110 can use those current measurements to perform defect analysis for built-in self-test (e.g., possibly after storing and loading the current measurements from the memory 118).

[0040] In operation, the test controller 110 can use the test vector bus 106 to send a first test vector and a second test vector to all the test blocks 104. However, only one specific test block among the multiple test blocks 104-1 can be valid at a time (e.g., implemented using an enable line that is described in more detail below and Figure 1A not shown). For example, when sending the first test vector and the second test vector, the test block 104-1 can be enabled as the block under test during one phase of the test. In this case, the first test vector can be associated with (e.g.) a set of components within the test block 104-1 (e.g.,Figure 1A corresponds to the first configuration of the electronic components (not explicitly shown in the figure), and the second test vector can correspond to the second configuration of a set of components in the test block 104-1 (e.g., a configuration different from the first configuration).

[0041] Although in this example (and other examples described herein) the test controller 110 is shown as sending these test vectors via the test vector bus 106, it should be understood that a shared test vector bus such as the test vector bus 106 and the corresponding enable line is not the only way for the test controller to transfer test vectors to multiple test blocks in a given self-test circuit. For example, another way to direct the test block components of different test blocks to the desired test configuration (e.g., especially for a self-test circuit with a relatively small number of test blocks) can be to have a certain number of non-shared test vector lines connecting the test controller 110 and each test block 104. In this type of configuration, an enable line would not be needed because a particular value (e.g., all lines at "0" or low) can indicate that the test block will be in the configuration corresponding to normal operation (i.e., not enabled for testing) and other values (e.g., non-zero test vectors) can indicate that the test block will be in a particular test configuration, such as the first configuration or the second configuration described above (i.e., enabled for testing). In these types of embodiments, it should be understood that the number of test vector lines from the test controller to each test block does not need to be the same (although in some embodiments, this may be the case). For example, if the first test block has a small number of desired test configurations, the number of test vector lines going to that test block may be less than the number of test vector lines for a test block with a larger number of desired test configurations.

[0042] Once the first test vector has been sent to test block 104-1 and the components of test block 104-1 have been placed in the first configuration, current measurement circuit 108 can be configured to measure a first current drawn by test block 104-1 when the set of components is in the first configuration (e.g., and possibly when the first test vector is on test vector bus 106). Specifically, as shown, current 130-1 represents the current drawn by test block 104-1 from voltage rail 114 (i.e., the current consumed from power supply 112), and other currents 130 are similarly shown for the other test blocks (i.e., current 130-2 drawn by test block 104-2, current 130-N drawn by test block 104-N, etc.). It should be understood that since those other test blocks are not enabled in this example (since for this particular example, test block 104-1 is the block under test), these other currents 130-2 and 130-N will be zero and all currents measured by current measurement circuit 108 will be associated with the current 130-1 drawn by test block 104-1 (e.g., the current drawn by the components in test block 104-1 in the first configuration for this first measurement). At a subsequent time, when the set of components in test block 104-1 is in the second configuration (e.g., and possibly when the second test vector is on test vector bus 106), current measurement circuit 108 can then measure a second current drawn by test block 104-1. In this example, current measurement circuit 108 can thus measure current 130-1 again, but a different test vector has been transmitted for this second measurement (e.g., via test vector bus 106).

[0043] Test controller 110 is shown as being electrically connected to both test vector bus 106 (e.g., to allow test controller 110 to send appropriate test vectors on the bus at the timing set forth by the test plan built into instruction 122) and current measurement circuit 108 (e.g., to allow test controller 110 to receive measurements, direct measurements to be made, or measurements to be converted to digital values, etc.). As will be described in more detail below, test controller 110 can be configured to detect one or more defects in test block 104 based on a comparison between the currents that have been measured. For example, test controller 110 can detect a defect in test block 104-1 based on a comparison between the first current and the second current as described above.

[0044] The test controller 110 may perform any suitable operations to implement current-based built-in self-test in accordance with the principles described herein. For example, in one embodiment, the instructions 122 for process 124 may cause the test controller 110 to: 1) send a first test vector corresponding to a first configuration of a set of components in the test block 104-1 of the plurality of test blocks 104 (e.g., on the test vector bus 106 or via another suitable electrical connection such as the non-shared test vector lines described above); 2) send a second test vector corresponding to a second configuration of the set of components (wherein the second configuration is different from the first configuration); and 3) detect a defect in the test block 104-1 based on a comparison between a first current and a second current, wherein the first current is drawn by the test block 104-1 when the set of components is in the first configuration (e.g., when the first test vector is on the test vector bus 106), and wherein the second current is drawn by the test block 104-1 when the set of components is in the second configuration (e.g., when the second test vector is on the test vector bus 106).

[0045] As will be described and illustrated in more detail below, the self-test circuit 102 may use Figure 1A additional elements not explicitly shown therein to perform the process 124 and similar methods and processes described herein. For example, certain embodiments of the self-test circuit 102 may include a set of switches within the test block 104-1 (e.g., as well as other corresponding sets of switches within the other test blocks 104). The set of switches may be configured to produce a first configuration of the set of components when a first setting of the set of switches (a setting determined based on the first test vector) is applied. The set of switches may also be configured to produce a second configuration of the set of components when a second setting of the set of switches (a setting determined based on the second test vector) is applied.

[0046] Additionally, the self-test circuit 102 may also include an enable input for the test block 104-1 (e.g., and other corresponding enable inputs for each test block in the test block 104) and / or other suitable signaling lines (e.g., disconnection lines for each test block to prevent current from being drawn from a test block that is not in test when another test block is in test, etc.). The test block may be configured such that when the enable input is valid, the set of components in the test block is allowed to be placed in a new configuration (e.g., reconfigured, e.g., from a first configuration to a second configuration). Additionally, when the enable input is invalid, the set of components in the test block 104-1 is not allowed to be placed in a new configuration. Other mechanisms (e.g., power-off input, not explicitly shown) may also be used to prevent current from being drawn by the test block 104-1. The self-test circuit 102 may also include an analog-to-digital converter circuit configured to convert the measured current into a digital value, which may be stored in the memory 118 as the current measurement 126. For example, an analog-to-digital converter circuit (not explicitly shown) within the self-test circuit 102 may convert a first current into a first value and a second current into a second value such that the memory 118 may store the first value and the second value, and the comparison between the first current and the second current analyzed by the test controller 110 may be performed by comparing the first value and the second value stored in the memory 118.

[0047] As Figure 1A shown and as already described, current-based BIST can be used to thoroughly test each test block 104, where various currents are measured when the test block is in various different electrical configurations (e.g., its components are wired in different arrangements, etc.), and these currents are compared to each other according to a pre-specified test plan. In some embodiments, sufficient test coverage can be achieved in this way, specifically using this current-based built-in self-test. In other examples, it should be understood that external test equipment may also be used in combination with the built-in self-test described herein. Even in these cases that rely on a combination of BIST and external testing, it should be understood that due to the efficient current-based built-in self-test implemented according to the principles described herein, the desired external equipment, the time for external testing, the cost associated with external testing, etc. can all be significantly reduced.

[0048] In an example of the embodiment 100-A, detecting a defect in the test block is shown to be performed by a test controller integrated into the self-test circuit. That is, the test controller 110 is in Figure 1Ais shown as being built into the self-test circuit 102 to direct testing of test block 104-1 (as already described) and of each of the other test blocks among the plurality of test blocks 104. In some examples, the software for performing these various tasks (e.g., the instructions 122 embodying process 124, etc.) can be received from an external source (e.g., from a test device or other test equipment), but the microprocessor implementing the software can still be integrated into the self-test circuit 102 itself.

[0049] In contrast, Figure 1B Another implementation of the self-test circuit 102 is shown, in which the test controller 110 is not integrated into the self-test circuit. Specifically, as shown, an exemplary implementation 100-B of the self-test circuit 102 can be configured such that detecting defects in the respective test blocks 104 can be performed by a test controller that is integrated into a test device separate from the self-test circuit. For example, as shown in exemplary implementation 100-B, the self-test circuit 102 can still include a plurality of test blocks 104, a test vector bus 106, and a current measurement circuit 108, while the test controller 110 and / or the memory 118 can be implemented by a tester circuit 132 that is separate from the self-test circuit 102 (e.g., inside an automatic test equipment that performs the test). In this example, the power supply 112 is drawn as being distributed between the self-test circuit 102 and the tester circuit 132 to imply that the input power for the voltage rail 114 drawn from the power supply 112 can originate on the self-test circuit 102 (as described above for implementation 100-A) or on the tester circuit 132 (in this implementation, which can simultaneously provide power and direction for testing the self-test circuit 102). As described above regarding Figure 1A the other test vector communication interfaces (besides the shared test vector bus 106) described above, it should be understood that the test vectors can be transmitted by the test controller 110 via the test vector bus 106 or Figure 1B other suitable interfaces in the tester circuit configuration of. As another exemplary interface, for example, a JTAG communication interface (controlled by JTAG TDR) can be used by a controller in the tester circuit to limit the number of electrical interconnections between the tester circuit and the self-test circuit.

[0050] Figure 2 An exemplary method 200 similar to process 124 is shown, which can be used to perform current-based BIST on circuit components arranged in various configurations according to the principles described herein. Although Figure 2 exemplary operations 202 to 218 according to one implementation are shown, other implementations of method 200 can omit, add, reorder, and / or modify Figure 2 any of the operations 202 to 218 shown in. In some examples,Figure 2 shown in or with respect to Figure 2 The multiple operations described above can be performed simultaneously (e.g., in parallel) with respect to each other, rather than sequentially as illustrated and / or described. Each of operations 202 to 218 will now be described in more detail, as the operations can be performed by the self-test circuit 102 of an embodiment (e.g., one of embodiments 100-A or 100-B of the embodiment).

[0051] In operation 202, the self-test circuit can send a first test vector to one of a plurality of test blocks in the self-test circuit (e.g., via a test vector bus electrically connected to the plurality of test blocks or via another suitable communication interface such as described above). For example, the first test vector can correspond to a first configuration of a set of components in a particular test block of the plurality of test blocks. For example, in the example of embodiment 100-A of the self-test circuit 102, the particular test block can be test block 104-1, and the first test vector can be sent by the test controller 110 on the test vector bus 106. Upon receiving this first test vector (and in some examples, when activated or enabled via an enable input included in test block 104-1), test block 104-1 can be configured to electrically rearrange its components (e.g., by setting a plurality of switches or in some other suitable manner) into the first configuration. At this time, an amount of current 130-1 will be drawn from the voltage rail 114.

[0052] Thus, in operation 204, when the set of components is in the first configuration, the self-test circuit (e.g., the current measurement circuit 108) can measure a first current drawn by the test block. For example, using the first test vector on the test vector bus 106, the current measurement circuit 108 can measure current 130-1 to determine the current consumption of test block 104-1 and its components in the first configuration.

[0053] In operation 206, then, the self-test circuit can send a second test vector to the test block, the second test vector corresponding to a second configuration of the set of components. The second configuration can be different from the first configuration such that, for example, upon receiving this second test vector (and in some examples, when activated or enabled via an enable input included in test block 104-1), test block 104-1 can be configured to rearrange its components again, this time from the first configuration to the second configuration. At this time, another amount of current 130-1 (which can be expected to be approximately the same as the first current or otherwise have a predetermined relationship with the first current) will be drawn from the voltage rail 114.

[0054] Thus, in operation 208, when the set of components is in the second configuration, the self-test circuit (e.g., current measurement circuit 108) can measure the second current drawn by the test block. For example, the current measurement circuit 108 can measure the current 130-1 again to determine the current consumption of the test block 104-1 and its components in the second configuration.

[0055] In operation 210, the self-test circuit can compare the first current measured in operation 204 with the second current measured in operation 208. This comparison can be performed in various ways to be described, including for example by determining the difference between the currents (using a subtraction operation) or by determining the ratio of the currents (using a division operation). Then the comparison between the first current and the second current can be compared with some pre-determined expected values. For example, if it is expected that the first and second configurations should draw the same amount of current, it can be expected that the difference between the compared currents is close to zero, while the ratio of the compared currents is close to one. If the threshold associated with this expectation is not met, the process can proceed to operation 212 ("failed threshold"), while if the threshold is met, the process can proceed to operation 214 ("threshold met").

[0056] In operation 212, the self-test circuit can detect a defect in the particular test block being tested (e.g., test block 104-1 in the above example). For example, since the first current and the second current do not meet the threshold associated with the expected relationship between the currents, the test controller 110 can be configured to determine that some defect within the test block may have somehow impaired one of the currents, thus indicating that the test block has some defect and should be so marked.

[0057] Conversely, in operation 214, the self-test circuit can determine that no defect has been detected and determine whether all configurations of the currently tested block have been tested or whether there are additional configurations and tests to be performed. If there are more configurations to test ("no"), the process proceeds to operation 216, which can result in re-executing some or all of the methods in method 200 with new test vectors, configurations, measurements, and / or comparisons as may be required in a pre-specified test plan. On the other hand, if all configurations have been tested for the currently tested block ("yes"), the process can proceed to operation 218, where the self-test circuit can determine that no defect has been detected in the tested block (e.g., test block 104-1 in this example). According to the test plan, the self-test circuit can then proceed to execute method 200 for additional test blocks 104, or if all blocks have been tested, can perform a final evaluation of the self-test circuit and its defects (if any).

[0058] Figure 3Illustrates an additional exemplary method 300 for performing current-based built-in self-test on circuit components arranged in various configurations in accordance with the principles described herein. As shown, method 300 includes all the same operations 202 to 218 as described above with respect to Figure 2 All the same operations 202 to 218 as described above. Additionally, method 300 includes some additional operations 302 and 304 that will now be described. It should be understood that these operations may be optional in the sense that they may increase the efficiency and / or effectiveness of the current-based built-in self-test for certain self-test circuits, for certain test blocks, and / or in certain cases. However, for other self-test circuits, other test blocks, and / or in other cases, given the comparison in operation 210, operations 302 and 304 may not be particularly helpful and may thus be omitted (as shown in the example of method 200).

[0059] Operation 302 is shown to be performed in response to the measurement of the first current in operation 204 and before the transmission of the second test vector in operation 206. In operation 302, it is determined whether the first current meets a first fixed threshold or absolute threshold (as opposed to being judged relative to another current that will be performed in operation 210). For example, if the first current is expected to be somewhere between 100 μA and 200 μA, but it falls far outside that range (e.g., close to 0 μA or 1 mA), then the test controller 110 can determine the presence of a defect based on this alone (therefore, in this case, the flow is shown to move directly from operation 302 to operation 212 ("No")). Conversely, if the first current is within the expected range, or at least within its predetermined threshold, then the flow can continue to operation 206 ("Yes").

[0060] Operation 304 is shown to be performed in response to the measurement of the second current in operation 208 and before the comparison of the first current and the second current in operation 210. Similar to operation 302, in operation 304, it is determined whether the second current meets a second fixed threshold or absolute threshold (as opposed to being judged relative to another current that will be performed in operation 210). For example, if the second current is expected to be somewhere between 100 μA and 200 μA, but it falls far outside that range (e.g., close to 0 μA or 1 mA), then the test controller 110 can determine that a defect has been detected based on this alone (therefore, in this case, the flow is shown to move directly from operation 304 to operation 212 ("No")). Conversely, if the second current is within the expected range, or at least within its predetermined threshold, then the flow can continue to operation 210 ("Yes"), where the comparison can be made and the analysis described above can be performed.

[0061] It should be understood that operations 302 and 304 can be used as shortcuts in the flow of method 300 for situations where a very obvious defect happens to exist. For example, if a defect can be detected based on operation 302 or even operation 304, time for performing operations after these operations can be saved. In embodiments that include these shortcut operations, they may not be used to capture all potential defects. For example, a defect can be detected in a first test block (e.g., test block 104-1) using comparative analysis (e.g., using operation 210 instead of operation 302 or operation 304). Then, when the self-test circuit proceeds to test the next test block (e.g., test block 104-2), the self-test circuit can use these shortcuts to detect the defect there. More specifically, for example, the test controller 110 can send a third test vector to the test block 104-2, which corresponds to a specific configuration of a set of additional components in the test block 104-2. Then, when the set of additional components is in a specific configuration, the current measurement circuit 108 can measure a third current drawn by the test block 104-2. Using the shortcut illustrated by operation 302, the test controller 110 can detect a defect in the test block 104-2 based on the third current without comparing it to another current. That is, the defect in the test block 104-2 can be determined based on the failure of the third current to meet the fixed absolute threshold. For example, detecting a defect in the test block 104-2 can include determining that the third current indicates a short circuit condition in the test block 104-2 (e.g., if the third current is much larger than an expected range) or determining that the third current indicates an open condition in the test block 104-2 (e.g., if the third current is close to zero or much smaller than an expected range). The shortcut provided by operations 302 and 304 can also help improve test coverage (e.g., ensuring that the absolute current should be within a predefined range) and / or alleviate certain current ratio calculation challenges (e.g., if the measured current will be zero, so that the calculated ratio will result in a division by zero, then operations 302 and 304 will still be able to correctly process the threshold comparison).

[0062] Figure 4 1 shows an exemplary implementation of the current measurement circuit 108 described above. Specifically, as shown, the circuit implementing the current measurement circuit 108 in this example is powered by a power source (such as the power supply 112 described above). Figure 4 ) receives an input voltage (V IN ). The analog block on the left side of the circuit is labeled voltage regulator 402, while another analog block on the right side of the circuit is labeled current mirror 404. Together, these blocks form current measurement circuit 108, which both provides regulated voltage rail 114 to test block 104 (as described and illustrated above) and performs current sensing to facilitate the various current consumption measurements that have been described.

[0063] As shown, the output transistors at the top of voltage regulator 402 and current mirror 404 can be similarly positioned and can be transistors of the same type. For example, in the case where the transistor in voltage regulator 402 serves as the output transistor, another transistor in current mirror 404 can be implemented as a scaled-down copy of the output transistor that receives the same voltage and produces a copy of the output current that can be measured. Also shown is an amplifier configured to ensure that the voltage on the output node (i.e., voltage rail 114 going to the "test block") is the same as the voltage on the current sense node connected to analog-to-digital converter ("ADC") circuit 406. In this way, the output current delivered to the output node (e.g., drawn by any of the currently active and test-enabled test blocks 104) is replicated or mirrored at a known ratio that, when scaled by a current resistor (e.g., to convert current to voltage), allows ADC circuit 406 to determine the value representing the current currently being drawn by the test block from the output (i.e., from voltage rail 114).

[0064] One useful aspect of this type of design is that each current measured using current measurement circuit 108 can be converted into a digital value that can be used immediately or stored for later analysis, as may be required. For example, referring to the first and second currents described in the above example, where test block 104-1 is reconfigured to test different current draws with different electrical configurations (e.g., as described with respect to Figure 2 and Figure 3 in operations 202 through 208), the method can also include operations for converting the first current to a first value and the second current to a second value using ADC circuit 406. The method can then include storing the first value and the second value in a memory such as memory 118. In this example, then, the comparison between the first current and the second current (e.g., performed as part of operation 210, as described above) can be performed by comparing the first value and the second value stored in the memory. For example, the first value and the second value can be immediately compared by test controller 110 or stored for later comparison and analysis with other values in the memory (e.g., values associated with other configurations, other test blocks, other die on the same wafer, etc.), as will be described in more detail below.

[0065] Figure 5 Various illustrative current comparisons are shown that can be performed in accordance with the principles described herein to detect defects in test blocks. Specifically, as shown, a particular test plan may require different types of comparisons to have been made between any different current measurements (e.g., by current measurement circuit 108 as already described). To illustrate several exemplary comparisons, Figure 5Several examples 500-1, 500-2, and 500-3 are shown, each example involving various current measurements 502 (i.e., current measurements 502-A, 502-B, 502-C, and 502-D). Each of these current measurements 502 is understood to represent the current consumption measured by a current measurement circuit such as current measurement circuit 108 when a particular test block is enabled (activated) and current is drawn using components in its particular configuration. As an example, current measurement 502-A may represent a first current drawn by a first test block (e.g., test block 104-1) when its set of components are arranged in a first configuration, current measurement 502-B may represent a second current drawn by the same first test block (e.g., test block 104-1) when its set of components are arranged in a second configuration, current measurement 502-C may represent a third current drawn by a different test block (e.g., test block 104-2) in the same self-test circuit when its set of components are arranged in a particular configuration, and current measurement 502-D may represent a fourth current drawn by yet another test block (e.g., a test block corresponding to test block 104-1 but on a different die on the same wafer) in a different self-test circuit.

[0066] In other examples, each of the current measurements 502 may be associated with different configurations of the same test block, each of the current measurements 502 may be associated with the same configuration of corresponding test blocks on different self-test circuits, each of the current measurements 502 may be associated with similar test blocks on the same self-test circuit, and so on. In this way, the comparisons made by the test controller can be highly variable and flexible in implementing a thorough test plan that provides a desired amount of test coverage for each test block and self-test circuit. For example, currents can be compared between different configurations within the same test block, where these configurations are expected to draw similar amounts of current (e.g., two parallel branches). Currents can also be compared between equivalent test blocks on the same die (e.g., similar or identical test blocks on a single self-test circuit).

[0067] In some examples, a dynamic part average test (DPAT) method can be used, where the tester circuit analyzes the entire wafer and then comparisons can be performed between corresponding test blocks on different dice within the wafer. For example, currents can be compared between the same circuits (e.g., test blocks) on different dice within the same wafer using such DPAT methods.

[0068] More specifically, returning to reference method 200 and the first and second test vectors and configurations described in that example, the comparison between different test blocks within the same self-test circuit can be performed by including additional operations in method 200. For example, method 200 can further include the following operations: sending a third test vector that corresponds to a specific configuration of a set of additional components in an additional test block among the plurality of test blocks in the self-test circuit. Method 200 can further include the following operations: measuring a third current drawn by the additional test block when the set of additional components is in the specific configuration. In that example, then, detecting a defect in the test block (e.g., in operation 210) can also be based on a comparison between the first current and the third current.

[0069] In a similar manner, the comparison between corresponding test blocks in different self-test circuits can also be performed by including additional operations in method 200. For example, method 200 can further include the following operations: sending the first test vector to an additional test block that corresponds to the test block and is included within an additional plurality of test blocks in an additional self-test circuit, the additional self-test circuit being fabricated on the same wafer as the self-test circuit. Method 200 can further include the following operations: measuring a third current drawn by the additional test block when a set of additional components in the additional test block is in the first configuration. Then, detecting a defect in the test block (e.g., in operation 210) can also be based on a comparison between the first current and the third current.

[0070] Regardless of which specific self-test circuits, test blocks, and configurations are represented by the various current measurements 502 available (e.g., measured and stored at a previous time and then loaded from memory), Figure 5Shows that various different types of comparisons 504 can be performed between paired or grouped current measurements 502, as may be guided by a preconfigured test plan implemented, for example, in software instructions (e.g., instruction 122). For example, example 500-1 shows that one comparison can be performed between current measurements 502-A and 502-B, and a separate comparison can also be performed between current measurements 502-C and 502-D. Example 500-2 shows that another test plan (or another part of the same test plan) can require comparisons between current measurement 502-A and each of the other current measurements 502-B, 502-C, and 502-D. Example 500-3 then shows the situation where comparisons 504 are performed between current measurement 502-A and each of current measurements 502-B and 502-C and also includes another comparison 504 between current measurement 502-B and measurement 502-D. It should be understood that each of these comparisons is shown for illustrative purposes, and any number, combination, and arrangement of these types of one-to-one or one-to-many comparisons can be part of a given test plan that can serve a particular implementation.

[0071] Additionally, although in Figure 5In Examples 500-1 to 500-3, each comparison 504 is shown in the same way (i.e., as a double-headed arrow connecting two different current measurements 502), but it should be understood that different types of comparisons of current values can be performed in different situations, such that different threshold techniques or other defect analyses may be appropriate. As a first example, comparing a first value with a second value can include determining the ratio of the first value to the second value (e.g., by performing a division operation on the two values). These ratios can be effective tools for defect testing because it is known that integrated circuit manufacturing results in a large absolute distribution of component values. When analyzing absolute current consumption (as opposed to relative consumption represented by a ratio), process and temperature variations may limit test coverage because wide margins or careful DPAT may be required. In contrast, by using the ratio of two measured current values, process and temperature variations can be effectively canceled out, such that a narrower range can be examined and thus defect coverage can be improved. Detecting a defect in a test block can include determining that the ratio falls outside a predetermined range. In some examples, it may be desirable or expected that the ratio should be approximately 1, indicating that the two currents are expected to be equal. However, although relatively small ratios may be associated with the most reliable tests, the expected ratio or range need not be associated with the ratio 1. In some comparisons 504, for example, the expected ratio can be 2, 5, or 10, or some other relatively small ratio value. The threshold ranges for these examples can give a small margin to the calculated ratio while associating more significant deviations with detected defects. For example, if the expected ratio is 2, the expected range for the calculated ratio can be 1.8 to 2.2, and any ratio outside this range can trigger a presumed defect.

[0072] As a second example, comparing a first value with a second value can include determining the difference between the first value and the second value (e.g., by performing a subtraction operation on the two values). In this case, detecting a defect in a test block can similarly include determining that the difference falls outside a predetermined range. However, the assumption in this case can be that the currents should be approximately equal, such that the predetermined range only allows a small non-zero difference (e.g., the difference is less than 2 μA, or some other appropriate value given the expected current).

[0073] As described above, the measured current can also be compared to an expected fixed absolute value. For example, if the expected current is in the range of 100 μA to 200 μA and the current is measured to be close to 0 μA, it can be safely assumed that there is an open or other defect in the circuit that should be flagged. However, for less significant deviations (e.g., if the measured current in this example is closer to the 100 μA or 200 μA limit of its expected range), it should be understood that defect analysis based on the relative comparison between currents rather than on the absolute measured value can increase the reliability of the test and otherwise provide benefits. One reason is that each wafer can be manufactured under slightly different conditions or with slightly different parameters, such that different process characteristics can affect the absolute current drawn from wafer to wafer. Additionally, differences in temperature and / or other such circumstances can also have a significant impact on the absolute measured value when different tests are performed (e.g., when different currents are measured). Thus, one measurement can be well within the expected range and still represent an anomaly or problem given the dynamic variations in the process and temperature, while another measurement can be on the outer boundary of the expected range and be completely benign when its specific process and temperature dynamics are properly considered.

[0074] The methods and systems described herein rely on comparisons between current measurements, where it is expected that these variables remain relatively consistent such that they can thus be assumed to cancel out or otherwise be rendered insignificant rather than attempting to calculate and account for the exact expectations and ranges of these additional variables (e.g., process, temperature, etc.). These assumptions can generally be made for currents measured at the same temperature (e.g., at approximately the same time when the temperature does not have much chance to drift) and for circuits on the same die or at least the same wafer (such that they have the same process characteristics). By limiting the comparison to current measurements for which these assumptions can be made, test calibration and other efforts to account for temperature and process differences between tests can be alleviated or completely avoided, thus simplifying and reducing the time and cost of the built-in self-test described herein.

[0075] Figure 6 An illustrative embodiment of a test block 104 (e.g., test block 104-1, test block 104-2, etc.) in accordance with the principles described herein is shown, each test block including respective multiple sets of components 602 configured to be arranged in various configurations. More specifically, test block 104-1 is shown to include a number of components 602-1, and test block 104-2 is shown to include its own set of a number of components 602-2. While Figure 6Each of the components 602 shown in the figure is drawn as a non-descriptive box in the figure, but it should be understood that these various components can represent different types of electronic components (e.g., resistors, capacitors, transistors, operational amplifiers, logic gates, etc.) configured to be rearranged into different configurations in the manner described herein. Thus, the boxes representing the components 602 are shown to have different sizes, shapes, and arrangements in each of the test blocks in the test block, indicating that the various components can be placed in various different configurations as described herein.

[0076] Figure 6 Each of the test blocks 104 in is also shown to interface with signals incoming and outgoing on various input and output terminals. For example, as already described, the voltage rail 114 is shown to provide input power to all the test blocks 104. Additionally, the test vector bus 106 is shown to electrically connect each of the test blocks 104 to a test controller ( Figure 6 not shown in the figure) that drives the test vector bus. As already mentioned, corresponding enable inputs 604 are also shown as inputs received by each of the test blocks 104. Specifically, the test block 104-1 is shown to include an enable input 604-1, and the test block 104-2 is shown to include an enable input 604-2. These enable inputs 604 can also be driven by a test controller such as the test controller 110, such that only one particular test block under test is enabled at a time, which is the current focus of the test by the test controller. To this end, each of the test blocks 104 can be configured such that when the enable input 604 is valid, the test block allows its set of components 602 to be placed in a new configuration. Conversely, when the enable input is invalid, the test block will then be configured not to allow its set of components to be placed in a new configuration. As mentioned above, other inputs (e.g., break wires, etc., Figure 6 not explicitly shown in the figure) can also be used in conjunction with the enable input to control when current is allowed to be drawn or when current is not allowed to be drawn. For example, if the enable input 604-1 is valid at a given moment, the enable input 604-2 can be invalid, and the test block can be configured such that only the components 602-1 of the test block 104-1 can be reconfigured and / or allowed to draw any current from the voltage rail 114. Later, when a test corresponding to the test block 104-2 is to be performed, the enable input 604-2 can be valid and the enable input 604-1 can be invalid, such that only the components 602-2 in the test block 104-2 are reconfigurable and able to draw any current from the voltage rail 114.

[0077] Figure 6Also shown therein are other input terminals (labeled "IN_1" to "IN_4") and output terminals (labeled "OUT_1" to "OUT_4") that are included in various test blocks 104. These represent the interconnections of the test blocks to other parts of the self-test circuit 102 (e.g., to other test blocks 104, etc.) such that each test block can receive input signals and produce output signals according to any function that each test block may have. Thus, it should be understood that each test block may include any suitable number of inputs and / or outputs depending on its size, function, design, etc. However, in Figure 6 it should be noted that these input and output terminals are shown as unconnected. This does not indicate that each test block is isolated from the rest of the circuit during normal operation, as it should be understood that these input and output terminals will actually typically be interconnected to other parts of the circuit. Instead, the input and output terminals are shown as unconnected in Figure 6 to emphasize that the tests described herein generally do not depend on or focus on the normal operating configuration of the test blocks or any stimuli that pass through the test blocks in those configurations. Instead, the tests described herein generally do not know how the various test blocks 104 may be interconnected or what stimuli may pass through their input and output terminals (however, in some examples, basic stimuli may be selected to ensure that one test block does not interfere with the testing of another test block, etc.). Regardless of how the components 602 may be configured during normal operation and regardless of how the test blocks 104 may be interconnected, the tests described herein are based on the configurations of the corresponding sets of components 602 (e.g., based on the test vectors currently being sent on the test vector bus 106) and the current drawn from the voltage rails 114 to ground through the components 602 in their current configuration and being measured.

[0078] When a given test block 104 is enabled (i.e., when its corresponding enable input 604 is active, such as by being driven high), the test vectors on the test vector bus 106 indicate what configuration of the set of components 602 will be tested (e.g., how the components 602 will be electrically connected or arranged for testing). For example, if the test vector bus 106 is a four-bit bus, up to 2^4 = 16 different test vectors can be sent on the test vector bus 106. If a test block is desired to support more test configurations than can be represented by the test vector bus (e.g., for the example of a 4-bit bus, greater than 16 configurations), such as for a particularly complex test block that is desired to be tested in many configurations, additional enable inputs can be added to the test block to multiplex between different multiple sets of test vectors. Thus, for example, a 4-bit test vector bus can send up to 16 different test vectors to a test block with one enable input, up to 32 different test vectors to a test block with two enable inputs, and so on. As another example, a 6-bit test vector bus can send up to 64 different test vectors to a test block with one enable input, up to 128 different test vectors to a test block with two enable inputs, and so on. In yet other examples, dedicated (non-shared) electrical connections for conveying test vectors can be used instead of a test vector bus, as described above.

[0079] To decode the possible test vectors and convert them into an executable reconfiguration of a set of components in a test block (e.g., for settings of multiple switches within the test block, as will be described in more detail below), Figure 6 it is shown that each test block 104 can include a corresponding decoder 606 (e.g., decoder 606-1 in test block 104-1, decoder 606-2 in test block 104-2, etc.). The role of the decoder is to ensure that, at least when the enable input 604 of the test block is active, the set of components 602 of the test block is appropriately configured (e.g., electrically connected) according to the test vectors driven onto the test vector bus 106.

[0080] This reconfiguration can be performed in any suitable manner. For example, each test block 104 can include a set of switches that are strategically placed around respective components 602 within the test block in a manner that allows different electrical connections between the components based on the state or setting of the switches. Based on a first test vector on the test vector bus 106, a first setting of the set of switches within the test block (e.g., via a respective decoder 606, via the test controller 110, etc.) can be determined, where the set of switches is configured to produce a first configuration of the set of components when the first setting is applied. Similarly, based on a second test vector on the test vector bus 106, a second setting of the set of switches can be determined, where the set of switches is configured to produce a second configuration of the set of components when the second setting is applied. Additional configurations associated with additional test vectors can be similarly implemented via additional settings of the set of switches.

[0081] For illustration, Figures 7A to 7F Aspects are shown of how an exemplary set of switches within a test block according to the principles described herein can be configured with different settings to produce various configurations of a set of components in the test block. Specifically, Figure 7A A block diagram is shown representing various exemplary components 701, 702, 703, 704, 705, 706, 707, 708, and 709 that can be included in a particular test block. In Figure 7A a particular electrical configuration or wiring arrangement between the components is shown, which can be understood to represent how these components will be connected during normal operation of the test block (e.g., after testing is complete and the self-test circuit is being operated for its intended use).

[0082] Figure 7B A block diagram is shown of how a set of switches 710 can be added to the test block to allow a large number of potential reconfigurations of components 701 through 709. Specifically, in Figure 7B this and the other figures that follow, each switch 710 (only a few of which are explicitly labeled as such) is shown as a small square that will be understood to be open or unconnected when it is not filled (i.e., when the square is white, as shown in Figure 7B ) and closed or connected when it is filled (i.e., when the square is black). Although Figure 7B shows a relatively large number of switches to create a great deal of flexibility and a large number of ways in which components 701 through 709 can be configured, it should be understood that in some embodiments, the number and placement of switches within a set of switches for a test block can be designed in a more targeted manner. For example, a small number of well-placed switches between several components in the block can provide all of the potential configurations desired for a given test plan, as will be further illustrated in the expanded examples that follow.

[0083] In the case where a relatively large number of switches 710 are added to this particular test block, Figures 7C to 7F very different test configurations are shown that can be implemented by different settings of this set of switches (settings determined by a decoder such as described above). Specifically, Figure 7C a setting of these switches 710 is shown that causes all of the components 701 to 709 to be electrically connected in series with each other (e.g., to test for no breaks or interruptions in any of the components). In Figure 7D is shown a simplified diagram of the configuration created by the Figure 7C switch setting. Input node 712 and output node 714 are both marked in Figure 7C and Figure 7D to show how the setting of the switches 710 in Figure 7C can result in the equivalent configuration shown in Figure 7D of this example.

[0084] Conversely, Figure 7E a different setting of this set of switches 710 is shown that causes all of the components 701 to 709 to be electrically connected in parallel with each other (e.g., to test for no short circuits in any of the components). In Figure 7F is shown a simplified diagram of the configuration created by the Figure 7E switch setting. Input node 716 and output node 718 are both marked in Figure 7E and Figure 7F to show how the setting of the switches 710 in Figure 7E can result in the equivalent configuration shown in Figure 7F of this example.

[0085] The general components represented by components 701 to 709 in Figures 7A to 7F show the general principle of how switches can be used to allow electrical rearrangement and reconfiguration of a set of components within a test block. However, it should be understood that actual components can have different functions, different numbers of inputs and outputs, different wiring, and other characteristics, and these principles can be adapted to other characteristics in any way that can serve a particular implementation.

[0086] Figures 8A to 8H An extended example of a particular exemplary test block is shown and how it can be arranged in various configurations to test the various components included therein. As will be shown, in accordance with the principles already described, the components of this relatively simple example can be arranged in various configurations and tested using current-based built-in self-testing.

[0087] Figure 8AFIG. 800-A is a circuit diagram showing how the particular test block can be configured in operation. As shown, voltage sources 802-1 and 802-2 can provide power (voltage source 802-1) and / or a reference voltage (voltage source 802-2) to the components of the test block, which components include a resistor 804 having a resistance value R, an operational amplifier 806, and other components (e.g., other resistors, capacitors, etc.) not explicitly labeled.

[0088] Rather than the circuit in the operational configuration shown in test circuit diagram 800-A (or otherwise), the current-based built-in self-test techniques described herein involve reconfiguring the components of the test block and measuring the current drawn for each configuration. For illustration, Figure 8B FIG. 800-B is a circuit diagram showing how the test block can be implemented so as to be reconfigurable in the manner already described and testable using the current-based built-in self-test principle. Specifically, as shown, circuit diagram 800-B divides resistor 804 into two resistors 804-1 and 804-2, each having a resistance value of R / 2, such that the two resistors 804-1 and 804-2 together still provide the same amount of resistance R as shown in circuit diagram 800-A. Voltage sources 802-1 and 802-2, operational amplifier 806, and other resistors and capacitors are still shown as being included in circuit diagram 800-B. Additionally, circuit diagram 800-B shows the addition of a current monitor 808 that can be implemented by a current measurement circuit (e.g., current measurement circuit 108), a current 810 consumed by the test block and measured by the current monitor 808, and a set of switches 812 (only some of which are explicitly labeled as such) at various locations to allow the components to be set in different configurations as will be shown.

[0089] As a first example of how the circuit-based built-in self-test can be used, Figure 8C and Figure 8D show how resistor 804 can be tested. In this example, the set of components includes resistor components (i.e., resistor 804) implemented as a first resistor (i.e., resistor 804-1) and a second resistor (i.e., resistor 804-2), the first and second resistors being configured to be in series during operation of the test block and on separate current paths for a first configuration and a second configuration of the test block. More specifically, as shown, various switches 812 are set (e.g., opened or closed) so as to create Figure 8C the configuration 800-C shown for measuring a first current 810-C drawn by the test block and associated with a first measurement of the first resistor 804-1. Then, different settings of these switches 812 are applied to create Figure 8DConfiguration 800-D shown in the figure is used to measure the second current 810-D drawn by the test block and associated with the second measurement value of the second resistor 804-2. More specifically, as shown in the figure, configuration 800-C is implemented by closing the switch 812-2 between the voltage node of the voltage source 802-1 (where the first current 810-C is to be measured) and the node between the two resistors 804-1 and 804-2. The switch 812-1 is opened to disconnect the voltage source 802-2, thereby ensuring that all the current flowing through the resistor 804-1 will be measured by the current monitor 808. The switch 812-3 is closed to ground the other side of the resistor 804-1, thus completing the current path of the first current 810-C from the voltage source 802-1 through the current monitor 808 and the resistor 804-1 to ground. At the same time, configuration 800-C also shows that the switch 812-4 remains open, so that no current can flow through the resistor 804-2 during this test.

[0090] The supplementary configurations 800-C and 800-D show that the switch 812-2 remains closed and the switch 812-1 remains open to allow current to pass through the resistor components. However, although all of the current 810-C is directed through the resistor 804-1 in configuration 800-C, Figure 8D it is shown that for configuration 800-D, the switch 812-3 can be set to open and the switch 812-4 can be set to close. In this way, the current 810-D driven by the voltage source 802-1, which passes through the current monitor 808 and grounds through the resistor 804-2, will be measured. It should be noted that if there is a short circuit or other problem with the capacitor 814, the current 810-C will be affected, and thus the defect can be detected. In other words, configuration 800-C can not only help test the resistor components (resistors 804), but also help test the capacitor 814.

[0091] Once currents 810-C and 810-D have been measured, a test controller such as test controller 110 can detect a defect in the test block based on a comparison indicating that a first measured value (for current 810-C) differs from a second measured value (for current 810-D) by more than a predetermined threshold. That is, since resistors 804-1 and 804-2 are expected to have the same resistance value, and since configurations 800-C and 800-D are configured to direct and measure only the current flowing through two different resistors, any difference between the first measured value and the second measured value can indicate a problem. For example, one resistor may have an incorrect value, capacitor 814 may be shorted, one of the resistors may be shorted, one of the resistors may be open, or there may be another problem. Although a current difference above a predetermined threshold may not indicate which of these types of potential defects is present, it can indicate with high confidence that there are some defects that must be considered.

[0092] As another example of how circuit-based built-in self-test can be used, Figure 8E 、 Figure 8F 、 Figure 8G and Figure 8H illustrates how a dual-input component such as operational amplifier 806 can be tested. As shown, in this example, the set of components includes a dual-input component (i.e., operational amplifier 806) that includes a first input (in this example, the non-inverting input) and a second input (in this example, the inverting input). In a series of different configurations shown in different Figures 8E to 8H these inputs can be grounded or connected to the power supply voltage (the node of voltage source 802-1) in every possible combination.

[0093] Specifically, as shown in Figure 8E a first configuration corresponding to a first test vector can connect both the first input and the second input to the power supply voltage simultaneously. This is done by setting switches 812-6 and 812-7 to closed while setting switches 812-8 and 812-9 to open when measuring current 810-E. It should be noted that other switches such as switches 812-1, 812-2, and 812-3 (not explicitly labeled in Figures 8E to 8H are open so as not to allow current to flow through parts of the circuit associated with resistor 804 (these parts have been tested separately, as described above with respect to Figures 8C to 8D ).

[0094] As shown in Figure 8FAs shown, the second configuration corresponding to the second test vector can connect the first input to the supply voltage and ground the second input. This is accomplished by setting switches 812-6 and 812-9 to closed and switches 812-7 and 812-8 to open when measuring current 810-F. Similarly, other switches such as switches 812-1, 812-2, and 812-3 (not explicitly labeled in Figures 8E to 8H are open so as not to allow current to flow through portions of the circuit associated with resistor 804. However, in this example, the output of operational amplifier 806 is shown connected to the supply voltage by setting switch 812-5 to closed and switch 812-4 to open.

[0095] As Figure 8G shown, the third configuration corresponding to the third test vector can ground the first input and connect the second input to the supply voltage. This is accomplished by setting switches 812-7 and 812-8 to closed and switches 812-6 and 812-9 to open when measuring current 810-G. Similarly, other switches such as switches 812-1, 812-2, and 812-3 (not explicitly labeled in Figures 8E to 8H are open so as not to allow current to flow through portions of the circuit associated with resistor 804. However, in this example, the output of operational amplifier 806 is shown grounded by setting switch 812-4 to closed and switch 812-5 to open.

[0096] As Figure 8H shown, the fourth configuration corresponding to the fourth test vector can ground the first input and the second input. This is accomplished by setting switches 812-8 and 812-9 to closed and switches 812-6 and 812-7 to open when measuring current 810-H. Similarly, other switches such as switches 812-1, 812-2, and 812-3 (not explicitly labeled in Figures 8E to 8H are open so as not to allow current to flow through portions of the circuit associated with resistor 804.

[0097] Once all of the currents 810-E through 810-H have been measured and converted to corresponding current values, detecting a defect in the test block can also be performed based on one or more comparisons involving any current or all of these currents in any combination that can serve a particular implementation. For example, certain values can be expected to be the same or related by a predetermined ratio, and this predetermined ratio can be checked such that any difference above a predetermined threshold can indicate a defect in the test block.

[0098] The various methods and processes described herein can be implemented, at least in part, as instructions embodied in a non-transitory computer-readable medium and executable by one or more computing devices. Generally, a processor (e.g., a microprocessor) receives the instructions from a non-transitory computer-readable medium (e.g., a memory, etc.) and executes the instructions, thereby performing one or more operations such as those described herein. Such instructions can be stored and / or transmitted using any of a variety of known computer-readable media.

[0099] A computer-readable medium (also referred to as a processor-readable medium) includes any non-transitory medium that participates in providing data (e.g., instructions) that can be read by a processor. Such a medium can take many forms, including but not limited to non-volatile media and / or volatile media.

[0100] Numerous embodiments have been described. However, it should be understood that various modifications can be made without departing from the spirit and scope of this specification.

[0101] It should also be understood that when an element is referred to as being on another element, connected to another element, electrically connected to another element, coupled to another element, or electrically coupled to another element, the element can be directly on, connected to, or coupled to another element, or there can be one or more intervening elements. In contrast, when an element is referred to as being directly on another element, directly connected to another element, or directly coupled to another element, there are no intervening elements. Although the terms directly on, directly connected to, or directly coupled to may not be used throughout the detailed description, elements shown as being directly on, directly connected, or directly coupled can be referred to in such a manner. The claims of this application can be amended to recite the exemplary relationships described in the specification or shown in the drawings.

[0102] The various devices and techniques described herein can be implemented using a variety of semiconductor processing and / or packaging techniques. Some embodiments can be implemented using various types of semiconductor processing techniques associated with a semiconductor substrate, which includes but is not limited to, for example, silicon (Si), gallium arsenide (GaAs), silicon carbide (SiC), etc.

[0103] It should also be understood that when an element such as a layer, region, or substrate is referred to as being on another element, connected to another element, electrically connected to another element, coupled to another element, or electrically coupled to another element, the element can be directly on, connected to, or coupled to another element, or there can be one or more intervening elements. In contrast, when an element is referred to as being directly on another element or layer, directly connected to another element or layer, or directly coupled to another element or layer, there are no intervening elements or layers.

[0104] Although the terms "directly on," "directly connected to," or "directly coupled to" may not be used throughout the detailed description, elements shown as directly on, directly connected, or directly coupled may be referred to in such a manner. The claims of this application may be amended to recite the illustrative relationships described in the specification or shown in the drawings.

[0105] As used in this specification, unless specifically stated otherwise in context, the singular forms may include the plural forms. Except for the orientations shown in the drawings, the spatial relative terms (e.g., "above," "directly above," "over," "below," "beneath," "directly below," "under," etc.) are intended to cover different orientations of the device in use or operation. In some embodiments, the relative terms "above" and "below" may respectively include "vertically above" and "vertically below." In some embodiments, the term "adjacent" may include laterally adjacent or horizontally adjacent thereto.

[0106] Although certain features of the described embodiments have been illustrated as described herein, many modifications, substitutions, changes, and equivalents will now occur to those skilled in the art. Accordingly, it should be understood that the appended claims are intended to cover all such modifications and changes that fall within the scope of the embodiments. It should be understood that these modifications and changes are presented by way of example only and not by way of limitation, and various changes in form and detail may be made. Except for mutually exclusive combinations, any part of the devices and / or methods described herein may be combined in any combination. The embodiments described herein may include various combinations and / or sub - combinations of the functions, components, and / or features of the described different embodiments.

[0107] Additionally, the logical flow depicted in the drawings does not require the particular order or sequential order shown to achieve the desired result. Additionally, other steps may be provided, or steps may be eliminated from the process, and other components may be added to or removed from the system. Accordingly, other embodiments are within the scope of the following claims.

[0108] It should be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. The first element may be named the second element, and similarly, the second element may be named the first element, without departing from the scope of the embodiments of the present disclosure. As used herein, the term "and / or" includes any combination and all combinations of one or more of the associated listed items.

[0109] Although certain features of the described embodiments have been illustrated as described herein, many modifications, alternatives, variations, and equivalents will now occur to those skilled in the art. Accordingly, it should be understood that the appended claims are intended to cover such modifications and variations that fall within the scope of the embodiments. It should be understood that they are presented by way of example only and not by way of limitation, and that various changes may be made in form and detail. Any part of the apparatus and / or method described herein may be combined in any combination, except for mutually exclusive combinations. The embodiments described herein may include various combinations and / or sub - combinations of the functions, components, and / or features of the described different embodiments. Accordingly, the scope of the present invention is not limited to the specific combinations claimed below, but extends to cover any combination of the features or exemplary embodiments described herein, whether or not that specific combination is specifically recited in the appended claims at this time.

Claims

1. A method, comprising: sending a first test vector to a test block in a plurality of test blocks in a self-test circuit, the first test vector corresponding to a first configuration of a set of components in the test block; measuring a first current drawn by the test block when the set of components is in the first configuration; sending a second test vector to the test block, the second test vector corresponding to a second configuration of the set of components, the second configuration being different from the first configuration; measuring a second current drawn by the test block when the set of components is in the second configuration; as well as A defect in the test block is detected based on a comparison between the first current and the second current.

2. The method according to claim 1, further comprising: determining a first setting for a set of switches within the test block based on the first test vector, the set of switches being configured to produce the first configuration of the set of components when the first setting is applied; as well as A second setting for the set of switches is determined based on the second test vector, the set of switches being configured to produce the second configuration of the set of components when the second setting is applied.

3. The method according to claim 1, wherein: The test block includes an enable input and is configured to: allowing the set of components in the test block to be placed into a new configuration when the enable input is asserted; as well as When the enable input is deasserted, the set of components in the test block is not permitted to be placed into the new configuration.

4. The method according to claim 1, further comprising: sending a third test vector to an additional test block of the plurality of test blocks, the third test vector corresponding to a specific configuration of an additional set of components in the additional test block; and measuring a third current drawn by the additional test block when the set of additional components is in the particular configuration; Wherein, detecting the defect in the test block is also based on a comparison between the first current and the third current.

5. The method according to claim 1, further comprising: sending the first test vector to an additional test block, the additional test block being included in an additional self-test circuit and corresponding to the test block, the additional self-test circuit being manufactured on the same wafer as the self-test circuit; as well as measuring a third current drawn by the additional test block when an additional set of components in the additional test block is in the first configuration; Wherein, detecting the defect in the test block is also based on a comparison between the first current and the third current.

6. The method according to claim 1, further comprising: converting the first current to a first value and converting the second current to a second value using an analog-to-digital converter circuit; as well as storing the first value and the second value in a memory; Wherein, the comparison between the first current and the second current is performed by comparing the first value and the second value stored in the memory.

7. The method according to claim 6, wherein: comparing the first value and the second value comprises determining a ratio of the first value to the second value; and Detecting the defect in the test block includes determining that the ratio falls outside a predetermined range.

8. The method according to claim 6, wherein: comparing the first value and the second value comprises determining a difference between the first value and the second value; and Detecting the defect in the test block includes determining that the difference falls outside of a predetermined range.

9. The method according to claim 1, further comprising: sending a third test vector to an additional test block of the plurality of test blocks, the third test vector corresponding to a specific configuration of an additional set of components in the additional test block; measuring a third current drawn by the additional test block when the set of additional components is in the particular configuration; and Defects in the additional test block are detected based on the third current rather than a comparison with another current.

10. The method according to claim 9, wherein: Detecting the defect in the additional test block includes determining that the third current is indicative of a short condition or an open condition in the additional test block.

11. The method according to claim 1, wherein: the set of components including resistor components implemented as a first resistor and a second resistor, the first resistor and the second resistor being configured to be connected in series and on separate current paths in the first configuration and the second configuration during operation of the test block; the first current drawn by the test block being associated with a first measured value of the first resistor; the second current drawn by the test block being associated with a second measured value of the second resistor; and Detecting the defect in the test block is performed based on the comparison indicating that the first measurement value differs from the second measurement value by more than a predetermined threshold.

12. The method of claim 1, wherein: The set of components includes a dual input component including a first input and a second input; The first configuration connects the first input and the second input to a supply voltage; The second configuration connects the first input to the supply voltage and the second input to ground; a third configuration corresponding to a third test vector on the test vector bus grounds the first input and connects the second input to the supply voltage; a fourth configuration corresponding to a fourth test vector on the test vector bus grounding the first input and the second input; and Detecting the defect in the test block is also performed based on one or more comparisons involving a third current drawn by the test block when the set of components is in the third configuration and a fourth current drawn by the test block when the set of components is in the fourth configuration.

13. The method according to claim 1, wherein: Detecting the defect in the test block is performed by a test controller that is integrated into the self-test circuit.

14. The method according to claim 1, wherein: Detecting the defect in the test block is performed by a test controller that is integrated into a test device separate from the self-test circuit.

15. A self-test circuit, the self-test circuit comprising: a plurality of test blocks, the plurality of test blocks comprising a test block configured to receive a first test vector and a second test vector, the first test vector corresponding to a first configuration of a set of components in the test block and the second test vector corresponding to a second configuration of the set of components; a current measurement circuit configured to measure a first current drawn by the test block when the set of components is in the first configuration and to measure a second current drawn by the test block when the set of components is in the second configuration; and A test controller is electrically connected to the plurality of test blocks and the current measurement circuit, the test controller being configured to send the first test vector and the second test vector to the test block, and to detect a defect in the test block based on a comparison between the first current and the second current.

16. The self-test circuit of claim 15, further comprising a set of switches within the test block, the set of switches being configured to: producing the first configuration of the set of components when a first setting of the set of switches is applied, the first setting being determined based on the first test vector; and The second configuration of the set of components is produced when a second setting of the set of switches is applied, the second setting being determined based on the second test vector.

17. The self-test circuit of claim 15, further comprising an enable input of the test block, the test block being configured to: allowing the set of components in the test block to be placed into a new configuration when the enable input is asserted; and When the enable input is deasserted, the set of components in the test block is not permitted to be placed into the new configuration.

18. The self-test circuit according to claim 15, further comprising: an analog-to-digital converter circuit configured to convert the first current to a first value and to convert the second current to a second value; and a memory configured to store the first value and the second value; Wherein, the comparison between the first current and the second current is performed by comparing the first value and the second value stored in the memory.

19. A non-transitory computer readable medium storing instructions that, when executed, cause a test controller associated with a self-test circuit to perform a process comprising: sending a first test vector to a test block in a plurality of test blocks in the self-test circuit, the first test vector corresponding to a first configuration of a set of components in the test block; sending a second test vector to the test block, the second test vector corresponding to a second configuration of the set of components, the second configuration being different from the first configuration; as well as Defects in the test block are detected based on a comparison between a first current drawn by the test block when the set of components is in the first configuration and a second current drawn by the test block when the set of components is in the second configuration.

20. The non-transitory computer readable medium of claim 19, wherein: The process also includes: determining a first setting for a set of switches within the test block based on the first test vector, the set of switches being configured to produce the first configuration of the set of components when the first setting is applied; and A second setting for the set of switches is determined based on the second test vector, the set of switches being configured to produce the second configuration of the set of components when the second setting is applied.

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