Nonvolatile memory device, memory device, and method of operating memory device

Abstract

A non-volatile memory device, a memory device, and a method of operating the memory device are provided. The memory device includes a nonvolatile memory device configured to receive a command and an address for a write operation or an erase operation via a command address pin, transmit and receive write data or read data via a data pin, generating degradation information by measuring at least one of a program execution time for performing a write operation and an erase execution time for performing an erase operation; and a memory controller configured to receive the degradation information from the non-volatile memory device, and control the non-volatile memory device to adjust at least one of a program voltage of the write operation and an erase voltage of the erase operation based on the degradation information.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2023-0189173, filed with the Korean Intellectual Property Office (KIPO) on Dec. 22, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Example embodiments generally relate to semiconductor integrated circuits, and more particularly, to non-volatile memory devices, storage devices including non-volatile memory devices, and methods of operating storage devices. Background Art

[0003] Recently, storage devices such as solid state drives (SSDs) have been widely used. A storage device may correspond to a memory system including a non-volatile memory device such as a flash memory and a storage controller (or memory controller) that controls the non-volatile memory device. The non-volatile memory device may communicate with the storage controller via predetermined pins according to a protocol to transmit and receive input and output signals. For example, the non-volatile memory device may receive a command and an address from the storage controller through specific input / output (I / O) pins, and may transmit data to the storage controller and receive data from the storage controller through the same input / output pins. According to such an I / O interface, data may not be transmitted while a command and / or an address is being transmitted, and the efficiency of the I / O interface may be reduced. Accordingly, there is a need for an I / O interface that can efficiently transmit data between a non-volatile memory device and a storage controller. Summary of the Invention

[0004] Some example embodiments provide a non-volatile memory device according to a separate command address (SCA) protocol, a storage device including the non-volatile memory device, and a method of operating the storage device that can effectively provide and reflect a degradation degree of the non-volatile memory device.

[0005] According to an aspect of one or more example embodiments, a storage device includes: a non-volatile memory device configured to receive a command and an address for a write operation or an erase operation via command address pins, transmit and receive write data or read data via data pins, and generate degradation information by measuring at least one of a programming execution time for performing a write operation and an erase execution time for performing an erase operation; and a storage controller configured to receive the degradation information from the non-volatile memory device and control the non-volatile memory device to adjust at least one of a programming voltage for a write operation and an erase voltage for an erase operation based on the degradation information.

[0006] According to another aspect of one or more example embodiments, a method of operating a storage device including a non-volatile memory device and a storage controller configured to control the non-volatile memory device includes: generating degradation information by measuring at least one of a programming execution time for performing a write operation and an erase execution time for performing an erase operation of the non-volatile memory device; providing the degradation information from the non-volatile memory device to the storage controller; and controlling the non-volatile memory device to adjust at least one of a programming voltage for the write operation and an erase voltage for the erase operation based on the degradation information.

[0007] According to another aspect of one or more example embodiments, a memory cell array includes a plurality of non-volatile memory cells; command address pins configured to transmit commands and addresses for write operations or erase operations; data pins configured to transmit write data and read data; status pins configured to transmit status signals, the status signals being activated at a first logic level indicating a ready state when in a ready state and deactivated at a second logic level indicating a busy state when performing internal operations for write operations or erase operations, and a degradation detector circuit configured to generate degradation information by identifying at least one of a programming execution time for performing a write operation and an erase execution time for performing an erase operation based on the status signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects and features will become more apparent from the following description of example embodiments in conjunction with the accompanying drawings.

[0009] Figure 1 is a flowchart showing a method of operating a storage device according to an example embodiment.

[0010] Figure 2 and Figure 3 is a diagram showing an example embodiment of adjusting a programming voltage of a storage device according to an example embodiment.

[0011] Figure 4 and Figure 5 is a diagram showing an example embodiment of adjusting an erase voltage of a storage device according to an example embodiment.

[0012] Figure 6A is a block diagram showing a storage system according to an example embodiment.

[0013] Figure 6B is a diagram showing an example embodiment of a reference table managed by a degradation controller included in a storage device according to an example embodiment.

[0014] Figure 7 is a block diagram showing a storage device according to an example embodiment.

[0015] Figure 8 is a diagram illustrating an example embodiment of an interface of a non-volatile memory device according to an example embodiment.

[0016] Figure 9 is a timing diagram illustrating an example embodiment of transmitting a command and an address in a storage device according to an example embodiment.

[0017] Figure 10 is a diagram illustrating a change in state of memory cells of a non-volatile memory device according to an example embodiment.

[0018] Figure 11 is a diagram illustrating Figure 10 an example of state bit mapping information indicating a mapping relationship between states and bit values in

[0019] Figure 12 is a block diagram illustrating a storage controller included in a storage device according to an example embodiment.

[0020] Figure 13 is a block diagram illustrating a non-volatile memory device according to an example embodiment.

[0021] Figure 14 is a block diagram illustrating a storage device according to an example embodiment.

[0022] Figure 15 is a circuit diagram illustrating an equivalent circuit of a memory block included in a non-volatile memory device according to an example embodiment.

[0023] Figure 16 is a circuit diagram illustrating a programming bias condition of a non-volatile memory device according to an example embodiment.

[0024] Figure 17 and Figure 18 is a diagram illustrating incremental step pulse programming (ISPP) of a non-volatile memory device according to an example embodiment.

[0025] Figure 19 is a timing diagram illustrating an example embodiment of a write operation of a non-volatile memory device according to an example embodiment.

[0026] Figure 20 is a diagram illustrating an example embodiment of adjusting a programming voltage of a storage device according to an example embodiment.

[0027] Figure 21 is a circuit diagram illustrating an erase bias condition of a non-volatile memory device according to an example embodiment.

[0028] Figure 22 and Figure 23Is a diagram showing incremental step pulse erase (ISPE) of a non-volatile memory device according to an exemplary embodiment.

[0029] Figure 24 Is a timing diagram of an exemplary embodiment showing an erase operation of a non-volatile memory device according to an exemplary embodiment.

[0030] Figure 25 Is a diagram showing an exemplary embodiment of adjusting an erase voltage of a storage device according to an exemplary embodiment.

[0031] Figure 26 And Figure 27 Is a diagram showing an exemplary embodiment of degradation information in a method of operating a storage device according to an exemplary embodiment.

[0032] Figure 28 Is a block diagram showing a data center including a storage device according to an exemplary embodiment. Detailed Description

[0033] Hereinafter, exemplary embodiments will be described with reference to the accompanying drawings. The embodiments described herein are provided as examples, and thus the present disclosure is not limited thereto and may be implemented in various other forms. Each exemplary embodiment provided in the following description does not exclude being associated with one or more features of another example or another exemplary embodiment that is also provided herein or not provided herein but consistent with the present disclosure. It will be understood that when an element or layer is referred to as being "on", "connected to", or "coupled to" another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly connected to", or "directly coupled to" another element or layer, no intervening elements or layers are present. Expressions such as "at least one of..." when following a list of elements modify the entire list of elements rather than a single element in the list. For example, the expression "at least one of a, b, and c" should be understood to include: only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0034] Figure 1 Is a flowchart showing a method of operating a storage device according to an exemplary embodiment. As will be described below, the storage device includes a non-volatile memory device and a storage controller configured to control the non-volatile memory device.

[0035] Refer to Figure 1, degradation information may be generated by measuring at least one of a program execution time for performing a write operation and an erase execution time for performing an erase operation of a non-volatile memory device (S100). In one example embodiment, as will be described below with reference to Figure 18 and Figure 19 described, degradation information may be generated by measuring the program execution time taken to perform a write operation. In another example embodiment, as will be described below with reference to Figure 23 and Figure 24 described, degradation information may be generated by measuring the erase execution time taken to perform an erase operation.

[0036] The degradation information may be transmitted (i.e., provided by the non-volatile memory device) from the non-volatile memory device to the storage controller (S200). In some example embodiments, as will be further described with reference to Figures 7 to 9 the non-volatile memory device and the storage controller may transmit commands and addresses via command address pins and transmit data via data pins different from the command address pins. In one example embodiment, the non-volatile memory device may transmit the degradation information to the storage controller via the command address pins.

[0037] The storage controller may control the non-volatile memory device to adjust at least one of a program voltage for a write operation and an erase voltage for an erase operation based on the degradation information (S300).

[0038] In one example embodiment, as will be described below with reference to Figure 2 , Figure 3 and Figure 20 described, the storage controller may control the non-volatile memory device based on the measured program execution time: as the degree of degradation of the non-volatile memory device increases (i.e., as the measured program execution time included in the degradation information decreases), the program voltage is reduced. By reducing the program voltage of the non-volatile memory device based on the degradation information to reflect the actual degree of degradation, the storage controller can reduce the stress on the non-volatile memory cells and improve the performance and lifespan of the non-volatile memory device and the storage device.

[0039] In another example embodiment, as will be described below with reference to Figure 4 , Figure 5 and Figure 25As described, the storage controller may control the non-volatile memory device based on the measured erase execution time: as the degradation degree of the non-volatile memory device included in the degradation information increases (i.e., as the measured erase execution time increases), the erase voltage is increased. Based on the measured degradation information, the storage controller may increase the erase voltage of the non-volatile memory device to reflect the actual degradation degree, thereby reducing the erase time of the non-volatile memory device and improving the performance of the non-volatile memory device and the storage device.

[0040] Figure 2 and Figure 3 is a diagram showing an example embodiment of adjusting the programming voltage of a storage device according to an example embodiment.

[0041] Figure 2 Shows the general trend of the optimal programming voltage VPGM as a function of the program / erase count (or program / erase cycle) P / E of the non-volatile memory device. As the program / erase count P / E increases, as electrons are repeatedly pulled in and out of the nitride floating gate of the memory cells in the non-volatile memory device, electrons are trapped in the tunneling oxide between the floating gate and the channel. Therefore, when the program / erase count P / E increases, the trapped electrons accelerate the programming (i.e., writing) operation. In this regard, increasing the program / erase count P / E makes programming easier, and if the same programming voltage VPGM is maintained, the stress on the memory cells may increase unnecessarily.

[0042] Figure 3 Shows an example embodiment of adjusting the programming voltage VPGM of a storage device according to an example embodiment. Referring to Figure 3 , the storage controller may control the non-volatile memory device based on the degradation information such that the programming voltage VPGM decreases as the degradation degree of the non-volatile memory device increases. In one example embodiment, the degradation information may be updated whenever the program / erase count P / E reaches each of the threshold counts N11, N12, and N13, respectively, and the programming voltage VPGM may decrease in a stepwise manner as shown in Figure 3 in response to the update of the degradation information.

[0043] Figure 4 and Figure 5 is a diagram showing an example embodiment of adjusting the erase voltage of a storage device according to an example embodiment.

[0044] Figure 4Shows the overall trend of the optimal erase voltage VERS as a function of the program / erase count (P / E) of a non-volatile memory device. As described above, as the program / erase count (P / E) increases, as electrons are repeatedly placed into and removed from the nitride floating gate of the memory cells of the non-volatile memory device, electrons are trapped in the tunneling oxide between the floating gate and the channel. Thus, as the program / erase count (P / E) increases, the erase rate slows down due to the trapped electrons. In this regard, as the program / erase count (P / E) increases, erasing becomes more difficult, and when maintaining the same erase voltage VERS, the erase time increases unnecessarily.

[0045] Figure 5 Shows an example embodiment of adjusting the erase voltage VERS of a storage device according to an example embodiment. Referring to Figure 5 , the storage controller may control the non-volatile memory device based on the degradation information such that the erase voltage VERS increases as the degree of degradation of the non-volatile memory device increases. In one example embodiment, the degradation information may be updated whenever the program / erase count reaches each of the reference counts N21, N22, and N23, respectively, and the erase voltage VERS may increase incrementally as shown in Figure 5 .

[0046] The operating voltage of the non-volatile memory device may be uniformly adjusted based on the program / erase count (P / E). In this case, since it is impossible to reflect the degradation characteristics of the corresponding non-volatile memory device, depending on the non-volatile memory device, the stress on the memory cells may increase or the operating speed may decrease.

[0047] According to an example embodiment, the performance and lifespan of the storage device can be improved by measuring at least one of the program execution time and the erase execution time to provide degradation information indicating the actual degree of degradation of the non-volatile memory device, and adjusting the program voltage VPGM and / or the erase voltage VERS based on the measured degradation information to reflect the actual degree of degradation.

[0048] Figure 3 and Figure 5An example embodiment showing the measurement of the programming execution time tPROG and / or the erasure execution time tERS based on the programmed erase count P / E is shown, but the example embodiment is not limited thereto. According to the example embodiment, the non-volatile memory device may measure the programming execution time tPROG and / or the erasure execution time tERS in response to a request from a host device or a storage controller. For example, the non-volatile memory device may also measure the programming execution time tPROG and / or the erasure execution time tERS in response to a request from a host device or a storage controller to update the degradation information. The programming execution time tPROG and / or the erasure execution time tERS may be performed during normal operation of the non-volatile memory device, or may be performed during a test operation of the non-volatile memory device.

[0049] Figure 6A is a block diagram showing a storage system according to an example embodiment, and Figure 6B is a diagram showing an example embodiment of a reference table managed by a degradation controller included in a storage device according to an example embodiment.

[0050] Referring to Figure 6A , the storage system 1000 may include a host device 1100, a storage device 1200, and a link 30 connecting the host device 1100 and the storage device 1200. The storage device 1200 may include a storage controller 100 and a non-volatile memory device 400. The non-volatile memory device 400 may include a degradation detector DMT (i.e., a degradation detector circuit system), and the degradation detector DMT may generate degradation information DINF by measuring at least one of the programming execution time spent performing a write operation and the erasure execution time spent performing an erase operation.

[0051] The degradation information DINF generated by the non-volatile memory device 400 may be sent to the storage controller 100. The storage controller 100 may include a degradation controller DCON, and the degradation controller DCON may adjust the programming voltage VPGM and / or the erasure voltage VERS of the non-volatile memory device 400 based on the degradation information DINF. According to the example embodiment, the degradation controller DCON may be implemented in the form of hardware or firmware.

[0052] The storage controller 100 may manage the degradation information DINF as part of the metadata. The metadata is different from the user data stored in the non-volatile memory device 400 in response to the request of the host device 1100, and is generated and managed by the firmware of the storage controller 100 to manage the user data or the data of the non-volatile memory device 400. The metadata may include a mapping table representing the mapping relationship between the logical address of the host device 1100 and the physical address of the non-volatile memory 400. In addition, the metadata may include other information for managing the memory space of the non-volatile memory device 400.

[0053] The metadata may be loaded from the non-volatile memory device 400 when the storage system 1000 is powered on and stored in the memory of the storage controller 100 (e.g., volatile memory such as dynamic random access memory (DRAM) or static random access memory (SRAM)). The metadata stored in the non-volatile memory device 400 may be referred to as non-volatile metadata NVMDT, and the metadata stored in the storage controller 100 may be referred to as firmware metadata FMDT. The firmware metadata FMDT may change during the operation of the storage device 1200, and a logging technique may be used to maintain the consistency between the firmware metadata FMDT and the non-volatile metadata NVMDT.

[0054] Referring to Figure 6B , the degradation controller DCON may manage a reference table RFTB representing the mapping relationship between a plurality of time periods indicating the programming execution time tPROG and the programming voltage VPGM. The reference table RFTB may be generated by testing the non-volatile memory device and stored in the storage device 1200. Figure 6B The case where the degradation information DINF indicates the programming execution time tPROG is shown, but the exemplary embodiments are not limited thereto.

[0055] If the measured programming execution time tPROG is greater than the first time t1, the degradation controller DCON may set the programming voltage VPGM to the first voltage level VL1. If further degradation occurs and the measured programming execution time tPROG is greater than the second time t2 and less than or equal to the first time t1, the degradation controller DCON may set the programming voltage VPGM to a second voltage level VL2 lower than the first voltage level VL1. If the degradation further progresses and the measured programming execution time tPROG is greater than the third time t3 and less than or equal to the second time t2, the degradation controller DCON may set the programming voltage VPGM to a third voltage level VL3 lower than the second voltage level VL2.

[0056] In this way, by reducing the programming voltage of the non-volatile memory device based on the degradation information measured above to reflect the actual degradation degree, the stress on the non-volatile memory cells can be reduced, and the performance and lifespan of the non-volatile memory device and the storage device can be improved.

[0057] For example, the storage device 1200 can be a solid state drive (SSD), an embedded multimedia card (eMMC), a universal flash storage (UFS) device, etc. In one example embodiment, the link 30 can be a peripheral component interconnect (PCI) express (PCIe) link.

[0058] The host device 1100 can be a data processing device capable of processing data (such as a central processing unit (CPU), a processor, a microprocessor, or an application processor). The storage device 1200 can be embedded in an electronic device having the host device 1100, or it can be removably electrically connected to an electronic device including the host device 1100.

[0059] The host device 1100 can send a data access request (i.e., request REQ) and a logical address LADD to the storage controller 100, and can send data DTA to the storage controller 100 and receive data DTA from the storage controller 100. The storage controller 100 can send a response RSND to the host device 1100 in response to the data access request REQ. The data access request REQ can include a data read request, a data write request, and a data erase request.

[0060] The storage controller 100 can control the non-volatile memory device 400 in response to a request REQ from the host device 1100. By providing the non-volatile memory device 400 with an address ADDR (i.e., physical address PADD) mapped to the logical address LADD, a command CMD, and a control signal CTRL, the storage controller 100 can perform a read operation and a write operation on the non-volatile memory device 400. The write operation can be referred to as a programming operation. For example, the storage controller 100 can perform a flash translation layer (FTL) operation to convert the logical address LADD sent from the host device 1100 into a physical address PADD.

[0061] For example, the storage controller 100 may control the non-volatile memory device 400 to read data stored in the non-volatile memory device 400 in response to a data read request received from the host device 1100, or may control the non-volatile memory device 400 to write data to the non-volatile memory device 400 in response to a data write request received from the host device 1100. In addition, in response to an erase request received from the host device 1100, the non-volatile memory device 400 may be controlled to erase the data stored in the non-volatile memory device 400. The non-volatile memory device 400 may send a response RSND in response to the command CMD to the storage controller 100.

[0062] The non-volatile memory device 400 may be implemented using one or more non-volatile memories NVM (such as flash memory, magnetic RAM (MRAM), ferroelectric RAM (FeRAM), phase change RAM (PRAM), and resistive RAM (ReRAM)). The non-volatile memory device 400 may be connected to the storage controller 100 via a plurality of channels. For ease of description, the non-volatile memory device 400 may be illustrated and described below as a non (NAND) flash memory device.

[0063] Figure 7 is a block diagram showing a storage device according to an exemplary embodiment.

[0064] Referring to Figure 7 , the storage device 1200 may include a storage controller 100 and a non-volatile memory device 400. As will be referred to below Figure 14 described, the non-volatile memory device 400 may correspond to one of a plurality of non-volatile memory devices NVM11 to NVMmn that communicate with the storage controller 620 based on one of a plurality of channels CH1 to CHm. The storage controller 100 may correspond to Figure 6A the storage controller 100.

[0065] The non-volatile memory device 400 may include a memory interface circuit (MIF) 450, first pins P11 to fifth pins P15 connected to the memory interface circuit (MIF) 450, a memory cell array 410, and a control circuit 460. The memory interface circuit 450 may send and receive a command address signal CA[1] and CA[0], a data signal DQ[7:0], a command address clock signal CA_CLK, and a status signal R / B via the first pins P11 to fifth pins P15. The command address clock signal CA_CLK may be referred to as a command address strobe signal, and the status signal R / B may be referred to as a ready busy signal.

[0066] The memory interface circuit 450 may receive command address signals CA[1] and CA[0] from the memory controller 100 via a first pin P11 and a second pin P12 corresponding to command address pins. The memory interface circuit 450 may receive data signals DQ[7:0] from the memory controller 100 via a third pin P13 corresponding to data pins and transmit the data signals DQ[7:0] to the memory controller 100. Additionally, the memory interface circuit 450 may receive a command address clock signal CA_CLK from the memory controller 100 via a fourth pin P14 and transmit a status signal R / B to the memory controller 100 via a fifth pin P15 corresponding to a status pin.

[0067] The command address clock signal CA_CLK may be maintained in a static state (e.g., high level or low level) and then switch between high and low levels at a specific interval. For example, the command address clock signal CA_CLK may switch during an interval when transmitting a command CMD or an address ADDR. In this case, the memory interface circuit 450 may sample the command CMD or the address ADDR based on the command address clock signal CA_CLK. For example, the memory interface circuit 450 may sample the command CMD or the address ADDR during an interval when the command address clock signal CA_CLK switches.

[0068] The control circuit 460 may provide overall control for various operations of the non-volatile memory device 400. The control circuit 460 may receive a command / address CMD / ADDR obtained from the memory interface circuit 450. The control circuit 460 may generate control signals based on the received command / address CMD / ADDR to control other components of the non-volatile memory device 400. For example, the control circuit 460 may generate various control signals to program data into the memory cell array 410 or read data from the memory cell array 410.

[0069] The memory cell array 410 may store data DTA obtained from the memory interface circuit 450 under the control of the control circuit 460. Additionally, the memory cell array 410 may output the stored data DTA to the memory interface circuit 450 under the control of the control circuit 460.

[0070] The memory cell array 410 may include a plurality of non-volatile memory cells. For example, the plurality of memory cells may be flash memory cells. However, the example embodiments are not limited thereto, and the memory cells may be resistive random access memory (RRAM) cells, ferroelectric random access memory (FRAM) cells, phase change random access memory (PRAM) cells, thyristor random access memory (TRAM) cells, or magnetic random access memory (MRAM) cells. In the present disclosure, the example embodiments will be described focusing on the case where the memory cells are NAND flash memory cells.

[0071] The storage controller 100 may include a memory interface circuit 150 and first to fifth pins P21 to P25 connected to the memory interface circuit 150. The first to fifth pins P21 to P25 may respectively correspond to the first to fifth pins P11 to P15 of the non-volatile memory device 400. Accordingly, the memory interface circuit 150 may transmit command address signals CA[1] and CA[0], data signals DQ[7:0], and a command address clock signal CA_CLK via the first to fifth pins P21 to P25, and receive a status signal R / B.

[0072] Figure 8 is a diagram illustrating an example embodiment of an interface of a non-volatile memory device according to an example embodiment, and Figure 9 is a timing diagram illustrating an example embodiment of transmitting commands and addresses in a storage device according to an example embodiment.

[0073] Referring to Figure 8 , the memory interface circuit 450 may include buffers 311a to 311g and first to third flip-flops 312a to 312c.

[0074] The command address signals CA[1] and CA[0] and the data signals DQ[7:0] received via the first to third pins P11 to P13 may be provided to the first, second, and third flip-flops 312a, 312b, and 312c via buffers 311a, 311c, and 311e, respectively. The command address clock signal CA_CLK received through the fourth pin P14 may be provided to the first, second, and third flip-flops 312a, 312b, and 312c via buffer 311g. As Figure 9 shown, the first, second, and third flip-flops 312a, 312b, and 312c may sample the command address signals CA[1] and CA[0] and the data signals DQ[7:0] at the rising and falling edges of the command address clock signal CA_CLK, and output the sampled command CMD, address ADDR, and write data WDTA.

[0075] According to an example embodiment, the memory interface circuit 450 may send the degradation information DINF of the non-volatile memory device 400 to the storage controller 100 via at least one of the first pin P11 and the second pin P12. For example, as Figure 8 shown, the buffers 311b and 311d may send the command address signals CA[1] and CA[0] including the degradation information DINF to the storage controller 100. In this way, the communication between the non-volatile memory device and the storage controller can be efficiently performed by carrying the degradation information DINF and the data DTA on different pins. For example, when the data DTA is sent from the non-volatile memory device (e.g., Figure 14 the non-volatile memory device NVM11) to the storage controller 100, the degradation information DINF of another non-volatile memory device (e.g., Figure 14 the non-volatile memory device NVM12) can be provided to the storage controller 100 from another non-volatile memory device (e.g., Figure 14 the non-volatile memory device NVM12). In some example embodiments, the buffer 311f may send the data signal DQ[7:0] including the read data RDTA to the storage controller 100.

[0076] Referring to Figure 9 , the commands and addresses sent through the command address signals CA[1] and CA[0] may be sent in the form of packets. Each packet may include a header and a body, and each bit may be sampled synchronously with the rising edge and the falling edge of the command address clock signal CA_CLK.

[0077] The header may include four bits h0 to h3, and the body may include eight bits b0 to b7. According to the values of the bits h0 to h3 in the header, the bits b0 to b7 in the body may be classified as commands CMD, addresses ADDR, etc.

[0078] Referring to Figures 7 to 9 the interface between the non-volatile memory device and the storage controller described may conform to the separate command address (SCA) protocol. According to the SCA protocol, the data signal and the command address signal may be sent on separate data pins and command address pins. In some example embodiments, the non-volatile memory device may be a NAND flash device operating according to the SCA protocol.

[0079] Figure 10 is a diagram showing the state change of the memory cells of the non-volatile memory device according to an example embodiment.

[0080] In Figure 10In this figure, the horizontal axis represents the threshold voltage VTH of the memory cells, and the vertical axis represents the number of memory cells corresponding to the threshold voltage VTH. Although Figure 10 a three-level cell (TLC) scheme is shown in which each memory cell stores a 3-bit value, the exemplary embodiments are not limited thereto, and the number of bits stored in each selected memory cell can be determined differently.

[0081] Referring to Figure 10 , the memory cells can be erased to an erased state S0 having a threshold voltage lower than the erase verification voltage VVE through an erase operation ERO.

[0082] Thereafter, a programming operation PRO can be performed such that each memory cell corresponds to one state corresponding to the written data among the first state S1 to the eighth state S8. Here, the first state S1 corresponds to the erased state. During the programming operation PRO, the programming execution results of the first state S1 to the eighth state S8 can be determined by sequentially applying the first verification read voltage VVR1 to the seventh verification read voltage VVR7 to the selected word line. Additionally, during the read operation, each bit of the first state S1 to the eighth state S8 can be determined by sequentially applying the normal read voltages VR1 to VR7 to the selected word line.

[0083] Figure 11 is a diagram showing an example of state bit mapping information indicating the mapping relationship between the states and bit values in Figure 10 .

[0084] Referring to Figure 11 , the state bit mapping information SBM can indicate the mapping relationship between the states and bits stored in multiple three-level cells. Figure 11 shows an example of the bit values corresponding to the first state S1 to the eighth state S8 in Figure 10 . The first state S1 to the eighth state S8 can be represented by different values corresponding to the least significant bit (LSB), the middle bit (CSB), and the most significant bit (MSB) (i.e., different values of the first bit LSB, the second bit CSB, and the third bit MSB). For example, as shown in Figure 11 , the first state S1 corresponds to "111", the second state S2 corresponds to "110", the third state S3 corresponds to "100", the fourth state S4 corresponds to "000", the fifth state S5 corresponds to "010", the sixth state S6 corresponds to "011", the seventh state S7 corresponds to "001", and the eighth state S8 corresponds to "101".

[0085] In this case, the first read voltage VR1 and the fifth read voltage VR5 may be used to determine the first least significant bit LSB, the second read voltage VR2, the fourth read voltage VR4, and the sixth read voltage VR6 may be used to determine the second complementary significant bit CSB, and the third read voltage VR3 and the seventh read voltage VR7 may be used to determine the third most significant bit MSB.

[0086] As the memory cells degrade, the read margin or read window RW may become narrower. As the read window RW narrows, the error increases in determining the first erased state S1 and the second programmed state S2, and the performance of the non-volatile memory device may deteriorate. According to an example embodiment, the stress on the memory cells may be reduced by adjusting the programming voltage and / or the erase voltage to reflect the actual degradation degree of the memory cells, thereby reducing the degradation of the memory cells.

[0087] Figure 12 is a block diagram showing a memory controller included in a storage device according to an example embodiment.

[0088] Referring to Figure 12 , the memory controller 100 may include a processor 110, a buffer memory (BUFF) 140, a degradation controller (DCON) 130, a host interface (HIF) 120, an error correction code (ECC) engine 170, a memory interface (MIF) circuit 150, an advanced encryption standard (AES) engine 180, and an internal bus system 160 that connects the components in the memory controller 100.

[0089] The processor 110 may control the operation of the memory controller 100 in response to a command received via the host interface 120 from a host device (e.g., Figure 6A the host device 1100 in Figure 6A ). For example, the processor 110 may control the operation of the storage device (e.g.,

[0090] the storage device 1200 in

[0091] The buffer memory 140 may store instructions and data executed and processed by the processor 110. For example, the buffer memory 140 may be implemented using a volatile memory such as DRAM, SRAM, cache, etc.

[0091] The ECC engine 170 for error correction can perform encoding modulation using Bose-Chaudhuri-Hocquenghem (BCH) codes, low-density parity-check (LDPC) codes, turbo codes, Reed-Solomon codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), block-coded modulation (BCM), and the like. In some example embodiments, the ECC engine 170 can perform ECC encoding and ECC decoding using the above codes or other error-correction codes.

[0092] The host interface 120 can provide a physical connection between the host device 1100 and the storage device 1200. The host interface 120 can provide an interface corresponding to the bus format of the host device 1100 to communicate between the host device 1100 and the storage device 1200. In some example embodiments, the bus format of the host device 1100 can be a Small Computer System Interface (SCSI) or a Serial Attached SCSI (SAS) interface. In other example embodiments, the bus format of the host device can be a Universal Serial Bus (USB), PCIe, Advanced Technology Attachment (ATA), Parallel ATA (PATA), Serial ATA (SATA), Non-Volatile Memory (NVM) Express (NVMe), or other formats.

[0093] The memory interface circuit 150 can exchange data with a non-volatile memory device (e.g., Figure 6A the non-volatile memory device 400 in

[0094] The AES engine 180 can perform at least one of an encryption operation and a decryption operation on data input to the storage controller 100 using a symmetric key algorithm. The AES engine 180 can include an encryption module and a decryption module. For example, the encryption module and the decryption module can be implemented as separate modules. In another example, a single module capable of performing both the encryption operation and the decryption operation can be implemented in the AES engine 180.

[0095] As described above, the non-volatile memory device 400 may measure the programming execution time and / or the erasing execution time, and provide the degradation information DINF to the storage controller 100, and the degradation controller 130 in the storage controller 100 may adjust the programming voltage VPGM and / or the erasing voltage VERS of the non-volatile memory device 400 based on the degradation information DINF. In some example embodiments, the degradation controller 130 may be implemented in the form of hardware or firmware.

[0096] Figure 13 is a block diagram showing a non-volatile memory device according to an example embodiment.

[0097] Referring to Figure 13 , the non-volatile memory 500 includes a memory cell array 510, an address decoder 520, a page buffer circuit 530, a data I / O circuit 540, a voltage generator 550, a control circuit 560, and a degradation detector DMT 570.

[0098] The memory cell array 510 is connected to the address decoder 520 via a plurality of string selection lines SSL, a plurality of word lines WL, and a plurality of ground selection lines GSL. The memory cell array 510 is also connected to the page buffer circuit 530 via a plurality of bit lines BL. The memory cell array 510 may include a plurality of memory cells (e.g., a plurality of non-volatile memory cells) connected to the plurality of word lines WL and the plurality of bit lines BL. The memory cell array 510 may be divided into a plurality of memory blocks BLK1, BLK2,..., BLKz, each memory block including memory cells. Additionally, each of the plurality of memory blocks BLK1, BLK2,..., BLKz may be divided into a plurality of pages.

[0099] In some example embodiments, the plurality of memory cells included in the memory cell array 510 may be arranged in a two-dimensional (2D) array structure or a three-dimensional (3D) vertical array structure. The memory cell array having a 3D vertical array structure will be described below with reference to Figure 15 description.

[0100] The control circuit 560 receives a command CMD and an address ADDR from an external source (e.g., from the Figure 6A storage controller 100 therein), and controls the erasing operation, the writing operation, and the reading operation of the non-volatile memory 500 based on the command CMD and the address ADDR. The writing operation may include performing a series of programming cycles, and the erasing operation may include performing a series of erasing cycles. Each programming cycle may include a programming operation and a programming verification operation. Each erasing cycle may include an erasing operation and an erasing verification operation. The reading operation may include a normal reading operation and a data recovery reading operation.

[0101] For example, the control circuit 560 may generate a control signal CON for controlling the voltage generator 550 based on the command CMD, may generate a control signal PBC for controlling the page buffer circuit 530, and may generate a row address R_ADDR and a column address C_ADDR based on the address ADDR. The control circuit 560 may provide the row address R_ADDR to the address decoder 520 and may provide the column address C_ADDR to the data I / O circuit 540.

[0102] The address decoder 520 may be connected to the memory cell array 510 via a plurality of string selection lines SSL, a plurality of word lines WL, and a plurality of ground selection lines GSL.

[0103] For example, in a data erase / write / read operation, the address decoder 520 may determine at least one of the plurality of word lines WL as a selected word line based on the row address R_ADDR, and may determine the remaining word lines other than the selected word line as unselected word lines.

[0104] In addition, in a data erase / write / read operation, the address decoder 520 may determine at least one of the plurality of string selection lines SSL as a selected string selection line based on the row address R_ADDR, and may determine the remaining string selection lines other than the selected string selection line as unselected string selection lines.

[0105] Furthermore, in a data erase / write / read operation, the address decoder 520 may determine at least one of the plurality of ground selection lines GSL as a selected ground selection line based on the row address R_ADDR, and may determine the remaining ground selection lines other than the selected ground selection line as unselected ground selection lines.

[0106] The voltage generator 550 may generate a voltage VS required for the operation of the non-volatile memory 500 based on the power PWR and the control signal CON. The voltage VS may be applied to the plurality of string selection lines SSL, the plurality of word lines WL, and the plurality of ground selection lines GSL via the address decoder 520. In addition, the voltage generator 550 may generate an erase voltage VERS required for a data erase operation based on the power PWR and the control signal CON. The erase voltage may be applied directly or via the bit line BL to the memory cell array 510.

[0107] For example, during an erase operation, the voltage generator 550 may apply the erase voltage to the common source line and / or the bit line BL of a memory block (e.g., a selected memory block), and may apply an erase permission voltage (e.g., ground voltage) to all or a part of the word lines of the memory block via the address decoder 520. In addition, during an erase verification operation, the voltage generator 550 may apply the erase verification voltage to all the word lines of the memory block simultaneously, or may apply the erase verification voltage to the word lines one by one sequentially.

[0108] For example, during a programming operation, the voltage generator 550 may apply a programming voltage to a selected word line via the address decoder 520, and may apply a programming pass voltage to unselected word lines. Additionally, during a programming verification operation, the voltage generator 550 may apply a programming verification voltage to a selected word line via the address decoder 520, and may apply a verification pass voltage to unselected word lines.

[0109] Furthermore, during a normal read operation, the voltage generator 550 may apply a read voltage to a selected word line via the address decoder 520, and may apply a read pass voltage to unselected word lines. During a data recovery read operation, the voltage generator 550 may apply a read voltage to word lines adjacent to a selected word line via the address decoder 520, and may apply a recovery read voltage to the selected word line.

[0110] The page buffer circuit 530 may be connected to the memory cell array 510 via a plurality of bit lines BL. The page buffer circuit 530 may include a plurality of page buffers. In some example embodiments, each page buffer may be connected to one bit line. In other example embodiments, each page buffer may be connected to two or more bit lines.

[0111] The page buffer circuit 530 may store data DAT to be programmed into the memory cell array 510, or may read data DAT sensed (i.e., read) from the memory cell array 510. In this regard, the page buffer circuit 530 may operate as a write driver or a sense amplifier according to the operation mode of the non-volatile memory 500.

[0112] The data I / O circuit 540 may be connected to the page buffer circuit 530 via data lines DL. The data I / O circuit 540 may provide data DAT from outside the non-volatile memory 500 to the memory cell array 510 via the page buffer circuit 530 based on a column address C_ADDR, or may provide data DAT from the memory cell array 510 to the outside of the non-volatile memory 500.

[0113] The control circuit 560 activates the status signal R / B to a first logic level indicating a ready state when not performing internal operations for a write operation or an erase operation, and deactivates the status signal R / B to a second logic level indicating a busy state when performing internal operations. Here, the internal operations may include a voltage application operation of applying a programming voltage VPGM or an erase voltage VERS to the memory cell array 510, and a verification operation of applying a programming verification voltage or an erase verification voltage to the memory cell array to check the result of the voltage application operation. The status signal R / B may be provided to an external storage controller.

[0114] The degradation detector DMT 570 can generate degradation information DINF by measuring at least one of the programming execution time required to perform a write operation and the erase execution time required to perform an erase operation. In one example embodiment, the degradation detector DMT 570 can generate degradation information DINF based on the status signal R / B. In some example embodiments, the degradation detector DMT 570 can generate degradation information DINF by identifying at least one of the programming execution time for performing a write operation and the erase execution time for performing an erase operation based on the status signal R / B.

[0115] Although the non-volatile memory is described based on NAND flash memory, the example embodiments are not limited thereto, and the non-volatile memory can be any non-volatile memory (e.g., phase change random access memory (PRAM), resistive random access memory (RRAM), nano floating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), thyristor random access memory (TRAM), etc.).

[0116] Figure 14 is a block diagram showing a storage device according to an example embodiment.

[0117] Referring to Figure 14 , the storage device 600 may include a non-volatile memory device 610 and a storage controller 620. The storage device 600 can support multiple channels CH1, CH2, ……, CHm, and the non-volatile memory device 610 can be connected to the storage controller 620 through the multiple channels CH1 to CHm. For example, the storage device 600 can be implemented as a universal flash storage (UFS), a solid state drive (SSD), etc.

[0118] The non-volatile memory device 610 may include a plurality of non-volatile memories NVM11, NVM12, ……, NVM1n, NVM21, NVM22, ……, NVM2n, NVMm1, NVMm2, ……, NVMmn. Each of the non-volatile memories NVM11 to NVMmn may be connected to one of the plurality of channels CH1 to CHm through its corresponding path. For example, the non-volatile memories NVM11 to NVM1n may be connected to the first channel CH1 through paths W11, W12, ……, W1n, the non-volatile memories NVM21 to NVM2n may be connected to the second channel CH2 through paths W21, W22, ……, W2n, and the non-volatile memories NVMm1 to NVMmn may be connected to the m-th channel CHm through paths Wm1, Wm2, ……, Wmn. In some example embodiments, each of the non-volatile memories NVM11 to NVMmn may be implemented as a memory cell that can operate according to a separate command from the storage controller 620. For example, each of the non-volatile memories NVM11 to NVMmn may be implemented as a chip or a die, but the example embodiments are not limited thereto.

[0119] The storage controller 620 may send signals to and receive signals from the non-volatile memory device 610 through the plurality of channels CH1 to CHm. For example, the storage controller 620 may send commands CMDa, CMDb, ……, CMDm, addresses ADDRa, ADDRb, ……, ADDRm, and data DATAa, DATAb, ……, DATAm to the non-volatile memory device 610 through the channels CH1 to CHm, or may receive data DATAa to DATAm from the non-volatile memory device 610 through the channels CH1 to CHm.

[0120] The storage controller 620 may use a corresponding one of the channels CH1 to CHm to select one of the non-volatile memories NVM11 to NVMmn connected to each of the channels CH1 to CHm, and may send signals to and receive signals from the selected non-volatile memory. For example, the storage controller 620 may select the non-volatile memory NVM11 from among the non-volatile memories NVM11 to NVM1n connected to the first channel CH1. The storage controller 620 may send the command CMDa, the address ADDRa, and the data DATAa to the selected non-volatile memory NVM11 through the first channel CH1, or may receive the data DATAa from the selected non-volatile memory NVM11 through the first channel CH1.

[0121] The memory controller 620 can send signals to and receive signals from the non-volatile memory device 610 in parallel through different channels. For example, the memory controller 620 can send command CMDa to the non-volatile memory device 610 through the first channel CH1 while sending command CMDb to the non-volatile memory device 610 through the second channel CH2. For example, the memory controller 620 can receive data DATAa from the non-volatile memory device 610 through the first channel CH1 while receiving data DATAb from the non-volatile memory device 610 through the second channel CH2.

[0122] The memory controller 620 can control the overall operation of the non-volatile memory device 610. The memory controller 620 can send signals to channels CH1 to CHm and can control each of the non-volatile memories NVM11 to NVMmn connected to channels CH1 to CHm. For example, the memory controller 620 can send command CMDa and address ADDRa to the first channel CH1 and can control one selected from among the non-volatile memories NVM11 to NVM1n.

[0123] Each of the non-volatile memories NVM11 to NVMmn can operate under the control of the memory controller 620. For example, the non-volatile memory NVM11 can program data DATAa based on command CMDa, address ADDRa, and data DATAa provided from the memory controller 620 through the first channel CH1. For example, the non-volatile memory NVM21 can read data DATAb based on command CMDb and address ADDRb provided from the memory controller 620 through the second channel CH2 and can send the read data DATAb to the memory controller 620 through the second channel CH2.

[0124] Although Figure 14 an example is shown in which the non-volatile memory device 610 communicates with the memory controller 620 through m channels and includes n non-volatile memories corresponding to each channel, the example embodiment is not limited thereto, and the number of channels and the number of non-volatile memories connected to one channel can be changed differently.

[0125] Figure 15 is a circuit diagram showing an equivalent circuit of a memory block included in a non-volatile memory device according to an example embodiment.

[0126] Refer to Figure 15, each memory block BLKi included in the memory cell array may be formed on a substrate in a three-dimensional structure (or vertical structure). For example, the NAND strings or cell strings included in the memory block BLKi may be formed in a vertical direction D3 perpendicular to the upper surface of the substrate. The first direction D1 and the second direction D2 are parallel to the upper surface of the substrate.

[0127] The memory block BLKi may include NAND strings NS11 to NS33 coupled between bit lines BL1, BL2, and BL3 and a common source line CSL. Each of the NAND strings NS11 to NS33 may include a string select transistor SST, memory cells MC1 to MC8, and a ground select transistor GST. In Figure 15 , each of the NAND strings NS11 to NS33 is shown as including eight memory cells MC1 to MC8. However, the example embodiments are not limited thereto, and each of the NAND strings NS11 to NS33 may include various numbers of memory cells.

[0128] Each string select transistor SST may be connected to a corresponding string select line (one of SSL1 to SSL3). The memory cells MC1 to MC8 may be respectively connected to corresponding gate lines GTL1 to GTL8. The gate lines GTL1 to GTL8 may be word lines, and some of the gate lines GTL1 to GTL8 may be dummy word lines. Each ground select transistor GST may be connected to a corresponding ground select line (one of GSL1 to GSL3). Each string select transistor SST may be connected to a corresponding bit line (e.g., one of BL1, BL2, and BL3), and each ground select transistor GST may be connected to the common source line CSL.

[0129] Word lines having the same height (e.g., GTL1) may be commonly connected, the ground select lines GSL1 to GSL3 may be separated, and the string select lines SSL1 to SSL3 may be separated. In Figure 15 , the memory block BLKi is shown as being coupled to eight gate lines GTL1 to GTL8 and three bit lines BL1 to BL3. However, the example embodiments are not limited thereto, and each memory block in the memory cell array 510 may be coupled to various numbers of word lines and various numbers of bit lines.

[0130] Figure 16 is a circuit diagram showing a programming bias condition of a non-volatile memory device according to an example embodiment.

[0131] For ease of description, in Figure 16 , the NAND strings NS11 and NS21 connected to the first bit line BL1 and the NAND strings NS12 and NS22 connected to the second bit line BL2 are shown.

[0132] The first bit line BL1 may be a programmed bit line to which a programming enable voltage (e.g., 0V) is applied, and the second bit line BL2 may be a programmed inhibit bit line to which a programming inhibit voltage (such as the power supply voltage VCC) is applied. During a programming operation, if the NAND string NS21 among the NAND strings NS11 and NS21 is selected, a voltage of 0V may be applied to the first string select line SSL1, and the power supply voltage VCC may be applied to the second string select line SSL2.

[0133] A voltage of 0V may be applied to the ground select lines GSL1 and GSL2 and the common source line CSL. A programming voltage VPGM (e.g., 18V) may be applied to the selected word line (e.g., WL5), and a pass voltage VPASS (e.g., 8V) may be applied to the unselected word lines (e.g., WL4 and WL6).

[0134] Under programming bias conditions, a programming voltage VPGM of 18V may be applied to the gate of the memory cell A having a channel voltage of 0V. Since a strong electric field is formed between the gate and the channel of the memory cell A, the memory cell A may be programmed. However, since the corresponding channels of the memory cells C and D are in a floating state, their channel voltages may be raised to, for example, approximately 8V, and thus, the memory cells C and D may not be programmed. Since a weak electric field is formed between the gate and the channel of the memory cell B, the memory cell B may not be programmed. Figure 13 The voltage generator 550 in may generate the programming voltage VPGM and the programming pass voltage VPASS applied to multiple word lines during a programming operation.

[0135] Figure 17 and Figure 18 are diagrams showing incremental step pulse programming (ISPP) of a non-volatile memory device according to an exemplary embodiment.

[0136] Referring to Figure 17 and Figure 18 , according to ISPP, a programming operation PRO may be performed by sequentially executing a plurality of programming cycles PLOOP(1), PLOOP(2), PLOOP(3),... until data programming is completed. As the programming cycles are repeated, the programming voltages VPGM1, VPGM2, VPGM3,... may be gradually increased.

[0137] Each programming loop PLOOP(i) may include a programming period and a verification period. During the programming period, programming execution operations may be performed to apply programming voltages VPGM1, VPGM2, VPGM3, … to selected word lines to program selected memory cells. Subsequently, during the verification period, programming verification operations may be performed to apply a programming verification output voltage VVR to the selected word lines to verify the success of the programming.

[0138] Referring to Figure 13 and Figure 18 When the write data is stored in the page buffer circuit 530 and the non-volatile memory 500 is ready to perform internal operations for programming the write data, the control circuit 560 may deactivate the status signal R / B to a second logic level (e.g., logic low level L) (S10).

[0139] The control circuit 560 may initialize the loop number (i) to 1, thereby enabling the execution of the first programming loop PLOOP(1) (S11), applying the programming voltage VPGMi corresponding to the i-th programming loop to the selected word line (S12), and then applying the programming verification output voltage VVR to the selected word line (S13). The control circuit 560 may determine whether a pass condition is satisfied (S14).

[0140] If the pass condition is satisfied (S14: yes), the control circuit 560 may activate the status signal R / B to a first logic level (e.g., logic high level H) and terminate the internal operations for programming (S17).

[0141] If the pass condition is not satisfied (S14: no), the control circuit 560 may determine whether the loop number i has reached the maximum value MAX (S15). If the loop number i has not reached the maximum value MAX (S15: no), the control circuit 560 may increment the loop number i by 1 (S16), and repeat the programming execution operation S12 and the programming verification operation S13 based on the increased programming voltage VPGMi until the pass condition is satisfied (S14: yes) or the loop number i reaches the maximum value MAX (S15: yes).

[0142] If the pass condition is still not satisfied after executing the programming loop the maximum number of times MAX (S14: no, S15: yes), the control circuit 560 may consider the programming for the selected word line as a failure (S18), activate the status signal R / B to the first logic level H, and terminate the internal operations for programming (S17).

[0143] In this manner, the above programming execution operation and the above programming verification operation may be repeatedly executed while gradually increasing the programming voltages VPGM1, VPGM2, VPGM3, … until a pass condition is satisfied or the loop count i reaches a maximum value MAX. Here, the pass condition indicates the maximum allowable number of unprogrammed memory cells among the memory cells to be programmed that are selected and have a threshold voltage lower than the programming verification voltage VVR, and the programming loop may be repeated until the number of unprogrammed memory cells is less than the maximum allowable number. The maximum allowable number may be determined based on the ECC level of the non-volatile memory device.

[0144] Figure 19 FIG. 4 is a timing diagram of an example embodiment showing a write operation of a non-volatile memory device according to an example embodiment.

[0145] Referring to Figure 19 , in a first operation period P11, the non-volatile memory device may sequentially receive commands CMD1, CMD2, SCE, SCT, and CMD3 and an address ADD via command address signals CA[1] and CA[0]. Additionally, the non-volatile memory device may receive write data WDTA via data signals DQ[7:0], where the commands SCE and SCT indicate the transmission and termination of data.

[0146] In a second operation period P12, the non-volatile memory device may perform an internal operation including applying a programming voltage and verifying the success of the applied programming voltage in order to program the received write data WDTA. The non-volatile memory device may deactivate the status signal R / B to a second logic level when performing the internal operation. The start of the programming execution time tPROG corresponds to the time when the status signal R / B transitions to a logic low level indicating the busy state of the non-volatile memory device, at which time the measurement of the clock period of the command address clock signal CA_CLK starts. The end of the programming execution time tPROG corresponds to the status signal R / B transitioning to a logic high level indicating the ready state of the non-volatile memory device, at which time the measurement of the clock period of the command address clock signal CA_CLK ends.

[0147] In a third operation period P13, the measured clock period value is sent from the non-volatile memory device to the storage controller as degradation information DINF. The measured clock period value of the command address clock signal CA_CLK indicates the programming execution time tPROG during the actual programming operation of the non-volatile memory device.

[0148] During the write operation, Figure 13The degradation detector DMT 570 can generate degradation information DINF based on such a status signal R / B. That is to say, the degradation detector DMT 570 can measure the programming execution time tPROG based on the time interval during which the status signal R / B is deactivated to the second logic level.

[0149] As described above with reference to Figure 19 The non-volatile memory device can receive commands and addresses synchronously with the command address clock signal CA_CLK provided by the storage controller. In this case, during a write operation, the degradation detector DMT can measure the programming execution time tPROG by counting the number of cycles of the command address clock signal CA_CLK when the status signal R / B is deactivated to the second logic level. To count the number of cycles, the degradation detector DMT can include a counter that takes the command address clock signal CA_CLK and the status signal R / B as inputs. The storage controller can continue to switch the command address clock signal CA_CLK when the status signal R / B is deactivated to the second logic level.

[0150] The programming execution time tPROG can be substantially proportional to the number of executions of the program loop referred to Figure 17 and Figure 18 described. In one exemplary embodiment, the degradation detector DMT can measure the programming execution time tPROG based on the number of programming loops executed until the write operation is completed (i.e., until the pass condition is satisfied).

[0151] Figure 20 is a diagram showing an exemplary embodiment of adjusting the programming voltage of a storage device according to an exemplary embodiment.

[0152] Figure 20 Shows the programming voltages VPGM1 and VPGM1' corresponding to the measured programming execution times tPROG and tPROG' of the first programming loop PLOOP(1) respectively. As described with reference to Figure 20 As the degradation of the memory cells progresses, the programming execution time decreases. In this regard, the programming execution time tPROG' for relatively large degradation is less than the programming execution time tPROG for relatively small degradation. The storage controller can control the programming voltages VPGM1 and VPGM1' of the first programming loop PLOOP(1) such that the programming voltage VPGM1' corresponding to the relatively small programming execution time tPROG' is less than the programming voltage VPGM1 corresponding to the relatively large programming execution time tPROG. In this way, the storage controller can control the non-volatile memory device based on the degradation information DINF indicating the programming execution time such that the programming voltage decreases as the degradation degree of the non-volatile memory device increases.

[0153] Figure 21It is a circuit diagram showing the erase bias conditions of a non-volatile memory device according to an exemplary embodiment.

[0154] For ease of description, in Figure 21 the NAND strings NS11 and NS21 connected to the first bit line BL1 and the NAND strings NS12 and NS22 connected to the second bit line BL2 are shown.

[0155] During an erase operation, an erase voltage VERS may be applied to the first bit line BL1 and the second bit line BL2. In this case, for example, a power supply voltage VCC is applied to the first string select line SSL1 and the second string select line SSL2. In addition, during an erase operation, an erase voltage VERS may be applied to the common source line CSL. In this case, the power supply voltage VCC may be applied to the first ground select line GSL1 and the second ground select line GSL2. An erase enable voltage VERSWL may be applied to the word lines WL4, WL5, and WL6.

[0156] Under this erase bias condition, the voltages of the drains and sources of the memory cells of the memory block may be, for example, 20V, and a voltage of, for example, 0V may be applied to the gates. During an erase operation, Figure 13 the voltage generator 550 of

[0157] Figure 22 and Figure 23 is a diagram showing the incremental step pulse erase (ISPE) of a non-volatile memory device according to an exemplary embodiment.

[0158] Referring to Figure 22 and Figure 23 , according to ISPE, an erase operation ERO may be performed by sequentially executing a plurality of erase cycles ELOOP(1), ELOOP(2), ELOOP(3),... until the erase of the memory cells is completed. As the erase cycles are repeated, the erase voltages VERS1, VERS2, VERS3,... may be gradually increased.

[0159] Each erase cycle ELOOP(i) may include an erase period and a verification period. During the erase period, an erase execution operation may be performed to apply the erase voltages VERS1, VERS2, VERS3,... to the bit lines and / or the source line to erase the memory cells. Subsequently, during the verification period, an erase verification operation may be performed to apply an erase verification output voltage VVE to the selected word lines to verify the success of the erase operation.

[0160] Referring to Figure 13 and Figure 23When the internal operation for the erase operation is ready to be executed, the control circuit 560 may deactivate the status signal R / B to a second logic level (e.g., logic low level L) (S30).

[0161] The control circuit 560 may initialize the loop count (i) to 1 to perform the first erase loop ELOOP(1) (S31), apply the erase voltage VERSi corresponding to the i-th erase loop to the bit line and / or the source line (S32), and then apply the erase verification output voltage VVE to the selected word line (S33). The control circuit 560 may determine whether the pass condition is satisfied (S34).

[0162] If the pass condition is satisfied (S34: Yes), the control circuit 560 may activate the status signal R / B to the first logic level (e.g., logic high level H) and terminate the internal operation for the erase operation.

[0163] If the pass condition is not satisfied (S34: No), the control circuit 560 may determine whether the loop count i has reached the maximum value MAX (S35). If the loop count i has not reached the maximum value MAX (S35: No), the control circuit 560 may increment the loop count i by 1 (S36), and repeat the erase execution operation S32 and the erase verification operation S33 based on the increased erase voltage VERSi until the pass condition is satisfied (S34: Yes) or the loop count i reaches the maximum value MAX (S35: Yes).

[0164] If the pass condition is still not satisfied after executing the maximum number of erase loops MAX (S34: No, S35: Yes), the control circuit 560 may regard the erase of the memory cell as a failure (S38), activate the status signal R / B to the first logic level H, and terminate the internal operation for the erase (S37).

[0165] In this way, the above erase execution operation and the above erase verification operation may be repeatedly executed while gradually increasing the erase voltages VERS1, VERS2, VERS3,... until the pass condition is satisfied or the loop count i reaches the maximum value MAX. Here, the pass condition indicates the maximum allowable number of un-erased memory cells among the selected memory cells to be erased whose threshold voltage is higher than the erase verification voltage VVE, and the erase loop may be repeated until the number of un-erased memory cells is less than the maximum allowable number. The maximum allowable number may be determined based on the ECC level of the non-volatile memory device.

[0166] Figure 24 is a timing diagram showing an example embodiment of an erase operation of a non-volatile memory device according to an example embodiment.

[0167] Refer to Figure 24, in the first operation period P21, the non-volatile memory device may sequentially receive commands CMD1, CMD2, and CMD5 and an address ADD via command address signals CA[1] and CA[0].

[0168] In the second operation period P22, the non-volatile memory device may perform internal operations for erasing memory cells including applying an erase voltage and verifying the erase. The non-volatile memory device may deactivate the status signal R / B to a second logic level when performing the internal operations. The start of the erase execution time tERS corresponds to the time when the status signal R / B transitions to a logic low level indicating the busy state of the non-volatile memory device, at which time the measurement of the clock period of the command address clock signal CA_CLK starts. The end of the erase execution time tERS corresponds to the status signal R / B transitioning to a logic high level indicating the ready state of the non-volatile memory device, at which time the measurement of the clock period of the command address clock signal CA_CLK ends.

[0169] In the third operation period P23, the measured clock period value is sent from the non-volatile memory device to the storage controller as degradation information DINF. The measured clock period value of the command address clock signal CA_CLK indicates the erase execution time tERS during the actual erase operation of the non-volatile memory device.

[0170] During the erase operation, Figure 13 the degradation detector DMT 570 may generate degradation information DINF based on such a status signal R / B, that is, the degradation detector DMT 570 may measure the erase execution time tERS based on the time interval during which the status signal R / B is deactivated to the second logic level.

[0171] As described above with reference to Figure 24 the non-volatile memory device may receive commands and addresses synchronously with the command address clock signal CA_CLK provided by the storage controller. In this case, during the erase operation, the degradation detector DMT570 may measure the erase execution time tERS by counting the number of cycles of the command address clock signal CA_CLK when the status signal R / B is deactivated to the second logic level. To count the number of cycles, the degradation detector DMT 570 may include a counter that takes the command address clock signal CA_CLK and the status signal R / B as inputs. The storage controller may continue to switch the command address clock signal CA_CLK when the status signal R / B is deactivated to the second logic level.

[0172] The erase execution time tERS may be substantially the same as that with reference to Figure 22 and Figure 23Proportional to the number of erase cycles described. In one example embodiment, the degradation detector DMT 570 may measure the erase execution time tERS based on the number of erase cycles executed until the erase operation is completed (i.e., until the pass condition is satisfied).

[0173] Figure 25 is a diagram showing an example embodiment of adjusting an erase voltage of a storage device according to an example embodiment.

[0174] In Figure 25 are shown the erase voltages VERS1 and VERS1' corresponding to the measured erase execution times tERS and tERS' of the first erase cycle ELOOP(1), respectively. As described with reference to Figure 25 the erase execution time increases as the degradation of the memory cells progresses. In this regard, the erase execution time tERS' for a relatively large degradation is greater than the erase execution time tERS for a relatively small degradation. The storage controller may control the erase voltages VERS1 and VERS1' of the first erase cycle ELOOP(1) such that the erase voltage VERS1' corresponding to the relatively large erase execution time tERS' is higher than the erase voltage VERS1 corresponding to the relatively small programming execution time tERS. In this way, the storage controller may control the non-volatile memory device based on the degradation information DINF indicating the erase execution time such that the erase voltage increases as the degradation level of the non-volatile memory device increases.

[0175] Figure 26 and Figure 27 is a diagram showing an example embodiment of degradation information in a method of operating a storage device according to an example embodiment.

[0176] In one example embodiment, as shown in Figure 26 the count values CNT1, CNT2, and CNT3 corresponding to the memory blocks BLK1, BLK2, and BLK3, respectively, may be generated and managed as the degradation information DINF. As described above, the count values CNT1, CNT2, and CNT3 may be values obtained by counting the number of cycles of the command address clock signal CA_CLK when the status signal R / B is deactivated to a second logic level.

[0177] In one example embodiment, the programming execution time tPROG may be measured for all word lines of each memory block, so as to control the programming voltage VPGM on a per-word-line basis. In addition, the programming voltage VPGM of each memory block may be controlled based on the average value of the measured programming execution times tPROG of the word lines of each memory block.

[0178] In one exemplary embodiment, at least one target word line among the word lines of each memory block may be set, the programming execution time tPROG of the target word line may be measured, and may be applied as the degradation information DINF of the entire memory block. For example, the target word line may correspond to the word line associated with the memory cells having the worst degradation characteristics. The target word line may be established through a test process of the non-volatile memory device.

[0179] In another exemplary embodiment, as Figure 27 shown, the memory blocks BLK1 and BLK2 may be divided into a first sub-block SB1 including some word lines WL0 to WLk, and a second sub-block SB2 including other word lines WLk+1 to WLn, and the count values corresponding to the degradation information DINF may be generated and managed sub-block by sub-block. The first sub-block SB1 and the second sub-block SB2 may each independently undergo an erase operation. According to an exemplary embodiment, each memory block may be divided into three or more sub-blocks. In one exemplary embodiment, as Figure 27 shown, the count values CNT11 and CNT12 corresponding to the first sub-block SB1 and the count values CNT21 and CNT22 corresponding to the second sub-block SB2 may be generated.

[0180] Figure 28 is a block diagram showing a data center including a storage device according to an exemplary embodiment.

[0181] In some exemplary embodiments, the systems described above with reference to the drawings may be used as an application server and / or a storage server, and are included in the data center 5000. The error management according to an exemplary embodiment may be applied to each of the application server and / or the storage server.

[0182] Referring to Figure 28 , the data center 5000 may collect various data and provide services, and is also referred to as a data storage center. For example, the data center 5000 may be a system configured to operate a search engine and a database, or a computing system used by a company (such as a bank) or a government agency. As Figure 28 shown, the data center 5000 may include application servers 50_1 to 50_n and storage servers 60_1 to 60_m (where each of m and n is an integer greater than 1). The number n of the application servers 50_1 to 50_n and the number m of the storage servers 60_1 to 60_m may be differently selected according to an exemplary embodiment. In some exemplary embodiments, the number n of the application servers 50_1 to 50_n may be different from the number m of the storage servers 60_1 to 60_m.

[0183] The application servers 50_1 to 50_n may include any one or any combination of processors 51_1 to 51_n, memories 52_1 to 52_n, switches 53_1 to 53_n, network interface cards (NICs) 54_1 to 54_n, and storage devices 55_1 to 55_n. The processors 51_1 to 51_n may control all operations of the application servers 50_1 to 50_n, access the memories 52_1 to 52_n, and execute instructions and / or data loaded into the memories 52_1 to 52_n. Non-limiting examples of the memories 52_1 to 52_n may include double data rate synchronous DRAM (DDR SDRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), dual in-line memory module (DIMM), Optane DIMM, or non-volatile DIMM (NVDIMM).

[0184] According to an example embodiment, the number of processors and memories included in the application servers 50_1 to 50_n may be differently selected according to the example embodiment. In some example embodiments, the processors 51_1 to 51_n and the memories 52_1 to 52_n may provide a processor-memory pair. In some example embodiments, the number of the processors 51_1 to 51_n may be different from the number of the memories 52_1 to 52_n. The processors 51_1 to 51_n may include single-core processors or multi-core processors. In some example embodiments, as Figure 28 shown by the dashed line in, the storage devices 55_1 to 55_n may be omitted from the application servers 50_1 to 50_n. The number of the storage devices 55_1 to 55_n included in the storage servers 50_1 to 50_n may be differently selected according to the example embodiment. The processors 51_1 to 51_n, the memories 52_1 to 52_n, the switches 53_1 to 53_n, the NICs 54_1 to 54_n, and / or the storage devices 55_1 to 55_n may communicate with each other through the links described above with reference to the drawings.

[0185] The storage servers 60_1 to 60_m may include any one or any combination of processors 61_1 to 61_m, memories 62_1 to 62_m, switches 63_1 to 63_m, NICs 64_1 to 64_n, and storage devices 65_1 to 65_m. The processors 61_1 to 61_m and the memories 62_1 to 62_m may operate similarly to the processors 51_1 to 51_n and the memories 52_1 to 52_n of the above-described application servers 50_1 to 50_n.

[0186] Application servers 50_1 to 50_n can communicate with storage servers 60_1 to 60_m via network 70. In some example embodiments, network 70 can be implemented using Fibre Channel (FC) or Ethernet. FC can be a medium for relatively high-speed data transmission. An optical switch providing high performance and high availability can be used as FC. Storage servers 60_1 to 60_m can be provided as file storage devices, block storage devices, or object storage devices according to the access method of network 70.

[0187] In some example embodiments, network 70 can be a storage-only network (such as a Storage Area Network (SAN)). For example, the SAN can be an FC-SAN, which can use an FC network and implement using the Fibre Channel Protocol (FCP). In another case, the SAN can be an Internet Protocol (IP)-SAN, which uses a Transmission Control Protocol / Internet Protocol (TCP / IP) network and is implemented according to the SCSI over TCP / IP or Internet Small Computer System Interface (iSCSI) protocol. In some example embodiments, network 70 can be a general network (such as a TCP / IP network). For example, network 70 can be implemented according to a protocol (such as Fibre Channel over Ethernet (FCoE), Network Attached Storage (NAS), Non-Volatile Memory Express (NVMe) over Fabric (NVMe-oF)).

[0188] The application server 50_1 and the storage server 60_1 will be mainly described, but it should be noted that the description of the application server 50_1 can also be applied to another application server (e.g., 50_n), and the description of the storage server 60_1 can also be applied to another storage server (e.g., 60_m).

[0189] The application server 50_1 can store the data requested to be stored by a user or client in one of the storage servers 60_1 to 60_m via network 70. In some example embodiments, the application server 50_1 can obtain the data requested to be read by a user or client from one of the storage servers 60_1 to 60_m via network 70. For example, the application server 50_1 can be implemented using a web server or a Database Management System (DBMS).

[0190] The application server 50_1 can access the memory 52_n and / or the storage device 55_n included in another application server 50_n through the network 70, and / or access the memories 62_1 to 62_m and / or the storage devices 65_1 to 65_m included in the storage servers 60_1 to 60_m through the network 70. Therefore, the application server 50_1 can perform various operations on the data stored in the application servers 50_1 to 50_n and / or the storage servers 60_1 to 60_m. For example, the application server 50_1 can execute instructions to migrate or copy data between the application servers 50_1 to 50_n and / or the storage servers 60_1 to 60_m. In this case, the data can be migrated from the storage devices 65_1 to 65_m of the storage servers 60_1 to 60_m to the memories 52_1 to 52_n of the application servers 50_1 to 50_n through the memories 62_1 to 62_m of the storage servers 60_1 to 60_m, or directly from the storage devices 65_1 to 65_m of the storage servers 60_1 to 60_m to the memories 52_1 to 52_n of the application servers 50_1 to 50_n. In some example embodiments, the data migrated through the network 70 can be encrypted data for security or privacy.

[0191] In the storage server 60_1, the interface IF can provide a physical connection between the processor 61_1 and the controller CTRL and a physical connection between the NIC 64_1 and the controller CTRL. For example, the interface IF can be implemented using a direct attached storage (DAS) method that directly connects the storage device 65_1 to a dedicated cable. For example, the interface IF can be implemented using various interface methods (such as, Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), PCI, PCIe, NVMe, IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card, Multimedia Card (MMC), Embedded MMC (eMMC), UFS, Embedded UFS (eUFS), and Compact Flash (CF) card interfaces).

[0192] In the storage server 60_1, the switch 63_1 can selectively connect the processor 61_1 to the storage device 65_1 or selectively connect the NIC 64_1 to the storage device 65_1 based on the control of the processor 61_1.

[0193] In some example embodiments, NIC 64_1 may include a network interface card (NIC) and a network adapter. NIC 54_1 may be connected to network 70 through a wired interface, a wireless interface, a Bluetooth interface, or an optical interface. NIC 54_1 may include an internal memory, a digital signal processor (DSP), and a host bus interface, and is connected to processor 61_1 and / or switch 63_1 through the host bus interface. In some example embodiments, NIC 64_1 may be integrated with any one or any combination of processor 61_1, switch 63_1, and storage device 65_1.

[0194] In application servers 50_1 to 50_n or storage servers 60_1 to 60_m, processors 51_1 to 51_n and 61_1 to 61_m may send commands to storage devices 55_1 to 55_n and 65_1 to 65_m or memories 52_1 to 52_n and 62_1 to 62_m, and may program or read data. In this case, the data may be data whose errors are corrected by an error correction code (ECC) engine. The data may be data processed using data bus inversion (DBI) or data masking (DM), and includes cyclic redundancy code (CRC) information. The data may be encrypted data for security or privacy.

[0195] In response to read commands received from processors 51_1 to 51_n and 61_1 to 61_m, storage devices 55_1 to 55_n and 65_1 to 65_m may send control signals and command / address signals to a non-volatile memory device (e.g., a NAND flash device) NVM. Thus, when reading data from the non-volatile memory device NVM, a read enable signal may be input as a data output control signal to output the data to the DQ bus. The read enable signal may be used to generate a data strobe signal. The command and address signals may be latched according to the rising edge or falling edge of the write enable signal.

[0196] The controller CTRL can control all operations of the storage device 65_1. In an exemplary embodiment, the controller CTRL may include a static RAM (SRAM). The controller CTRL can write data to the non-volatile memory device NVM in response to a write command or read data from the non-volatile memory device NVM in response to a read command. For example, write commands and / or read commands can be generated based on requests provided from a host (e.g., the processor 61_1 of the storage server 60_1, the processor 61_m of another storage server 60_m, or the processors 51_1 to 51_n of the application servers 50_1 to 50_n). The buffer BUF can temporarily store (or buffer) the data to be written to the non-volatile memory device NVM or the data read from the non-volatile memory device NVM. In some exemplary embodiments, the buffer BUF may include a DRAM. The buffer BUF can store metadata. The metadata can represent user data or data generated by the controller CTRL to manage the non-volatile memory device NVM. The storage device 65_1 can include a security element (SE) for security or privacy.

[0197] According to the above exemplary embodiments, the storage devices 55_1 to 55_n and 65_1 to 65_m can measure at least one of the programming execution time required for performing a write operation and the erase execution time required for performing an erase operation to provide degradation information. At least one of the programming voltage for the write operation and the erase voltage for the erase operation can be adjusted based on at least one of the programming execution time and the erase execution time.

[0198] As described above, according to an exemplary embodiment, the non-volatile memory device can measure at least one of the programming execution time and the erase execution time to provide degradation information indicating the actual degradation level of the non-volatile memory device. Based on the measured degradation information, the storage controller can reduce the programming voltage of the non-volatile memory device to reflect the actual degradation level, thereby reducing the stress on the non-volatile memory cells and improving the performance and lifespan of the non-volatile memory device and the storage device. In addition, the storage controller can increase the erase voltage of the non-volatile memory device based on the measured degradation information to reflect the actual degradation level, thereby reducing the erase time of the non-volatile memory device and improving the performance of the non-volatile memory device and the storage device.

[0199] The exemplary embodiments can be applied to any electronic device and system. For example, the exemplary embodiments can be applied to systems such as mobile phones, smart phones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, video cameras, personal computers (PCs), server computers, workstations, laptop computers, digital televisions (TVs), set-top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, server systems, autonomous driving systems, data centers, etc.

[0200] In some exemplary embodiments, according to the exemplary embodiments, each component represented by blocks as shown in Figure 6A , Figure 7 , Figures 12 to 14 and Figure 28 can be implemented as various numbers of hardware and / or firmware structures that perform the respective functions described above. For example, at least one of these components may include various hardware components that can perform the respective functions through the control of one or more microprocessors or other control devices. The various hardware components include digital circuits, programmable or non-programmable logic devices or arrays, application specific integrated circuits (ASICs), transistors, capacitors, logic gates, or other circuitry using direct circuit structures such as memories, processors, logic circuits, look-up tables, etc. In addition, at least one of these components may also include a processor such as a central processing unit (CPU), microprocessor, etc. that performs the respective functions, or may be implemented by a processor such as a central processing unit (CPU), microprocessor, etc. that performs the respective functions. The functional aspects of the exemplary embodiments can be implemented as algorithms executed on one or more processors. In addition, the components, elements, modules, or units represented by blocks or processing steps may employ any number of related technologies for electronic configuration, signal processing and / or control, data processing, etc.

[0201] Although aspects of the exemplary embodiments have been specifically shown and described, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A storage device, comprising: a nonvolatile memory device configured to receive a command and an address for a write operation or an erase operation via a command address pin, to send and receive write data or read data via a data pin, and to generate degradation information by measuring at least one of a program execution time for performing a write operation and an erase execution time for performing an erase operation; as well as The memory controller is configured to receive degradation information from the nonvolatile memory device and control the nonvolatile memory device to adjust at least one of a program voltage of a write operation and an erase voltage of an erase operation based on the degradation information.

2. The storage device according to claim 1, wherein: The nonvolatile memory device is further configured to send the degradation information to the memory controller via the command address pins.

3. The storage device according to claim 1, wherein: The memory controller is further configured to control the nonvolatile memory device to reduce a program voltage based on the degradation information indicating a reduction in the program execution time.

4. The storage device according to claim 1, wherein: The memory controller is further configured to control the nonvolatile memory device to increase the erase voltage based on the degradation information indicating an increase in the erase execution time.

5. The storage device according to claim 1, wherein: The nonvolatile memory device is further configured to update the degradation information by measuring the program execution time and the erase execution time whenever the program erase count reaches any one of the plurality of reference counts.

6. The storage device according to claim 1, wherein: The nonvolatile memory device is also configured to update the degradation information by measuring a program execution time and an erase execution time based on a request from the memory controller.

7. The storage device according to claim 1, wherein: The nonvolatile memory device is further configured to: provide a status signal to the memory controller, the status signal being activated at a first logic level indicating a ready state when in a ready state, and being deactivated at a second logic level indicating a busy state when performing an internal operation for a write operation or an erase operation, and The nonvolatile memory device is further configured to measure a programming execution time or an erasing execution time based on a time interval during which the state signal is deactivated to the second logic level during a writing operation or an erasing operation.

8. The storage device according to claim 7, wherein: The nonvolatile memory device is further configured to: receive a command and an address in synchronization with a command address clock signal provided from the memory controller, and The nonvolatile memory device is further configured to: during a write operation, measure a program execution time by counting clock cycles of a command address clock signal when the state signal is deactivated to a second logic level.

9. The storage device according to claim 1, wherein: The nonvolatile memory device is a NAND flash memory device configured to operate according to a separate command address protocol.

10. The storage device according to claim 1, wherein: The nonvolatile memory device is also configured to set at least one target word line among the word lines of the memory block, and measure a program execution time for the at least one target word line.

11. The storage device according to claim 1, wherein: The nonvolatile memory device is further configured to measure a program execution time for each of a plurality of word lines of the memory block to obtain a plurality of program execution times, and control a program voltage for the memory block based on an average of the plurality of program execution times.

12. The storage device according to claim 1, wherein: The non-volatile memory device is further configured to: Performing a write operation according to incremental step pulse programming; As the programming cycle is repeated, incrementally increasing the programming voltage; and The program execution time is measured based on the number of program loops performed to complete a write operation.

13. The storage device according to claim 1, wherein: The non-volatile memory device is further configured to: Performing an erase operation according to incremental step pulse erase; As the erase cycle is repeated, gradually increasing the erase voltage; and The erase execution time is measured based on the number of erase cycles performed to complete the erase operation.

14. The storage device according to claim 1, wherein: The non-volatile memory device is further configured to: Performing a write operation according to incremental step pulse programming; and As the programming cycle is repeated, incrementally increasing the programming voltage; The memory controller is further configured to control the nonvolatile memory device to reduce a programming voltage of a first programming loop of the incremental step pulse programming based on degradation information indicating an increased degree of degradation of the nonvolatile memory device.

15. The storage device according to claim 1, wherein: The non-volatile memory device is further configured to: Performing an erase operation according to incremental step pulse erase; and As the erase cycle is repeated, the erase voltage is incrementally increased, and The memory controller is further configured to control the nonvolatile memory device to increase an erase voltage of a first erase cycle of the incremental step pulse erase based on degradation information indicating an increased degree of degradation of the nonvolatile memory device.

16. A method of operating a storage device, the storage device comprising a non-volatile memory device and a storage controller configured to control the non-volatile memory device, the method comprising: generating degradation information by measuring at least one of a program execution time for performing a write operation and an erase execution time for performing an erase operation of the nonvolatile memory device; providing degradation information from the non-volatile memory device to a memory controller; as well as The nonvolatile memory device is controlled to adjust at least one of a program voltage of a write operation and an erase voltage of an erase operation based on the degradation information.

17. The method according to claim 16, wherein: The steps to generate degradation information include: generating a state signal which is activated at a first logic level indicating a ready state when in a ready state, and is deactivated at a second logic level indicating a busy state when performing an internal operation for a write operation or an erase operation; and During a write operation or an erase operation, a program execution time or an erase execution time is measured based on a time interval during which the state signal is deactivated to the second logic level.

18. The method according to claim 16, wherein: The step of controlling the nonvolatile memory device includes controlling the nonvolatile memory device to reduce a program voltage based on the degradation information indicating a reduction in the program execution time.

19. The method according to claim 16, wherein: The step of controlling the nonvolatile memory device includes controlling the nonvolatile memory device to increase an erase voltage based on the degradation information indicating an increase in the erase execution time.

20. A non-volatile memory device comprising: a memory cell array comprising a plurality of nonvolatile memory cells; command address pins configured to transmit commands and addresses for write operations or erase operations; Data pins, configured to transmit write data and read data; a status pin configured to transmit a status signal which is activated at a first logic level indicating a ready state when in a ready state and is deactivated at a second logic level indicating a busy state when performing an internal operation for a write operation or an erase operation, and The degradation detector circuit is configured to generate degradation information by identifying at least one of a program execution time for performing a write operation and an erase execution time for performing an erase operation based on the state signal.

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