Wafer acceptance test structure and wafer acceptance test method
By designing a wafer receiving test structure containing a conductive connection layer, the problem of leakage channels caused by polymer residues in semiconductor integrated circuit manufacturing is solved, and efficient detection and monitoring of the surrounding gate structure is achieved.
Patent Information
- Application Number
- CN202510368133.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-26
- Publication Date
- 2025-06-24
AI Technical Summary
In semiconductor integrated circuit manufacturing processes, the complexity of the gate side wall structure and process leads to frequent polymer residues, and the prior art is difficult to effectively monitor and detect, resulting in the formation of leakage channels.
A wafer acceptance test structure is designed, including a substrate, a polysilicon layer, an interlayer dielectric layer, a conductive connection layer and a metal layer. The polysilicon structure is surrounded by a conductive connection layer and led out to the top metal layer, forming a test circuit for whether there is polymer residue around the gate structure and causing leakage.
The leakage detection of different locations around the gate structure is realized, and the leakage caused by polymer residues can be monitored in a timely manner, improving the accuracy and efficiency of the test.
Smart Images
Figure CN120199756A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuit manufacturing, and particularly to a wafer acceptance test (WAT) structure and a wafer acceptance test method. Background Art
[0002] In the semiconductor integrated circuit manufacturing process, due to the complexity of the gate sidewall structure and process, it is often a high-incidence area of polymer residue. The residual polymer contains C elements that can form leakage channels.
[0003] In the actual process, the polymer residue can be monitored by defect scan technology and electron beam (E-beam) technology. However, due to the high transparency of the polymer itself, the defect scan technology often has difficulty in detecting it, while the E-beam technology can only indirectly judge through the on-off of the contact hole structure, and the scanning time is long and the monitoring quantity is limited. Summary of the Invention
[0004] The purpose of the present invention is to provide a wafer acceptance test structure and a wafer acceptance test method to solve one or more problems in the prior art.
[0005] To solve the above technical problems, the present invention provides a wafer acceptance test structure, including:
[0006] A substrate;
[0007] A plurality of first active regions formed in the substrate, and adjacent first active regions are isolated by STI structures;
[0008] A polysilicon layer formed on the substrate, the polysilicon layer includes a plurality of discrete polysilicon structures, and the region formed by the intersection of each first active region and each polysilicon structure is a gate structure region;
[0009] An interlayer dielectric layer covering the substrate and the polysilicon layer;
[0010] A conductive connection layer formed in the interlayer dielectric layer, and each polysilicon structure is surrounded by the conductive connection layer, and each part of the conductive connection layer is electrically connected to each other. The conductive connection layer includes a first conductive part and a second conductive part. The first conductive part at least includes the part of the conductive connection layer between adjacent polysilicon structures. The first conductive part is isolated from the substrate by the interlayer dielectric layer, and the second conductive part is electrically connected to the substrate; and,
[0011] A metal layer located above the conductive connection layer and electrically connected to the first conductive part and the second conductive part respectively.
[0012] Optionally, in the wafer acceptance test structure, the polysilicon layer includes a first polysilicon row and a second polysilicon row;
[0013] The first polysilicon row extends in a first direction and is strip-shaped;
[0014] The second polysilicon row includes a plurality of polysilicon blocks, and the plurality of polysilicon blocks are arranged at intervals in sequence along the first direction.
[0015] Optionally, in the wafer acceptance test structure, the first polysilicon rows are arranged on both sides in a second direction of the second polysilicon row, and the second direction is perpendicular to the first direction.
[0016] Optionally, in the wafer acceptance test structure, the conductive connection layer includes a frame-shaped portion distributed around the whole formed by all the first polysilicon rows and the second polysilicon rows, a long strip portion formed between the first polysilicon rows and the second polysilicon rows and arranged along the first direction, and short strip portions located on both sides of each polysilicon block in the first direction and arranged along the second direction. The frame-shaped portion, the long strip portion and the short strip portions are electrically connected to each other so that the peripheries of each first polysilicon row and each polysilicon block are surrounded by the conductive connection layer, and the second direction is perpendicular to the first direction.
[0017] Optionally, in the wafer acceptance test structure, the long strip portion and the short strip portions constitute the first part, and the outer frame portion constitutes the second part.
[0018] Optionally, in the wafer acceptance test structure, a plurality of first active regions are arranged at intervals and in parallel along the first direction. Below each polysilicon block, there is correspondingly provided a first active region, and each first active region and each first polysilicon row have an overlapping region.
[0019] Optionally, in the wafer acceptance test structure, it further includes a plurality of second active regions. The plurality of second active regions are arranged at intervals and in parallel along the second direction. Adjacent second active regions are isolated from each other by an STI structure, and each second active region and each polysilicon block have an overlapping region, and the second direction is perpendicular to the first direction.
[0020] Optionally, in the wafer acceptance test structure, there is a height difference between the first active region and the second active region and the corresponding STI structure.
[0021] Optionally, in the wafer acceptance test structure, the substrate is an N-type substrate or a P-type substrate.
[0022] The present invention also provides a method for performing a wafer acceptance test using the wafer acceptance test structure as described in any one of the preceding items, including:
[0023] Applying a target voltage to both ends of a test circuit formed by the first conductive part, the substrate, the interlayer dielectric layer, and the second conductive part through the metal layer, and judging whether there is leakage according to the withstand voltage condition of the wafer acceptance test structure.
[0024] In summary, the wafer acceptance test structure provided by the present invention includes: a substrate, a plurality of first active regions formed in the substrate, and adjacent first active regions are isolated by STI structures; a polysilicon layer formed on the substrate, the polysilicon layer includes a plurality of discrete polysilicon structures, and the region formed by the intersection of each first active region and each polysilicon structure is a gate structure region interlayer dielectric layer, and the interlayer dielectric layer covers the substrate and the polysilicon layer; a conductive connection layer formed in the interlayer dielectric layer, and each polysilicon structure is surrounded by the conductive connection layer on all sides, and each part of the conductive connection layer is electrically connected to each other. The conductive connection layer includes a first conductive part and a second conductive part. The first conductive part at least includes the part of the conductive connection layer located between adjacent polysilicon structures. The first conductive part is isolated from the substrate by the interlayer dielectric layer, and the second conductive part is electrically connected to the substrate; and a metal layer located above the conductive connection layer and electrically connected to the first conductive part and the second conductive part respectively. Compared with the prior art:
[0025] (1) For the wafer acceptance test structure provided by the embodiments of the present invention, in view of the easy occurrence of polymer residues at the gate sidewall, a part of the interlayer dielectric layer with a certain thickness is reserved in the region between adjacent polysilicon structures and led out to the top metal layer through the conductive connection layer. At the same time, the substrate is also led out to the top metal layer through the conductive connection layer. In this way, a test circuit for testing whether there is leakage due to polymer residues around the gate structure is formed.
[0026] (2) Since the conductive connection layer surrounds each polysilicon structure on all sides and each part of the conductive connection layer is electrically connected to each other, when leakage occurs at different position points around the gate structure, it can be detected. Description of the Drawings
[0027] Figure 1 is a schematic plan view of the wafer acceptance test structure provided by the embodiments of the present invention;
[0028] Figure 2 is Figure 1 a schematic cross-sectional view of the wafer acceptance test structure shown along AA1;
[0029] Among them, the descriptions of each reference numeral are as follows:
[0030] 10 - Substrate; 20 - First active region; 30 - Polysilicon layer; 40 - Interlayer dielectric layer; 50 - Conductive connection layer; 60 - Second active region;
[0031] 31 - First polysilicon row; 32 - Second polysilicon row;
[0032] 51 - Frame part; 52 - Long strip part; 53 - Short strip part. Detailed implementation manners
[0033] To make the objectives, advantages, and features of the present invention clearer, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in very simplified forms and use non - precise scales, and are only used to conveniently and clearly assist in explaining the objectives of the embodiments of the present invention. In addition, the structures shown in the accompanying drawings are often a part of the actual structure. In particular, the accompanying drawings need to show different focuses, and sometimes different scales are used. It should be recognized that relative terms such as "above", "below", "top", "bottom", etc. shown in the accompanying drawings can be used to describe the relationships between various elements with respect to each other. These relative terms are intended to cover different orientations of the elements in addition to the orientations depicted in the accompanying drawings. For example, if the device is inverted relative to the view in the accompanying drawing, an element described as "above" another element will now be below that element. It should also be understood that unless otherwise specifically stated or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish each component, element, step, etc. in the specification, rather than to represent the logical relationship or sequential relationship between each component, element, step, etc.
[0034] Please refer to Figure 1 and in combination with Figure 2 , an embodiment of the present invention provides a wafer acceptance test structure, including:
[0035] Substrate 10;
[0036] A plurality of first active regions 20 formed in the substrate 10, and adjacent first active regions 20 are isolated by STI structures;
[0037] A polysilicon layer 30 formed on the substrate 10, the polysilicon layer 30 includes a plurality of discrete polysilicon structures, and the regions formed by the intersection of each first active region 20 and each polysilicon structure are gate structure regions;
[0038] An interlayer dielectric layer 40, the interlayer dielectric layer 40 covers the substrate 10 and the polysilicon layer 30;
[0039] A conductive connection layer 50 is formed within the interlayer dielectric layer 40. The periphery of each polysilicon structure is surrounded by the conductive connection layer 50, and each part of the conductive connection layer 50 is electrically connected to each other. The conductive connection layer 50 includes a first conductive part and a second conductive part. The first conductive part at least includes the part of the conductive connection layer 50 located between adjacent polysilicon structures. The first conductive part is isolated from the substrate 10 by the interlayer dielectric layer 40. The second conductive part is electrically connected to the substrate 10; and,
[0040] A metal layer 70 is located above the conductive connection layer 50 and is electrically connected to the first conductive part and the second conductive part respectively.
[0041] It can be understood that in the existing semiconductor integrated circuit manufacturing process, a spacer is generally formed on the side of the polysilicon located in the gate structure region to form a gate structure. As mentioned above, when forming the spacer, due to the complexity of the spacer structure and process, it is often a high-incidence area of polymer residue.
[0042] For the wafer acceptance test structure provided by the embodiments of the present invention, in view of the easy occurrence of polymer residue at the gate spacer, the area prone to polymer residue is covered by the interlayer dielectric layer 40 and led out to the top metal layer 70 through the conductive connection layer 50. At the same time, the substrate 10 is also led out to the top metal layer 70 through the conductive connection layer 50. In this way, a test circuit for testing whether there is leakage due to the presence of polymer residue around the gate structure is formed. In addition, since the conductive connection layer 50 surrounds the periphery of each polysilicon structure and each part of the conductive connection layer 50 is electrically connected to each other, when leakage occurs at different position points around the gate structure, it can be detected.
[0043] On this basis, the embodiments of the present invention further provide a method for performing a wafer acceptance test using the wafer acceptance test structure as described in this embodiment, including:
[0044] Applying a target voltage to both ends of the test circuit formed by the first conductive part, the substrate 10, the interlayer dielectric layer 40, and the second conductive part through the metal layer 70, and judging whether there is leakage according to the breakdown voltage situation of the wafer acceptance test structure.
[0045] It can be understood that whether there is polymer residue around the gate will affect the conduction performance between the first conductive part and the substrate 10. Specifically, when there is no polymer residue, the first conductive part and the substrate 10 are isolated by the interlayer dielectric layer 40. When a voltage is applied, the test circuit can withstand a relatively large voltage. However, when there is polymer residue, the polymer will form a leakage channel between the first conductive part and the substrate 10, making the test circuit unable to withstand a relatively large voltage.
[0046] The inventors have found through research that after the formation of the gate sidewall, the characteristics of polymer residue around the gate include:
[0047] (1) At the densely distributed gates, polymer residue is more likely to appear around them. However, since there is usually no electrical connection at the densely distributed gates, it is impossible to monitor the polymer residue at this location.
[0048] (2) Affected by the process operation, polymers are more likely to accumulate at the gate sidewalls formed by the laterally distributed polysilicon.
[0049] Based on this, the wafer acceptance test structure provided by the embodiments of the present invention further simulates several situations where polymer residue is likely to occur. When there is polymer residue, anomalies can be monitored in a timely manner.
[0050] Specifically, further, the polysilicon layer 30 includes: a first polysilicon row 31 and a second polysilicon row 32; the first polysilicon row 31 extends in a first direction and is strip-shaped, and the second polysilicon row 32 includes a plurality of polysilicon blocks, and the plurality of polysilicon blocks are arranged at intervals in the first direction in sequence. Preferably, the first polysilicon row 31 is arranged on both sides in a second direction perpendicular to the first direction of the second polysilicon row 32.
[0051] That is, for the wafer acceptance test structure provided by the embodiments of the present invention, in view of the situations where polymer residue is likely to occur, not only polysilicon strips are designed, but also polysilicon blocks are designed. The areas where the plurality of polysilicon blocks are located form a polysilicon dense area, which can well simulate the situation of dense gate structure distribution, and the designed polysilicon strips can well simulate the situation where polymers are likely to accumulate at the laterally distributed polysilicon sidewalls.
[0052] Preferably, the conductive connection layer 50 includes a frame-shaped portion 51 that is integrally distributed around all the first polysilicon rows 31 and the second polysilicon rows 32, a strip-shaped portion 52 formed between the first polysilicon rows 31 and the second polysilicon rows 32 and arranged along the first direction, and a short strip portion 53 formed between adjacent polysilicon blocks and arranged along the second direction. The three portions are electrically connected to each other, so that the periphery of each polysilicon block and the first polysilicon row 31 are surrounded by the conductive connection layer 50.
[0053] Based on the above analysis, it can be seen that polymers are more likely to remain in the regions where the strip-shaped portion 52 and the short strip portion 53 are located. Therefore, in this embodiment, optionally, the strip-shaped portion 52 and the short strip portion 53 constitute the first conductive portion, and the frame-shaped portion 51 constitutes the second conductive portion. That is, the strip-shaped portion 52 and the short strip portion 53 are isolated from the substrate 10 by the interlayer dielectric layer 40, while the frame-shaped portion 51 is electrically connected to the substrate 10.
[0054] In some other embodiments, it may also be that the frame-shaped portion 51, the strip-shaped portion 52, and the short strip portion 53 together constitute the first conductive portion, and the second conductive portion is provided at other positions on the substrate 10 and is electrically connected to the first conductive portion; or, a part of the strip-shaped portion 52, the short strip portion 53, and the frame-shaped portion 51 together constitute the first conductive portion, and the remaining part of the frame-shaped portion 51 constitutes the second conductive portion. For example, since polysilicon residues are more likely to occur on both sides of the polysilicon strip in the second direction, the portion of the frame-shaped portion 51 in the second direction of the first polysilicon row 31 can also be used as the first portion, and the remaining part of the frame-shaped portion 51 can be used as the second portion.
[0055] Optionally, in this embodiment, the first active regions 20 are provided in one-to-one correspondence with the polysilicon blocks. Specifically, a plurality of the first active regions 20 are arranged at intervals and in parallel along the first direction. Below each polysilicon block, there is correspondingly provided a first active region 20, and each of the first active regions 20 extends along the second direction and has an overlapping region with each of the first polysilicon rows 31.
[0056] In addition, the inventors' research also found that the characteristics of polymer residues also include:
[0057] (3) There is a height difference at the junction of the active region and the STI structure, and polymers are often more likely to accumulate.
[0058] Based on this, in the wafer acceptance test structure provided in this embodiment, there is also a height difference between the first active region 20 and the STI structure. Since the conductive connection layer 50 surrounds each polysilicon structure and is electrically conductive between its various parts, therefore, at the junction of each first active region 20 and the STI structure, it is also electrically connected through the conductive connection layer 50. Thus, if there is a leakage situation caused by polysilicon residue at the junction of the first active region 20 and the STI structure, it can also be detected.
[0059] Preferably, the active region further includes a plurality of second active regions 60. The plurality of second active regions 60 are arranged in parallel at intervals along the second direction. Adjacent second active regions 60 are isolated from each other by STI structures, and each second active region 60 extends along the first direction and has an overlapping region with each polysilicon block.
[0060] That is, the second active regions 60 are arranged corresponding to the polysilicon dense regions. On the basis that polymer residues are likely to appear in the regions where polysilicon is densely distributed, by arranging the second active regions 60 in these polysilicon dense regions, it is also easy for polymer residues to appear in these regions due to the height difference between the STI and the active regions. The two jointly simulate a structural feature that is more likely to have polymer residues, thereby improving the accuracy of wafer acceptance testing.
[0061] In addition, optionally, the substrate 10 is an N-type substrate or a P-type substrate.
[0062] In summary, the wafer acceptance test structure and the wafer acceptance test method provided in the embodiments of the present invention include: a substrate, a plurality of first active regions formed in the substrate, a plurality of polysilicon structures formed on the substrate. The overlapping regions generated by the intersection of each first active region and each polysilicon structure are gate structure regions. The regions between at least adjacent polysilicon structures are covered by an interlayer dielectric layer and are led out to the top metal layer through a conductive connection layer. At the same time, the substrate is also led out to the top metal layer through the conductive connection layer. In this way, a test circuit for testing whether there is leakage caused by polymer residues around the gate structure is formed. By applying a voltage to the top metal layer, the purpose of detecting whether there is leakage around the gate structure can be achieved. In addition, since the conductive connection layer surrounds the periphery of each polysilicon structure and the various parts of the conductive connection layer are electrically conductive with each other, therefore, when leakage occurs at different position points around the gate structure, it can be detected.
[0063] It should be noted that although the present invention has been disclosed above with preferred embodiments, for any person skilled in the art, without departing from the scope of the technical solution of the present invention, many possible changes and modifications can be made to the technical solution of the present invention by using the technical content disclosed above, or it can be modified into equivalent embodiments with equivalent changes. Therefore, all content that does not depart from the technical solution of the present invention, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention still belong to the scope protected by the technical solution of the present invention.
Claims
1. A wafer acceptance test structure, characterized in that: include: substrate; A plurality of first active regions are formed in the substrate, wherein adjacent first active regions are isolated by an STI structure; A polysilicon layer formed on the substrate, the polysilicon layer comprising a plurality of discretely arranged polysilicon structures, and an area formed by the overlap of each of the first active regions and each of the polysilicon structures being a gate structure area; an interlayer dielectric layer, the interlayer dielectric layer covering the substrate and the polysilicon layer; A conductive connection layer is formed in the interlayer dielectric layer, each of the polysilicon structures is surrounded by the conductive connection layer, and the parts of the conductive connection layer are electrically connected to each other, the conductive connection layer includes a first conductive part and a second conductive part, the first conductive part at least includes a part of the conductive connection layer located between adjacent polysilicon structures, the first conductive part is isolated from the substrate by the interlayer dielectric layer, and the second conductive part is electrically connected to the substrate; as well as, The metal layer is located above the conductive connection layer and is electrically connected to the first conductive portion and the second conductive portion respectively.
2. The wafer acceptance test structure according to claim 1, wherein: The polysilicon layer includes a first polysilicon row and a second polysilicon row; The first polysilicon row extends along a first direction and is in a strip shape; The second polysilicon row includes a plurality of polysilicon blocks, and the plurality of polysilicon blocks are sequentially arranged at intervals along the first direction.
3. The wafer acceptance test structure according to claim 2, wherein: The first polysilicon rows are arranged on both sides of the second polysilicon row in a second direction, and the second direction is perpendicular to the first direction.
4. The wafer acceptance test structure according to claim 2, wherein: The conductive connection layer includes a frame-shaped portion that is integrally distributed around all the first polysilicon rows and the second polysilicon rows, a long strip portion that is formed between the first polysilicon rows and the second polysilicon rows and arranged along the first direction, and a short strip portion that is located on both sides of each polysilicon block in the first direction and arranged along the second direction. The frame-shaped portion, the long strip portion, and the short strip portion are electrically connected to each other so that each of the first polysilicon rows and each of the polysilicon blocks are surrounded by the conductive connection layer, and the second direction is perpendicular to the first direction.
5. The wafer acceptance test structure according to claim 4, wherein: The long strip portion and the short strip portion constitute the first portion, and the outer frame portion constitutes the second portion.
6. The wafer acceptance test structure according to claim 2, wherein: A plurality of the first active regions are arranged in parallel and spaced apart in sequence along the first direction. A first active region is correspondingly disposed below each of the polysilicon blocks, and each of the first active regions and each of the first polysilicon rows has an overlapping area.
7. The wafer acceptance test structure according to claim 6, wherein: It also includes a plurality of second active areas, which are arranged in parallel and spaced apart in sequence along the second direction, adjacent second active areas are isolated by an STI structure, and each of the second active areas has an overlapping area with each of the polysilicon blocks, and the second direction is perpendicular to the first direction.
8. The wafer acceptance test structure according to claim 5, wherein: There is a height difference between the first active region and the second active region and the corresponding STI structure.
9. The wafer acceptance test structure according to claim 1, wherein: The substrate is an N-type substrate or a P-type substrate.
10. A method for performing a wafer acceptance test using the wafer acceptance test structure according to any one of claims 1 to 9, characterized in that: include: A target voltage is applied to both ends of a test circuit formed by the first conductive part, the substrate, the interlayer dielectric layer, and the second conductive part through the metal layer, and whether there is leakage is determined based on the withstand voltage of the wafer acceptance test structure.