Universal serial bus power transfer power adapter and operating method thereof

Abstract

A universal serial bus power transfer power adapter and a method of operating the same are disclosed. In an embodiment of the technology presented herein, a universal serial bus power transfer (USB-PD) power adapter includes: a USB port; and a USB controller configured to transmit power to the USB port, where the USB controller includes: a voltage regulator configured to generate a supply voltage based on a pulse frequency modulation (PFM) signal; and a variable current bleeder unit configured to generate a variable current bleeder load on the voltage regulator based on the frequency of the PFM signal to maintain the frequency of the PFM signal above an audible frequency range.

Description

Technical Field

[0001] The present disclosure relates to a Universal Serial Bus (USB) power delivery power adapter and a method of operating the same. Background Art

[0002] Various electronic devices (e.g., such as smart phones, tablets, notebook computers, laptop computers, hubs, chargers, adapters, etc.) are configured to transfer power through a USB connector according to a USB power delivery protocol defined in various revisions of the Universal Serial Bus (USB) power delivery (USB-PD) specification. An alternating current to direct current (AC-DC) converter converts power from an alternating current (AC) source to a direct current (DC) source at a specified voltage level. A buck converter is a DC-DC switching converter that reduces the input voltage while increasing the load current. One technique for controlling a buck converter is pulse frequency modulation (PFM) technique, which uses a signal that changes the pulse frequency according to the load current to control a switch to maintain the output voltage. As the load current increases, the PFM frequency increases, and as the load current decreases, the PFM frequency decreases. Summary of the Invention

[0003] The Summary of the Invention is provided to introduce a series of concepts in a simplified form that will be further described in the Detailed Description below. The Summary of the Invention is not intended to identify key elements or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0004] In an embodiment of the techniques presented herein, a Universal Serial Bus (USB) power delivery (USB-PD) power adapter includes: a USB port; and a USB controller configured to transfer power to the USB port, wherein the USB controller includes: a voltage regulator configured to generate a supply voltage based on a pulse frequency modulation (PFM) signal; and a variable current sink unit configured to generate a variable current sink load on the voltage regulator based on the frequency of the PFM signal to keep the frequency of the PFM signal above an audible frequency range.

[0005] In an embodiment of the techniques presented herein, a method of operating a Universal Serial Bus (USB) power delivery (USB-PD) power adapter includes: transferring power to a USB port using a USB controller; generating a supply voltage for the USB controller in a voltage regulator based on a pulse frequency modulation (PFM) signal; and generating a variable current sink load on the voltage regulator based on the frequency of the PFM signal to keep the frequency of the PFM signal above an audible frequency range.

[0006] In an implementation of the technology presented herein, a system for operating a Universal Serial Bus Power Delivery (USB-PD) power adapter includes: means for transmitting power to a USB port using a USB controller; means for generating a supply voltage for the USB controller in a voltage regulator based on a Pulse Frequency Modulation (PFM) signal; and means for generating a variable current drain load on the voltage regulator based on the frequency of the PFM signal to keep the frequency of the PFM signal above the audible frequency range.

[0007] In an implementation of the technology presented herein, a Universal Serial Bus Power Delivery (USB-PD) power adapter includes: a USB port; a power switch connected between a voltage input terminal and the USB port; and a USB controller configured to control the power switch to transmit power from the voltage input terminal to the USB port, wherein the USB controller includes: a voltage regulator configured to generate a supply voltage based on a Pulse Frequency Modulation (PFM) signal; and a variable current drain unit configured to generate a variable current drain load on the voltage regulator based on the frequency of the PFM signal to keep the frequency of the PFM signal above the audible frequency range.

[0008] To achieve the foregoing and related purposes, the following description and drawings set forth certain illustrative aspects and implementations. These illustrative aspects and implementations only indicate some of the various ways in which one or more aspects may be employed. When considered in conjunction with the drawings, other aspects, advantages, and novel features of the present disclosure will become apparent from the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram showing a Universal Serial Bus (USB) Power Delivery (USB-PD) adapter according to some implementations.

[0010] Figure 2 is a diagram showing the operation of a high voltage regulator according to some implementations.

[0011] Figure 3 is a block diagram of a digital variable current drain unit according to some implementations.

[0012] Figure 4A is a block diagram of an analog variable current drain unit according to some implementations.

[0013] Figure 4B is a circuit diagram of an analog variable current drain unit according to some implementations.

[0014] Figure 5FIG. is a diagram showing the operation of an analog variable current discharge unit as a function of load current i_L in accordance with some embodiments.

[0015] Figure 6 FIG. is a diagram showing the operation of a digital variable current discharge unit and an analog variable current discharge unit as a function of PFM frequency T PFM in accordance with some embodiments.

[0016] Figure 7 FIG. is a flowchart showing a method of operating a USB power adapter to avoid audible noise generation in accordance with some embodiments.

[0017] Figure 8 FIG. is a diagram of an on-chip integrated circuit (IC) USB controller in accordance with some embodiments. DETAILED DESCRIPTION

[0018] The claimed subject matter is now described with reference to the drawings, wherein like reference numerals are used throughout to refer to like elements. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of the claimed subject matter. It is evident, however, that the claimed subject matter may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing the claimed subject matter.

[0019] It should be understood that the following description of embodiments is not to be taken in a limiting sense. The scope of the present disclosure is not intended to be limited by the embodiments or drawings described hereinafter which are to be regarded as illustrative only. The drawings are considered to be schematic representations and the elements shown in the drawings are not necessarily shown to scale. Rather, the various elements are represented such that their function and general purpose become apparent to a person skilled in the art.

[0020] All numerical values in the detailed description herein and the claims are indicative values modified by "about" or "approximately" and account for experimental errors and variations that would be expected by a person of ordinary skill in the art.

[0021] Figure 1FIG. is a block diagram showing a Universal Serial Bus (USB) Power Delivery (USB-PD) adapter 100 according to some embodiments. In some embodiments, as shown, the USB-PD adapter 100 includes a USB controller 102 (also referred to as a USB-PD controller) as part of a DC / DC controller or subsystem. The USB-PD adapter 100 includes at least one USB port 104, however, any number of USB ports may be provided. The USB port 104 is connected to provide an output voltage VBUS_OUT to a connected load. The USB controller 102 controls a power switch 106 to transfer power from an input terminal VBUS_IN to the USB port 104.

[0022] In some embodiments, the USB controller 102 includes a microcontroller unit (MCU) subsystem 108 that includes logic, memory (e.g., flash memory, static read-only memory (SROM), static random access memory (SRAM), or other memory), and a microprocessor or controller, an analog-to-digital converter (ADC), a plurality of general-purpose input / output (GPIO), and a serial communication bus (SCB) for executing a program stored in the memory of the MCU subsystem. The USB controller 102 includes: a power switch 110 connected in parallel with the power switch 106 between VBUS_IN and VBUS_OUT, a gate driver 112 for controlling the power switch 106, a gate driver 114 for controlling the power switch 110, and a current sensing unit 116 configured to measure the current through the power switch 110 and control the gate driver 114 to limit the current provided through the power switch 110. In some embodiments, the current sensing unit 116 includes logic for controlling the gate driver 114. In some embodiments, the logic in the current sensing unit 116 may be provided by the MCU subsystem 108. The use of the path through the power switch 106 and the current limiting path through the power switch 110 depends on the protocol established by the USB controller 102 with the device connected to the USB port 104.

[0023] The USB controller 102 further includes a voltage regulation subsystem 118 for providing protection for the USB controller 102 and generating an internal voltage source. In some embodiments, the voltage regulation subsystem 118 includes an overvoltage / undervoltage (OV / UV) unit 120 configured to provide protection on the VBUS_IN line, a high voltage (HV) regulator 122, a low dropout regulator (LDO) 124, and a low voltage (LV) regulator 126. In some embodiments, external circuit elements such as an inductor 128 or capacitors 130, 132, 134 are provided as storage and filtering elements for the HV regulator 122, LDO 124, and LV regulator 126.

[0024] In some embodiments, the HV regulator 122 is a pulse frequency modulation (PFM) buck converter that provides a PFM signal to a switch to store energy in the inductor 128, thereby generating an output voltage (e.g., 3.6V) at the capacitor 130 by reducing the input voltage VBUS_IN. The frequency of the PFM signal (e.g., the time interval between pulses) depends on the load on the HV regulator 122. As the load current decreases and the frequency drops, the PFM frequency may fall within the audible range (e.g., 20 Hz to 20 KHz), where the user can hear the vibrations in the inductor 128 and the capacitor 130. To avoid generating audible noise in the HV regulator 122, a variable current bleeder unit (VCB) 136 is provided to generate an additional current load on the HV regulator 122 to keep the PFM signal outside the audible range. When the load on the HV regulator 122 decreases, the VCB 136 increases the bleed current to avoid generating audible noise. The variable bleed current method only draws the minimum current required to keep the system outside the audible frequency range, thereby saving power compared to a fixed bleed current method. The VCB 136 can be implemented using digital circuitry or analog circuitry.

[0025] Figure 2 is a schematic diagram 200 showing the operation of the HV regulator 122 according to some embodiments. The HV regulator 122 operates in a hysteretic or ripple mode, where a DC set voltage is selected for the internal supply voltage of the USB controller 102, e.g., 3.6V. The HV regulator 122 employs a series of switching cycles in the PFM pulse 202 during the charging interval T PFM_ON to induce current in the inductor 128 and generate the internal supply voltage on the capacitor 130. The PFM pulse 202 is initiated in response to the voltage on the capacitor 130 reaching the negative hysteresis limit 204, and the PFM pulse 202 is maintained until the DC voltage on the capacitor 130 reaches the positive hysteresis limit 206. The time interval T PFM between the PFM pulses 205 is determined using the internal supply voltage and the bleed current i_BL generated by the VCB 136 based on the load current i_L of the device in the USB controller 102. According to the following formula, the length of the PFM period 202 depends on the total current of the HV regulator 122, the hysteresis voltage V HYS and the capacitance C CNVT :

[0026]

[0027] The ripple or hysteresis voltage V HYS of the HV regulator 122 is the difference between the hysteresis limits 204 and 206. As the load decreases, T PFM increases. Without intervention from the VCB 136, TPFM can correspond to frequencies within the audible range, thereby generating audible noise in the inductor 128, capacitor 130, or other components of the USB controller 102.

[0028] Figure 3 is a block diagram of the digital VCB 136D according to some embodiments. In some embodiments, the digital VCB 136D is implemented in the firmware of the USB controller 102. The PFM signal is received by a frequency calculator 300 that determines the frequency of the PFM signal based on the time interval T between the PFM pulses 205 PFM to determine the frequency of the PFM signal. The controller 302 compares the PWM frequency with a first threshold value, such as a value greater than 20 KHz. If the PFM frequency is less than the first threshold, the controller 302 increments the current code provided to the current digital-to-analog converter (DAC) 304. The current DAC 304 is a circuit that generates a current based on the digital value of the current code, such as a binary weighted current ladder. If the PFM frequency is greater than a second threshold, the controller 302 decrements the current code. Thus, when the load on the HV regulator 122 decreases and the PFM frequency decreases, the controller 302 increments the current code to increase the current load generated by the digital VCB 136D, thereby keeping the PFM frequency outside the audible range. At a later time, when the load on the HV regulator 122 increases and the PFM frequency increases, the controller 302 decrements the current code to decrease the current load generated by the digital VCB 136D, thereby avoiding generating more current than necessary to keep the PFM frequency outside the audible range, thus saving power.

[0029] Figure 4A is a block diagram of the analog VCB 136A according to some embodiments, and Figure 4B is a circuit diagram of the analog VCB 136A according to some embodiments. In some embodiments, the analog VCB 136A includes a frequency-to-voltage (F2V) converter 400 configured to generate a voltage corresponding to the frequency of the PFM signal and a voltage-to-current (V2I) converter 402 configured to generate a discharge current based on the output of the F2V converter 400. In some embodiments, the F2V converter 400 includes a rising-edge reset unit 406 that generates a reset signal for a pulse generator 408 based on the rising edge of the PFM signal. The pulse generator 408 generates a pulse of a fixed width T PULSE and the time period of this signal indicates the time interval between the PFM pulses. The output of the pulse generator 408 is provided to an RC filter 410 that generates a control voltage V PULSE based on T RC where:

[0030]

[0031] In some embodiments, the pulse generator 408 includes a reset switch 411 controlled by a rising-edge reset unit 406, a capacitor 412 with a capacitance of C1 that is charged by a current source 414 outputting a current I1, and a comparator 416. After the capacitor 412 is discharged through the switch 411 at the rising edge of the PFM signal, the capacitor 412 is charged based on the current I1 from the current source 414 and the capacitance C1. The reference voltage v1 of the comparator is based on T PULSE , I1, and C1. In the example, T PULSE = 25 us, I1 = 50 nA, and C1 = 1 pF. The reference voltage for this example is:

[0032]

[0033] According to the following formula, the voltage V RC corresponding to the time between PFM pulses is provided to a transconductance amplifier 417, which has an input branch 418 controlled by V RC , an output branch 420 controlled by a reference voltage V REF , a current mirror 422 that generates a transconductance current i GM , and output stages 424 and 426 that generate a discharge current i_BL:

[0034]

[0035] i_bl = G m (V REF - V RC ),

[0036] where, in the example, G m = 20 mS and N = 1000.

[0037] The reference voltage V REF is selected such that when i_L = 0 mA, i_bl draws current to keep T PFM at 50 us or less. As i_L increases, i_BL decreases. An increase in V RC corresponds to a decrease in T PFM .

[0038] Figure 5FIG. 500 is a schematic diagram showing the operation of the analog VCB 136A as a function of the load current i_L according to some embodiments. The discharge current curve 502 shows that the discharge current i_BL increases as the load current i_L decreases. The PFM frequency curve 504 shows that the PFM frequency is maintained above an audible range, such as 20 KHz, based on the discharge current compensation generated by the analog VCB 136A.

[0039] Figure 6 FIG. 600 is a schematic diagram showing the operation of the digital VCB 136D and the analog VCB 136A as a function of the PFM frequency T PFM according to some embodiments. Curve 602 shows the discharge current i_BL generated by the digital VCB 136D as a function of the PFM frequency. Curve 602 shows a stepwise increase according to the digital current code provided to the current DAC 304. Curve 604 shows the discharge current i_BL generated by the analog VCB 136A as a function of the PFM frequency. Curve 602 shows an approximately linear function of the discharge current with respect to the PFM frequency.

[0040] Figure 7 FIG. 700 is a flowchart showing a method of operating a USB power adapter to avoid audible noise generation according to some embodiments. At 702, power is transmitted to the USB port 104 using the USB controller 102. At 704, a supply voltage for the USB controller 102 is generated in the voltage regulator 122 based on a pulse frequency modulation (PFM) signal. At 706, a variable current discharge load is generated on the voltage regulator 122 based on the frequency of the PFM signal to keep the frequency of the PFM signal above the audible frequency range.

[0041] Figure 8It is a block diagram showing a system 800 for a USB device according to some embodiments. In some embodiments, the system 800 includes a peripheral subsystem 802, a peripheral interconnect 804, a CPU subsystem 808, and a USB-PD controller 809. In some embodiments, the peripheral subsystem 802 includes multiple components for USB Power Delivery (USB-PD). The peripheral subsystem 802 may include a peripheral interconnect 804, which includes a Peripheral Clock Module (PCLK) 806 for providing clock signals to various components of the peripheral subsystem 802. The peripheral interconnect 804 may be a peripheral bus, such as a single-level or multi-level Advanced High-Performance Bus (AHB), and may provide a data and control interface between the peripheral subsystem 802 and the CPU subsystem 808. The peripheral interconnect 804 may include controller circuitry such as a Direct Memory Access (DMA) controller, which may be programmed to transfer data between peripheral blocks without input from the CPU subsystem 808, without control from the CPU subsystem 808, or without imposing the same transfer.

[0042] The peripheral interconnect 804 may be used to couple the components of the peripheral subsystem 802 to other components of the system 800. A plurality of General-Purpose Input / Output (GPIO) 812 may be coupled to the peripheral interconnect 804 for sending and receiving signals. The GPIO 812 may include circuitry configured to implement various functions such as pull-up, pull-down, input threshold selection, input and output buffer enable / disable, multiplexing, etc. Other functions may also be implemented by the GPIO 812. One or more Timer / Counter / Pulse-Width Modulator (TCPWM) 814 may also be coupled to the peripheral interconnect and may include circuitry implementing a timing circuit (timer), a counter, a pulse-width modulator (PWM), a decoder, and other digital functions associated with working with I / O signals, and may provide digital signals for the system components of the system 800. The peripheral subsystem 802 may also include one or more Serial Communication Blocks (SCB) 816 for implementing serial communication interfaces such as I2C, Serial Peripheral Interface (SPI), Universal Asynchronous Receiver / Transmitter (UART), Controller Area Network (CAN), CXPI (Clock eXtended Peripheral Interface), etc.

[0043] For USB power delivery applications, the peripheral subsystem 802 may include a USB power delivery subsystem 818 that is coupled to the peripheral interconnect 804 and includes a set of USB PD modules 820 for use with USB power delivery. The USB PD modules 820 may be coupled to the peripheral interconnect 804 via a USB-PD interconnect 822. The USB PD modules 820 may include: an LVDO, an LED driver, a VBUS FET unit, a gate driver, a VBUS discharge unit, an OV / UV unit, a communication channel PHY (CC PHY) logic for supporting communication on a Type-C communication channel (CC), a 5V pump unit, a high voltage regulator (HV REG) for converting the supply voltage to the precise voltage (e.g., 3.6V) required by the USB controller 102, and one or more ADC units.

[0044] The USB power delivery subsystem 818 may further include pads 824 for external connection and an electrostatic discharge (ESD) suppression circuit 826 that may be required on the Type-C port. The USB PD modules 820 may further include a communication module for retrieving and transmitting information such as control signals, for example, from the USB controller 102.

[0045] The GPIO 812, TCPWM 814, and SCB 816 may be coupled to an input / output (I / O) subsystem 828 that may include a high speed (HS) I / O matrix 830 connected to a plurality of GPIOs 832. The GPIO 812, TCPWM 814, and SCB 816 may be coupled to the GPIOs 832 via the HS-I / O matrix 830.

[0046] A central processing unit (CPU) subsystem 808 is provided for processing instructions, storing program information, and data. The CPU subsystem 808 may include one or more processing units 834 for executing instructions and reading from and writing to memory locations in a plurality of memories. The processing unit 834 may be a processor suitable for operating in an integrated circuit (IC) or system-on-chip (SOC) device. In some embodiments, the processing unit 834 may be optimized for low-power operation using a large amount of clock gating. In this embodiment, different internal control circuits may be implemented for the operation of the processing unit in different power states. For example, the processing unit 834 may include a single-wire debug (SWD) module, a terminal count (TC) module, a fast multiplier, a nested vector interrupt controller (NVIC), and an interrupt multiplexer (IRQMUX). The CPU subsystem 808 may include one or more memories, including a flash memory 836, a static random access memory (SRAM) 838, and a read-only memory (ROM) 840. The flash memory 836 may be a non-volatile memory (such as NAND flash, NOR flash, etc.) configured to store data, programs, and / or other firmware instructions. The flash memory 836 may include a system performance controller interface (SPCIF) register and a read accelerator, and improve the access times by being integrated into the CPU subsystem 808. The SRAM 838 may be a volatile memory configured to store data and firmware instructions accessible by the processing unit 834. The ROM 840 may be configured to store boot routines, configuration parameters, and other firmware parameters and settings that do not change during the operation of the system 800. The SRAM 838 and the ROM 840 may have associated control circuitry. The processing unit 834 and the memory modules 836, 838, 840 may be coupled to a system interconnect 842 to route signals to various components of the CPU subsystem 808 and route signals from various components of the CPU subsystem 808 to other blocks or modules of the system 800. The system interconnect 842 may be implemented as a system bus, such as a single-level or multi-level AHB. The system interconnect 842 may be configured as an interface for coupling various components of the CPU subsystem 808 together. The system interconnect 842 may be coupled to a peripheral interconnect 804 to provide a signal path between the components of the CPU subsystem 808 and the components of the peripheral subsystem 802.

[0047] System resources 810 may include a power module 844, a clock module 846, a reset module 848, and a test module 850. The power module 844 may include a sleep control module, a wake interrupt control (WIC) module, a power-on reset (POR) module, multiple voltage references (REF), and a PWRSYS module. In some embodiments, the power module 844 may include circuitry that enables the system 800 to draw power from and / or supply power to an external source at different voltage and / or current levels and control operations in different power states such as active, low power, or sleep states. The clock module 846 may include a clock control module, a watchdog timer (WDT), an internal low oscillator (ILO), and an internal master oscillator (IMO). The reset module 848 may include a reset control module and an external reset module (XRES module). The test module 850 may include a module for controlling and entering a test mode, and a test control module for simulating functional and digital functions (digital test and analog DFT).

[0048] The system 800 may be implemented in a single (e.g., monolithic) semiconductor chip. In other embodiments, different parts or modules of the system 800 may be implemented on different semiconductor dies. For example, the memory modules 836, 838, 840 of the CPU subsystem 808 may be on-chip or off-chip. In still other embodiments, circuitry with independent dies may be packaged in a single "chip" or remain independent and arranged as separate components on a circuit board (or in a USB cable connector).

[0049] System 800 can be implemented in multiple application environments to provide USB PD functionality. In any application environment, an electronic device (e.g., a USB-enabled device) can have an IC controller or an SOC implementation implemented by System 800, which is arranged and configured to perform operations according to the techniques described herein. In an implementation, System 800 can be arranged and configured in a personal computer (PC) power adapter for a laptop computer, notebook computer, etc. In another implementation, System 800 can be housed in a power adapter (e.g., a wall charger) for a mobile electronic device (e.g., a smart phone, a tablet, etc.). In another implementation, System 800 can be placed and configured in a wall socket that is configured to provide power via a USB Type-A and / or Type-C port. In another implementation, System 800 can be arranged and configured in a vehicle charger that is configured to provide power via a USB Type-A and / or Type-C port. In yet another implementation, System 800 can be arranged and configured in a power bank that can be charged via a USB Type-A and / or Type-C port and then provide power to another electronic device. In other implementations, a system such as System 800 can be configured with the power switch gate control circuitry described herein and incorporated into various other USB-enabled electronic or electromechanical devices.

[0050] It should be understood that a system implemented on or as an IC controller, such as System 800, can be placed in various applications that vary according to the type of power source used and the power supply direction. For example, in the case of a vehicle charger, the power source is the vehicle battery that provides DC power, while in the case of a mobile power adapter, the power source is an AC wall socket. Additionally, in the case of a PC power adapter, the flow of power input is from the provider device to the consumer device, while in the case of a power bank, the flow of power input can be in either direction, depending on whether the power bank is operating as a power provider (e.g., powering another device) or as a power consumer (e.g., allowing itself to be charged). For these reasons, the various applications of System 800 should be considered illustrative rather than restrictive in nature.

[0051] In an embodiment of the technology presented herein, a Universal Serial Bus Power Delivery (USB-PD) power adapter includes: a USB port; and a USB controller configured to transfer power to the USB port, wherein the USB controller includes: a voltage regulator configured to generate a supply voltage based on a Pulse Frequency Modulation (PFM) signal; and a variable current sink unit configured to generate a variable current sink load on the voltage regulator based on the frequency of the PFM signal to keep the frequency of the PFM signal above the audible frequency range.

[0052] In an embodiment of the technology presented herein, the variable current sink unit includes a digital variable current sink unit.

[0053] In an embodiment of the technology presented herein, the digital variable current sink unit includes: a frequency calculator configured to determine the frequency of the PFM signal; a current digital-to-analog converter configured to generate a variable current sink load based on a current code; and a controller configured to generate the current code based on the frequency of the PFM signal.

[0054] In an embodiment of the technology presented herein, the variable current sink unit includes an analog variable current sink unit.

[0055] In an embodiment of the technology presented herein, the analog variable current sink unit includes: a frequency-to-voltage converter configured to generate a control voltage according to the frequency of the PFM signal; and a voltage-to-current converter configured to generate a variable current sink load based on the control voltage.

[0056] In an embodiment of the technology presented herein, the frequency-to-voltage converter includes: a pulse generator configured to generate pulses based on the time interval between PFM pulses in the PFM signal; a rising edge reset unit configured to generate a reset signal for the pulse generator based on the rising edge of the PFM signal to terminate the pulses; and a filter configured to generate a control voltage based on the pulses.

[0057] In an embodiment of the technology presented herein, the pulse generator includes: a current source; a capacitor connected to the current source; a switch controlled by the reset signal to discharge the capacitor; and a comparator configured to generate pulses based on a reference voltage and the voltage on the capacitor.

[0058] In an embodiment of the technology presented herein, the voltage-to-current converter includes a transconductance amplifier.

[0059] In an implementation of the technology presented herein, a method for operating a Universal Serial Bus Power Delivery (USB-PD) power adapter includes: transmitting power to a USB port using a USB controller; generating a supply voltage for the USB controller in a voltage regulator based on a Pulse Frequency Modulation (PFM) signal; and generating a variable current sink load on the voltage regulator based on the frequency of the PFM signal to keep the frequency of the PFM signal above the audible frequency range.

[0060] In an implementation of the technology presented herein, generating a variable current sink load includes: configuring a digital variable current sink unit based on the frequency of the PFM signal.

[0061] In an implementation of the technology presented herein, configuring a digital variable current sink unit includes: determining the frequency of the PFM signal in a frequency calculator; generating a variable current sink load in a current digital-to-analog converter based on a current code; and generating a current code based on the frequency of the PFM signal.

[0062] In an implementation of the technology presented herein, generating a variable current sink load includes: configuring an analog variable current sink unit based on the frequency of the PFM signal.

[0063] In an implementation of the technology presented herein, configuring an analog variable current sink unit includes: generating a control voltage in a frequency-to-voltage converter according to the frequency of the PFM signal; and generating a variable current sink load in a voltage-to-current converter based on the control voltage.

[0064] In an implementation of the technology presented herein, generating a control voltage in a frequency-to-voltage converter includes: generating a pulse in a pulse generator based on the time interval between PFM pulses in the PFM signal; generating a reset signal for the pulse generator based on the rising edge of the PFM signal to terminate the pulse, and generating a control voltage based on the pulse.

[0065] In an implementation of the technology presented herein, generating a pulse in a pulse generator includes: charging a capacitor using a current source; generating a pulse based on a reference voltage and the voltage on the capacitor; and controlling a switch based on the reset signal to discharge the capacitor to terminate the pulse.

[0066] In an implementation of the technology presented herein, generating a variable current sink load in a voltage-to-current converter includes: generating a variable current sink load in a transconductance amplifier.

[0067] In an implementation of the technology presented herein, a Universal Serial Bus Power Delivery (USB-PD) power adapter includes: a USB port; a power switch connected between a voltage input terminal and the USB port; and a USB controller configured to control the power switch to transfer power from the voltage input terminal to the USB port, wherein the USB controller includes: a voltage regulator configured to generate a supply voltage based on a Pulse Frequency Modulation (PFM) signal; and a variable current sink unit configured to generate a variable current sink load on the voltage regulator based on the frequency of the PFM signal to keep the frequency of the PFM signal above the audible frequency range.

[0068] In an implementation of the technology presented herein, the variable current sink unit includes a digital variable current sink unit, and the digital variable current sink unit includes: a frequency calculator configured to determine the frequency of the PFM signal; a current digital-to-analog converter configured to generate a variable current sink load based on a current code; and a controller configured to generate the current code based on the frequency of the PFM signal.

[0069] In an implementation of the technology presented herein, the variable current sink unit includes an analog variable current sink unit, and the analog variable current sink unit includes: a frequency-to-voltage converter configured to generate a control voltage according to the frequency of the PFM signal; and a voltage-to-current converter configured to generate a variable current sink load based on the control voltage.

[0070] In an implementation of the technology presented herein, the frequency-to-voltage converter includes: a pulse generator configured to generate pulses based on the time interval between PFM pulses in the PFM signal; a rising-edge reset unit configured to generate a reset signal for the pulse generator based on the rising edge of the PFM signal to terminate the pulses; and a filter configured to generate a control voltage based on the pulses; and the voltage-to-current converter includes a transconductance amplifier.

[0071] Various operations of embodiments are provided herein. In an embodiment, one or more of the described operations may constitute computer-readable instructions stored on one or more computer-readable media, which, if executed by a computing device, will cause the computing device to perform the described operations. The order of some or all of the described operations should not be construed as implying that these operations must be order-dependent. Those skilled in the art who benefit from this specification will understand alternative orders. In addition, it should be understood that not all operations must be present in every embodiment provided herein. In addition, it should be understood that not all operations are required in some embodiments.

[0072] In addition, unless otherwise stated, "first", "second", etc. are not intended to imply aspects such as time, space, order, etc. Rather, such terms are only used as identifiers, names, etc. of features, elements, items, etc. For example, a first object and a second object generally correspond to object A and object B or two different or two identical objects or the same object.

[0073] In addition, "exemplary" etc. are used herein to mean being used as an example, instance, illustration, etc., and are not necessarily advantageous. As used herein, "or" is intended to mean an inclusive "or" rather than an exclusive "or". Additionally, unless otherwise specified or clear from the context for the singular form, "a" and "an" as used in this application can generally be construed to mean "one or more". In addition, at least one of A and B and / or the like generally means A or B and / or both A and B. To the extent that "includes", "having", "has", "with" and / or their variants are used in the detailed description or claims, such terms are intended to be inclusive in a manner similar to the term "comprising".

[0074] In addition, although the present disclosure has been shown and described with respect to one or more implementations, equivalent changes and modifications will occur to those skilled in the art based on a reading and understanding of this specification and the drawings. The present disclosure includes all such modifications and changes and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the components described above (e.g., elements, resources, etc.), unless otherwise indicated, the terms used to describe such components are intended to correspond to any component that performs the specified function of the described component (e.g., is functionally equivalent), even if not structurally equivalent to the disclosed structure. Additionally, although a particular feature of the present disclosure may have been disclosed with respect to only one of several implementations, such a feature may be combined with one or more other features of other implementations as may be desired and advantageous for any given or particular application.

Claims

1. A universal serial bus power transmission USB-PD power adapter, comprising: USB port; as well as A USB controller configured to transmit power to the USB port, wherein the USB controller comprises: a voltage regulator configured to generate a supply voltage based on a pulse frequency modulation (PFM) signal; and A variable current bleeder unit is configured to generate a variable current bleeder load on the voltage regulator based on the frequency of the PFM signal to keep the frequency of the PFM signal above an audible frequency range.

2. The USB-PD power adapter according to claim 1, wherein: The variable current discharge unit includes a digital variable current discharge unit.

3. The USB-PD power adapter according to claim 2, wherein: The digital variable current discharge unit comprises: a frequency calculator configured to determine a frequency of the PFM signal; a current digital-to-analog converter configured to generate the variable current dump load based on a current code; and A controller is configured to generate the current code based on a frequency of the PFM signal.

4. The USB-PD power adapter according to claim 1, wherein: The variable current discharge unit includes an analog variable current discharge unit.

5. The USB-PD power adapter according to claim 4, wherein: The analog variable current discharge unit comprises: a frequency-to-voltage converter configured to generate a control voltage according to a frequency of the PFM signal; and A voltage-to-current converter is configured to generate the variable current bleeder load based on the control voltage.

6. The USB-PD power adapter according to claim 5, wherein: The frequency-to-voltage converter comprises: a pulse generator configured to generate pulses based on time intervals between PFM pulses in the PFM signal; a rising edge reset unit configured to generate a reset signal for the pulse generator based on a rising edge of the PFM signal to terminate the pulse; and A filter is configured to generate the control voltage based on the pulses.

7. The USB-PD power adapter according to claim 6, wherein: The pulse generator comprises: Current source; a capacitor connected to the current source; a switch controlled by the reset signal to discharge the capacitor; and A comparator is configured to generate the pulse based on a reference voltage and a voltage on the capacitor.

8. The USB-PD power adapter according to claim 5, wherein: The voltage-to-current converter includes a transconductance amplifier.

9. A method for operating a Universal Serial Bus Power Delivery (USB-PD) power adapter, comprising: Use a USB controller to deliver power to the USB port; generating a supply voltage for the USB controller in a voltage regulator based on a pulse frequency modulation (PFM) signal; as well as A variable current bleeder load is generated on the voltage regulator based on the frequency of the PFM signal to maintain the frequency of the PFM signal above an audible frequency range.

10. The method according to claim 9, wherein: Generating the variable current discharge load includes: The digital variable current bleeder unit is configured based on the frequency of the PFM signal.

11. The method according to claim 10, wherein: Configuring the digital variable current discharge unit includes: determining the frequency of the PFM signal in a frequency calculator; generating the variable current dump load in a current digital-to-analog converter based on a current code; and The current code is generated based on a frequency of the PFM signal.

12. The method according to claim 9, wherein: Generating the variable current discharge load includes: An analog variable current bleeder unit is configured based on the frequency of the PFM signal.

13. The method according to claim 12, wherein: Configuring the analog variable current discharge unit includes: generating a control voltage in a frequency-to-voltage converter according to the frequency of the PFM signal; and The variable current dump load is generated in a voltage-to-current converter based on the control voltage.

14. The method according to claim 13, wherein: Generating the control voltage in the frequency-to-voltage converter includes: generating pulses in a pulse generator based on time intervals between PFM pulses in the PFM signal; generating a reset signal for the pulse generator based on a rising edge of the PFM signal to terminate the pulse; and The control voltage is generated based on the pulses.

15. The method according to claim 14, wherein: Generating the pulse in the pulse generator comprises: Using a current source to charge the capacitor; generating the pulse based on a reference voltage and a voltage on the capacitor; and A switch is controlled based on the reset signal to discharge the capacitor to terminate the pulse.

16. The method according to claim 13, wherein: Generating the variable current dump load in the voltage-to-current converter includes: The variable current bleeder load is generated in a transconductance amplifier.

17. A universal serial bus power transmission USB-PD power adapter, comprising: USB port; A power switch connected between a voltage input terminal and the USB port; as well as A USB controller configured to control the power switch to transfer power from the voltage input terminal to the USB port, wherein the USB controller comprises: a voltage regulator configured to generate a supply voltage based on a pulse frequency modulation (PFM) signal; and A variable current bleeder unit is configured to generate a variable current bleeder load on the voltage regulator based on the frequency of the PFM signal to keep the frequency of the PFM signal above an audible frequency range.

18. The USB-PD power adapter according to claim 17, wherein: The variable current discharge unit includes a digital variable current discharge unit, and the digital variable current discharge unit includes: a frequency calculator configured to determine a frequency of the PFM signal; a current digital-to-analog converter configured to generate the variable current dump load based on a current code; and A controller is configured to generate the current code based on a frequency of the PFM signal.

19. The USB-PD power adapter according to claim 17, wherein: The variable current discharge unit includes an analog variable current discharge unit, and the analog variable current discharge unit includes: a frequency-to-voltage converter configured to generate a control voltage according to a frequency of the PFM signal; and A voltage-to-current converter is configured to generate the variable current bleeder load based on the control voltage.

20. The USB-PD power adapter according to claim 19, wherein: The frequency-to-voltage converter comprises: a pulse generator configured to generate pulses based on time intervals between PFM pulses in the PFM signal; a rising edge reset unit configured to generate a reset signal for the pulse generator based on a rising edge of the PFM signal to terminate the pulse; and a filter configured to generate the control voltage based on the pulses; and The voltage-to-current converter includes a transconductance amplifier.

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