Pulse latch with pre-writing and data recovery functions and digital circuit
By introducing pre-write and data recovery functions into the pulse latch, using MTJ and specific transistor structures, the problems of low write success rate and large area overhead under harsh timing conditions are solved, and higher stability and functional expansion are achieved.
Patent Information
- Application Number
- CN202510270800.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-07
- Publication Date
- 2025-06-24
AI Technical Summary
Under the harsh timing conditions of existing pulse latches, the writing success rate of non-volatile memory devices is low, and the pulse generator occupies a large area.
A pulse latch with pre-write and data recovery functions is designed, using magnetic tunnel junction device MTJ and a specific transistor structure, and the pulse latch mode and data recovery mode are realized through a level-time controller.
It improves the write success rate under harsh timing conditions, reduces the number and area overhead of the pulse generator, and improves the stability and functional expansion of the latch.
Smart Images
Figure CN120200588A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a latch in the field of integrated circuit technology, and particularly to a pulsed latch with pre-write and data recovery functions, and also relates to a digital circuit. Background Art
[0002] A pulsed-latch uses a pulsed signal instead of a clock signal acting on the clock terminal of the latch, so that the transparent time of the latch is very short to avoid generating additional timing overhead. The pulsed-latch mainly consists of two parts: 1) A pulse generator for generating a pulse with a certain width. 2) A latch that transfers the input data D to the output Q when the pulsed signal arrives and latches the output Q in the storage unit.
[0003] In the current pulsed-latch design, to overcome the adverse effects brought by changes in manufacturing processes, circuit voltages, environmental temperatures, etc., and to reduce the timing overhead, the pulse generator part usually adopts a dynamic OR gate (XOR) structure, and automatically controls the pulse width by comparing the values of the input D and the output Q. The pulsed-latch part realizes the function of storing data when powered off by embedding a non-volatile storage unit (MTJ) composed of a magnetic tunnel structure in the latch structure. However, the existing pulsed-latch has the following problems: The pulse generator using the dynamic OR gate (XOR) structure consumes a large number of transistors to maintain the potential stability of its key nodes and generate correct pulses. The usage of its transistors can account for 60% of the overall pulse generator. That is to say, the current pulse generator based on the dynamic OR gate (XOR) structure will generate a large area overhead. At the same time, since the pulse generated by the pulsed-latch has a short time, and the non-volatile storage device needs a continuous current for a certain time to store data, the difficulty of writing data to the non-volatile storage device embedded in the latch is increased in an environment with strict timing requirements. Summary of the Invention
[0004] To solve the technical problem that the success rate of writing data to the non-volatile device in the latch is low under strict timing conditions of the existing pulsed-latch based on the dynamic OR gate, the present invention provides a pulsed-latch and a digital circuit with pre-write and data recovery functions.
[0005] The present invention is implemented by the following technical solutions: A pulsed-latch with pre-write and data recovery functions, which includes a pulse generation unit for generating a pulsed signal and a data latch unit for latching data when the pulsed signal arrives, and further includes:
[0006] An MTJ memory cell, which includes a magnetic tunnel junction device MTJ, at least one NMOS transistor, and at least two PMOS transistors; the magnetic tunnel junction device is connected to the storage node of the data latch unit through one of the PMOS transistors; at least one NMOS transistor and another one of the PMOS transistors are used to sense the written data in advance and provide a full-swing potential for the magnetic tunnel junction device MTJ and one of the PMOS transistors; the MTJ memory cell is used to store data and provide a pulse latch mode and a data recovery mode when the circuit is powered off through different resistance states of the magnetic tunnel junction device MTJ; and
[0007] A level-timing controller, which is used to transfer input data to the data latch unit and the MTJ memory cell when the pulse generating unit generates the pulse signal in the pulse latch mode, and control the MTJ memory cell to write the corresponding stored data back to the data latch unit in the data recovery mode.
[0008] By setting a pulse latch mode and a data recovery mode when the circuit is powered off, under the control of the level-timing controller, the input data is transferred to the data latch unit and the MTJ memory cell, and the pulse latch mode is realized when the circuit is powered off. The present invention utilizes the different resistance states of the magnetic tunnel junction device MTJ under different voltages and currents to realize the data recovery mode, and the MTJ memory cell writes the corresponding stored data back to the data latch unit, thus realizing the functions of data pre-writing and data recovery, expanding the functions of the pulse latch, improving the stability, and being able to improve the writing success rate of the magnetic tunnel junction device MTJ in the latch under harsh timing conditions, and solving the technical problem that the writing success rate of non-volatile devices in the existing pulse latch based on a dynamic OR gate is low under harsh timing conditions of the latch.
[0009] As a further improvement of the above solution, the pulse latch further includes:
[0010] A data input unit, which is used to transmit input data; and
[0011] A data update logic judgment unit, which is used to judge whether the stored data in the data latch unit is the same as the input data. If so, it controls the pulse generating unit not to generate the pulse signal, otherwise it drives the pulse generating unit to generate the pulse signal.
[0012] As a further improvement of the above solution, in the MTJ memory cell, the two PMOS transistors are PMOS transistor M18 and PMOS transistor M19 respectively, and one NMOS transistor is NMOS transistor M20; one end of the magnetic tunnel junction device MTJ is connected to the control line CTRL of the level-timing controller, and the other end is connected to the sources of PMOS transistor M18, PMOS transistor M19 and NMOS transistor M20; the gate of PMOS transistor M18 is connected to the word line control line S1 of the level-timing controller, and the drain is connected to one of the storage nodes Q of the data latch unit; the gate of PMOS transistor M19 is connected to the other storage node Qb of the data latch unit, and the drain is connected to the power supply VDD; the gate of NMOS transistor M20 is connected to the storage node Qb, and the source is connected to the ground wire VSS.
[0013] Further, the data latch unit includes transistors M12, M13, M14, M15, M16, M17; the gate of transistor M12 is connected to the storage node Q, the drain is connected to the power supply VDD, and the source is connected to the drain of transistor M13; the gate of transistor M13 is connected to the pulse signal PULSE generated by the pulse generation unit, and the source is connected to the storage node Qb; the gate of transistor M14 is connected to the inverted pulse signal PULSEB generated by the pulse generation unit, the drain is connected to the storage node Qb, and the source is connected to the drain of transistor M15; the gate of transistor M15 is connected to the storage node Q, and the source is grounded; the gate of transistor M16 is connected to the storage node Qb, the drain is connected to the power supply VDD, and the source is connected to the storage node Q; the gate of transistor M17 is connected to the storage node Qb, the drain is connected to the storage node Q, and the source is grounded.
[0014] Still further, the pulse generation unit includes transistors M7, M8, M9, M10, M11; the gate of transistor M7 is connected to the source of transistor M8, the drain of transistor M9, the gate of transistor M10, and the gate of transistor M11. The drain of transistor M7 is connected to the gate of transistor M8 and the gate of transistor M9. The source of transistor M7 is connected to the data update logic judgment unit; the drain of transistor M8 is connected to the power supply VDD, the source of transistor M9 is grounded, the drain of transistor M10 is connected to the clock signal CLK generated by the level-timing controller, and the source of transistor M10 is used as the output terminal of the pulse signal PULSE generated by the pulse generation unit; the drain of transistor M11 is connected to the source of transistor M10, and the source is grounded.
[0015] Further, the data update logic judgment unit includes transistors M1, M2, M3, M4, M5, and M6; the gate of transistor M1 is connected to the clock signal CLK, the drain is connected to the power supply VDD, and the source is connected to the drains of transistor M7, transistor M2, and transistor M3; the gate of transistor M2 is connected to the storage node Q, and the source is connected to the drain of transistor M4; the gate of transistor M3 stores the node Qb, and the source is connected to the drain of transistor M5; the gate of transistor M4 is connected to the input signal D of the input data, and the source is connected to the sources of transistor M7, transistor M5, and the drain of transistor M6; the gate of transistor M5 is connected to the inversion signal Db of the input data; the gate of transistor M6 is connected to the clock signal CLK, and the source is grounded.
[0016] Further, the signals of the storage node Q and the storage node Qb are opposite, and the input signal D and the inversion signal Db are opposite signals.
[0017] Further, the data input unit includes an inverter INV1, an inverter INV2, a transistor M21, and a transistor M22; the input terminal of the inverter INV1 is connected to the input signal D, and the output terminal transmits the inversion signal Db of the output data; the input terminal of the inverter INV2 is connected to the pulse signal PULSE, and the output terminal is connected to the inverted pulse signal PULSEB; the gate of the transistor M21 is connected to the pulse signal PULSE, the source is connected to the output terminal of the inverter INV1, and the drain is connected to the storage node Qb; the gate of the transistor M22 is connected to the inverted pulse signal PULSEB, the source is connected to the output terminal of the inverter INV1, and the drain is connected to the storage node Qb.
[0018] Further, the pulse generation unit is used to generate a pulse square wave in the pulse latch mode and hold the node potential by itself when the clock signal CLK is at a high level.
[0019] The present invention also provides a digital circuit, which includes any one of the above-mentioned pulse latches with pre-write and data recovery functions.
[0020] Compared with the existing pulse latches, the pulse latch and digital circuit with pre-write and data recovery functions of the present invention have the following beneficial effects:
[0021] 1. The pulse latch with pre-write and data recovery functions sets the pulse latch mode and the data recovery mode when the circuit is powered off. The data update logic judgment unit determines whether the stored data in the data latch unit is the same as the input data. If they are the same, no pulse signal is generated and no data update is performed, saving the energy consumption of the pulse latch. If they are different, under the control of the level-timing controller, the input data is transmitted to the data latch unit and the MTJ storage unit, and the pulse latch mode is realized when the circuit is powered off. The present invention utilizes the different resistance states of the magnetic tunnel junction device MTJ under different voltages and currents to realize the data recovery mode. The MTJ storage unit writes the corresponding stored data back to the data latch unit, thus realizing the functions of data pre-write and data recovery, expanding the functions of the pulse latch, enhancing the stability, and being able to improve the writing success rate of the magnetic tunnel junction device MTJ in the latch under harsh timing conditions, solving the technical problem that the writing success rate of non-volatile devices in the existing pulse latch based on a dynamic OR gate is low under harsh timing conditions of the latch.
[0022] 2. In the pulse latch with pre-write and data recovery functions, the number of transistors in its pulse generation unit is optimized compared with the dynamic OR gate (XOR) structure used in the existing pulse generator. The number of transistors is reduced, resulting in a large reduction in the area of the pulse generation structure, that is, a small-area pulse generation unit, thus solving the problem of the relatively high area occupation of the existing pulse latch based on a dynamic OR gate. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 is the framework diagram of the pulse latch with pre-write and data recovery functions according to Embodiment 1 of the present invention;
[0024] Figure 2 is Figure 1 the circuit diagram of the data update logic judgment unit and the pulse generation unit of the pulse latch with pre-write and data recovery functions in
[0025] Figure 3 is Figure 1 the circuit diagram of the data input unit, data latch unit, and MTJ storage unit of the pulse latch with pre-write and data recovery functions in
[0026] Figure 4 is the timing diagram of the data latch unit of the pulse latch with pre-write and data recovery functions according to Embodiment 2 of the present invention storing the data "0" in the pulse latch mode;
[0027] Figure 5 is the timing diagram of the pulse latch in Embodiment 2 storing the data "1" in the pulse latch mode;
[0028] Figure 6It is a timing diagram of the pulse latch in the data recovery mode in Embodiment 2 for recovering data. Detailed implementation manners
[0029] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.
[0030] Embodiment 1
[0031] Please refer to Figure 1 、 Figure 2 and Figure 3 This embodiment provides a pulse latch with pre-write and data recovery functions. The pulse latch has the functions of pre-writing data and recovering data when the circuit is powered off. Among them, the pulse latch includes a pulse generation unit, a data latch unit, an MTJ storage unit, a data input unit, a data update logic judgment unit, and a level-timing controller. In some other embodiments, the latch may further include some other unit modules, which can be added according to actual functional requirements.
[0032] The MTJ storage unit includes a magnetic tunnel junction device MTJ, at least one NMOS transistor, and at least two PMOS transistors. The MTJ storage unit is used to store data and provide a pulse latch mode and a data recovery mode when the circuit is powered off through different resistance states of the magnetic tunnel junction device MTJ. One end of the magnetic tunnel junction device MTJ is connected to the control line of the level-timing controller, and the other end is connected to the storage node of the data latch unit through one of the PMOS transistors. At least one NMOS transistor and another one of the PMOS transistors are used to sense the written data in advance and provide a full-swing potential to the magnetic tunnel junction device MTJ and one of the PMOS transistors.
[0033] In this embodiment, for simplicity of structure, these transistors are PMOS transistor M18, PMOS transistor M19, and NMOS transistor M20. One end of the magnetic tunnel junction device MTJ is connected to the control line CTRL of the level-timing controller, and the other end is connected to the sources of PMOS transistor M18, PMOS transistor M19, and NMOS transistor M20. The gate of PMOS transistor M18 is connected to the word line control line S1 of the level-timing controller, and the drain is connected to one of the storage nodes Q of the data latch unit. The gate of PMOS transistor M19 is connected to the other storage node Qb of the data latch unit, and the drain is connected to the power supply VDD. The gate of NMOS transistor M20 is connected to the storage node Qb, and the source is connected to the ground wire VSS. The sources of PMOS transistor M18, the sources of PMOS transistor M19, and the drain of NMOS transistor M20 are connected to the other end of the magnetic tunnel junction device MTJ at node N.
[0034] Compared with the latch without non-volatile memory cells, the MTJ memory cell of Embodiment 1 provides the function of restoring data after power-off for the pulse latch, and can improve the writing success rate of the magnetic tunnel junction device MTJ in the latch under harsh timing conditions.
[0035] It should be noted that the magnetic tunnel junction device MTJ has the following characteristics:
[0036] (1) The magnetic tunnel junction device MTJ will present two states of high resistance and low resistance due to different directions of the passing current. That is to say, if the current direction is from the drain of the transistor M18 to the control line CTRL, the magnetic tunnel junction device MTJ is in the low-resistance state, and the entire memory cell is also in the low-resistance state; if the current direction is from the control line CTRL to the drain of the transistor M18, the magnetic tunnel junction device MTJ is in the high-resistance state, and the entire memory cell is also in the high-resistance state.
[0037] (2) The relationship between the writing time and the current of the magnetic tunnel junction device MTJ is described by the following formula:
[0038]
[0039] where τ is the time required for the magnetization state to switch from the initial state to the stable state, is the relaxation rate, that is, the switching speed. C is a constant related to the material and the device geometry, ξ is a parameter related to the thermal fluctuation of the magnetization state, μ B is the Bohr magneton, representing the basic unit of the magnetic moment, P fixed is the spin polarization rate of the fixed layer, P free is the spin polarization rate of the free layer, e is the electron charge, m is the magnetic moment of the free layer, I C is the applied current, I C0 is the critical current, below which the magnetization switching cannot be achieved. Among them, when I C is greater than I C0 , is positive, indicating that the magnetization state can be switched, and I C is less than I C0 , is negative, indicating that the switching cannot be achieved.
[0040] As can be seen from the above formula, writing data to the magnetic tunnel junction device MTJ means that the change in the resistance state of the magnetic tunnel junction device MTJ is related to the voltage across it (i.e., the magnitude of the current flowing through the magnetic tunnel junction device MTJ). The pulse latch has a relatively high operating frequency, and the transistor causes a short write time for the magnetic tunnel junction device MTJ. The transistor M18 has a threshold voltage loss when transmitting a high level, which will reduce the current flowing through the magnetic tunnel junction device MTJ. Therefore, there is a problem of low write success rate for the magnetic tunnel junction device MTJ under strict timing conditions. The transistors M19 and M20 have the functions of pre-sensing (pre-writing) the written data and providing a full-swing potential for the connection node between the magnetic tunnel junction device MTJ and the transistor M18, thereby improving the write success rate of the magnetic tunnel junction device MTJ.
[0041] (3) If the reference data of the latch storage node Q is "0", the magnetic tunnel junction device MTJ is in a high-resistance state, and the entire storage cell is also in a high-resistance state; if the reference data of the latch storage node Q is "1", the magnetic tunnel junction device MTJ is in a low-resistance state, and the entire storage cell is also in a low-resistance state.
[0042] The pulse generation unit is a pulse generation unit for generating a pulse signal. The pulse generation unit is used to generate a pulse square wave in the pulse latch mode and self-hold the node potential when the clock signal CLK is at a high level. The pulse generation unit includes transistors M7, M8, M9, M10, and M11. The gate of transistor M7 is connected to the source of transistor M8, the drain of transistor M9, the gate of transistor M10, and the gate of transistor M11 (all of which are connected to node Y). The drain of transistor M7 is connected to the gate of transistor M8 and the gate of transistor M9. The source of transistor M7 is connected to the data update logic judgment unit. The drain of transistor M8 is connected to the power supply VDD. The source of transistor M9 is grounded. The drain of transistor M10 is connected to the clock signal CLK generated by the level-timing controller. The source of transistor M10 serves as the output terminal of the pulse signal PULSE generated by the pulse generation unit. The drain of transistor M11 is connected to the source of transistor M10, and the source is grounded.
[0043] In this way, only when node X is at a low level, transistor M8 conducts, node Y is raised to a high level, and then transistor M7 conducts, making the potentials of node X and node Z the same, and performing the node potential self-holding function. At this time, the CLK clock signal is at a high level, and transistor M6 conducts, pulling node Z down to GND.
[0044] The data latch unit is used to latch data when a pulse signal arrives. The data latch unit includes transistors M12, M13, M14, M15, M16, and M17. The gate of transistor M12 is connected to the storage node Q, the drain is connected to the power supply VDD, and the source is connected to the drain of transistor M13. The gate of transistor M13 is connected to the pulse signal PULSE generated by the pulse generation unit, and the source is connected to the storage node Qb. The gate of transistor M14 is connected to the inverted pulse signal PULSEB generated by the pulse generation unit, the drain is connected to the storage node Qb, and the source is connected to the drain of transistor M15. The gate of transistor M15 is connected to the storage node Q, and the source is grounded. The gate of transistor M16 is connected to the storage node Qb, the drain is connected to the power supply VDD, and the source is connected to the storage node Q. The gate of transistor M17 is connected to the storage node Qb, the drain is connected to the storage node Q, and the source is grounded.
[0045] The data input unit is used to transmit input data. The data input unit includes inverter INV1, inverter INV2, transistor M21, and transistor M22. The input terminal of inverter INV1 is connected to the input signal D, and the output terminal transmits the inverted signal Db of the output data. The input terminal of inverter INV2 is connected to the pulse signal PULSE, and the output terminal is connected to the inverted pulse signal PULSEB. The gate of transistor M21 is connected to the pulse signal PULSE, the source is connected to the output terminal of inverter INV1, and the drain is connected to the storage node Qb. The gate of transistor M22 is connected to the inverted pulse signal PULSEB, the source is connected to the output terminal of inverter INV1, and the drain is connected to the storage node Qb. In this way, only when the pulse signal PULSE and the inverted pulse signal PULSEB arrive, transistors M21 and M22 are turned on, and the inverted signal Db of the output data is transmitted to the latch storage node Qb.
[0046] The data update logic judgment unit is used to judge whether the stored data in the data latch unit is the same as the input data. If so, it controls the pulse generation unit not to generate a pulse signal; otherwise, it drives the pulse generation unit to generate a pulse signal. The data update logic judgment unit includes transistors M1, M2, M3, M4, M5, and M6. The gate of transistor M1 is connected to the clock signal CLK, the drain is connected to the power supply VDD, and the source is connected to the drains of transistors M7, M2, and M3, that is, connected to node X. The gate of transistor M2 is connected to the storage node Q, and the source is connected to the drain of transistor M4. The gate of transistor M3 is connected to the storage node Qb, and the source is connected to the drain of transistor M5. The gate of transistor M4 is connected to the input signal D of the input data, and the source is connected to the sources of transistors M7, M5, and M6, that is, connected to node Z. The gate of transistor M5 is connected to the inverted signal Db of the input data. The gate of transistor M6 is connected to the clock signal CLK, and the source is grounded. The signals of storage node Q and storage node Qb are opposite, and the input signal D and the inverted signal Db are opposite signals, so that transistors M2, M4 or transistors M3, M5 are turned on when Q and D are both high level / low level.
[0047] The level-timing controller is used to control the data input unit to transfer the input data to the data latch unit and the MTJ storage unit when the pulse generation unit generates a pulse signal in the pulse latch mode, and control the MTJ storage unit to write the corresponding stored data back to the data latch unit in the data recovery mode. The level-timing controller is used to control the timing and voltage of related signals (such as S1, CTRL, CLK, REVDD, etc.) to ensure the normal operation of the pulse latch mode and the data recovery mode.
[0048] Compared with the existing pulse latch, the pulse latch with pre-write and data recovery functions in this embodiment has the following beneficial effects:
[0049] 1. The pulse latch with pre-writing and data recovery functions sets the pulse latch mode and the data recovery mode when the circuit is powered off. The data update logic judgment unit determines whether the stored data in the data latch unit is the same as the input data. If they are the same, no pulse signal is generated and no data update is performed, saving the energy consumption of the pulse latch. If they are different, under the control of the level-timing controller, the input data is transmitted to the data latch unit and the MTJ storage unit, and the pulse latch mode is implemented when the circuit is powered off. The present invention utilizes the different resistance states of the magnetic tunnel junction device MTJ under different voltages and currents to implement the data recovery mode. The MTJ storage unit writes the corresponding stored data back to the data latch unit, thus realizing the functions of data pre-writing and data recovery, expanding the functions of the pulse latch, enhancing the stability, and improving the writing success rate of the magnetic tunnel junction device MTJ in the latch under harsh timing conditions, solving the technical problem of the low writing success rate of non-volatile devices in the existing pulse latch based on the dynamic OR gate under harsh timing conditions.
[0050] 2. For the pulse latch with pre-writing and data recovery functions, the number of transistors in its pulse generation unit is optimized compared with the dynamic OR gate (XOR) structure used in the existing pulse generator. The number of transistors is reduced, resulting in a large reduction in the area of the pulse generation structure, that is, a small-area pulse generation unit, thus solving the problem of the high area occupancy of the existing pulse latch based on the dynamic OR gate.
[0051] Embodiment 2
[0052] Please refer to Figure 4 、 Figure 5 and Figure 6 , this embodiment provides a pulse latch with pre-writing and data recovery functions, and the pulse latch is subjected to simulation analysis on the basis of Embodiment 1.
[0053] 1. The pulse latch mode is that after the pulse generation unit successfully generates a pulse signal, the data input unit is opened and the input data is stored in the data latch unit.
[0054] Then, the following specifically describes the situation where the input data "0" and the input data "1" are stored in the latch after the pulse signal is correctly issued in the pulse latch mode:
[0055] (1) Write to the latch, where the stored data is "0".
[0056] The timing diagram of storing data "0" in the pulse latch mode is shown in Figure 4 .
[0057] The level-timing controller generates a clock signal CLK.
[0058] Among them, in the data update logic judgment unit, when CLK is at a low level, the gate of transistor M1 is at a low level, making transistor M1 conduct. VDD pre-charges node X through transistor M1, and node X is pre-charged to a high level.
[0059] Assume that at this time Q≠D, that is, transistors M2 - M5 do not conduct, and node X maintains a high level.
[0060] The gate of transistor M9 (node X) is at a high level, making transistor M9 conduct, and node Y is pulled down to a low level.
[0061] The gate of transistor M10 (node Y) is at a low level, making transistor M10 conduct. When CLK is at a high level, the CLK signal is transmitted to the pulse generation unit through M10, generating a pulse signal PULSE.
[0062] The pulse signal PULSE is input to INV2, generating an inverted pulse signal PULSEB.
[0063] The gate of transistor M21 is at a high level, making transistor M21 conduct. The gate of transistor M22 is at a low level, making transistor M22 conduct. The input signal IN = 0 is input to INV1, making node Qb = 1;
[0064] The gate of transistor M20 is at a high level, making M20 conduct. Node N is pulled down to a low level. The CTRL signal generated by the level - timing controller is at a high level. During this process, the current direction through the MTJ memory cell is from CTRL to node N. Then the MTJ memory cell is in a high - impedance state, that is, writing "0".
[0065] The gate of transistor M17 is at a high level, making M17 conduct. Node Q is pulled down to a low level.
[0066] At this time, Q = D = 0, Qb = Db = 1. The gates of transistors M3 and M5 are at a high level, making transistors M3 and M5 conduct. Since CLK is still at a high level at this time, the gate of transistor M6 is at a high level, making transistor M6 conduct. Node X is pulled down to a low level. The gate of transistor M8 (node X) is at a low level, making M8 conduct. Node Y is raised to a high level. The gate of transistor M7 (node Y) is at a high level, making transistor M7 conduct, and the low - level state of node X can be continuously maintained, avoiding node X from being in a floating state.
[0067] The gate of transistor M11 (node Y) is at a high level, making transistor M11 conduct. Transistor M10 is turned off. Node PULSE is pulled down to a low level, PULSE = 0, and the pulse ends. The gate of transistor M21 is at a low level, making transistor M21 turn off. The gate of transistor M22 is at a high level, making transistor M22 turn off.
[0068] The gate of transistor M13 is at a low level, turning on transistor M13. The gate of transistor M12 (node Q) is at a low level, turning on transistor M12. Qb is connected to VDD, maintaining a high level, Qb = 1, Q = 0, and data is latched while the latch is powered on.
[0069] (2) Write data into the latch, where the data to be stored is "1".
[0070] For the timing diagram of storing data "1" in the pulse latch mode, see Figure 5 。
[0071] The level-timing controller generates the clock signal CLK.
[0072] Among them, in the data update logic judgment unit, when CLK is at a low level, the gate of transistor M1 is at a low level, turning on transistor M1. VDD pre-charges node X through transistor M1, and node X is pre-charged to a high level.
[0073] Assume that at this time Q≠D, that is, transistors M2 - M5 are not turned on, and node X maintains a high level.
[0074] The gate of transistor M9 (node X) is at a high level, turning on transistor M9, and node Y is pulled down to a low level.
[0075] The gate of transistor M10 (node Y) is at a low level, turning on M10. When CLK is at a high level, the CLK signal is input into the pulse generation unit through M10, generating a pulse signal PULSE.
[0076] The pulse signal PULSE is input into INV2, generating an inverted pulse signal PULSEB.
[0077] The gate of transistor M21 is at a high level, turning on transistor M21. The gate of transistor M22 is at a low level, turning on transistor M22. The input signal IN = 1 is input into INV1, making node Qb = 0;
[0078] The gate of transistor M19 is at a low level, turning on transistor M19. Node N is pulled up to a high level. The CTRL signal generated by the level-timing controller is at a low level. During this process, the current direction through the MTJ memory cell is from node N to CTRL. Then the MTJ memory cell is in a low-resistance state, that is, writing "1".
[0079] The gate of transistor M17 is at a high level, turning on transistor M17, and node Q is pulled down to a low level.
[0080] At this time, Q = D = 1, Qb = Db = 0. The gates of transistors M2 and M4 are at high level, turning on transistors M2 and M4. Since CLK is still at high level at this time, the gate of transistor M6 is at high level, turning on transistor M6. Node X is pulled down to low level. The gate of transistor M8 (node X) is at low level, turning on transistor M8. Node Y is raised to high level. The gate of transistor M7 (node Y) is at high level, turning on transistor M7, and the low-level state of node X can be continuously maintained to prevent node X from being in a floating state.
[0081] The gate of transistor M11 (node Y) is at high level, turning on transistor M11, and transistor M10 is turned off. Node PULSE is pulled down to low level, PULSE = 0, and the pulse ends. The gate of transistor M21 is at low level, turning off transistor M21, and the gate of transistor M22 is at high level, turning off transistor M22.
[0082] The gate of transistor M14 is at high level, turning on transistor M14. The gate of transistor M15 (node Q) is at high level, turning on transistor M15. Qb is connected to GND, maintaining low level, Qb = 0, Q = 1, and data is latched during the power-on of the latch.
[0083] 2. The data recovery mode is an operation to restore the data stored in the latch after the data stored in the latch is lost due to power-off of the circuit.
[0084] In the data recovery mode, the pulse generation unit does not generate a pulse signal, PULSE = 0, PULSEB = 1.
[0085] The gate of transistor M21 is at low level, turning off transistor M21, and the gate of transistor M22 is at high level, turning off M22.
[0086] The gate of transistor M13 is at low level, turning on transistor M13. The gate of transistor M14 is switched by the level-timing controller to connect to REVDD. All ports of transistors M12 - M17 that are connected to VDD in the pulse latching mode are switched by the level-timing controller to connect to REVDD.
[0087] The gate of transistor M19 is switched by the level-timing controller to connect to high level, turning off transistor M19, and the gate of transistor M20 is switched by the level-timing controller to connect to low level, turning off transistor M20.
[0088] In the data recovery mode, since the circuit is powered off, at this time, both nodes Q and Qb are at low level.
[0089] For the timing diagram of data recovery in the data recovery mode, see Figure 6 。
[0090] The timing of the REVDD, S1, and CTRL signals in the data recovery mode will be described in detail below.
[0091] In the data recovery mode, CTRL is first raised to the high level. Thereafter, S1 is adjusted to the high level, and the gate of the transistor M18 is at the high level, turning on the transistor M18. Thereafter, REVDD is adjusted to the high level, and the data unit resumes power supply. During this process, if the tunnel junction device MTJ memory cell is in the low-resistance state, a relatively large current flows into the node Q, which is quickly raised to the high level. If the tunnel junction device MTJ memory cell is in the high-resistance state, a relatively small current flows into the node Q, and the node Qb is raised to the high level faster than the node Q, and Q is at the low level.
[0092] Embodiment 3
[0093] This embodiment provides a digital circuit, which includes the pulse latch with pre-write and data recovery functions in Embodiment 1 or 2. In this embodiment, the minimum number of pulse latches is one, or there can be multiple. The digital circuit can not only include the pulse latch in Embodiment 1, but also include the pulse latches in other embodiments, and can also be in the form of combination with existing latches. When the number of pulse latches is multiple, the multiple pulse latches can be combined into a register to store multiple bits of data, or can form a static random access memory in the form of an array, or can also form a processor. The digital circuit in this embodiment is not limited to being used in circuits such as a multiplexed resetter circuit, a data distributor circuit, a debounce circuit, a clock divider circuit, a synchronous counter circuit, etc., and can also be used in newly designed circuits.
[0094] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.
Claims
1. A pulse latch with pre-writing and data recovery functions, comprising a pulse generating unit for generating a pulse signal and a data latch unit for latching data when the pulse signal arrives, characterized in that: It also includes: An MTJ storage unit, comprising a magnetic tunnel junction device MTJ, at least one NMOS tube and at least two PMOS tubes; the magnetic tunnel junction device is connected to a storage node of the data latch unit through one of the PMOS tubes; at least one NMOS tube and another of the PMOS tubes are used to sense write data in advance and provide a full swing potential to the magnetic tunnel junction device MTJ and one of the PMOS tubes; the MTJ storage unit is used to store data, and provides a pulse latch mode and a data recovery mode when the circuit is powered off through different resistance states of the magnetic tunnel junction device MTJ; and A level-timing controller is used to transfer input data to the data latch unit and the MTJ storage unit when the pulse generating unit generates the pulse signal in the pulse latch mode, and to control the MTJ storage unit to write back the corresponding storage data to the data latch unit in the data recovery mode.
2. The pulse latch with pre-write and data recovery functions as claimed in claim 1, characterized in that: The pulse latch also includes: a data input unit for transmitting input data; and The data update logic judgment unit is used to judge whether the storage data in the data latch unit is the same as the input data. If yes, the pulse generating unit is controlled not to generate the pulse signal; otherwise, the pulse generating unit is driven to generate the pulse signal.
3. The pulse latch with pre-write and data recovery functions as claimed in claim 1, characterized in that: In the MTJ storage unit, the two PMOS tubes are respectively PMOS tube M18 and PMOS tube M19, and the one NMOS tube is NMOS tube M20; one end of the magnetic tunnel junction device MTJ is connected to the control line CTRL of the level-timing controller, and the other end is connected to the source of the PMOS tube M18, PMOS tube M19 and NMOS tube M20; the gate of the PMOS tube M18 is connected to the word line control line S1 of the level-timing controller, and the drain is connected to one of the storage nodes Q of the data latch unit; the gate of the PMOS tube M19 is connected to another storage node Qb of the data latch unit, and the drain is connected to the power supply VDD; the gate of the NMOS tube M20 is connected to the storage node Qb, and the source is connected to the ground line VSS.
4. The pulse latch with pre-write and data recovery functions as claimed in claim 3, characterized in that: The data latch unit includes a transistor M12, a transistor M13, a transistor M14, a transistor M15, a transistor M16, and a transistor M17; the gate of the transistor M12 is connected to the storage node Q, the drain is connected to the power supply VDD, and the source is connected to the drain of the transistor M13; The gate of the transistor M13 is connected to the pulse signal PULSE generated by the pulse generating unit, and the source is connected to the storage node Qb; The gate of the transistor M14 is connected to the inverted pulse signal PULSEB generated by the pulse generating unit, the drain is connected to the storage node Qb, and the source is connected to the drain of the transistor M15; The gate of the transistor M15 is connected to the storage node Q, and the source is grounded; The gate of the transistor M16 is connected to the storage node Qb, the drain is connected to the power supply VDD, and the source is connected to the storage node Q; The transistor M17 has a gate connected to the storage node Qb, a drain connected to the storage node Q, and a source connected to the ground.
5. The pulse latch with pre-write and data recovery functions as claimed in claim 4, characterized in that: The pulse generating unit includes a transistor M7, a transistor M8, a transistor M9, a transistor M10, and a transistor M11; the gate of the transistor M7 is connected to the source of the transistor M8, the drain of the transistor M9, the gate of the transistor M10, and the gate of the transistor M11; the drain of the transistor M7 is connected to the gate of the transistor M8 and the gate of the transistor M9; the source of the transistor M7 is connected to the data updating logic judgment unit; The drain of the transistor M8 is connected to the power supply VDD, the source of the transistor M9 is grounded, the drain of the transistor M10 is connected to the clock signal CLK generated by the level-timing controller, and the source of the transistor M10 serves as the output end of the pulse signal PULSE generated by the pulse generating unit; The drain of the transistor M11 is connected to the source of the transistor M10 , and the source is grounded.
6. The pulse latch with pre-writing and data recovery functions as claimed in claim 5, characterized in that: The data update logic judgment unit includes a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, and a transistor M6; the gate of the transistor M1 is connected to the clock signal CLK, the drain is connected to the power supply VDD, and the source is connected to the drain of the transistor M7, the drain of the transistor M2, and the drain of the transistor M3; the gate of the transistor M2 is connected to the storage node Q, and the source is connected to the drain of the transistor M4; The gate of transistor M3 is connected to the storage node Qb, and the source is connected to the drain of transistor M5; The gate of the transistor M4 is connected to the input signal D of the input data, and the source is connected to the source of the transistor M7, the source of the transistor M5, and the drain of the transistor M6; The gate of the transistor M5 is connected to the flip signal Db of the input data; The gate of the transistor M6 is connected to the clock signal CLK, and the source is grounded.
7. The pulse latch with pre-write and data recovery functions as claimed in claim 6, characterized in that: The signals at the storage node Q and the storage node Q b are opposite, and the input signal D and the inversion signal Db are opposite signals.
8. The pulse latch with pre-writing and data recovery functions as claimed in claim 6, characterized in that: The data input unit includes an inverter INV1, an inverter INV2, a transistor M21 and a transistor M22; the input end of the inverter INV1 is connected to the input signal D, and the output end transmits the flip signal Db of the output data; the input end of the inverter INV2 is connected to the pulse signal PULSE, and the output end is connected to the inverted pulse signal PULSEB; The gate of the transistor M21 is connected to the pulse signal PULSE, the source is connected to the output end of the inverter INV1, and the drain is connected to the storage node Qb; The transistor M22 has a gate connected to the inverted pulse signal PULSEB, a source connected to the output end of the inverter INV1, and a drain connected to the storage node Qb.
9. The pulse latch with pre-writing and data recovery functions as claimed in claim 5, characterized in that: The pulse generating unit is used for generating a pulse square wave in a pulse latching mode and self-maintaining a node potential when a clock signal CLK is at a high level.
10. A digital circuit, characterized in that: It comprises a pulse latch with pre-writing and data recovery functions as claimed in any one of claims 1 to 9.