Automatic VGA image content acquisition device and method based on FPGA

Abstract

The invention discloses an FPGA-based VGA image content automatic acquisition device and method. The device comprises a VGA signal receiving circuit, an FPGA core circuit, a network module circuit and a power supply circuit, the VGA signal receiving circuit is responsible for receiving a VGA signal of external equipment and then transmitting the processed signal to the FPGA core circuit; the FPGA core circuit and the clock circuit provide high-precision clock signals through an external crystal oscillator and provide stable work clock signals for the FPGA; the downloading circuit loads the configuration data into the FPGA chip, so that the FPGA chip can work according to design requirements; the network module circuit communicates with an upper computer; the power supply circuit has a voltage value suitable for working of each chip; the scheme of FPGA parallel pipeline processing is adopted, that is, the VGA image is controlled to be read, the image content is extracted and sent to the upper computer at the same time, the problems of high cost, poor compatibility, low acquisition speed, low automation degree and the like in the prior art are solved, and rapid, accurate and automatic acquisition of the VGA image content is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of image acquisition, and in particular to a VGA image content automatic acquisition device and method based on FPGA. Background Art

[0002] In electromagnetic confrontation training, the confrontation results between the red and blue sides need to collect data such as the working conditions and disturbed states of the electronic confrontation equipment of both sides. Currently, newly equipped equipment generally has a network interface, and they can transmit equipment data through a unified network protocol. However, old equipment, especially those without an export function, cannot automatically transmit equipment data. As Figure 1 shown, in previous confrontation training, there are usually three ways to record these equipment data. One is to record manually on-site; the second is to record the screen through screen recording software and manually enter the data by playing it back afterwards; the third is to record the screen data by shooting with a camera.

[0003] The method of manually recording data has many data omissions and even often makes mistakes. The methods of screen recording and shooting and playback have a long cycle and insufficient real-time performance. These recording methods are not convenient for subsequent automated processing.

[0004] In the existing image recognition technology based on cameras, at the technical level, its image recognition algorithm is constantly refined. Relying on cutting-edge technologies such as deep learning and machine learning, it can quickly and accurately classify, detect, and recognize the collected images, and is widely used in many fields such as face recognition in security monitoring, license plate recognition in intelligent transportation, and defect detection in industrial production, providing key support for the intelligent transformation of various industries. However, this technology also faces some problems. One is that it cannot recognize each frame of the image displayed on the screen, resulting in insufficient real-time performance of recognition. The other is that the image quality is greatly affected by factors such as light and vibration in a complex environment, with extremely high requirements for the robustness of the algorithm. And as the recognition accuracy improves, the demand for computing resources increases sharply, and the hardware cost also rises accordingly. Summary of the Invention

[0005] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a VGA image content automatic acquisition device and method based on FPGA. By adopting a parallel pipelining processing scheme of FPGA, that is, while controlling the reading of VGA images, extracting image content, and sending it to the host computer, the problems existing in the prior art such as high cost, poor compatibility, slow acquisition speed, and low automation degree are solved, and the fast, accurate, and automatic acquisition of VGA image content is realized.

[0006] To achieve the above object, the present invention adopts the following technical solutions: A VGA image content automatic acquisition device based on FPGA, comprising a VGA signal receiving circuit, an FPGA core circuit, a network module circuit, and a power supply circuit; wherein the VGA signal receiving circuit is responsible for receiving the VGA signal of an external device, and performing preliminary conditioning on the signal, including filtering and amplifying operations, to ensure the stability and quality of the signal, and then performing analog-to-digital conversion on the processed signal, extracting the horizontal synchronization signal and vertical synchronization signal therein, and transmitting them to the FPGA core circuit;

[0007] The FPGA core circuit, the clock circuit relies on an external crystal oscillator to provide a high-precision clock signal to provide a stable working clock signal for the FPGA; the download circuit loads the configuration data into the FPGA chip so that it can work according to the design requirements;

[0008] The network module circuit communicates with the host computer, and is responsible for on the one hand processing the analog signal received from the network line, including signal amplification, filtering, and A / D conversion, and on the other hand responsible for encoding and decoding network data packets, modulating and demodulating signals, to ensure the effective transmission of data on the physical medium;

[0009] The power supply circuit adopts AMS1117-3.3 / 2.5 / 1.2 voltage-regulating components, and through a step-down and voltage-regulating circuit, converts the externally input power supply into voltage values suitable for the operation of each chip.

[0010] A method for acquiring a VGA image content automatic acquisition device based on FPGA, in the FPGA development environment, use the Verilog hardware description language to write the key codes of the image acquisition control module, the image content recognition module, and the UDP communication protocol module;

[0011] The image acquisition control module strictly follows the timing of the horizontal synchronization, vertical synchronization signals and pixel clock of the VGA signal, cooperates with the metastable beat circuit, and through the caching of two-level FIFOs, realizes the stable acquisition of 24-bit RGB pixel data, and at the same time the subsequent processing clock is switched from the image pixel clock to the internal working clock of the FPGA; the front-stage FIFO can be optimized for different image resolutions to ensure the best resource utilization of the system;

[0012] The image content recognition module adopts an algorithm based on a convolutional neural network. First, according to the vertical synchronization signal, horizontal synchronization signal counting, and pixel clock signal, find the area range of the content to be extracted, perform binarization processing on the pixel data within the area range, and send it to the recognition network for convolutional calculation in a pipeline form to recognize the corresponding numbers; utilize the parallel processing ability of the FPGA to perform recognition operations on multiple image areas simultaneously, greatly improving the recognition speed, and finally judge the final result through data caching and output it to the UDP communication protocol module;

[0013] The UDP communication protocol module designs a data encapsulation and parsing module to build a protocol stack. It encapsulates the recognition result into a 1500-byte frame with CRC32 checksum according to the UDP protocol standard format and sends it to the host computer through the network interface. At the same time, it accurately unpacks the data at the receiving end to ensure the accuracy and efficiency of data transmission.

[0014] The beneficial effects of the present invention are as follows: Adopting the FPGA parallel pipelining processing scheme, that is, while controlling the reading of the VGA image, extracting the image content and sending it to the host computer, it solves the problems existing in the prior art such as high cost, poor compatibility, slow acquisition speed and low automation degree, and realizes the fast, accurate and automatic acquisition of VGA image content; Compared with the traditional dedicated image acquisition card, this device is based on FPGA, which reduces the hardware cost, and the reprogrammable characteristic of FPGA is convenient for subsequent function upgrade, further saving costs; It can adapt to VGA signal sources with different resolutions and refresh rates, widely compatible with various devices with VGA interfaces, and after combining with the camera image recognition technology, different camera models can be accessed through software adaptation to expand the application boundary; Through the preprocessing of the signal receiving module and the precise timing control of FPGA, it ensures that the collected image data quality is stable and reliable, the image quality is not affected by the ambient light, and the recognition accuracy is improved; The host computer can remotely configure the acquisition parameters through the network to achieve automatic acquisition, with simple operation, reducing manual intervention. The image recognition function is integrated at the host computer end to realize the automated process from acquisition to preliminary analysis, improving work efficiency; The parts not detailed in the present invention are common existing technologies. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The present invention will be further described below with reference to the drawings:

[0016] Figure 1 The flowchart of the previous training data processing;

[0017] Figure 2 It is the overall framework diagram;

[0018] Figure 3 The VGA signal receiving circuit diagram;

[0019] Figure 4 The FPGA download circuit and clock circuit diagram;

[0020] Figure 5 The power supply circuit diagram;

[0021] Figure 6 The network module circuit diagram;

[0022] Figure 7 The PCB layout design diagram;

[0023] Figure 8 The VGA image timing

[0024] Figure 9 Image acquisition control module interface diagram;

[0025] Figure 10 Convolutional neural network algorithm structure diagram;

[0026] Figure 11 Image recognition module interface diagram;

[0027] Figure 12 UDP communication protocol module transmission state machine diagram;

[0028] Figure 13 UDP communication protocol module reception state machine diagram;

[0029] Figure 14 UDP communication protocol module interface diagram. Detailed implementation manners

[0030] The present invention will be further described in detail below in conjunction with embodiments and specific implementation manners:

[0031] As Figure 2 shown, a VGA image content automatic acquisition device based on FPGA includes a VGA signal receiving circuit, an FPGA core circuit, a network module circuit, and a power supply circuit; as Figure 3 shown, the VGA signal receiving circuit is responsible for receiving the VGA signal from an external device, performing preliminary conditioning on the signal, including filtering and amplification operations, to ensure the stability and quality of the signal, and then performing analog-to-digital conversion on the processed signal, extracting the horizontal synchronization signal and vertical synchronization signal therein, and transmitting them to the FPGA core circuit;

[0032] As Figure 4 shown, for the FPGA core circuit, the clock circuit relies on an external crystal oscillator to provide a high-precision clock signal to provide a stable working clock signal for the FPGA; the download circuit loads the configuration data into the FPGA chip so that it can work according to the design requirements, and consists of a JTAG interface and a configuration chip;

[0033] As Figure 6 shown, the network module circuit communicates with the host computer. On the one hand, it processes the analog signal received from the network line through the signal conditioning part, including signal amplification, filtering, and A / D conversion, to remove the noise and interference in the signal. On the other hand, the encoding / decoding module and the modulation / demodulation module are responsible for encoding, decoding, modulating, and demodulating network data packets to ensure the effective transmission of data on the physical medium;

[0034] As Figure 5As shown in the figure, the power supply circuit uses AMS1117 - 3.3 / 2.5 / 1.2 voltage - regulating components. Through the step - down and voltage - regulating circuits, the externally input power supply is converted into voltage values suitable for the operation of each chip.

[0035] As Figure 7 shown, the PCB layout design diagram shows the layout of the entire device on the printed circuit board. During the layout process, signal integrity, power integrity, and heat dissipation factors are fully considered; the functional modules of the VGA signal receiving circuit, FPGA core circuit, network module circuit, and power supply circuit are reasonably partitioned to reduce interference between signals. The high - frequency signal lines are routed in a short and straight manner and are well shielded to prevent signal radiation and crosstalk. The power layer and ground layer are reasonably layered and segmented, and good power connection and grounding are achieved by increasing vias, widening line widths, etc., to reduce power noise. At the same time, sufficient heat dissipation space is reserved near the chips with large heat generation, such as the FPGA chip, and the positions for heat dissipation holes or heat sinks are designed to ensure the stability of the device during long - term operation.

[0036] According to the above - mentioned module design and circuit board diagram design, a certain series of chips from Xilinx and Intel companies are selected. Based on their pin functions and electrical characteristics, peripheral circuits are designed, including download circuits, clock circuits, etc., to ensure the normal operation of the FPGA. Appropriate VGA analog - to - digital conversion chips, network interface chips, and voltage - regulating chips are selected, and peripheral circuits are designed to ensure the normal function of each part of the circuit. A physical hardware circuit board is made, and the peripheral circuits of each device are debugged, including the power supply circuit, clock circuit, etc., to ensure the normal operation of each part of the circuit board.

[0037] Embodiment 2

[0038] In the system initialization stage, reset and initialization operations are performed on each register, buffer, and related hardware module inside the FPGA to ensure that the system is in a stable initial state. In the FPGA development environment, key codes such as the image acquisition control module, image content recognition module, and UDP communication protocol are written using the Verilog hardware description language. Through rigorous timing analysis and code optimization, the correct implementation of each module's function and the efficient operation of the overall system are ensured.

[0039] The image acquisition control module, according to the synchronization signal (HSYNC) and data clock signal of the VGA signal, the VGA image timing is as Figure 8 shown.

[0040] Under precise timing control, data is sampled at the rising edge of the data clock and stored in the internal buffer FIFO. The signal interface diagram of the image acquisition control module is as Figure 9 shown.

[0041] The introduction of each signal of the image acquisition control module is shown in Table 1

[0042] Table 1 Introduction of each signal of the image acquisition control module

[0043]

[0044]

[0045] The image content recognition module reads the image data from the FIFO. In this module, an algorithm based on a convolutional neural network is used to analyze and recognize the image content. The structure of the algorithm is as Figure 10 shown. The field synchronization signal of the VGA image generates a convolution calculation start signal. After the VGA image data is binarized, it is multiplied by the pre-trained weight data, and then added under the control of the control logic to obtain the convolution. Finally, the final result is judged through the data cache and output to the UDP protocol generation module. During the recognition process, the parallel processing ability of the FPGA is utilized to process multiple image regions or features simultaneously to improve the recognition speed. When configuring the upper computer, the recognition mode can be modified by modifying the states of the weight counter and the controller; the signal interface of the image recognition module is as Figure 11 shown; the introduction of each signal of the image recognition module interface is shown in Table 2 below

[0046] Table 2 Introduction of each signal of the image recognition module

[0047]

[0048]

[0049] Finally, the UDP communication protocol module packs the recognition result and sends it to the upper computer through the network interface. The UDP communication protocol sending module is implemented using a state machine and a counter as the main architecture. The state transition diagram corresponding to the state machine is as Figure 12 shown. The implementation of this module is relatively simple. Among them, the preamble, Ethernet frame header, IP header, and UDP header data are stored in the RAM and have been configured during initialization. It is not necessary to calculate the UDP checksum, only the IP header checksum needs to be calculated. Finally, pay attention to filling the UDP data to be sent and calculate the CRC checksum

[0050] The UDP communication protocol receiving module is also implemented using a state machine and a counter as the main architecture. The state transition diagram corresponding to the state machine is as Figure 13 shown; the implementation method of this module is mainly to match and detect the preamble, Ethernet frame header, IP header, and UDP header data in sequence. After all are matched and the CRC check is correct, the UDP data is output to configure the image content recognition module; the signals of the UDP communication protocol module are as Figure 14As shown in the figure, the introduction of each signal of the UDP communication protocol module is shown in Table 3.

[0051] Table 3 Introduction of Each Signal of the UDP Communication Protocol Module

[0052]

[0053]

[0054] The host computer can realize the communication connection, parameter configuration, and the reception and processing functions of image data with the acquisition device by using a network debugging assistant or developing corresponding control software in programming languages such as C++ and Python.

[0055] In practical applications, first connect this acquisition device to a device with a VGA interface. After turning on the power, the device will be automatically initialized. The host computer starts the control software, configures the acquisition parameters according to the requirements, and then the acquisition device starts to work, collecting the VGA image content in real time and transmitting it to the host computer for subsequent processing.

[0056] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A VGA image content automatic acquisition device based on FPGA, characterized in that: It includes a VGA signal receiving circuit, an FPGA core circuit, a network module circuit and a power supply circuit; the VGA signal receiving circuit is responsible for receiving the VGA signal from the external device, performing preliminary signal conditioning, including filtering and amplification operations, to ensure the stability and quality of the signal, and then performing analog-to-digital conversion on the processed signal, extracting the horizontal synchronization signal and the field synchronization signal therein, and transmitting them to the FPGA core circuit; FPGA core circuit, the clock circuit relies on an external crystal oscillator to provide a high-precision clock signal, providing a stable working clock signal for the FPGA; the download circuit loads the configuration data into the FPGA chip so that it can work according to the design requirements; The network module circuit communicates with the host computer and is responsible for processing the analog signals received from the network line, including signal amplification, filtering, and A / D conversion. On the other hand, it is responsible for the encoding, decoding, modulation and demodulation of network data packets to ensure the effective transmission of data on the physical medium. The power supply circuit uses the AMS1117-3.3 / 2.5 / 1.2 voltage regulator element, which converts the external input power into a voltage value suitable for the operation of each chip through a step-down and voltage-stabilizing circuit.

2. A collection method of the FPGA-based VGA image content automatic collection device as claimed in claim 1, characterized in that: In the FPGA development environment, use Verilog hardware description language to write the key codes of image acquisition control module, image content recognition module and UDP communication protocol module; The image acquisition control module strictly follows the timing of the VGA signal's line synchronization, field synchronization signal and pixel clock, cooperates with the metastable beat circuit, and realizes the stable acquisition of 24-bit RGB pixel data through the two-level FIFO cache. At the same time, the subsequent processing clock is switched from the image pixel clock to the FPGA internal working clock. The front-stage FIFO can optimize the design size for different image resolutions to ensure the best resource utilization of the system; The image content recognition module uses an algorithm based on a convolutional neural network. First, according to the field synchronization signal, the line synchronization signal count and the pixel clock signal, the area range of the content to be extracted is found, the pixel data in the area is binarized, and the data is sent to the recognition network in the form of a pipeline for convolution calculation to identify the corresponding numbers. The parallel processing capability of the FPGA is used to perform recognition operations on multiple image areas at the same time, which greatly improves the recognition speed. Finally, the final result is judged through the data cache and output to the UDP communication protocol module. UDP communication protocol module, designs data encapsulation and parsing modules to build a protocol stack, encapsulates the recognition results into 1500-byte frames with CRC32 check according to the standard format of the UDP protocol, and sends them to the host computer through the network interface. At the same time, it is accurately unpacked at the receiving end to ensure the accuracy and efficiency of data transmission.

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