Printed circuit board

Abstract

The present disclosure provides a printed circuit board including: an interconnection portion including one or more insulating layers, one or more interconnection layers, and one or more via layers, and having a cavity penetrating at least a portion of the one or more insulating layers; an electronic component disposed in the cavity; a first insulating material filling at least a portion of the cavity and filling at least a portion of the electronic component; a second insulating material disposed on the first insulating material; and a micro via penetrating at least a portion of the second insulating material and connected to the electronic component. The width of the micro via hole is smaller than the width of at least one via hole in the one or more via hole layers.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2023-0188535, filed with the Korean Intellectual Property Office on December 21, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a printed circuit board. Background Art

[0003] Recently, due to the latest developments in technologies such as artificial intelligence (AI) technology, multi-chip packages including memory chips (such as high bandwidth memory (HBM)) and processor chips (such as central processing unit (CPU), graphics processing unit (GPU), application specific integrated circuit (ASIC), and field programmable gate array (FPGA)) have been used to process exponentially growing data. In particular, the number of CPU cores and GPU cores in server products has increased rapidly, and it has become necessary to respond to a finer chip metal column pitch. In particular, research has been conducted to more finely form pads of a substrate to connect a chip to the substrate and increase its yield while improving the connection reliability between the chip and the substrate. Summary of the Invention

[0004] One aspect of the present disclosure is to provide a printed circuit board capable of implementing metal columns having a fine pitch for mounting electronic components, semiconductor chips, etc. in a printed circuit board.

[0005] Another aspect of the present disclosure is to provide a printed circuit board having improved warpage resistance reliability.

[0006] According to one aspect of the present disclosure, a printed circuit board includes: an interconnecting portion including one or more insulating layers, one or more interconnecting layers, and one or more via layers, and having a cavity penetrating at least a part of the one or more insulating layers; an electronic component disposed in the cavity; a first insulating material filling at least a part of the cavity and burying at least a part of the electronic component; a second insulating material disposed on the first insulating material; and micro-vias penetrating at least a part of the second insulating material and connected to the electronic component. The width of the micro-vias is smaller than the width of at least one via in the one or more via layers.

[0007] According to another aspect of the present disclosure, a printed circuit board includes: an interconnecting portion including one or more insulating layers and one or more interconnecting layers and having a cavity penetrating at least a part of the one or more insulating layers; a first insulating material filling at least a part of the cavity; and a second insulating material disposed on the first insulating material and including a reinforcing material, wherein the topmost interconnecting layer of the one or more interconnecting layers includes a first pad, and an upper surface of the first pad is located within the second insulating material. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which: Figure 1 is a block diagram schematically showing an example of an electronic device system; Figure 2 is a perspective view schematically showing an example of an electronic device; Figure 3 is a cross-sectional view schematically showing a printed circuit board according to an example; Figure 4 is Figure 3 an enlarged view of part A of Figures 5 to 12 is a cross-sectional view schematically showing parts involved in a method for manufacturing a printed circuit board according to an example. DETAILED DESCRIPTION

[0009] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the drawings, the shapes and sizes of components may be exaggerated or reduced for clearer description.

[0010] Electronic device Figure 1 is a block diagram schematically showing an example of an electronic device system.

[0011] Referring to Figure 1 , the electronic device 1000 houses a main board 1010. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the main board 1010. These components are also combined with other electronic components described below through various signal lines 1090.

[0012] The chip-related components 1020 include: memory chips such as volatile memories (e.g., DRAM) and non-volatile memories (e.g., ROM and flash memory); application processor chips such as central processors (e.g., CPU), graphics processors (e.g., GPU), digital signal processors, cryptographic processors, microprocessors, and microcontrollers; logic chips such as analog-to-digital converters (ADC) and application-specific integrated circuits (ASIC), but the present disclosure is not limited thereto, and may also include other types of chip-related components. Additionally, these chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips and / or electronic components.

[0013] The network-related components 1030 may include components that are compatible with or operate according to protocols such as: Wi-Fi (IEEE 802.11 series, etc.), WiMAX (IEEE 802.16 series, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed Packet Access Plus (HSPA+), High Speed Downlink Packet Access Plus (HSDPA+), High Speed Uplink Packet Access Plus (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Enhanced Digital Cordless Telecommunications (DECT), Bluetooth, Wireless Local Area Network (Wireless LAN), Third Generation Mobile Communication Technology (3G) protocol, Fourth Generation Mobile Communication Technology (4G) protocol, and Fifth Generation Mobile Communication Technology (5G) protocol, as well as any other wireless standard or protocol specified hereafter and wired standards or protocols, but the network-related components 1030 are not limited thereto, and may include components that are compatible with or operate according to any other wireless standard or protocol and wired standard or protocol. In addition, the network-related components 1030 and the chip-related components 1020 may be combined with each other.

[0014] The other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low-temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, the other components 1040 are not limited thereto, and may include passive components in the form of chip components for various other purposes. Additionally, the other components 1040 may be combined with the chip-related components 1020 and / or the network-related components 1030.

[0015] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected to the main board 1010 or are not physically and / or electrically connected to the main board 1010. These other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, and a battery 1080. However, the other electronic components are not limited thereto, and may include an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (such as a hard disk drive), a compact disc (CD) drive, a digital versatile disc (DVD) drive, etc. Additionally, depending on the type of the electronic device 1000, the electronic device 1000 may further include other electronic components for various purposes.

[0016] The electronic device 1000 may include a smart phone, a personal digital assistant (PDA), a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet computer, a laptop computer, a netbook, a television, a video game console, a smart watch, an automotive component, etc. However, the electronic device 1000 is not limited thereto, and may be any other electronic device capable of processing data in addition to the above-described electronic devices.

[0017] Figure 2 is a perspective view schematically showing an example of an electronic device.

[0018] Referring to Figure 2 FIG., the electronic device may be, for example, a smart phone 1100. A main board 1110 is accommodated in the smart phone 1100, and various components 1120 are physically and / or electrically connected to the main board 1110. Additionally, other components (such as a camera module 1130 and / or a speaker 1140) that are physically and / or electrically connected to the main board 1110 or are not physically and / or electrically connected to the main board 1110 are accommodated in the smart phone 1100. Some of the components 1120 may be the above-described chip-related components. For example, a component package 1121, but the present disclosure is not limited thereto. The component package 1121 may be in the form of a printed circuit board (PCB) on which electronic components (including active components and / or passive components) are surface-mounted. Optionally, the component package 1121 may be in the form of a PCB in which electronic components (including active components and / or passive components) are embedded. Furthermore, the electronic device need not be limited to the smart phone 1100, but may be other electronic devices as described above.

[0019] Printed circuit board Figure 3 is a cross-sectional view schematically showing a printed circuit board according to an example.

[0020] Referring to Figure 3, the printed circuit board 2000 according to the example may include an interconnect portion 100, a first insulating material 310, a second insulating material 320, and may further include an electronic component 200, a micro via 330, a solder mask layer 411, and a metal post 420.

[0021] The interconnect portion 100 may include one or more insulating layers 110, one or more interconnect layers 120 disposed on or within the one or more insulating layers respectively, and one or more via layers 130 penetrating through the one or more insulating layers to connect the one or more interconnect layers, and may have a cavity penetrating at least a portion of the one or more insulating layers.

[0022] The electronic component 200 may be disposed in the cavity. A connection pad 201 may be disposed on the upper surface of the electronic component 200.

[0023] The first insulating material 310 may fill at least a portion of the cavity and may bury at least a portion of the electronic component 200. The first insulating material 310 may be formed of a material including an insulating material but not including a fiber reinforcing material such as a glass cloth (for example, an Ajinomoto build-up film (ABF)). The ABF may be provided in the form of resin-coated copper (RCC), but the present disclosure is not limited thereto. If necessary, a photosensitive insulating material such as a photosensitive dielectric (PID) may be used.

[0024] The second insulating material 320 is disposed on the first insulating material 310 and may include a reinforcing material. Specifically, the second insulating material 320 may include a fiber reinforcing material such as a glass cloth and may be, for example, a prepreg. The stiffness of the second insulating material 320 may be greater than the stiffness of the first insulating material 310. The second insulating material 320 including a fiber reinforcing material such as a glass cloth may further enhance the stiffness of the printed circuit board 2000 and improve the warpage resistance reliability of the printed circuit board.

[0025] In the printed circuit board 2000 according to the present exemplary embodiment, the first insulating material 310 and the second insulating material 320 are disposed on the upper surface of the electronic component 200. The second insulating material 320 may be a prepreg including a fiber reinforcing material such as a glass cloth, and micro via holes may be formed by stamping using a mold before stacking the second insulating material 320. However, due to the flow of the resin during the hot pressing process of the prepreg, the size of the micro via holes may decrease. Therefore, the electronic component 200 is embedded in the first insulating material 310 before stacking the second insulating material 320, thereby minimizing the volume of the portion that must be filled with the second insulating material 320.

[0026] The topmost interconnect layer among one or more interconnect layers 120 may include a first pad 141. The first pad 141 may be disposed on the topmost insulating layer 112 among one or more insulating layers 110. The upper surface of the first pad 141 may be located inside the second insulating material 320. The side surface of the first pad 141 may be in contact with the first insulating material 310 and the second insulating material 320. The interface between the first insulating material 310 and the second insulating material 320 (e.g., the horizontal plane where the interface is located) may be located between the upper surface and the lower surface of the first pad 141. This is because, as described below, after forming the first insulating material 310, a part of the first insulating material 310 may be etched by an etching process.

[0027] The upper surface of the connection pad 201 of the electronic component 200 may be located inside the second insulating material 320. The side surface of the connection pad 201 may be in contact with the first insulating material 310 and the second insulating material 320. Similarly, the interface between the first insulating material 310 and the second insulating material 320 may be located between the upper surface and the lower surface of the connection pad 201.

[0028] When observing a cross-section using a measuring device such as a scanning electron microscope (SEM), the interface between the first insulating material 310 and the second insulating material 320 can be identified by distinguishing whether there is a reinforcing material.

[0029] The micro-vias 330 may penetrate at least a part of the second insulating material 320. The width (e.g., diameter) of the micro-vias 330 may be smaller than the width of at least one via in one or more via layers 130. Specifically, as described below Figure 4 shown, the width (e.g., diameter) d of the micro-vias 330 330 may be smaller than the width (e.g., diameter) d of at least one via in the first via layer 131 131 and / or the width (e.g., diameter) d of at least one via in the second via layer 132 132 . Additionally, the width (e.g., diameter) of the micro-vias 330 may be smaller than the width (e.g., diameter) d of the first pad 141 141 .

[0030] Figure 4 is Figure 3 an enlarged view of part A of. When the side surface of a via (e.g., various vias described in the present disclosure) tapers, the width (e.g., diameter) of one end of the via may be larger than the width (e.g., diameter) of the other end of the via. In this case, as Figure 4As shown, the width (e.g., diameter) of a relatively large end portion of the via can be measured and used as the width (e.g., diameter). For example, the width (e.g., diameter) of a relatively large end portion of at least one via in the second via layer 132 can be measured and used as the width (e.g., diameter) of at least one via in the second via layer 132. However, the present disclosure is not limited thereto, and the width (e.g., diameter) of the other end portion of the via can be measured and used as the width (e.g., diameter) according to convenience. The width (e.g., diameter) of the via can be measured multiple times, and the arithmetic mean of the values measured multiple times can be used as the width (e.g., diameter).

[0031] The micro via 330 can be spaced apart from one or more insulating layers 110. The micro via 330 can be spaced apart from the first insulating material 310. As described above, after the first insulating material 310 is formed, a part of the first insulating material 310 can be etched by an etching process.

[0032] The solder resist layer 411 can be disposed on the upper surface of the second insulating material 320.

[0033] The metal post 420 can be disposed on the micro via 330 and can penetrate at least a part of the solder resist layer 411.

[0034] One or more insulating layers 110 can include a first insulating layer 111 as a core layer and a second insulating layer 112 as a stacked insulating layer. The insulating layer 110 can include an insulating material. The insulating material can include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material formed by impregnating an inorganic filler, an organic filler, and / or glass fiber (such as glass cloth and / or glass fabric) into the thermosetting resin or the thermoplastic resin. The insulating material can be a photosensitive material and / or a non-photosensitive material. For example, the insulating material of the insulating layer 110 can be an insulating material such as ABF, but is not limited thereto. The insulating material of the insulating layer 110 can include a prepreg (PPG), resin-coated copper (RCC), photosensitive dielectric (PID), FR-4, bismaleimide triazine (BT), etc. However, the present disclosure is not limited thereto, and other materials having excellent stiffness, such as glass materials, can be used if necessary.

[0035] The cavity can penetrate at least a part of the second insulating layer 112. The cavity may not penetrate the first insulating layer 111 as the core layer. That is, the cavity according to the present exemplary embodiment can be a blind cavity.

[0036] One or more interconnect layers 120 can include a first interconnect layer 121 disposed on the first insulating layer 111 and a second interconnect layer 122 as a stacked interconnect layer disposed on or within the second insulating layer 112. Specifically, the interconnect layer disposed on or within the uppermost insulating layer among the second insulating layers 112 can be referred to as the first pad 141.

[0037] The interconnect layer 120 may include a metallic material. Copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), lead (Pb), titanium (Ti), or an alloy thereof may be used as the metallic material. The metallic material may preferably include copper (Cu), but the present disclosure is not limited thereto, and the first interconnect layer 121 and the second interconnect layer 122 may include different metallic materials. The interconnect layer 120 may perform various functions according to the design. For example, the interconnect layer 120 may include signal patterns, power patterns, ground patterns, etc., but is not limited thereto, and the interconnect layer 120 may be used as a pad for mounting electronic components and chips or may be used as a stopper 121M for forming a cavity. These patterns may each have various shapes, such as lines, planes, and pads. The interconnect layer 120 may have different pitches according to its function. When the interconnect layer 120 requires a high-density fine pitch for connection to a connection structure or a semiconductor chip, the gap between the interconnect layers 120 may be narrowed, and when the interconnect layer 120 requires performing signal connection, the gap between the interconnect layers 120 may be widened.

[0038] The interconnect layer 120 may be formed by any one of a semi-additive process (SAP), a modified semi-additive process (MSAP), a through-hole (TT) method, and a subtractive method, but the present disclosure is not limited thereto. The interconnect layer 120 may include an electroless plating layer (e.g., an electroless copper plating layer) as a seed layer and an electrolytic plating layer (e.g., an electrolytic copper plating layer) as a plating layer, but the present disclosure is not limited thereto. A sputtering layer may be formed to replace the electroless copper plating layer as the electroless plating layer. If necessary, the interconnect layer 120 may further include a copper foil.

[0039] One or more via layers 130 may penetrate one or more insulating layers 110 to connect one or more interconnect layers 120. One or more via layers 130 may include a first via layer 131 and a second via layer 132. The first via layer 131 is a via layer that penetrates the first insulating layer 111, and the second via layer 132 is a stacked via layer that penetrates at least a part of the second insulating layer 112.

[0040] The first via layer 131 may include a metal layer formed on the wall surface of a through hole penetrating the first insulating layer 111 and a plug portion filling the space between the metal layers. The metal layer may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof, and may preferably include copper (Cu), but the present disclosure is not limited thereto. The plug portion may include an insulating material (e.g., ink). The metal layer may include an electroless plating layer (e.g., electroless copper plating layer) and an electrolytic plating layer (e.g., electrolytic copper plating layer), but the present disclosure is not limited thereto. A sputtering layer may be formed to replace the electroless plating layer, or both a sputtering layer and an electroless plating layer may be formed. The first via layer 131 may perform various functions according to the design. For example, the first via layer 131 may include a ground via, a power via, a signal via, etc.

[0041] The second via layer 132 may include micro vias. The micro vias may be filling vias filling via holes or conformal vias provided along the wall surface of the via holes. The micro vias may be arranged in a stacked type and / or a staggered type. Each of the second via layers 132 may include a metal, and the metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof, and may preferably include copper (Cu), but the present disclosure is not limited thereto. The second via layer 132 may include an electroless plating layer (e.g., electroless copper plating layer) and an electrolytic plating layer (e.g., electrolytic copper plating layer), but the present disclosure is not limited thereto. A sputtering layer may be formed to replace the electroless plating layer, or both a sputtering layer and an electroless plating layer may be formed. The second via layer 132 may perform various functions according to the design of the corresponding layer. For example, the second via layer may include a ground via, a power via, a signal via, etc.

[0042] According to an example, the interconnect layer provided at the uppermost part of one or more interconnect layers 120 of a printed circuit board may include a first pad 141. The first pad 141 may be provided on or within the insulating layer provided at the uppermost part in the second insulating layer 112. As described above, the interconnect layer provided on the uppermost insulating layer in the second insulating layer 112 may be referred to as the first pad 141. In Figure 3 the first pad 141 is shown as being located on the second insulating layer 112 and protruding upward from the second insulating layer 112, but is not limited thereto. For example, the first pad 141 may also be embedded in the second insulating layer 112. The first pad 141 may be connected to at least a part of the second interconnect layer 122 through one of the second via layers 132.

[0043] The first pad 141 may include a metallic material, and the metallic material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, and may preferably include copper (Cu), but the present disclosure is not limited thereto. The first pad 141 may be disposed on the top of the printed circuit board, may be an area for mounting electronic components and chips, and may be connected to a circuit pattern to perform signal connection with other pads. However, the present disclosure is not limited thereto, and the micro via hole 330 may be formed above the first pad 141. The first pad 141 may perform various functions according to design. For example, the first pad 141 may include a ground pad, a power pad, a signal pad, etc. Here, the signal pad may include a pad for electrical connection of various signals (e.g., data signals) other than ground, power, etc. In the case where the first pad 141 requires a high-density fine pitch for mounting a semiconductor chip or the like, the gap between the first pads 141 may be narrowed, and in the case where the first pad 141 requires for mounting electronic components, the gap between the first pads 141 may be widened.

[0044] The printed circuit board according to the example may include a second pad 142 under the interconnecting portion 100. The second pad 142 may be disposed on or in the insulating layer disposed at the lowermost portion in the second insulating layer 112. In Figure 3 it, the second pad 142 is shown as being disposed on the second insulating layer 112 and protruding downward from the second insulating layer 112, but is not limited thereto, and the printed circuit board may have a coreless structure in which the second pad 142 is embedded on the lower side of the second insulating layer 112. The second pad 142 may be connected to at least a part of the second interconnecting layer 122 through one of the second via layers 132. The second pad 142 may include a metallic material, and the metallic material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, and may preferably include copper (Cu), but the present disclosure is not limited thereto.

[0045] The second pad 142 may be disposed at the bottom of the printed circuit board and may be used as a connection pad such that the lower surface of the printed circuit board may be connected to another component such as a main board. However, the present disclosure is not limited thereto, and the second pad 142 may also function as a connection to a component with a fine pitch such as a semiconductor chip, and the pitch may be designed differently according to the function. The second pad 142 may perform various functions according to design. For example, the second pad 142 may include a ground pad, a power pad, a signal pad, etc. Here, the signal pad may include a pad for electrical connection of various signals (such as data signals) other than ground and power.

[0046] The first pad 141 and the second pad 142 can be formed by any one of SAP, MSAP, TT method, and subtractive method, but are not limited thereto. For example, other methods that can be used by those skilled in the art can be used to form them.

[0047] The micro-via 330 can pass through at least a part of the second insulating material 320 and be connected to the electronic component 200. For example, it can be connected to the connection pad 201 of the electronic component 200. The micro-via 330 can extend from the connection pad 201. The micro-via 330 can be disposed on the top of the printed circuit board, which can be an area for mounting electronic components and chips, and can be connected to the circuit pattern to perform signal connection with other pads. The micro-via 330 can perform various functions according to the design. For example, the micro-via 330 can include a ground pad, a power pad, a signal pad, etc. Here, the signal pad can include a pad for electrical connection of various signals (such as data signals) other than ground and power. When the micro-via 330 requires a high-density micro-pitch for mounting a semiconductor chip or the like, the gap between the micro-vias 330 can be narrowed, and when the micro-via 330 requires for mounting an electronic component, the gap between the micro-vias 330 can be widened.

[0048] As described above, the width (e.g., diameter) of the micro-via 330 can be narrower than the width (e.g., diameter) of at least one via in one or more via layers 130. The micro-via 330 can be formed by stamping the second insulating material 320 with a mold to form a micro-channel hole before stacking the second insulating material 320, or can be formed by methods such as SAP, MSAP, TT method, or subtractive method. However, the present disclosure is not limited thereto, and the micro-via 330 can be formed by using other methods that can be used by those skilled in the art.

[0049] The printed circuit board according to the example can include a first solder resist layer 411 and a second solder resist layer 412 disposed above and below the interconnecting portion 100, respectively. The first solder resist layer 411 can be disposed on the topmost insulating layer in the second insulating layer 112, and the second solder resist layer 412 can be disposed on the lowermost insulating layer in the second insulating layer 112.

[0050] The first solder mask layer 411 and the second solder mask layer 412 may be respectively disposed on the outermost portions of the printed circuit board to protect the printed circuit board from external influences. The first solder mask layer 411 and the second solder mask layer 412 may use known solder resist, and the first solder mask layer 411 and the second solder mask layer 412 may each include an insulating resin and a filler, for example, may each include a thermosetting resin and inorganic fillers dispersed in the thermosetting resin, but may not include glass fibers. The insulating resin may be a photosensitive insulating resin, and the filler may be an inorganic filler and / or an organic filler, but the present disclosure is not limited thereto, and other polymer materials may be used as needed. When a photosensitive insulating resin is used as the solder mask layer, it may be advantageous in forming fine openings, but the present disclosure is not limited thereto, and the solder mask layer includes a non-photosensitive insulating resin, and fine openings may be formed using a UV (ultraviolet) laser.

[0051] The first solder mask layer 411 may cover at least a portion of the micro-via 330. In addition, the metal pillar 420 may penetrate a portion of the first solder mask layer 411 and may have a structure protruding from the first solder mask layer 411. The fact that the metal pillar 420 protrudes beyond the first solder mask layer 411 may mean that the upper surface of the metal pillar 420 may be located at a position higher than the upper surface of the first solder mask layer 411.

[0052] The first solder mask layer 411 may expose at least a portion of the micro-via 330 through a first opening (e.g., Figure 3 330P shown in), and the first opening may be filled with the metal pillar 420. Here, the width of the lower portion of the metal pillar 420 in the region where the metal pillar 420 and the micro-via 330 are in contact with each other may be formed to be smaller than the width of the micro-via 330. In addition, similar to the width of the second opening described below, the first opening formed in the first solder mask layer 411 may also have various widths, and the width of the metal pillar 420 may be formed to be wider than the width of the micro-via 330.

[0053] The second solder mask layer 412 may have a second opening, and at least a portion of the second pad 142 may be exposed through the second opening. The fact that at least a portion of the second pad 142 may be exposed by the second opening may mean that the second solder mask layer 412 partially covers the second pad 142, that is, the second solder mask layer 412 does not cover the second pad 142 in the region where the second opening is formed. In other words, it may mean that the second solder mask layer 412 does not cover at least a portion of the second pad 142 such that at least a portion of the second pad 142 is exposed to the outside of the printed circuit board, so as to be connectable to another component.

[0054] In addition, in Figure 3In [the figure], the second opening of the second solder mask layer 412 is shown to expose a part of the lower surface of the second pad 142. However, since the second solder mask layer 412, the second opening, and the second pad are not limited to being aligned in the form of solder mask defined (SMD), but can be aligned in the form of non-solder mask defined (NSMD), the relationship between the second pad 142 and the second solder mask layer 412 is not limited to the relationship shown in the drawing. In the case of alignment in the NSMD form, the width of the second opening of the second solder mask layer 412 can be formed wider than the width of the second pad 142, the lower surface of the second pad 142 can be exposed by the second solder mask layer 412, and the side surface of the second pad 142 can also be exposed by the second solder mask layer 412.

[0055] The printed circuit board according to the example may further include a metal post 420 disposed on at least a part of the micro via 330. The metal post 420 may be disposed on the micro via 330 and may penetrate at least a part of the first solder mask layer 411. The metal post 420 may include a metal material. Copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), lead (Pb), titanium (Ti), and / or their alloys may be used as the metal material. The metal material may preferably include copper (Cu), but the present disclosure is not limited thereto. The metal post 420 may be an area for mounting electronic components, chips, etc., and may have a protruding structure to facilitate connection when the electronic components, chips, etc. are mounted in the micro via 330. The metal post 420 may perform various functions according to the design of the micro via 330. The metal post 420 may achieve transmitting an electrical signal to the interconnect layer 120 and receiving an electrical signal from the interconnect layer 120.

[0056] In the case where the micro via 330 requires a high-density micro pitch for mounting a semiconductor chip, etc., not only the gap between the micro vias 330 can be narrowed, but also the gap between the metal posts 420 can be narrowed. Since the metal post 420 is disposed on the micro via 330, even when a micro pitch semiconductor chip is mounted, the possibility of short circuit of the connection member disposed between the semiconductor chip and the metal post 420 can be reduced, and the defect of the semiconductor chip coming off can be reduced. In addition, since the metal post 420 is disposed on the micro via 330, compared with the structure in which the connection member is directly disposed on the micro via 330, the adhesion can be ensured by the metal post 420, and thus, the reliability of the printed circuit board can be improved.

[0057] The metal post 420 can be formed by any one of SAP, MSAP, TT method, and subtractive method, but is not limited thereto. For example, it can be formed by using other methods available to those skilled in the art.

[0058] The printed circuit board according to the example may further include a surface treatment layer provided on at least a part of the metal posts 420. The surface treatment layer may include one metal among nickel (Ni), palladium (Pd), and gold (Au), and the surface treatment layer may be implemented as a plurality of metal layers. For example, the surface treatment layer may be at least a part of an electroless nickel electroless palladium immersion gold (ENEPIG) structure and may be at least a part of an electroless nickel immersion gold structure (ENIG). The surface treatment layer is not limited thereto and may include an organic solderability preservative (OSP) structure including an organic substance. The surface treatment layer may improve the adhesion and signal transmission between the metal posts 420 and the connection members. In Figure 3 the surface treatment layer is shown as including one layer, but the present disclosure is not limited thereto, and the surface treatment layer may be implemented as a plurality of metal layers as described above.

[0059] The surface treatment layer may cover at least a part of the metal posts 420. In Figure 3 the surface treatment layer is shown as covering the upper surface of the metal posts 420, but is not limited thereto, and the surface treatment layer may be provided to further cover at least a part of the exposed side surfaces of the metal posts 420.

[0060] The printed circuit board according to the example may further include an electronic component 200 and an adhesive layer 210. The electronic component 200 may be an integrated circuit (IC) in which hundreds to millions of elements are integrated in one chip. For example, the electronic component 200 may be a processor chip, such as a central processing unit (e.g., CPU), a graphics processing unit (e.g., GPU), a field programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, and specifically, the electronic component 200 may be an application processor (AP), but the present disclosure is not limited thereto, and the electronic component 200 may also be a memory, such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM, flash memory)), an analog-to-digital converter, or a logic chip (such as an application specific IC (ASIC)). The electronic component 200 may be a chip-type passive component, such as a chip inductor or a chip capacitor. Alternatively, the electronic component 200 may be a combination of an IC and a chip-type passive component, and in this case, a plurality of cavities may be formed within the printed circuit board.

[0061] The electronic component 200 may be disposed in a cavity penetrating at least a part of the second insulating layer 112 and filled with a first insulating material 310. The electronic component 200 may further include an adhesive layer 210 to be mounted in the cavity. A structure of the electronic component 200 may be formed using a structure available to those skilled in the art, and the electronic component 200 may be mounted using a mounting method available to those skilled in the art.

[0062] The connection pad 201 may be disposed on the upper surface of the electronic component 200. The electronic component 200 may be connected to the interconnect 100 through the connection pad 201, and the upper surface on which the connection pad 201 is disposed may be an active surface. However, the present disclosure is not limited thereto, and the electronic component 200 may include a double-sided connection structure and may include a three-dimensional connection structure in some cases.

[0063] The printed circuit board according to the example is not limited to Figure 3 the configuration shown in, and may further include other components, and some of the components may be omitted in some cases. That is, the printed circuit board may include more components that can be utilized by those skilled in the art.

[0064] Method for manufacturing a printed circuit board Figures 5 to 12 is a cross-sectional view schematically showing the respective parts involved in the method for manufacturing a printed circuit board according to the example.

[0065] The method for manufacturing a printed circuit board according to the example may include: an operation of preparing the interconnect 100 and mounting the electronic component 200; an operation of filling the electronic component 200 with the first insulating material 310; an operation of etching a part of the first insulating material 310; an operation of forming a second insulating material 320 having processed micro vias on the first insulating material 310; an operation of forming micro vias 330 on the second insulating material 320; an operation of forming solder resist layers 411 and 412 on the upper side and the lower side of the interconnect 100, respectively; and an operation of forming metal posts 420.

[0066] Referring to Figure 5 , the method for manufacturing a printed circuit board according to the example may include an operation of preparing the interconnect 100 and mounting the electronic component 200. The interconnect 100 may include one or more insulating layers 110, one or more interconnect layers 120 respectively disposed on or within the one or more insulating layers 110, and one or more via layers 130 penetrating the one or more insulating layers to connect the one or more interconnect layers. The operation of preparing the interconnect 100 may include an operation of forming a first interconnect layer 121 on the first insulating layer 111, may include an operation of forming a second insulating layer 112 and a second interconnect layer 122 on the first insulating layer 111, and may include an operation of forming one or more via layers 130 connecting the one or more interconnect layers. In addition, the method for manufacturing a printed circuit board according to the example may include an operation of forming a first pad 141 and a second pad 142 on the second insulating layer 112 disposed at the outermost portion. Here, the operations of forming the insulating layer 110 and the interconnect layer 120 may be performed by a known lamination process.

[0067] In addition, the method for manufacturing a printed circuit board according to the example may include an operation of forming a cavity penetrating at least a part of the second insulating layer 112 and mounting the electronic component 200 by adhering the electronic component 200 with the adhesive layer 210.

[0068] Referring to Figure 6 , the method for manufacturing a printed circuit board according to the example may include an operation of filling the electronic component 200 with the first insulating material 310. The first insulating material 310 may fill at least a part of the cavity and fill the electronic component 200. The first insulating material 310 may be formed of a material including an insulating material but not including a fiber reinforcing material such as a glass cloth (for example, Ajinomoto Build-up Film (ABF)). The ABF may be provided in the form of Resin Coated Copper (RCC), but the present disclosure is not limited thereto. If necessary, a photosensitive insulating material such as a Photo Induced Dielectric (PID) may be used.

[0069] Referring to Figure 7 , the method for manufacturing a printed circuit board according to the example may include an operation of etching a part of the first insulating material 310. The first insulating material 310 may be partially etched by an etching process. Therefore, the interface between the first insulating material 310 and the second insulating material 320 may be located between the upper surface and the lower surface of the first pad 141. Similarly, the interface between the first insulating material 310 and the second insulating material 320 may be located between the upper surface and the lower surface of the connection pad 201. As described below, due to the flow of the resin during the hot pressing process of the second insulating material 320 (prepreg), the size of the micro via hole may be reduced. To prevent this from occurring, before stacking the second insulating material 320, the electronic component 200 may be embedded in the first insulating material 310 and then etched, so as to minimize the volume of the portion that must be filled with the second insulating material 320.

[0070] Referring to Figure 8 and Figure 9 , the method for manufacturing a printed circuit board according to the example may include an operation of forming the second insulating material 320 processed with micro via holes on the first insulating material 310. Referring to Figure 8 , the micro via holes may be formed by stamping using a mold before stacking the second insulating material 320. The second insulating material 320 may be a prepreg including a fiber reinforcing material such as a glass cloth. Thereafter, as Figure 9 shown, the second insulating material 320 processed with micro via holes is stacked on the first insulating material 310.

[0071] Referring to Figure 10, The method for manufacturing a printed circuit board according to an example may include an operation of forming micro-vias 330 on a second insulating material. The micro-vias 330 may penetrate at least a part of the second insulating material 320. The width (e.g., diameter) of the micro-vias 330 may be smaller than the width (e.g., diameter) of at least one via in one or more via layers 130.

[0072] Referring to Figure 11 , The method for manufacturing a printed circuit board according to an example may include operations of forming solder resist layers 411 and 412 on the upper side and the lower side of the interconnecting portion 100, respectively. The solder resist layers 411 and 412 may be formed simultaneously, but the present disclosure is not limited thereto. The method for forming the first solder resist layer 411 and the second solder resist layer 412 is not limited and may be any known method for forming a solder resist layer.

[0073] Referring to Figure 12 , The method for manufacturing a printed circuit board according to an example may include an operation of forming metal posts 420 on the micro-vias 330. To form the metal posts 420, an opening may be formed in the first solder resist layer 411 to expose at least a part of the micro-vias 330. The method for forming the opening may be any known method for forming an opening, such as UV laser processing, etc. After forming the metal posts 420, a surface treatment layer may be formed on the upper surface of the metal posts 420.

[0074] In addition, the method for manufacturing a printed circuit board according to an example is not limited to the content referred to above Figures 5 to 12 described, and may be appropriately modified and varied as needed.

[0075] As an effect of the present disclosure, a printed circuit board capable of implementing metal posts for mounting electronic components, semiconductor chips, etc. with a fine pitch in the printed circuit board may be provided.

[0076] As another effect of the present disclosure, a printed circuit board capable of improving the warpage resistance reliability may be provided.

[0077] In the present disclosure, a cross-section may refer to a cross-sectional shape when an object is vertically cut or a cross-sectional shape when the object is viewed from the side. Additionally, "on a plane" may refer to a planar shape when an object is horizontally cut or a planar shape when the object is viewed from above or below.

[0078] In the present disclosure, based on the cross-section of the drawings, for convenience, terms such as upper side, upper portion, upper surface, etc. are used to indicate the direction toward the surface on which an electronic component may be mounted, and terms such as lower side, lower portion, lower surface, etc. are used for the opposite direction. However, this is a direction defined for convenience of description, and the scope of the claims is not specifically limited by such a description of the direction.

[0079] In the present disclosure, the term "connection" may not only refer to "direct connection", but may also include "indirect connection" by means of an adhesive layer or the like. In addition, the term "electrical connection" may include cases where elements are "physically connected" and cases where elements are "not physically connected". Further, it is understood that when an element is referred to as "first" and "second", the element is not limited thereto. They may be used only for the purpose of distinguishing the element from other elements, and may not limit the order or importance of the element. In some cases, the first element may be referred to as the second element without departing from the scope of the claims set forth herein. Similarly, the second element may also be referred to as the first element.

[0080] In the present disclosure, process errors, position deviations, errors during measurement, etc. generated during the manufacturing process may be determined. For example, being substantially coplanar may not only include being completely on the same plane, but may also include being approximately on the same plane.

[0081] In the present disclosure, the same material may not only refer to materials being completely the same, but may also refer to materials being of the same type. Thus, the compositions of the materials may be substantially the same, but their specific composition ratios may be slightly different.

[0082] The expression "exemplary embodiment or an example" used in the present disclosure does not refer to the same example, and is provided to emphasize the different unique features between each example. However, the examples provided in the above description do not exclude being associated with the features of other examples and may be implemented in combination with the features of other examples. For example, even if a matter described in a specific example is not described in a different example, unless otherwise mentioned in its description, the matter may be understood to be related to another example.

[0083] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the example embodiments. As used herein, the singular forms are also intended to include the plural forms unless the context clearly dictates otherwise.

[0084] Although the exemplary embodiments have been shown and described above, it will be readily understood by those skilled in the art that modifications and variations can be made without departing from the scope of the present disclosure defined by the appended claims.

Claims

1. A printed circuit board, comprising: an interconnection portion including one or more insulating layers, one or more interconnection layers, and one or more via layers, and having a cavity penetrating at least a portion of the one or more insulating layers; an electronic component disposed in the cavity; a first insulating material filling at least a portion of the cavity and burying at least a portion of the electronic component; A second insulating material is disposed on the first insulating material; as well as a micro via penetrating at least a portion of the second insulating material and connected to the electronic component, Wherein, the width of the micro via is smaller than the width of at least one via in the one or more via layers.

2. The printed circuit board according to claim 1, wherein: The one or more insulating layers include a first insulating layer and a second insulating layer disposed on the first insulating layer, and The one or more via layers include a first via penetrating the first insulating layer and a second via penetrating at least a portion of the second insulating layer.

3. The printed circuit board according to claim 2, wherein: The cavity penetrates at least a portion of the second insulating layer.

4. The printed circuit board according to claim 2, wherein: The width of the micro via hole is smaller than the width of the first via hole.

5. The printed circuit board according to claim 2, wherein: The width of the micro via hole is smaller than the width of the second via hole.

6. The printed circuit board according to claim 1, wherein: The micro via is spaced apart from the one or more insulating layers.

7. The printed circuit board according to claim 1, wherein: The micro via is spaced apart from the first insulating material.

8. The printed circuit board according to claim 1, further comprising: A solder resist layer is disposed on the upper surface of the second insulating material; as well as A metal column is disposed on the micro via and penetrates at least a portion of the solder resist layer.

9. The printed circuit board according to claim 1, wherein: The second insulating material includes a reinforcement material.

10. The printed circuit board according to claim 1, wherein: The first insulating material does not include fiber reinforcement material.

11. The printed circuit board according to claim 1, wherein: The second insulating material includes a material different from the first insulating material.

12. The printed circuit board according to claim 11, wherein The second insulating material has a stiffness greater than that of the first insulating material.

13. The printed circuit board according to claim 1, wherein: The electronic component includes connection pads disposed in the first insulating material and the second insulating material, and The micro via extends from the connection pad.

14. A printed circuit board, comprising: an interconnection portion including one or more insulating layers and one or more interconnection layers, and having a cavity penetrating at least a portion of the one or more insulating layers; a first insulating material filling at least a portion of the cavity; as well as a second insulating material, disposed on the first insulating material and comprising a reinforcing material, The uppermost interconnection layer among the one or more interconnection layers comprises a first pad, and an upper surface of the first pad is located inside the second insulating material.

15. The printed circuit board according to claim 14, wherein: An interface between the first insulating material and the second insulating material is located between the upper surface of the first pad and a lower surface of the first pad.

16. The printed circuit board of claim 14, further comprising: an electronic component disposed in the cavity and having connection pads disposed on an upper surface of the electronic component, Wherein, the upper surface of the connecting pad is located inside the second insulating material.

17. The printed circuit board according to claim 16, wherein: An interface between the first insulating material and the second insulating material is located between the upper surface of the connection pad and the lower surface of the connection pad.

18. The printed circuit board according to claim 14, wherein: The one or more insulating layers include a first insulating layer and a second insulating layer disposed on the first insulating layer, and The one or more interconnect layers include a first interconnect layer disposed on the first insulating layer and a second interconnect layer disposed within a second insulating layer.

19. The printed circuit board according to claim 18, wherein: The cavity penetrates at least a portion of the second insulating layer.

20. The printed circuit board of claim 14, wherein: The second insulating material has a stiffness greater than that of the first insulating material.

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