High-density interconnection differential via hole optimization method based on gradient spacing coupling optimization

Abstract

The invention discloses a high-density interconnection differential via hole optimization method based on gradient spacing coupling optimization, and the method comprises the steps: determining the center spacing value of a differential via hole at a top layer according to the layout limitation of a circuit board bonding pad; based on a preset spacing layering adjustment method and the center spacing value of the top layer, the center spacing of the differential via holes of the circuit board is adjusted layer by layer, and a gradient type conical via hole layout is formed; calculating the differential impedance, return loss and insertion loss of each layer of the circuit board through an electromagnetic field simulation tool, and performing fine adjustment on the differential via hole spacing of each layer according to the calculation result to obtain a layered spacing adjustment result; the diameter of the anti-bonding pad is optimized according to the layered spacing adjustment result, so that the parasitic capacitance influence is reduced; and manufacturing the high-density interconnection circuit board based on the layered spacing adjustment result and the optimized anti-pad diameter. Impedance matching can be realized and the high-frequency signal transmission performance can be improved by dynamically adjusting the distance between the differential holes in the inner layer of the circuit board and the holes.

Description

Technical Field

[0001] The present invention relates to the technical field of high-density interconnect technology, and in particular, to a method for optimizing differential vias in high-density interconnect based on gradient spacing coupling optimization. Background Art

[0002] With the development of electronic technology, high-density interconnect (HDI) is widely used in electronic products that require miniaturization, high performance, and high-frequency signal transmission. In HDI design, in order to improve the integration of circuit boards, microvias and smaller line widths and spacings are usually used to provide higher signal density and more excellent signal integrity. High-speed circuits and high-frequency signal transmission usually adopt differential signal transmission, and data is transmitted through a pair of differential signal pairs that are inverse to each other to ensure that the signal is not affected by external electromagnetic interference during transmission. The design of differential vias helps to maintain the continuity and symmetry of differential pairs between different layers. Since the impedance requirements for differential signal transmission lines are very strict, but differential vias will cause impedance discontinuity, resulting in signal reflection or distortion.

[0003] Currently, the design of differential vias usually adopts a straight-through structure with a fixed center spacing. For example, in a bare DIE BUMP packaging, due to the limited spacing of top-layer pads (such as 150 μm), the inner-layer via spacing cannot be adjusted, resulting in problems such as impedance discontinuity, signal reflection, and deterioration of insertion loss. Especially in high-speed scenarios, the imbalance of inductance (L) and capacitance (C) parameters of vias with fixed spacing will cause a decline in return loss and insertion loss performance.

[0004] Therefore, there is an urgent need for a method for optimizing differential vias in high-density interconnect based on gradient spacing coupling optimization, which can dynamically adjust differential via parameters to match impedance requirements, improve signal integrity, optimize the signal quality and transmission performance of the system, and meet the current usage requirements for high-speed signal transmission. Summary of the Invention

[0005] In view of this, the present invention provides a method for optimizing differential vias in high-density interconnect based on gradient spacing coupling optimization, so as to solve the technical problems of impedance discontinuity and poor signal integrity in the design of differential vias in high-density interconnect when the top-layer spacing is limited in the prior art.

[0006] To achieve the above technical objectives, the present invention adopts the following technical solutions:

[0007] In a first aspect, the present invention provides a method for optimizing differential vias in high-density interconnect based on gradient spacing coupling optimization, including:

[0008] Determine the center pitch value of differential vias on the top layer according to the layout restrictions of the circuit board pads;

[0009] Based on the preset pitch hierarchical adjustment method and the center pitch value of the top layer, adjust the center pitch of the differential vias on the circuit board layer by layer to form a gradient tapered via layout;

[0010] Through the electromagnetic field simulation tool, calculate the differential impedance, return loss and insertion loss of each layer of the circuit board, and fine-tune the differential via pitch of each layer according to the calculation results to obtain the hierarchical pitch adjustment result;

[0011] Optimize the anti-pad diameter according to the hierarchical pitch adjustment result to reduce the influence of parasitic capacitance;

[0012] Based on the hierarchical pitch adjustment result and the optimized anti-pad diameter, fabricate a high-density interconnect circuit board.

[0013] Further, the adjusting the center pitch of the differential vias on the circuit board layer by layer based on the preset pitch hierarchical adjustment method and the center pitch value of the top layer includes:

[0014] The positions of the center points of the differential vias on each layer are the same as those on the top layer. Expand or contract the via pitch on each layer unilaterally based on the upper layer. The pitch of each layer is adjusted according to the following formula:

[0015]

[0016] Among them, S n represents the current layer, S top represents the top layer, and ΔS i represents the basic pitch adjustment value.

[0017] Further, the adjusting the center pitch of the differential vias on the circuit board layer by layer further includes:

[0018] Use the electromagnetic field simulation tool to measure the impedance fluctuation feedback value, and dynamically adjust the basic pitch adjustment value ΔS i according to the impedance fluctuation feedback value, and make the adjacent layer pitches satisfy:

[0019] S n = S n-1 ±Δl·tanh(Z target / Z deviation ),

[0020] Among them, S n represents the current layer, S n-1 represents the upper layer of the current layer, Z deviation represents the impedance deviation of the current layer, Z target represents the target impedance value, and Δl represents the secondary pitch adjustment amount.

[0021] Further, the secondary spacing adjustment amount Δl does not exceed 1 / 5 of the via pad diameter.

[0022] Further, by using an electromagnetic field simulation tool, the differential impedance, return loss, and insertion loss of each layer of the circuit board are calculated, and according to the calculation results, the differential via spacing of each layer is finely adjusted to obtain a hierarchical spacing adjustment result, including:

[0023] Taking the impedance fluctuation range, the return loss and insertion loss in the 0-80 GHz bandwidth, and the return loss and insertion loss in the 80-112 GHz bandwidth as the optimization objectives, the differential via spacing of each layer is finely adjusted to obtain a hierarchical spacing adjustment result.

[0024] Further, optimizing the anti-pad diameter according to the hierarchical spacing adjustment result to reduce the influence of parasitic capacitance, including:

[0025] The anti-pad diameter is adjusted by the following formula:

[0026]

[0027] where D antipad represents the anti-pad diameter, S n represents the current layer, and k represents an adjustment coefficient determined according to the characteristics of the dielectric material.

[0028] Further, based on the hierarchical spacing adjustment result and the optimized anti-pad diameter, a high-density interconnect circuit board is manufactured, including:

[0029] Adopting a high-density interconnect process to manufacture differential vias including blind vias and buried vias;

[0030] Ensuring that the via pitch of each layer of differential vias conforms to the hierarchical spacing adjustment result and the optimized anti-pad diameter.

[0031] Further, determining the center pitch value of the differential vias on the top layer according to the layout restrictions of the circuit board pads, including:

[0032] According to the layout restrictions of the Bump or BGA pads, set the center pitch of the differential vias on the top layer.

[0033] In a second aspect, the present invention also provides a high-density interconnect board, manufactured by using the high-density interconnect differential via optimization method based on gradient spacing coupling as described in the above technical solution, including a six-layer circuit board, wherein:

[0034] The differential vias between L1 and L2 are blind vias with a pitch of 150 μm;

[0035] The differential vias between L2 and L3 are buried vias with a pitch of 160 μm;

[0036] The differential vias in the L3-L4 layer are buried vias with a pitch of 170 μm;

[0037] The differential vias in the L4-L5 layer are buried vias with a pitch of 180 μm;

[0038] The differential vias in the L5-L6 layer are blind vias with a pitch of 190 μm.

[0039] Thirdly, the present invention also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the optimization method of high-density interconnect differential vias based on gradient spacing coupling as described in the above technical solution is realized.

[0040] Compared with the prior art, the advantages of the optimization method of high-density interconnect differential vias based on gradient spacing coupling provided by the present invention are as follows:

[0041] (1) Improvement of impedance continuity: By increasing the via pitch layer by layer, the differential impedance fluctuation is reduced from ±6% to ±3%, and the smoothness of the impedance curve is significantly improved.

[0042] (2) Optimization of high-frequency performance: In the 80 GHz bandwidth, the return loss is optimized from -11.3781 dB to -13.5228 dB, and the insertion loss is optimized from -0.5959 dB to -0.469 dB, a reduction of 21.3%.

[0043] (3) Enhancement of compatibility: Under the condition of limited top-layer pitch, through dynamic adjustment of the inner layer, the Bump layout constraint and the signal integrity requirement are taken into account.

[0044] (4) Process feasibility: It is realized by using the standard HDI process without additional cost and is applicable to high-end electronic devices such as 5G communication and high-speed computing.

[0045] In summary, the present invention optimizes the differential vias through gradient spacing coupling, optimizes the signal transmission characteristics under the condition of limited top-layer pitch, and is realized by using the standard HDI process without additional cost, and is applicable to the usage scenarios of various high-end electronic devices such as high-speed computing. Description of the Drawings

[0046] Figure 1 It is a schematic flow chart of the optimization method of high-density interconnect differential vias based on gradient spacing coupling provided by the present invention;

[0047] Figure 2 It is a schematic structural diagram of a high-density interconnect board with a hierarchical pitch stepwise increasing via structure provided by the present invention;

[0048] Figure 3It is a schematic diagram of the structure of a traditional fixed-pitch differential via;

[0049] Figure 4 A schematic diagram of impedance comparison curves before and after adjustment of the layer spacing provided by the present invention;

[0050] Figure 5 A schematic diagram showing comparison of return loss simulation results at 80 GHz bandwidth provided by the present invention;

[0051] Figure 6 This is a schematic diagram for comparing insertion loss simulation results under 80 GHz bandwidth provided by the present invention. DETAILED DESCRIPTION

[0052] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not used to limit the scope of the present invention.

[0053] See also Figure 1 This embodiment provides a high-density interconnect differential via optimization method based on gradient spacing coupling optimization, including:

[0054] Step S101: determining the center spacing value of the differential vias on the top layer according to the layout restriction of the circuit board pads;

[0055] Step S102: Based on a preset spacing layer adjustment method and a center spacing value of the top layer, the center spacing of the circuit board differential vias is adjusted layer by layer to form a gradient tapered via layout;

[0056] Step S103: using an electromagnetic field simulation tool to calculate the differential impedance, return loss, and insertion loss of each layer of the circuit board, and fine-tuning the differential via spacing of each layer according to the calculation results to obtain a layer spacing adjustment result;

[0057] Step S104: optimizing the anti-pad diameter according to the layer spacing adjustment result to reduce the influence of parasitic capacitance;

[0058] Step S105: Based on the layer spacing adjustment result and the optimized anti-pad diameter, a high-density interconnection circuit board is manufactured.

[0059] The method of this embodiment breaks the limitation of the traditional fixed hole spacing design by optimizing parameters such as vias and via spacing, greatly improves the electrical performance and signal transmission quality of vias, and creates a new direction for high-density interconnection via design, which has extremely high scientific and application value. At the same time, the present invention is applicable to various high-density interconnection scenarios such as 2.5D / 3D packaging, bare DIE BUMP packaging, high-density PCB design and flexible circuit boards, and can realize differential signal transmission optimization in multiple application scenarios.

[0060] As a preferred embodiment, in step S101, determining the center pitch value of differential vias on the top layer according to the layout constraints of the circuit board pads includes:

[0061] Set the center pitch of differential vias on the top layer according to the layout constraints of Bump or BGA pads.

[0062] For example: If the center pitch of differential pads of Bump or BGA is 150 μm, then set the center pitch of differential vias on the top layer to a fixed value of 150 μm.

[0063] As a preferred embodiment, in step S102, layer-by-layer adjusting the center pitch of differential vias on the circuit board based on a preset pitch hierarchical adjustment method and the center pitch value on the top layer includes:

[0064] The positions of the center points of differential vias on each layer are the same as those on the top layer. Expand or contract the via pitch on each layer unilaterally based on the upper layer. The pitch of each layer is adjusted according to the following formula:

[0065]

[0066] Where S n represents the current layer, S top represents the top layer, and ΔS i represents the basic pitch adjustment value.

[0067] As a preferred embodiment, layer-by-layer adjusting the center pitch of differential vias on the circuit board further includes:

[0068] Measure the impedance fluctuation feedback value using an electromagnetic field simulation tool, and dynamically adjust the basic pitch adjustment value ΔS i so that the pitch between adjacent layers satisfies:

[0069] S n = S n-1 ±Δl·tanh(Z target / Z deviation ),

[0070] Where S n represents the current layer, S n-1 represents the upper layer of the current layer, Z deviation represents the impedance deviation of the current layer, Z target represents the target impedance value, and Δl represents the secondary pitch adjustment amount.

[0071] As a preferred embodiment, the secondary pitch adjustment amount Δl does not exceed 1 / 5 of the via pad diameter.

[0072] By the above method, the center spacing of differential vias is enlarged or reduced layer by layer from the top layer downwards to form a non-linear tapered coupling structure. By optimizing the distribution of differential impedance through this structure, signal transmission is made more stable, signal distortion and reflection are reduced, thereby improving signal integrity.

[0073] As a specific embodiment, if the center spacing of blind vias from layer L1 to layer L2 is maintained at S top = 150 μm, then the center spacing of differential buried vias from layer L2 to layer L3 is adjusted to S top ±ΔS1, with an outward or inward expansion of ΔS1 / 2 on one side. By adjusting the layer spacing synchronously, the delay offset of differential pairs is compensated. The same applies to the spacing of each subsequent layer to ensure that the phase difference is less than 5 ps.

[0074] Since there may be different signal transmission requirements and electrical characteristics between different layers, the non-linear tapered structure can reduce the electric field coupling between layers through the change in spacing, thereby reducing high-frequency noise and interference caused by parasitic inductance and capacitance, and improving the high-frequency response of the circuit.

[0075] As a preferred embodiment, in step S103, by using an electromagnetic field simulation tool, the differential impedance, return loss, and insertion loss of each layer of the circuit board are calculated, and the differential via spacing of each layer is finely adjusted according to the calculation results to obtain a layer spacing adjustment result, including:

[0076] Taking the impedance fluctuation range, return loss and insertion loss in the 0 - 80 GHz bandwidth, and return loss and insertion loss in the 80 - 112 GHz bandwidth as optimization objectives, the differential via spacing of each layer is finely adjusted to obtain a layer spacing adjustment result.

[0077] In some embodiments, the specific optimization objectives are set as:

[0078] (1) The optimization objective for impedance fluctuation is: the impedance fluctuation range is controlled within ±5% (such as 95 Ω ± 4.5 Ω);

[0079] (2) The optimization objectives for return loss and insertion loss in the 0 - 80 GHz bandwidth are: return loss ≤ 12 dB in the 0 - 80 GHz bandwidth;

[0080] (3) The optimization objectives for return loss and insertion loss in the 80 - 112 GHz bandwidth are: return loss ≤ 10 dB in the 80 - 112 GHz bandwidth.

[0081] According to the three-dimensional full-wave electromagnetic simulation results, the differential via spacing of each layer is finely adjusted to obtain an optimized layer spacing adjustment result. Specifically, through three-dimensional full-wave electromagnetic simulation, the performance of different spacing schemes is compared as follows:

[0082] When the 150μm pitch is fixed, the worst differential impedance is 88.73Ω, the return loss at 80GHz bandwidth is 11.3781dB, and the insertion loss is 0.5959dB; when it is incrementally layered to 190μm, the worst differential impedance is improved to 91.00Ω, the return loss at 80GHz bandwidth is 13.5228dB, and the insertion loss is 0.4623dB.

[0083] In addition to the pitch of the vias, the diameter of the anti-pad is also closely related to the size of the parasitic capacitance. By optimizing the diameter of the anti-pad, the parasitic capacitance associated with the pad can be effectively reduced, thereby reducing the impact on signal transmission, especially the attenuation and distortion of high-frequency signals. A smaller parasitic capacitance helps to improve signal integrity. As a preferred embodiment, in step S104, the optimizing the anti-pad diameter according to the layered pitch adjustment result to reduce the influence of the parasitic capacitance includes:

[0084] Adjust the anti-pad diameter through the following formula:

[0085]

[0086] where D antipad represents the anti-pad diameter, S n represents the current layer, and k represents the adjustment coefficient, which is determined according to the characteristics of the dielectric material.

[0087] As a preferred embodiment, in step S105, the manufacturing of a high-density interconnect circuit board based on the layered pitch adjustment result and the optimized anti-pad diameter includes:

[0088] Adopt a high-density interconnect process to fabricate differential vias including blind vias and buried vias;

[0089] Ensure that the via pitch of each layer of differential vias conforms to the layered pitch adjustment result and the optimized anti-pad diameter.

[0090] In some embodiments, when implementing the HDI process manufacturing, laser drilling and filling electroplating processes are used to ensure the position accuracy of the vias of each layer, and an optical detection device is used to verify the compliance of the pitch.

[0091] Embodiment 2

[0092] As Figure 2 shown, this embodiment provides a high-density interconnect board, which is fabricated by using the high-density interconnect differential via optimization method based on gradient pitch coupling as described in the above technical solution, and includes a six-layer circuit board, where:

[0093] The differential vias between L1-L2 layers are blind vias with a pitch of 150μm;

[0094] The differential vias between L2-L3 layers are buried vias with a pitch of 160μm;

[0095] The differential vias between L3 and L4 are buried vias with a pitch of 170 μm;

[0096] The differential vias between L4 and L5 are buried vias with a pitch of 180 μm;

[0097] The differential vias between L5 and L6 are blind vias with a pitch of 190 μm.

[0098] Compared with the high-density interconnect board structure with traditional fixed-pitch differential vias (please refer to Figure 3 ), the high-density interconnect board provided in this embodiment adopts a gradually increasing via pitch (from 150 μm to 190 μm). By gradually increasing the via pitch, the signal interference and crosstalk between different layers are effectively reduced to optimize the differential signal transmission path between layers in the circuit; the gradually increasing differential via pitch can also better match the impedance between different layers, optimize the signal propagation characteristics, avoid impedance mismatch caused by too small or too large via pitch, and enhance the signal integrity and stability; as the via pitch increases, the electromagnetic interference (EMI) problem of the circuit board is effectively controlled. In addition, adopting a gradient differential via pitch can not only optimize the electrical performance but also improve the control of the circuit board size and pad accuracy during the manufacturing process. For high-density interconnect circuit boards, such a design scheme can help ensure the high precision of the manufacturing process and reduce the errors generated during the production process.

[0099] To verify the effectiveness of the high-density interconnect board provided in this embodiment, the optimization effect is demonstrated below through the impedance comparison before and after the layer spacing adjustment, the return loss simulation result comparison under an 80 GHz bandwidth, and the insertion loss simulation result comparison diagram under an 80 GHz bandwidth.

[0100] As Figure 4 shown, Figure 4 shows the impedance comparison curves before and after the layer spacing adjustment. Figure 4 In it, the green curve represents the effect after adjustment. It can be seen from Figure 4 that before adjustment, the impedance fluctuates greatly or deviates from the target value within the frequency range; after adjustment, the impedance is smoother and closer to the design target.

[0101] Figure 5 and Figure 6 respectively show the return loss simulation result comparison diagram under an 80 GHz bandwidth and the insertion loss simulation result comparison diagram under an 80 GHz bandwidth. Figure 5 In it, the green return loss curve after the spacing adjustment remains at a low negative value within the 80 GHz bandwidth, indicating that the signal transmission performance of this transmission line within this frequency band is good and the reflection is small. Figure 6 In it, the green insertion loss curve after adjustment remains at a low insertion loss throughout the 80 GHz bandwidth, meeting the design requirements.

[0102] From the experimental comparison results, it can be seen that the high-density interconnect board provided in this embodiment can better match the impedance between different layers, effectively reduce signal interference and crosstalk between different layers, and optimize the propagation characteristics of signals.

[0103] Embodiment 3

[0104] This embodiment also provides a computer-readable storage medium. A computer program is stored in the computer-readable storage medium. When the computer program is executed by a processor, it implements the high-density interconnect differential via optimization method based on gradient spacing coupling as described in the above technical solution.

[0105] According to the computer-readable storage medium and computing device provided in the above embodiments of the present invention, reference may be made to the content specifically described for implementing a high-density interconnect differential via optimization method based on gradient spacing coupling as described above, and it has beneficial effects similar to those of a high-density interconnect differential via optimization method based on gradient spacing coupling as described above, which will not be elaborated here.

[0106] The present invention provides a high-density interconnect differential via optimization method based on gradient spacing coupling. By means of a gradient-based spacing adjustment method, it ensures that the center spacing of differential vias is gradually adjusted at different levels, optimizes the layout of the circuit board, and effectively improves the electromagnetic compatibility and signal transmission quality; by using an electromagnetic field simulation tool to calculate the differential impedance, return loss, and insertion loss of each layer of the circuit board, and fine-tuning the differential via spacing according to the simulation results, it can accurately predict and optimize the electrical performance of the circuit board at the design stage, thereby ensuring the stability of high-frequency signal transmission, reducing signal attenuation and distortion; by optimizing the diameter of the anti-pad, the influence of parasitic capacitance can be significantly reduced, which helps to improve the high-frequency characteristics of the circuit, reduce circuit noise and signal distortion; finally, based on the hierarchical spacing adjustment results and the optimized anti-pad diameter, a high-density interconnect circuit board is manufactured. The present invention significantly improves the electrical performance and reliability of high-density interconnect circuit boards, is applicable to electronic products with high-speed and high-frequency signals, and has high technical value and application prospects.

[0107] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A high-density interconnect differential via optimization method based on gradient spacing coupling optimization, characterized in that: include: Determine the center spacing of differential vias on the top layer based on the layout constraints of the PCB pads. Based on the preset spacing layer adjustment method and the center spacing value of the top layer, the center spacing of the circuit board differential vias is adjusted layer by layer to form a gradient tapered via layout; The electromagnetic field simulation tool is used to calculate the differential impedance, return loss, and insertion loss of each layer of the circuit board. The differential via spacing of each layer is fine-tuned based on the calculation results to obtain the layer spacing adjustment result. Optimize the anti-pad diameter according to the layer spacing adjustment results to reduce the impact of parasitic capacitance; Based on the layer spacing adjustment results and the optimized anti-pad diameter, a high-density interconnection circuit board is manufactured.

2. The high density interconnect differential via optimization method based on gradient spacing coupling optimization according to claim 1, characterized in that: The method of adjusting the center spacing of the differential vias of the circuit board layer by layer based on the preset spacing layer adjustment method and the center spacing value of the top layer includes: The position of the center point of the differential vias on each layer is consistent with the top layer. The spacing of the vias on each layer is expanded or contracted on one side based on the upper layer. The spacing of each layer is adjusted according to the following formula: Among them, S n Indicates the current layer, S top represents the top layer, ΔS i Indicates the basic spacing adjustment value.

3. The high density interconnect differential via optimization method based on gradient spacing coupling optimization according to claim 2, characterized in that: The step of adjusting the center spacing of the circuit board differential vias layer by layer also includes: The impedance fluctuation feedback value is measured using the electromagnetic field simulation tool, and the basic spacing adjustment value ΔS is adjusted according to the impedance fluctuation feedback value. i Dynamic adjustment is performed, and the distance between adjacent layers satisfies: S n =S n-1 ±Δl·tanh(Z target / Z deviation ), Among them, S n Indicates the current layer, S n-1 Indicates the previous layer of the current layer, Z deviation Indicates the impedance deviation of the current layer, Z target represents the target impedance value, and Δl represents the secondary spacing adjustment amount.

4. The high density interconnect differential via optimization method based on gradient spacing coupling optimization according to claim 3, characterized in that: The secondary spacing adjustment amount Δl shall not exceed 1 / 5 of the via pad diameter.

5. The high density interconnect differential via optimization method based on gradient spacing coupling optimization according to claim 1, characterized in that: The electromagnetic field simulation tool is used to calculate the differential impedance, return loss, and insertion loss of each layer of the circuit board, and the differential via spacing of each layer is fine-tuned according to the calculation results to obtain the layer spacing adjustment result, including: Taking the impedance fluctuation range, return loss and insertion loss in the bandwidth of 0-80 GHz, and return loss and insertion loss in the bandwidth of 80-112 GHz as optimization targets, the differential via spacing of each layer is fine-tuned to obtain the layer spacing adjustment result.

6. The high density interconnect differential via optimization method based on gradient spacing coupling optimization according to claim 1, characterized in that: Optimizing the anti-pad diameter according to the layer spacing adjustment result to reduce the influence of parasitic capacitance includes: The anti-pad diameter is adjusted using the following formula: Among them, D antipad Indicates the anti-pad diameter, S n Indicates the current layer, k indicates the adjustment coefficient, which is determined according to the characteristics of the dielectric material.

7. The high density interconnect differential via optimization method based on gradient spacing coupling optimization according to claim 1, characterized in that: The method of manufacturing a high-density interconnection circuit board based on the layer spacing adjustment result and the optimized anti-pad diameter includes: High-density interconnection technology is used to make differential vias including blind and buried vias; Ensure that the hole spacing of the differential vias on each layer complies with the layer spacing adjustment results and the optimized anti-pad diameter.

8. The high density interconnect differential via optimization method based on gradient spacing coupling optimization according to claim 1, characterized in that: Determining the center spacing value of the differential vias on the top layer according to the layout restriction of the circuit board pads includes: Set the center spacing of differential vias on the top layer according to the layout restrictions of the bump or BGA pad.

9. A high density interconnection board, characterized in that: The high-density interconnect differential via optimization method based on gradient spacing coupling optimization according to any one of claims 1 to 8 is used to manufacture the circuit board, comprising a six-layer circuit board, wherein: The differential vias in the L1-L2 layer are blind vias with a pitch of 150 μm; The differential vias in the L2-L3 layer are buried vias with a pitch of 160 μm; The differential vias in the L3-L4 layer are buried vias with a pitch of 170 μm; The differential vias in the L4-L5 layer are buried vias with a pitch of 180 μm; The differential vias in the L5-L6 layer are blind holes with a pitch of 190 μm.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the high-density interconnect differential via optimization method based on gradient spacing coupling optimization as described in any one of claims 1-8 is implemented.

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