Multilayer wiring board

Abstract

An overlapping pattern (20) is provided in the first conductor pattern (10) and the second conductor pattern (14). The overlapping pattern (20) includes a connection region (21) in which the first conductive line (13) and the second conductive line (17) are electrically connected. A via portion (22) is provided on the second conductive line (17) located in the connection region (21). The via portion (22) is electrically connected to the first conductive line (13) at an intersection point (P) at which the first conductive line (13) and the second conductive line (17) intersect in the connection region (21). The via portion (22) has a line width equal to or less than the line width of the second conductive line (17).

Description

Technical Field

[0001] The present disclosure relates to a multilayer wiring substrate. Background Art

[0002] Conventionally, as a multilayer wiring substrate having a via structure, for example, a multilayer wiring substrate shown in Patent Document 1 is known.

[0003] The wiring substrate of Patent Document 1 includes: a plurality of substrates stacked on top of each other in the vertical direction, a plurality of conductive patterns provided between and on the surfaces of the plurality of substrates, and a plurality of vias provided between the layers of the plurality of substrates. Each of the plurality of vias is configured to electrically connect the conductive patterns located between and on the surfaces.

[0004] Each conductive pattern is composed of a solid pad in the shape of a quadrilateral or a circle having a specified area. An allowable via offset range that is smaller than the specified area of each conductive pattern and is located within the specified area is set for each conductive pattern.

[0005] Each via is composed of a conductive paste filled in a through hole of each substrate, and each via is circular in plan view. Each via has an area smaller than the specified area of each conductive pattern. Each via overlaps with the above-described allowable via offset range such that the center of each via portion is located within the allowable via offset range in plan view.

[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 2004-241512 Summary of the Invention

[0007] -Technical Problem to be Solved by the Invention-

[0008] However, in recent years, in the field of multilayer wiring substrates, the demand for products having characteristics such as transparency and translucency has been increasing. On the premise of such a background, for example, the case of applying a substrate having transparency and translucency to the wiring substrate of Patent Document 1 is envisaged.

[0009] However, when a substrate having transparency and translucency is applied to the wiring substrate of Patent Document 1, in plan view, each of the solid conductive patterns having the specified area and each of the vias overlapping with the allowable via offset range become conspicuous. As a result, the above-described transparency and translucency are impaired. Thus, in the structure in which a substrate having transparency and translucency is applied to the wiring substrate of Patent Document 1, sufficient transparency and translucency cannot be obtained due to the above-described conductive patterns and vias.

[0010] The present disclosure has been completed to solve the above-described technical problem, and an object thereof is to ensure the transparency and translucency of a substrate in a multilayer wiring substrate having a via structure.

[0011] - Technical solution for solving technical problems -

[0012] In order to achieve the above object, an embodiment of the present disclosure is a multilayer wiring substrate, which includes: a substrate having transparency and light transmittance; and a first conductor pattern and a second conductor pattern disposed at different positions in the thickness direction of the substrate. The first conductor pattern is composed of a plurality of first conductive wires that are respectively thinned. The second conductor pattern is composed of a plurality of second conductive wires that are respectively thinned. An overlapping pattern is provided in the first conductor pattern and the second conductor pattern, and the overlapping pattern is formed such that a part of the first conductor pattern overlaps a part of the second conductor pattern in the thickness direction of the substrate. In the overlapping pattern, when viewed from above, the plurality of first conductive wires and the plurality of second conductive wires cross each other. The overlapping pattern includes at least one connection area, and the first conductive wire and the second conductive wire are electrically connected in the connection area. At least one via portion is provided on the second conductive wire located in the connection area. The via portion is configured to be electrically connected to the first conductive wire at the intersection where the first conductive wire and the second conductive wire cross in the connection area. Moreover, the via portion has a line width equal to or less than the line width of the second conductive wire.

[0013] - Effects of the invention -

[0014] According to the present disclosure, in a multilayer wiring substrate having a via structure, the transparency and light transmittance of the substrate can be ensured. Description of the drawings

[0015] Figure 1 is a perspective view showing the whole of the multilayer wiring substrate related to the embodiment of the present disclosure;

[0016] Figure 2 is a top view showing the whole of the multilayer wiring substrate related to the embodiment of the present disclosure;

[0017] Figure 3 is an enlarged view showing Figure 2 a partial enlarged top view of part III;

[0018] Figure 4 is an enlarged view showing Figure 3 a partial enlarged top view of part IV;

[0019] Figure 5 is an enlarged view showing Figure 4 a partial enlarged top view of the connection area shown and its periphery;

[0020] Figure 6 is a cross-sectional view taken along line VI-VI of Figure 5 ;

[0021] Figure 7 is an enlarged view showingFigure 6 Partial enlarged cross-sectional view of part VII;

[0022] Figure 8 is a cross-sectional view taken along Figure 5 line VIII - VIII;

[0023] Figure 9 is an enlarged partial cross-sectional view showing Figure 8 part IX;

[0024] Figure 10 is a diagram briefly showing a method of manufacturing a multilayer wiring substrate by an imprinting process;

[0025] Figure 11 is a top view briefly showing the structures of the first conductor pattern, the second conductor pattern, and the overlapping pattern in Modification 1 of the embodiment;

[0026] Figure 12 is a top view briefly showing the structures of the first conductor pattern, the second conductor pattern, and the overlapping pattern in Modification 2 of the embodiment;

[0027] Figure 13 is a top view briefly showing the structures of the first conductor pattern, the second conductor pattern, and the overlapping pattern in Modification 3 of the embodiment;

[0028] Figure 14 is a diagram showing a state in Modification 3 of the embodiment where a part of each first bridge portion in the connection region overlaps with the second conductive wire and a part of each second bridge portion in the connection region overlaps with the second conductive wire, corresponding to Figure 13 ;

[0029] Figure 15 is a diagram showing the cross-sectional structure of the connection region and its vicinity in Modification 4 of the embodiment, corresponding to Figure 6 ;

[0030] Figure 16 is a diagram showing the cross-sectional structure of the connection region and its vicinity in Modification 5 of the embodiment, corresponding to Figure 6 ;

[0031] Figure 17 is a diagram briefly showing a method of manufacturing a multilayer wiring substrate by an etching process;

[0032] Figure 18 is a diagram showing the cross-sectional structure of the connection region and its vicinity in Modification 6 of the embodiment, corresponding to Figure 6 ; Detailed Description

[0033] Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The following description of the embodiments is merely exemplary in nature and is not intended to limit the present disclosure, its application objects, or its uses.

[0034] Figure 1 And Figure 2 shows the overall structure of the multilayer wiring substrate 1 related to the embodiments of the present disclosure. In this embodiment, a multilayer wiring substrate 1 formed by an imprint process is exemplified. A plurality of mounting elements 2 are provided on the multilayer wiring substrate 1. As the mounting element 2, for example, an LED element or a diode can be cited. The plurality of mounting elements 2 are arranged on the upper side of the substrate 3 described later (the upper surface side of the first layer 5 described later).

[0035] It should be noted that, in this embodiment, for the sake of convenience of description, the Figure 2 direction from the left side to the right side of the paper surface in Figure 2 is defined as the "X direction", and on the other hand, the

[0036] (Substrate)

[0037] As shown in Figure 1 And Figure 2 the multilayer wiring substrate 1 includes a substrate 3. The substrate 3 has transparency and light transmittance. It should be noted that, in this embodiment, in the thickness direction of the substrate 3, the side where the film base material 4 described later is located is defined as the "lower side" of the substrate 3, and on the other hand, the side where the second layer 6 described later is located is defined as the "upper side" of the substrate 3.

[0038] The substrate 3 includes a film base material 4. The film base material 4 is made of a resin material having at least flexibility and light transmittance. Preferably, the film base material 4 has a light transmittance of 80% or more. The film base material 4 is, for example, 25 μm to 200 μm. In addition, the film base material 4 may also have transparency.

[0039] As the above resin material, for example, resin materials such as PET (polyethylene terephthalate), polycarbonate, COP (cycloolefin polymer), and COC (cycloolefin copolymer) can be cited.

[0040] As shown in Figure 6 the substrate 3 includes a first layer 5 and a second layer 6. The first layer 5 and the second layer 6 are each made of a resin material having insulation and light transmittance. This resin material is, for example, a thermosetting resin material or an ultraviolet curable resin material. The thickness of each of the first layer 5 and the second layer 6 is, for example, 1 μm to 6 μm.

[0041] The first layer 5 is a layer for arranging the first conductor pattern 10 described later. The first layer 5 is stacked on the upper side of the film base material 4. The upper surface of the first layer 5 is formed to be flat or slightly recessed at the central portion in a state where the conductive metal constituting each of the first conductive wires 13 described later is buried in the first recess 7 described later.

[0042] The second layer 6 is a layer for arranging the second conductor pattern 14 described later. The second layer 6 is stacked on the upper side of the first layer 5. The upper surface of the second layer 6 is formed to be flat or slightly recessed at the central portion in a state where the conductive metal constituting each of the second conductive wires 17 described later is buried in the second recess 8 described later.

[0043] As Figure 6 and Figure 10 shown, a plurality of bottomed first recesses 7 recessed downward from the upper surface of the first layer 5 are provided on the first layer 5. The plurality of first recesses 7 linearly extend on the upper surface of the first layer 5 in a manner of forming a predetermined pattern described later.

[0044] The groove depth of the first recess 7 is set to be, for example, 0.5 μm or more and 5 μm or less. The first recess 7 is configured to have a groove width dimension of 15 μm or less.

[0045] As Figures 8 - 10 shown, a plurality of second recesses 8 recessed downward from the upper surface of the second layer 6 are provided on the second layer 6. The plurality of second recesses 8 linearly extend on the upper surface of the second layer 6 in a manner of forming a predetermined pattern described later. It should be noted that the second recess 8 is configured such that only the portion where the via hole portion 22 described later is formed penetrates the second layer 6 in the thickness direction of the substrate 3.

[0046] The groove depth of the second recess 8 is set to be, for example, 0.5 μm or more and 5 μm or less. The second recess 8 is configured to have a groove width dimension of 15 μm or less.

[0047] (First Conductor Pattern)

[0048] As Figures 1 - 3 shown, the multilayer wiring substrate 1 includes a plurality of first conductor patterns 10. When viewed from above, the plurality of first conductor patterns 10 are arranged at intervals (equally spaced in the illustrated example) from each other in the X direction. Each of the first conductive wires 13 described later constituting the first conductor pattern 10 is arranged in the first layer 5 (see Figure 6 ). It should be noted that in Figures 1 - 3 , for the convenience of illustration, each of the first conductor patterns 10 is briefly shown by dot shading.

[0049] Each first conductor pattern 10 has a first main body portion 11 and a plurality (four in the illustrated example) of first branch portions 12. When viewed from above, the first main body portion 11 and each first branch portion 12 are formed in a substantially strip shape. When viewed from above, the first main body portion 11 extends in a substantially strip shape along the Y direction. Each first branch portion 12 branches from a middle portion of the first main body portion 11. Specifically, each first branch portion 12 is configured to extend from a middle portion of the first main body portion 11 in a direction opposite to the X direction (toward Figure 2 and Figure 3 the left side of the paper surface of

[0050] As Figure 4 shown, the first conductor pattern 10 is composed of a plurality of first conductive wires 13. Each first conductive wire 13 is thinned. Specifically, the line width of each first conductive wire 13 is configured to be 15 μm or less.

[0051] The plurality of first conductive wires 13 are arranged on the surface of the first layer 5 in a manner to form a predetermined pattern. In Figure 4 , as an example of the above-mentioned predetermined pattern, a grid pattern formed by arranging the plurality of first conductive wires 13 in a grid shape is shown.

[0052] The grid pattern (first conductor pattern 10) composed of the plurality of first conductive wires 13 is configured to be in a state where the plurality of first conductive wires 13 cross each other and the plurality of first conductive wires 13 are arranged at a predetermined interval (equal intervals in the illustrated example). Each first conductive wire 13 constituting the grid pattern extends in a direction inclined with respect to both the X direction and the Y direction.

[0053] As Figure 7 and Figure 9 shown, each first conductive wire 13 includes an adhesion layer 13a and a conductive layer 13b. It should be noted that in Figure 6 , Figure 8 and Figure 10 , for the convenience of illustration, the illustration of the adhesion layer 13a and the conductive layer 13b is omitted.

[0054] The adhesion layer 13a is an element for ensuring the adhesion of the conductive layer 13b to the first recess 7 (refer to Figure 6 and Figure 7 ). In addition, the adhesion layer 13a has low reflectivity. That is, the adhesion layer 13a has a function of making it difficult to visually recognize the conductive layer 13b when viewed from the side where the first layer 5 is located ( Figure 7 the lower side of the paper surface of

[0055] The adhesion layer 13a is a metal layer composed of, for example, a metal nitride, a metal oxide, or a metal oxynitride containing both a metal nitride and a metal oxide, which contains at least one metal selected from the group consisting of Ti, Al, V, W, Ta, Si, Cr, Ag, Mo, Cu, and Zn. It should be noted that the adhesion layer 31a can be a single layer or a laminate formed by laminating a plurality of layers with different compositions.

[0056] The adhesion layer 13a is formed on the side surface and the bottom surface of the first recess 7. Specifically, the adhesion layer 13a is laminated in a thin film state on the side surface and the bottom surface of the first recess 7 by, for example, evaporation or sputtering.

[0057] The conductive layer 13b is an element for ensuring the conductivity of the first conductive wire 13. The conductive layer 13b is buried in the first recess 7 in a state of being laminated on the adhesion layer 13a. The conductive layer 13b is composed of a conductive metal. For example, copper, silver, gold, or an alloy containing at least one of these metals is suitable as the conductive metal. The conductive layer 13b is formed by, for example, evaporation, sputtering, electroless plating treatment, or electroplating treatment. It should be noted that preferably, the upper surface of the conductive layer 13b is formed flush with the upper surface of the first layer 5 (refer to Figure 7 ).

[0058] (Second conductor pattern)

[0059] As Figures 1 - 3 shown, the multilayer wiring substrate 1 includes a plurality of second conductor patterns 14. When viewed from above, the plurality of second conductor patterns 14 are arranged at intervals (equally spaced in the illustrated example) in the Y direction. It should be noted that in Figures 1 - 3 , for the convenience of illustration, the second conductor pattern 14 is briefly shown by dot shading.

[0060] Each of the second conductor wires 17, which will be described later and constitute the second conductor pattern 14, is arranged on the second layer 6 (refer to Figure 6 ). That is, the second conductor pattern 14 is arranged at a different position in the thickness direction of the substrate 3 from the first conductor pattern 10.

[0061] Each of the second conductor patterns 14 has a second main body portion 15 and a plurality of (four in the illustrated example) second branch portions 16. When viewed from above, the second main body portion 15 and each of the second branch portions 16 are formed in a substantially strip shape. When viewed from above, the second main body portion 15 extends in a substantially strip shape along the X direction. Each of the second branch portions 16 branches from a middle portion of the second main body portion 15. Specifically, each of the second branch portions 16 extends from a middle portion of the second main body portion 15 toward the direction opposite to the Y direction ( Figure 2 the lower side of the paper surface in

[0062] AsFigure 4 As shown, the second conductor pattern 14 is composed of a plurality of second conductive lines 17. Each of the second conductive lines 17 is thinned. Specifically, the line width of each second conductive line 17 is configured to be 15 μm or less. It should be noted that, in Figure 4 , in order to distinguish the first conductive line 13 from the second conductive line 17, the second conductive line 17 is shown by a line thicker than the first conductive line 13.

[0063] As Figure 4 and Figure 6 shown, a plurality of second conductive lines 17 are arranged on the surface of the second layer 6 in a manner to form a specified pattern. It should be noted that, in Figure 4 , as an example of the above-mentioned specified pattern, a grid pattern formed by arranging a plurality of second conductive lines 17 in a grid shape is shown.

[0064] As Figure 4 shown, the grid pattern (second conductor pattern 14) composed of a plurality of second conductive lines 17 is configured to be in a state where a plurality of second conductive lines 17 cross each other and a plurality of second conductive lines 17 are arranged at a specified interval (equal intervals in the illustrated example). Each second conductive line 17 constituting the grid pattern extends in a direction inclined with respect to both the X direction and the Y direction. It should be noted that, in the present embodiment, the grid pattern composed of a plurality of second conductive lines 17 has the same aperture ratio as the grid pattern (first conductor pattern 10) composed of a plurality of first conductive lines 13.

[0065] Here, the ratio of the plurality of first conductive lines 13 in the first conductor pattern 10 or the ratio of the plurality of second conductive lines 17 in the second conductor pattern 14 is referred to as the "shadow ratio". Moreover, the ratio obtained by subtracting the above-mentioned shadow ratio from the total area (100%) of the first conductor pattern 10 corresponds to the aperture ratio of the first conductor pattern 10. Similarly, the ratio obtained by subtracting the above-mentioned shadow ratio from the total area (100%) of the second conductor pattern 14 corresponds to the aperture ratio of the second conductor pattern 10.

[0066] As Figure 7 and Figure 9 shown, each second conductive line 17 includes an adhesion layer 17a, a conductive layer 17b, and a blackening layer 18. It should be noted that, in Figure 6 , Figure 8 and Figure 10 , for the sake of easy illustration, the illustration of the adhesion layer 17a, the conductive layer 17b, and the blackening layer 18 is omitted.

[0067] The adhesion layer 17a is for ensuring the relative position of the conductive layer 17b with respect to the second recess 8 (refer to Figure 8 and Figure 9The element of close contact. In addition, the close contact layer 17a has low reflectivity. That is, the close contact layer 17a has the function of making the conductive layer 17b difficult to be visually recognized when observing the multilayer wiring substrate 1 from the side where the first layer 5 is located ( Figure 7 the lower side of the paper surface of).

[0068] The close contact layer 17a is, for example, a metal layer composed of a metal nitride, a metal oxide, or a metal oxynitride containing both a metal nitride and a metal oxide, which contains at least one or more metals selected from the group consisting of Ti, Al, V, W, Ta, Si, Cr, Ag, Mo, Cu, and Zn. It should be noted that the close contact layer 17a can be a single layer or a laminate formed by laminating multiple layers with different compositions.

[0069] The close contact layer 17a is formed on the side surface and the bottom surface of the second recess 8. Specifically, the close contact layer 17a is, for example, laminated in a thin film form on the side surface and the bottom surface of the second recess 8 by evaporation or sputtering. In addition, in the second recess 8, the close contact layer 17a is also formed at the position where a via portion 22 described later is formed (specifically, the position corresponding to the lower surface and the side surface of the via portion 22).

[0070] The conductive layer 17b is an element for ensuring the conductivity of the second conductive wire 17. The conductive layer 17b is buried in the second recess 8 in a state of being laminated on the close contact layer 17a. The conductive layer 17b is composed of a conductive metal. For example, copper, silver, gold, or an alloy containing at least one of these metals is suitable as the conductive metal. The conductive layer 17b is formed, for example, by evaporation, sputtering, electroless plating treatment, or electroplating treatment.

[0071] As Figure 7 and Figure 9 shown, the blackening layer 18 is laminated on the upper surface of the conductive layer 17b. In addition, the blackening layer 18 has low reflectivity. That is, the blackening layer 18 has the function of making the conductive layer 17b difficult to be visually recognized when observing the multilayer wiring substrate 1 from the side where the second layer 6 is located. The thickness of the blackening layer 18 is, for example, 7 nm to 10 nm. The blackening layer 18 is formed, for example, by evaporation, sputtering, electroplating treatment, or electroless plating treatment.

[0072] For example, in the case where the blackened layer 18 is formed by the above non-electrolytic plating treatment, the composition of the non-electrolytic plating solution used in the non-electrolytic plating treatment is not particularly limited. For example, when the metal atom of the conductive layer 17b is copper, as the atom that replaces copper (that is, the constituent atom of the blackened layer 18), an element selected from the group consisting of Pd, Hg, Ag, Ir, Pt, and Au can be cited. It should be noted that in the following description, the case where palladium (Pd) is applied as the constituent atom of the blackened layer 18 is exemplified.

[0073] In this embodiment, the blackened layer 18 is formed by replacing the grains at the boundaries (so-called "grain boundaries") between the surface-layer-side grains of the conductive metal constituting the conductive layer 17b with palladium (blackening treatment is performed). Specifically, in the blackening treatment, intergranular corrosion proceeds along the above grain boundaries, and the grains such as copper on the surface layer of the conductive metal are replaced with palladium. It should be noted that preferably, the upper surface of the blackened layer 18 (corresponding to the upper surface of each second conductive wire 17) is formed flush with the upper surface of the second layer 6 (refer to Figure 9 ).

[0074] (Overlapping pattern)

[0075] As Figure 3 and Figure 4 shown, overlapping patterns 20 are provided in the first conductor pattern 10 and the second conductor pattern 14. The overlapping pattern 20 is configured such that a part of the first conductor pattern 10 and a part of the second conductor pattern 14 overlap in the thickness direction of the substrate 3. The overlapping pattern 20 of this embodiment is configured such that a part of the first branch portion 12 and a part of the second branch portion 16 overlap in the thickness direction of the substrate 3.

[0076] In the overlapping pattern 20, the interval between the first conductive wires 13 and 13 is larger than the interval between the first conductive wires 13 and 13 other than the overlapping pattern 20 in the first conductor pattern 10. In this embodiment, the interval between the first conductive wires 13 and 13 constituting the overlapping pattern 20 is about twice the interval between the first conductive wires 13 and 13 other than the overlapping pattern 20 in the first conductor pattern 10. Similarly, the interval between the second conductive wires 17 and 17 constituting the overlapping pattern 20 is about twice the interval between the second conductive wires 17 and 17 other than the overlapping pattern 20 in the second conductor pattern 14.

[0077] In the overlapping pattern 20, when viewed from above, the plurality of first conductive wires 13 and the plurality of second conductive wires 17 cross each other. Moreover, the overlapping pattern 20 is configured such that when viewed from above, the first conductive wires 13 and the second conductive wires 17 are arranged at a predetermined interval (equidistant in the illustrated example).

[0078] The opening ratio of the overlapping pattern 20 is preferably configured such that the difference from the opening ratio of the first conductor pattern 10 (or the opening ratio of the second conductor pattern 14) in the region other than the connection region 21 described later is 30% or less. More preferably, the difference in the opening ratios of the two is 10% or less. The overlapping pattern 20 of this embodiment has an opening ratio equal to the opening ratio of the first conductor pattern 10 (or the opening ratio of the second conductor pattern 14) other than the overlapping pattern 20.

[0079] (Connection region)

[0080] As Figure 4 and Figure 5 shown, the overlapping pattern 20 includes a connection region 21. In the connection region 21, the first conductive wire 13 and the second conductive wire 17 are electrically connected. It should be noted that the overlapping pattern 20 of this embodiment includes one connection region 21.

[0081] In this embodiment, the connection region 21 has a region smaller than the region occupied by the overlapping pattern 20. A plurality of (four in the illustrated example) first conductive wires 13 and a plurality of (two in the illustrated example) second conductive wires 17 are located in the connection region 21. In the connection region 21, a plurality of first conductive wires 13 cross one second conductive wire 17 (refer to the intersection point P shown in Figure 5 ). The four intersection points P are located in the connection region 21 shown in Figure 5 .

[0082] (Via portion)

[0083] As Figures 6 - 9 shown, one via portion 22 is provided on each second conductive wire 17 located in the connection region 21. The via portion 22 is arranged in the connection region 21. The via portion 22 is made of the same material as the conductive metal of the conductive layer 17b constituting each second conductive wire 17.

[0084] The via portion 22 is formed integrally with the second conductive wire 17 (conductive layer 17b) located in the connection region 21. The via portion 22 of this embodiment protrudes from the lower part of the second conductive wire 17 (conductive layer 17b) toward the position corresponding to the upper surface of the first layer 5.

[0085] The via portion 22 is configured to have a line width equal to or less than the line width of the second conductive wire 17. The via portion 22 of this embodiment has a line width equal to the line width of the second conductive wire 17 (refer to Figure 8 ).

[0086] In this embodiment, the via portion 22 is configured such that the angle formed by the side surface of the via portion 22 and the lower surface of the second conductive wire 17 in a cross-sectional view is approximately a right angle (refer to Figure 6)。In addition, the angle formed by the side surface of the via portion 22 and the lower surface of the second conductive wire 17 is not limited to a right angle, and may also be an obtuse angle slightly larger than a right angle (specifically, the angle corresponding to the draft angle generated when forming the second recess 8 by an embossing process). It should be noted that a mode in which the angle formed by the side surface of the via portion 22 and the lower surface of the second conductive wire 17 is an obtuse angle larger than the above-mentioned draft angle will be described in a modified example 4 described later.

[0087] The via portion 22 is configured such that at the intersection point ( Figure 5 the intersection point P shown) where the first conductive wire 13 and the second conductive wire 17 intersect in the connection region 21, the via portion 22 is electrically connected to the first conductive wire 13. In this embodiment, at the intersection point P, the lower surface of the via portion 22 is connected to the upper surface of the first conductive wire 13 located in the connection region 21.

[0088] In this embodiment, the via portion 22 is electrically connected to the two first conductive wires 13, 13 at the two intersection points P, P where the two first conductive wires 13, 13 and one second conductive wire 17 intersect. The via portion 22 is configured such that the length ( Figure 6 the dimension L shown) along the extending direction of the second conductive wire 17 is a length equal to or greater than the sum of the pitch ( Figure 6 the dimension A shown) between the first conductive wires 13, 13 adjacent to each other in this extending direction and the line width ( Figure 6 the dimension W shown) of one first conductive wire 13. In this embodiment, one via portion 22 and the two first conductive wires 13, 13 adjacent to each other in the extending direction of the second conductive wire 17 overlap in the thickness direction of the substrate 3 (refer to Figure 6 ). It should be noted that the second layer 6 is interposed between the first conductive wire 13 that does not overlap with the via portion 22 and each second conductive wire 17 (refer to Figure 6 ).

[0089] (dummy pattern)

[0090] As Figure 3 and Figure 4 shown, the multilayer wiring substrate 1 includes a plurality of dummy patterns 30. In Figure 3 , each dummy pattern 30 is briefly shown by dot shading. It should be noted that in Figure 1 and Figure 2 , the illustration of each dummy pattern 30 is omitted.

[0091] In this embodiment, the plurality of dummy patterns 30 are arranged on the first layer 5. Specifically, in a plan view, the plurality of dummy patterns 30 are arranged in a region of the first layer 5 where the first conductor pattern 10 and the second conductor pattern 14 do not exist (refer to Figure 1 and Figure 2 ).

[0092] As Figure 4 shown, the pseudo-pattern 30 is composed of a plurality of pseudo-conductive lines 31. Each pseudo-conductive line 31 is thinned. Specifically, the line width of each pseudo-conductive line 31 is configured to be 15 μm or less.

[0093] Each pseudo-conductive line 31 includes a conductive metal embedded in a recess (not shown) in the first layer 5. For example, copper, silver, gold, or an alloy containing at least one of these metals is suitable as the conductive metal. In addition, the above-mentioned recess is formed on the upper surface side of the region of the first layer 5 where the first conductor pattern 10 does not exist. The above-mentioned recess has the same structure as the first recess 7. The upper surface of each pseudo-conductive line 31 may also be formed flush with the upper surface of the first layer 5, which is not shown here.

[0094] The plurality of pseudo-conductive lines 31 are formed by a grid pattern in which the plurality of pseudo-conductive lines 31 are arranged in a grid. The grid pattern formed by the plurality of pseudo-conductive lines 31 has the same structure as the grid pattern formed by the plurality of first conductive lines 13. Each pseudo-pattern 30 has an opening ratio equal to that of the first conductor pattern 10.

[0095] When viewed from above, the plurality of pseudo-conductive lines 31 and the plurality of first conductive lines 13 are arranged at intervals, where the plurality of first conductive lines 13 constitute the first conductor pattern 10 adjacent to each pseudo-pattern 30. That is, each pseudo-pattern 30 is in a state of non-electrical conduction with the first conductor pattern 10. In addition, each pseudo-pattern 30 is insulated from each second conductor pattern 14 via the second layer 6, which is not shown here.

[0096] (Method for manufacturing a multilayer wiring substrate)

[0097] Refer to Figure 10 to describe the manufacturing method of the multilayer wiring substrate 1. Specifically, in this embodiment, a method for manufacturing the multilayer wiring substrate 1 by an imprint process is described.

[0098] First, the first layer 5 is formed on the upper surface of the film substrate 4. Specifically, a resin material having insulating properties and light transmissibility (the above-mentioned thermosetting resin material or ultraviolet curable resin material) is coated on the upper surface of the film substrate 4. Then, the first recess 7 is formed on the upper surface side of the first layer 5 by an imprint process. Thus, a state is achieved in which the first layer 5 having a plurality of first recesses 7 is stacked on the upper surface of the film substrate 4 (refer to the cross-sectional view shown in (a) of Figure 10 ). It should be noted that the angle formed by the bottom surface and the side surface of the first recess 7 is a right angle or an obtuse angle slightly larger than a right angle (that is, the angle corresponding to the draft angle generated when the first recess 7 is formed by an imprint process).

[0099] Next, a plurality of first conductive lines 13 constituting the first conductor pattern 10 are formed. Specifically, an adhesion layer 13a is formed in each of the first recesses 7 by evaporation or sputtering. Then, a conductive layer 13b made of a conductive metal such as copper is laminated on the adhesion layer 13a by, for example, electroplating treatment. Thus, the state is reached where the plurality of first conductive lines 13 are formed in the first layer 5 (refer to the cross-sectional view shown in (b) of Figure 10 ).

[0100] Next, a second layer 6 is formed on the upper surface of the first layer 5. Specifically, a resin material having insulating properties and light-transmitting properties (the above-mentioned thermosetting resin material or ultraviolet curable resin material) is applied to the upper surface of the first layer 5. Then, second recesses 8 are formed on the upper surface side of the second layer 6 by an imprint process. Thus, the state is reached where the second layer 6 having a plurality of second recesses 8 is laminated on the upper surface of the first layer 5 (refer to the cross-sectional view shown in (c) of Figure 10 ). Then, the remaining portion 6a formed on the bottom side of the second recess 8 is removed by ashing treatment (refer to the cross-sectional view shown in (e) of Figure 10 ). It should be noted that the angle formed by the bottom surface and the side surface of the second recess 8 is a right angle or an obtuse angle slightly larger than a right angle (specifically, the angle corresponding to the draft angle generated when the second recess 8 is formed by an imprint process).

[0101] Next, each second conductive line 17 constituting the second conductor pattern 14 is formed. Specifically, an adhesion layer 17a is formed in each of the second recesses 8 by evaporation or sputtering (refer to Figure 7 and Figure 9 ). Then, a conductive layer 17b made of a conductive metal such as copper is laminated on the adhesion layer 17a by, for example, electroplating treatment (refer to Figure 7 and Figure 9 ). Further, a blackening layer 18 is formed on the upper surface side of the conductive layer 17b by blackening treatment (refer to Figure 7 and Figure 9 ). Thus, the state is reached where the second conductive lines 17 are formed on the second layer 6 (refer to the cross-sectional view shown in (e) of Figure 10 ). In addition, in this process, a via hole portion 22 is formed at the position of the second recess 8 where the above-mentioned remaining portion 6a has been removed.

[0102] After the above steps, the manufacturing of the multilayer wiring substrate 1 is completed.

[0103] [Function and effect of the embodiment]

[0104] As described above, the multilayer wiring substrate 1 according to the embodiments of the present disclosure includes a plurality of first conductor patterns 10 and a plurality of second conductor patterns 14 disposed at different positions in the thickness direction of the substrate 3. Each first conductor pattern 10 is composed of a plurality of first conductive wires 13 that are respectively thinned. Each second conductor pattern 14 is composed of a plurality of second conductive wires 17 that are respectively thinned. Compared with the structure of the prior art (for example, the wiring substrate including a solid conductive pattern and a solid via hole disclosed in the above-mentioned Patent Document 1), with this structure, in the multilayer wiring substrate 1, the transparency and light transmittance of the substrate 3 can be ensured.

[0105] In addition, the via hole portion 22 is configured such that in the connection region 21 of the overlapping pattern 20, at the intersection point P where the first conductive wire 13 and the second conductive wire 17 intersect, the via hole portion 22 is electrically connected to the first conductive wire 13. With this structure, the first conductor pattern 10 and the second conductor pattern 14 can be electrically connected to each other. That is, in the multilayer wiring substrate 1, the first conductor pattern 10 and the second conductor pattern 14 disposed at different positions in the thickness direction of the substrate 3 can be electrically connected through the via hole portion 22.

[0106] Moreover, each via hole portion 22 of this embodiment has a line width equal to the line width of each second conductive wire 17. Thus, when viewed from above, it can be said that each second conductive wire 17 completely covers the via hole portion 22 in the line width direction. That is, when viewed from above, the via hole portion 22 is not obvious. As a result, compared with the structure of the prior art (the wiring substrate shown in the above-mentioned Patent Document 1), in the multilayer wiring substrate 1, the transparency and light transmittance of the substrate 3 can be ensured without being impaired.

[0107] As described above, in the embodiments of the present disclosure, in the multilayer wiring substrate 1 having a via hole structure, the transparency and light transmittance of the substrate 3 can be ensured.

[0108] In addition, in the connection region 21 of this embodiment, two first conductive wires 13, 13 intersect with one second conductive wire 17. Moreover, at the two intersection points P, P where the two first conductive wires 13, 13 intersect with one second conductive wire 17, the via hole portion 22 is electrically connected to the two first conductive wires 13, 13. Therefore, for example, even if there is some abnormality in the electrical connection state between the first conductive wire 13 and the second conductive wire 17 at one intersection point P, as long as the electrical connection state between the first conductive wire 13 and the second conductive wire 17 at the other intersection point P is normal, the electrical connection state between the first conductor pattern 10 and the second conductor pattern 14 can be stabilized in the connection region 21. That is, the conduction reliability of the multilayer wiring substrate 1 can be improved.

[0109] Further, for example, in the multilayer wiring substrate 1 formed by an imprinting process, at the intersection P described above, in a cross-sectional view, the first conductive wire 13 and the via portion 22 overlap each other in the thickness direction of the substrate 3. Thus, the first conductive wire 13 and the via portion 22 are in an electrically connected state. Therefore, in the connection region 21, the electrical connection state between the first conductor pattern 10 and the second conductor pattern 14 can be stabilized.

[0110] Further, the via portion 22 is configured such that the length ( Figure 6 the dimension L shown in ) in the extending direction of the second conductive wire 17 is equal to or greater than the sum of the pitch ( Figure 6 the dimension A shown in ) between the first conductive wires 13, 13 adjacent to each other in the extending direction and the line width ( Figure 6 the dimension W shown in ) of one first conductive wire 13. According to this structure, it is easy to arrange the via portion 22 to be connected to at least one first conductive wire 13 located in the connection region 21. Thus, for example, in the process of manufacturing the multilayer wiring substrate 1, even when the alignment of the first conductor pattern 10 and the second conductor pattern 14 in a top view is slightly shifted, the via portion 22 can be electrically connected to at least one first conductive wire 13 located in the connection region 21. Therefore, the electrical connection state between the first conductor pattern 10 and the second conductor pattern 14 can be stabilized.

[0111] Further, the connection region 21 of this embodiment is smaller than the region occupied by the overlapping pattern 20. Thus, in the connection region 21, even when the alignment of the first conductor pattern 10 and the second conductor pattern 14 in a top view is slightly shifted, the number of intersections P between the first conductive wire 13 and the second conductive wire 17 can be kept constant. As a result, the electrical connection state between the first conductor pattern 10 and the second conductor pattern 14 can be stabilized.

[0112] Further, the substrate 3 includes a flexible film base material 4. Therefore, not only can the multilayer wiring substrate 1 including the substrate 3 be mounted on a flat mounting surface, but also it can be mounted on an external device (not shown) having a mounting surface with a curved surface shape or the like.

[0113] Further, the upper surface of the first layer 5 is formed in a flat shape in a state where each first conductive wire 13 is buried in the first recess 7. Thus, it is easy to stack the second layer 6 on the upper surface side of the first layer 5. Further, the upper surface of the second layer 6 is formed in a flat shape in a state where each second conductive wire 17 is buried in each second recess 8. Thus, it is easy to arrange each mounting element 2 on the multilayer wiring substrate 1. Further, when a functional layer (not shown) is stacked on the multilayer wiring substrate 1, the total thickness of the multilayer wiring substrate 1 and the above-described functional layer is likely to become constant. Therefore, it is easy to stack other component layers such as the above-described functional layer on the multilayer wiring substrate 1.

[0114] In addition, the first conductor pattern 10 and the second conductor pattern 14 are each formed of a grid pattern, and each of the first conductive lines 13 and each of the second conductive lines 17 are configured to have a line width of 15 μm or less. With this structure, the transparency and light transmittance of the substrate 3 can be ensured.

[0115] In addition, the overlapping pattern 20 has an aperture ratio equal to the aperture ratio of each of the first conductor patterns 10 and the aperture ratio of each of the second conductor patterns 14. Thus, when viewed from above, the visibility of the overlapping pattern 20 is the same as the visibility of each of the first conductor patterns 10 and each of the second conductor patterns 14. That is to say, when viewed from above, the overlapping pattern 20 is less conspicuous than each of the first conductor patterns 10 and each of the second conductor patterns 14. Therefore, the visual recognition of the multilayer wiring substrate 1 can be improved.

[0116] In addition, the dummy pattern 30 has an aperture ratio equal to the aperture ratio of the first conductor pattern 10 and the aperture ratio of the second conductor pattern 14. Thus, when viewed from above, the visibility of the dummy pattern 30 is the same as the visibility of each of the first conductor patterns 10 and each of the second conductor patterns 14. As a result, when viewed from above, each of the first conductor patterns 10 and each of the second conductor patterns 14 are less conspicuous. Therefore, when viewed from above or below, the visibility of each of the first conductor patterns 10 and each of the second conductor patterns 14 located in the plane of the multilayer wiring substrate 1 is unified, and the multiple wirings forming each pattern are difficult to be visually recognized. Thereby, the visual recognition of the multilayer wiring substrate 1 can be improved.

[0117] In addition, each of the second conductive lines 17 includes: a close contact layer 17a formed on at least the bottom surface of the second recess 8, and a blackening layer 18 laminated on the upper surface of the conductive layer 17b. When the multilayer wiring substrate 1 is viewed from above and below, each of the second conductive lines 17 is difficult to be visually recognized due to the close contact layer 17a and the blackening layer 18. Therefore, the visual recognition of the multilayer wiring substrate 1 can be improved.

[0118] [Modification Example 1 of the Embodiment]

[0119] In the above embodiment, as each of the first conductor patterns 10, a mode formed of a grid pattern in which a plurality of first conductive lines 13 are arranged in a grid shape is shown, but it is not limited to this mode. Each of the second conductor patterns 14 is also not limited to a mode formed of a grid pattern in which a plurality of second conductive lines 17 are arranged in a grid shape.

[0120] For example, as Figure 11 shown in Modification Example 1, each of the first conductor patterns 10 may be formed of a pattern (ladder-like pattern) in which a plurality of first conductive lines 13 are arranged in a ladder shape. Similarly, each of the second conductor patterns 14 may be formed of a pattern (ladder-like pattern) in which a plurality of second conductive lines 17 are arranged in a ladder shape.

[0121] Moreover, in this modification, each of the first conductive wires 13 and each of the multiple second conductive wires 17 are configured to have a line width of 15 μm or less. That is to say, each of the first conductive wires 13 and each of the multiple second conductive wires 17 are thinned. Therefore, similar to the above-described embodiment, the transparency and light transmittance of the substrate 3 can also be ensured in this modification.

[0122] In addition, in the above-described embodiment, the connection region 21 is smaller than the region occupied by the overlapping pattern 20, but it is not limited to this manner. For example, as in Modification 1, the connection region 21 may have the same size as the overlapping pattern 20. That is to say, the connection region 21 of Modification 1 coincides with the overlapping pattern 20.

[0123] However, a plurality of first bridge portions 41 are provided in the first conductor pattern 10 in the region other than the connection region 21. Each of the first bridge portions 41 extends along the direction (X direction) orthogonal to the extending direction of each of the first conductive wires 13, and is arranged between adjacent first conductive wires 13, 13. In this way, by providing the plurality of first bridge portions 41, the conduction reliability of the first conductor pattern 10 is thereby improved.

[0124] A plurality of second bridge portions 42 are provided in the second conductor pattern 14 in the region other than the connection region 21. Each of the second bridge portions 42 extends along the direction (Y direction) orthogonal to the extending direction of each of the second conductive wires 17, and is arranged between adjacent first conductive wires 13, 13.

[0125] On the other hand, the first bridge portion 41 and the second bridge portion 42 are not arranged in the connection region 21. In addition, in the connection region 21, the first conductive wire 13 and the second conductive wire 17 are further thinned. Specifically, each of the first conductive wires 13 is configured such that the line width of the portion located in the connection region 21 is about half of the line width of the portion located in the region other than the connection region 21. Similarly, each of the second conductive wires 17 is configured such that the line width of the portion located in the connection region 21 is about half of the line width of the portion located in the region other than the connection region 21. According to this structure, in the connection region 21 (overlapping pattern 20), it is easy to obtain the desired aperture ratio.

[0126] It should be noted that it is preferably configured that, similar to the above-described embodiment, the difference between the aperture ratio of the overlapping pattern 20 (connection region 21) in Modification 1 and the aperture ratio of the first conductor pattern 10 (or the aperture ratio of the second conductor pattern 14) in the region other than the connection region 21 is 30% or less. More preferably, the difference between the aperture ratios of the two is 10% or less.

[0127] [Modification 2 of the Embodiment]

[0128] Figure 12 The modified example 2 shown is a further modified example of the above-described modified example 1. In this modified example 2, it is configured such that the number of the first conductive wires 13 and the number of the second conductive wires 17 in the connection region 21 are less than the number of the first conductive wires 13 and the number of the second conductive wires 17 in the region outside the connection region 21.

[0129] Specifically, as Figure 12 shown, the number of the first conductive wires 13 in the region outside the connection region 21 is five, while the number of the first conductive wires 13 in the connection region 21 is three. Similarly, the number of the second conductive wires 17 in the region outside the connection region 21 is five, while the number of the second conductive wires 17 in the connection region 21 is three. Thereby, the aperture ratio of the overlapping pattern 20 can be made larger than the aperture ratio of the first conductor pattern 10 and / or the aperture ratio of the second conductor pattern 14 in the region outside the connection region 21.

[0130] It should be noted that in the modified example 2, the line width of each of the first conductive wires 13 in the connection region 21 is equal to the line width of each of the first conductive wires 13 in the region outside the connection region 21. Similarly, the line width of each of the second conductive wires 17 in the connection region 21 is equal to the line width of each of the second conductive wires 17 in the region outside the connection region 21.

[0131] [Modified Example 3 of the Embodiment]

[0132] Figure 13 and Figure 14 The modified example 3 shown is a further modified example of the above-described modified example 1. Different from the above-described modified example 1, in this modified example 3, a plurality of first bridge portions 41 and a plurality of second bridge portions 42 are also provided in the connection region 21 (overlapping pattern 20).

[0133] In addition, different from the above-described modified example 1, in the modified example 3, the line width of each of the first conductive wires 13 in the connection region 21 is equal to the line width of each of the first conductive wires 13 in the region outside the connection region 21. The line width of each of the second conductive wires 17 in the connection region 21 is also equal to the line width of each of the second conductive wires 17 in the region outside the connection region 21.

[0134] That is to say, as long as the difference between the aperture ratio of the overlapping pattern 20 (connection region 21) and the aperture ratio of the first conductor pattern 10 (or the aperture ratio of the second conductor pattern 14) in the region outside the overlapping pattern 20 is 30% or less, it may be configured as in the modified example 3.

[0135] However, Figure 13When viewed from above in the state shown below, all of the first bridge portions 41 located in the connection region 21 overlap with the second conductive wires 17, and all of the second bridge portions 42 located in the connection region 21 overlap with the first conductive wires 13.

[0136] On the other hand, Figure 14 When viewed from above, a part of each of the first bridge portions 41 located in the connection region 21 overlaps with each of the second conductive wires 17, and a part of each of the second bridge portions 42 located in the connection region 21 overlaps with each of the first conductive wires 13. Even in Figure 14 the state shown, as long as the difference between the opening ratio of the overlapping pattern 20 (connection region 21) and the opening ratio of the first conductor pattern 10 (or the opening ratio of the second conductor pattern 14) in the region outside the overlapping pattern 20 is 30% or less, there will be no particular impact on ensuring the transparency and light transmittance of the substrate 3.

[0137] [Modification Example 4 of the Embodiment]

[0138] In addition, in the above-described embodiment, the via portion 22 is configured such that the angle formed by the side surface portion in a cross-sectional view and the lower surface of the second conductive wire 17 is approximately a right angle, but it is not limited to this configuration. For example, as Figure 15 shown in Modification Example 4, the via portion 22 may be configured such that the angle formed by the side surface of the via portion 22 and the lower surface of the second conductive wire 17 in a cross-sectional view is an obtuse angle.

[0139] Specifically, as Figure 15 shown, the via portion 22 of Modification Example 4 has an inclined portion 23. The inclined portion 23 is formed such that, in a cross-sectional view, the front end of the inclined portion 23 gradually tapers as it approaches the lower side of the substrate 3 from below the second conductive wire 17. Preferably, the angle formed by the inclined portion 23 and the lower surface of the second conductive wire 17 is an angle (obtuse angle) larger than the draft angle generated when forming the second recess 8 by an imprint process. Moreover, the joint portion between the lower portion of the second conductive wire 17 and the inclined portion 23 is formed to have a curved shape (gentle R shape) in a cross-sectional view. Thus, compared with the above-described embodiment, in this Modification Example 4, current easily flows from the second conductive wire 17 to the via portion 22. As a result, the electrical conduction state between the first conductive wire 13 and the second conductive wire 17 can be improved.

[0140] It should be noted that, similar to the above-described embodiment, in this modification, the angle formed by the bottom surface and the side surface of the first recess 7 is an obtuse angle slightly larger than a right angle (an angle equivalent to the draft angle). The angle formed by the bottom surface and the side surface of the second recess 8 is an obtuse angle slightly larger than a right angle (an angle equivalent to the draft angle).

[0141] [Modification Example 5 of the Embodiment]

[0142] In the above-described embodiment, the multilayer wiring substrate 1 formed by an imprint process is shown, but the multilayer wiring substrate 1 may also be formed by a process other than the imprint process. For example, as Figure 16 and Figure 17 in Modification 5 shown, the multilayer wiring substrate 1 may also be formed by an etching process.

[0143] Hereinafter, with reference to Figure 17 , a method for manufacturing the multilayer wiring substrate 1 by an etching process will be described.

[0144] First, a plurality of first conductive lines 13 constituting the first conductor pattern 10 are formed on the upper surface of the film base material 4 by etching (photolithography) (refer to the cross-sectional view shown in (a) of Figure 17 ).

[0145] Next, a first layer 5 is formed on the upper surface of the film base material 4. Specifically, a resin material having insulating properties and light-transmitting properties (a thermosetting resin material or an ultraviolet curable resin material) is applied to the upper surface of the film base material 4. As a result, the first layer 5 is in a state of being stacked on the upper surface of the film base material 4 (refer to the cross-sectional view shown in (b) of Figure 17 ).

[0146] Next, a notch portion 5a for forming the via hole portion 22 is formed in the first layer 5 by ashing (refer to the cross-sectional view shown in (c) of Figure 17 ). Then, a plurality of second conductive lines 17 constituting the second conductor pattern 14 are formed on the upper surface of the first layer 5 by etching (photolithography) (refer to the cross-sectional view shown in (d) of Figure 17 ). In addition, while the second conductive lines 17 are being formed, the via hole portion 22 is formed at a position corresponding to the notch portion 5a.

[0147] After the above steps, the manufacturing of the multilayer wiring substrate 1 according to Modification 5 is completed.

[0148] As Figure 16 shown, in the multilayer wiring substrate 1 formed by the etching process, at a position corresponding to the intersection point P, in a cross-sectional view, the via hole portion 22 is in a state of covering the first conductive line 13. Thus, similarly to the above-described embodiment, the via hole portion 22 is in a state of being electrically connected to the first conductive line 13. Therefore, in Modification 5 as well, the first conductor pattern 10 and the second conductor pattern 14 disposed at different positions in the thickness direction of the substrate 3 can be electrically connected by the via hole portion 22 shown in Figure 16 .

[0149] [Modification 6 of the Embodiment]

[0150] In the above-described embodiment, a way is shown in which one via portion 22 overlaps two first conductive lines 13, 13 adjacent to each other in the extending direction of the second conductive line 17 in the thickness direction of the substrate 3, but the way is not limited to this. That is to say, the via portion 22 may not be configured to have a length along the extending direction of the second conductive line 17 that is equal to or greater than the sum of the pitch between the first conductive lines 13, 13 adjacent to each other in this extending direction and the line width of one first conductive line 13.

[0151] For example, as Figure 18 shown in the modification example 6, one via portion 22 may also be arranged to be connected to one first conductive line 13. In this modification example 6, it is also possible to electrically connect the first conductor pattern 10 and the second conductor pattern 14 arranged at different positions in the thickness direction of the substrate 3 through the via portion 22.

[0152] [Other Embodiments]

[0153] In the above-described embodiment, a way is shown in which the overlapping pattern 20 includes one connection region 21, but the way is not limited to this. For example, the overlapping pattern 20 may also include a plurality of connection regions 21. That is to say, the overlapping pattern 20 only needs to include at least one connection region 21.

[0154] In the above-described embodiment, a way is shown in which one via portion 22 is provided on each second conductive line 17 located in the connection region 21, but it is not limited to this way. For example, a plurality of via portions 22 may also be provided on each second conductive line 17 located in the connection region 21. That is to say, at least one via portion 22 is provided on each second conductive line 17 located in the connection region 21.

[0155] In the above-described embodiment, a way is shown in which the line width of the via portion 22 is equal to the line width of the second conductive line 17, but it is not limited to this way. That is to say, the via portion 22 may also be configured to have a line width smaller than the line width of the second conductive line 17. Even with such a structure, similar to the above-described embodiment, in a top view, it can be said that each second conductive line 17 completely covers the via portion 22 in the line width direction, so that the via portion 22 is not conspicuous. Therefore, the transparency and light transmittance of the substrate 3 can be ensured.

[0156] In the above-described embodiment, a way is shown in which the via portion 22 is electrically connected to the two first conductive lines 13, 13 at two intersection points P, P where two first conductive lines 13, 13 and one second conductive line 17 intersect each other, but it is not limited to this way. That is to say, the via portion 22 may also be electrically connected to the plurality of first conductive lines 13 at two or more intersection points P, P,... where a plurality of first conductive lines 13 and one second conductive line 17 intersect.

[0157] In the above-described embodiment, the opening ratio of each first conductor pattern 10 is shown to be equal to the opening ratio of each second conductor pattern 14, but it is not limited to this. That is to say, the opening ratio of each first conductor pattern 10 and the opening ratio of each second conductor pattern 14 may also be unequal to each other.

[0158] In addition, in the above-described embodiment, the overlapping pattern 20 is shown to have an opening ratio equal to the opening ratio of each first conductor pattern 10 and the opening ratio of each second conductor pattern 14, but it is not limited to this. For example, when the opening ratio of each first conductor pattern 10 and the opening ratio of each second conductor pattern 14 are unequal to each other, the overlapping pattern 20 may also be configured to have an opening ratio equal to the opening ratio of each first conductor pattern 10. Alternatively, the overlapping pattern 20 may also be configured to have an opening ratio equal to the opening ratio of each second conductor pattern 14.

[0159] In the above-described embodiment, the manner of arranging each dummy pattern 30 on the first layer 5 is shown, but it is not limited to this. That is to say, each dummy pattern 30 may also be arranged on the second layer 6.

[0160] The above has described the embodiments of the present disclosure, but the present disclosure is not limited to the above-described embodiments, and various changes can be made within the scope of the present disclosure.

[0161] -Industrial Applicability-

[0162] The present disclosure can be industrially used as a multilayer wiring substrate.

[0163] -Symbolic Explanation-

[0164] 1: Multilayer wiring substrate

[0165] 2: Mounting element

[0166] 3: Substrate

[0167] 4: Film base material

[0168] 5: First layer

[0169] 6: Second layer

[0170] 7: First recess

[0171] 8: Second recess

[0172] 10: First conductor pattern

[0173] 11: First main body portion

[0174] 12: First branch portion

[0175] 13: First conductive wire

[0176] 13a: Close contact layer

[0177] 13b: Conductive layer

[0178] 14: Second conductor pattern

[0179] 15: Second main body part

[0180] 16: Second branch part

[0181] 17: Second conductive wire

[0182] 17a: Close contact layer

[0183] 17b: Conductive layer

[0184] 18: Blackening layer

[0185] 20: Overlapping pattern

[0186] 21: Connection area

[0187] 22: Via part

[0188] 23: Tilted part

[0189] 30: False pattern

[0190] 31: False conductive wire

[0191] 41: First bridge part

[0192] 42: Second bridge part

[0193] P: Intersection point

Claims

1. A multilayer wiring substrate, characterized in that: The multi-layer wiring substrate includes: a substrate having transparency and translucency; and a first conductor pattern and a second conductor pattern disposed at different positions in the thickness direction of the substrate, the first conductor pattern being composed of a plurality of first conductive wires each thinned, the second conductor pattern being composed of a plurality of second conductive wires each thinned, an overlapping pattern is provided in the first conductor pattern and the second conductor pattern, and the overlapping pattern is formed such that a part of the first conductor pattern overlaps with a part of the second conductor pattern in the thickness direction of the substrate, in the overlapping pattern, when viewed from above, the plurality of first conductive wires and the plurality of second conductive wires cross each other, the overlapping pattern includes at least one connection region, and the first conductive wire and the second conductive wire are electrically connected in the connection region, at least one via portion is provided on the second conductive wire located in the connection region, the via portion is configured such that at the intersection where the first conductive wire and the second conductive wire cross in the connection region, the via portion is electrically connected to the first conductive wire, the via portion has a line width equal to or less than the line width of the second conductive wire.

2. The multi-layer wiring substrate according to claim 1, wherein: a plurality of the first conductive wires and a plurality of the second conductive wires are arranged in the connection region, in the connection region, a plurality of the first conductive wires cross one second conductive wire, the via portion is electrically connected to the plurality of first conductive wires at two or more intersections where the plurality of first conductive wires cross one second conductive wire.

3. The multi-layer wiring substrate according to claim 1, wherein: at the intersection, in a cross-sectional view, the via portion and the first conductive wire overlap each other in the thickness direction.

4. The multi-layer wiring substrate according to claim 1, wherein: at the intersection, in a cross-sectional view, the via portion covers the first conductive wire.

5. The multi-layer wiring substrate according to claim 1, wherein: the via portion is configured such that the length of the via portion along the extending direction of the second conductive wire is equal to or greater than the sum of the pitch between the first conductive wires adjacent to each other in the extending direction and the line width of one first conductive wire.

6. The multi-layer wiring substrate according to claim 1, wherein: the connection region is smaller than the region occupied by the overlapping pattern.

7. The multi-layer wiring substrate according to claim 1, wherein: the substrate includes a flexible film substrate.

8. The multi-layer wiring substrate according to claim 7, wherein: the substrate includes a first layer and a second layer, the first layer is laminated on the upper side of the film substrate, and the first layer is for arranging the first conductor pattern, the second layer is laminated on the upper side of the first layer, and the second layer is for arranging the second conductor pattern, the first layer and the second layer are each made of an insulating material, A plurality of first recesses recessed downward from the upper surface of the first layer are provided on the first layer. A plurality of second recesses recessed downward from the upper surface of the second layer are provided on the second layer. Each of the plurality of first conductive wires is embedded in the first recess, while each of the plurality of second conductive wires is embedded in the second recess. The upper surface of the first layer is formed in a flat shape in a state where each of the plurality of first conductive wires is embedded in the first recess. The upper surface of the second layer is formed in a flat shape in a state where each of the plurality of second conductive wires is embedded in the second recess.

9. The multilayer wiring substrate according to claim 1, wherein: The first conductor pattern and the second conductor pattern are each composed of a grid pattern. The plurality of first conductive wires and the plurality of second conductive wires are configured such that their respective wire widths are 15 μm or less.

10. The multilayer wiring substrate according to claim 1, wherein: The overlapping pattern has an aperture ratio equal to the aperture ratio of the first conductor pattern and / or the aperture ratio of the second conductor pattern.

11. The multilayer wiring substrate according to claim 1, wherein: The multilayer wiring substrate further includes a dummy pattern, and in a plan view, the dummy pattern is disposed in a region of the substrate where the first conductor pattern and the second conductor pattern do not exist. The dummy pattern has an aperture ratio equal to the aperture ratio of the first conductor pattern and / or the aperture ratio of the second conductor pattern.

12. The multilayer wiring substrate according to claim 8, wherein: The second conductive wire includes a close contact layer and a conductive layer. The close contact layer is formed on at least the bottom surface of the second recess. The conductive layer is stacked on the close contact layer and embedded in the second recess.

13. The multilayer wiring substrate according to claim 12, wherein: The second conductive wire further includes a blackening layer, and the blackening layer is stacked on the upper surface of the conductive layer.

14. The multilayer wiring substrate according to claim 1, wherein: The first conductor pattern and the second conductor pattern are each composed of a ladder-shaped pattern. The plurality of first conductive wires and the plurality of second conductive wires are configured such that their respective wire widths are 15 μm or less.

15. The multilayer wiring substrate according to claim 1, wherein: The via portion is formed integrally with the second conductive wire in the connection region and protrudes downward from the lower portion of the second conductive wire toward the lower side of the substrate. The via portion has an inclined portion, and the inclined portion is formed such that, in a cross-sectional view, the front end of the inclined portion becomes thinner as it approaches the lower side of the substrate from the lower portion of the second conductive wire. In a cross-sectional view, the joint portion between the lower portion of the second conductive wire and the inclined portion is formed in a curved shape.

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