Line insertion black circuit, display panel and line insertion black circuit driving method

Abstract

The invention relates to a row black insertion circuit, a display panel and a row black insertion circuit driving method. The row black insertion circuit comprises a pixel driving sub-circuit and an electrochromic material driving sub-circuit. The electrochromic material is disposed between the backlight layer and the pixels. The row black insertion circuit can drive an electrochromic material to perform a low transmittance mode before target pixels of a target row are refreshed, row black insertion is performed on the target row, then the target pixels of the target row are refreshed according to data of a data line, M rows recover a high transmittance mode after the target pixels of the target row are refreshed, and the row black insertion is performed on the target row. The original effective refresh rate is maintained while the pixel response speed is improved and the smear phenomenon is avoided, and the visual effect is improved.

Description

Technical Field

[0001] The present application relates to the technical field of display panels, and in particular, to a row black insertion circuit, a display panel, and a driving method for the row black insertion circuit. Background Art

[0002] With the change of market demand, people's requirements for a higher refresh rate of liquid crystal display (LCD) are becoming increasingly obvious. However, due to the basic physical properties of liquid crystal materials, it takes time for liquid crystal molecules to adjust their deflection angles under a fixed voltage, which limits the high refresh rate to a certain extent. When the refresh rate gradually increases, the horizontal blanking (H-Blanking) and the data charging time are shortened, and the response of liquid crystal molecules is not complete, resulting in phenomena such as ghosting and image retention, which affect the visual effect.

[0003] To improve image ghosting, there is currently a "black insertion technology" that inserts black frames between image frames, that is, an intermediate frame is inserted between two images that require large deflection of liquid crystal molecules, so that the liquid crystal molecules are deflected to the intermediate angle in advance, improving the phenomenon of untimely response to a certain extent. However, based on the existing architecture, the black insertion technology is full-screen black insertion, which increases black screens in the original frames for display and reduces the effective refresh rate. For example, when M black frames are inserted into N frames in one second, the actual number of data frames effectively displayed within one second is only (N - M) frames. In addition, since the gray-scale 0 data of the "black frame" is also provided by the integrated circuit (IC), the IC load is increased. Summary of the Invention

[0004] The present application provides a row black insertion circuit, a display panel, and a driving method for the row black insertion circuit to solve the technical problem that full-screen black insertion reduces the effective refresh rate.

[0005] In a first aspect, the present application provides a row black insertion circuit, which includes: a pixel driving sub-circuit and an electrochromic material driving sub-circuit; The pixel driving sub-circuit is configured to drive the target pixels in the target row to be refreshed according to the data on the data line under the action of the first row scanning signal of the first gate driving unit; The electrochromic material driving sub-circuit is configured to drive the electrochromic material in the target row to enter a low transmittance mode N rows before the target pixels in the target row are refreshed and restore a high transmittance mode M rows after the target pixels in the target row are refreshed under the action of the second row scanning signal of the second gate driving unit; wherein, the electrochromic material is disposed between the backlight layer and the pixels.

[0006] Optionally, the pixel driving sub-circuit includes: a first gate driving unit, a driving unit, and an enabling unit; The first gate driving unit is connected to the gate driving end of the driving unit; the output end of the driving unit is connected to the input end of the enabling unit; the output end of the enabling unit is connected to the electrochromic material driving sub-circuit; The first gate driving unit is configured to output the first row scanning signal to the driving unit; the driving unit drives the target pixels in the target row to be refreshed under the action of the first row scanning signal; the enabling unit is configured to control the enabling of the electrochromic material driving sub-circuit under the action of an enabling signal.

[0007] Optionally, the driving unit includes: a first thin film transistor and a storage capacitor; The gate of the first thin film transistor is connected to the first gate driving unit, the source of the first thin film transistor is connected to the data line, and the drain of the first thin film transistor is connected to the first end of the storage capacitor and the first input end of the enabling unit; the second end of the storage capacitor is connected to the ground voltage.

[0008] Optionally, the enabling unit includes a second thin film transistor; The gate of the second thin film transistor is connected to the enabling signal, and the electrochromic material driving sub-circuit is enabled under the action of the enabling signal; the source of the second thin film transistor serves as the first input end of the enabling unit and is connected to the drain of the first thin film transistor; the drain of the second thin film transistor serves as the first output end of the enabling unit and is connected to the electrochromic material driving sub-circuit.

[0009] Optionally, the enabling unit further includes a third thin film transistor; The gate of the third thin film transistor is connected to the drain of the second thin film transistor, the source of the third thin film transistor is connected to the reference voltage, and the drain of the third thin film transistor is connected to the electrochromic material driving sub-circuit.

[0010] Optionally, the electrochromic material driving sub-circuit includes: a second gate driving unit, an electrochromic unit, and an AND gate unit; The second gate driving unit is connected to the first input end of the electrochromic unit, and the second input end of the electrochromic unit is connected to the output end of the AND gate unit; the AND gate unit is connected to the output end of the enabling unit; The second gate driving unit is configured to output the second row scanning signal to the electrochromic unit; the electrochromic unit drives the electrochromic material in the target row to enter the low transmittance mode or restore the high transmittance mode under the combined action of the second row scanning signal and the signal input at the output end of the AND gate unit.

[0011] Optionally, the electrochromic unit includes: a fourth thin-film transistor, a fifth thin-film transistor, a first capacitor, and a row color-changing module; the row color-changing module is made of an electrochromic material; The gate of the fourth thin-film transistor is connected to the second gate driving unit and the first end of the first capacitor. The source of the fourth thin-film transistor is connected to the first power supply. The drain of the fourth thin-film transistor is connected to the drain of the fifth thin-film transistor and the first end of the row color-changing module. The source of the fifth thin-film transistor is connected to the ground voltage. The gate of the fifth thin-film transistor is connected to the output end of the AND gate unit. The second end of the first capacitor is connected to the gate-off voltage. The second end of the row color-changing module is connected to the ground voltage.

[0012] Optionally, the AND gate unit includes: an AND gate module, a first resistor, a second resistor, a third resistor, and a sixth thin-film transistor; The first input terminal of the AND gate module is connected to the first end of the first resistor. The second input terminal of the AND gate module is connected to the first end of the second resistor and the source of the sixth thin-film transistor. The output end of the AND gate module is connected to the gate of the fifth thin-film transistor. The second end of the first resistor is connected to the gate-on voltage. The second end of the second resistor is connected to the gate-off voltage. The gate of the sixth thin-film transistor is connected to the first end of the third resistor and the output end of the pixel driving sub-circuit. The drain of the sixth thin-film transistor is connected to the second end of the third resistor and the first row scanning signal of the next row pixel driving sub-circuit.

[0013] In a second aspect, the present application provides a display panel, and the display panel includes the row blanking circuit according to any one of the first aspect.

[0014] In a third aspect, the present application provides a method for driving a row blanking circuit, which is applied to the row blanking circuit according to any one of the first aspect. The method includes: Under the action of the first row scanning signal of the first gate driving unit, the pixel driving sub-circuit refreshes the target pixels of the target row according to the data on the data line. Under the action of the second row scanning signal of the second gate driving unit, the electrochromic material driving sub-circuit drives the electrochromic material of the target row to enter the low transmittance mode in the N rows before the target pixels of the target row are refreshed, and resumes the high transmittance mode in the M rows after the target pixels of the target row are refreshed; wherein, the electrochromic material is disposed between the backlight layer and the pixels.

[0015] The above technical solution provided by the embodiment of the present application has the following advantages compared with the prior art: The line insertion blackening circuit provided by the embodiment of the present application includes: a pixel driving sub-circuit and an electrochromic material driving sub-circuit; the pixel driving sub-circuit is used to drive the target pixels of the target row to be refreshed according to the data of the data line under the action of the first row scanning signal of the first gate driving unit; the electrochromic material driving sub-circuit is used to drive the electrochromic material of the target row to enter the low transmittance mode in the N rows before the target pixels of the target row are refreshed and restore the high transmittance mode in the M rows after the target pixels of the target row are refreshed under the action of the second row scanning signal of the second gate driving unit; wherein, the electrochromic material is disposed between the backlight layer and the pixel. The line insertion blackening circuit can drive the electrochromic material to enter the low transmittance mode before the target pixels of the target row are refreshed, perform line insertion blackening on the target row, then drive the target pixels of the target row to be refreshed according to the data of the data line, and restore the high transmittance mode in the M rows after the target pixels of the target row are refreshed, maintaining the original effective refresh rate while improving the pixel response speed and avoiding the ghosting phenomenon, and improving the visual effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present application and, together with the specification, are used to explain the principles of the present application.

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, other drawings can also be obtained according to these drawings without creative efforts.

[0018] One or more embodiments are illustrated by way of example in the accompanying drawings, and these exemplary illustrations do not limit the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, and unless otherwise stated, the drawings in the drawings do not constitute a proportional limitation.

[0019] Figure 1 Schematic diagram of the structure of a line insertion blackening circuit provided by an embodiment of the present application; Figure 2 Circuit schematic diagram of a line insertion blackening circuit provided by an embodiment of the present application; Figure 3 Schematic diagram of the progressive scanning of an inserted black line provided by an embodiment of the present application; Figure 4 Schematic diagram of the line insertion blackening circuit in the first stage provided by an embodiment of the present application; Figure 5The timing diagram of the scanning signal of the first-stage row blanking insertion circuit provided by an embodiment of the present application; Figure 6 The schematic diagram of the second-stage row blanking insertion circuit provided by an embodiment of the present application; Figure 7 The timing diagram of the scanning signal of the second-stage row blanking insertion circuit provided by an embodiment of the present application; Figure 8 The schematic diagram of the third-stage row blanking insertion circuit provided by an embodiment of the present application; Figure 9 The timing diagram of the scanning signal of the third-stage row blanking insertion circuit provided by an embodiment of the present application; Figure 10 The schematic diagram of the second-stage row blanking insertion circuit when the data voltage is higher than the reference voltage provided by an embodiment of the present application; Figure 11 The schematic diagram of the third-stage row blanking insertion circuit when the data voltage is higher than the reference voltage provided by an embodiment of the present application; Figure 12 The schematic diagram of the second-stage row blanking insertion circuit when the data voltage is lower than the reference voltage provided by an embodiment of the present application; Figure 13 The schematic diagram of the third-stage row blanking insertion circuit when the data voltage is lower than the reference voltage provided by an embodiment of the present application.

[0020] The reference signs are as follows: 101 - Pixel driving sub-circuit; 102 - Electrochromic material driving sub-circuit; 201 - First gate driving unit; 202 - Driving unit; 203 - Enable unit; 204 - Second gate driving unit; 205 - Electrochromic unit; 206 - AND gate unit; T1 - First thin-film transistor; Cst - Storage capacitor; Q1 - Second thin-film transistor; Q2 - Third thin-film transistor; Q3 - Fourth thin-film transistor; Q4 - Fifth thin-film transistor; Q5 - Sixth thin-film transistor; C1 - First capacitor; A - AND gate module. Detailed implementation manners

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some but not all of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0022] The following disclosure provides many different embodiments or examples for implementing different structures of the present application. To simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are only examples and are not intended to limit the present application. In addition, the present application may repeat reference numerals and / or letters in different examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed.

[0023] To solve the technical problem that the full-screen black insertion in the prior art reduces the effective refresh rate, the present application provides a line black insertion circuit, a display panel, and a line black insertion circuit driving method, which can drive an electrochromic material to enter a low transmittance mode before refreshing the target pixels of the target line, perform line black insertion on the target line, and then drive the target pixels of the target line to be refreshed according to the data on the data line, and restore the high transmittance mode M lines after refreshing the target pixels of the target line, maintaining the original effective refresh rate while improving the pixel response speed and avoiding the smear phenomenon, and improving the visual effect.

[0024] Embodiment 1 The first embodiment of the present application provides a line black insertion circuit, as Figure 1 , the line black insertion circuit includes: a pixel driving sub-circuit 101 and an electrochromic material driving sub-circuit 102.

[0025] The pixel driving sub-circuit 101 is configured to drive the target pixels of the target line to be refreshed according to the data on the data line under the action of the first row scanning signal of the first gate driving unit; The electrochromic material driving sub - circuit 102 is used to drive the electrochromic material of the target row to enter the low transmittance mode in the N rows before the target pixel of the target row is refreshed under the action of the second row - scanning signal of the second gate driving unit, and restore the high transmittance mode in the M rows after the target pixel of the target row is refreshed; wherein, the electrochromic material is disposed between the backlight layer and the pixel. N can be set to 1, that is, drive the electrochromic material to enter the low transmittance mode in the row before the target pixel of the target row is refreshed. N can also be set to a number greater than 1 without limitation. Similarly, M can be set to 1, that is, drive the electrochromic material to restore the high transmittance mode in the row after the target pixel of the target row is refreshed. In the subsequent specific embodiments, M is taken as 1 for illustration, which does not represent a limitation on the specific value of M. In fact, M can also be set to a number greater than 1. It should be noted that the values of M and N can be the same (for example, both N and M are set to 1. At this time, drive the electrochromic material to enter the low transmittance mode in the row before the target pixel of the target row is refreshed, and drive the electrochromic material to restore the high transmittance mode in the row after the target pixel of the target row is refreshed), or different (for example, N is set to 2 and M is set to 1. At this time, drive the electrochromic material to enter the low transmittance mode in the two rows before the target pixel of the target row is refreshed, and drive the electrochromic material to restore the high transmittance mode in the row after the target pixel of the target row is refreshed).

[0026] This line blanking circuit can drive the electrochromic material to enter the low transmittance mode before the target pixel of the target row is refreshed, perform line blanking on the target row, then drive the target pixel of the target row to be refreshed according to the data on the data line, and restore the high transmittance mode in the M rows after the target pixel of the target row is refreshed. While improving the pixel response speed and avoiding the smear phenomenon, it maintains the original effective refresh rate and improves the visual effect.

[0027] In a specific embodiment, the line blanking circuit is as Figure 2As shown, the pixel driving sub-circuit 101 includes: a first gate driving unit 201, a driving unit 202, and an enabling unit 203. The electrochromic material driving sub-circuit 102 includes: a second gate driving unit 204, an electrochromic unit 205, and an AND gate unit 206. Among them, GOA (Gate Driven on Array) represents integrated gate driving on the array substrate, GOA1 represents the first gate driving unit 201, GOA1 is a circuit normally used to generate the row scanning signal required for the pixel driving sub-circuit, and the generated row scanning signal is represented by scan. GOA2 represents the second gate driving unit 204, GOA2 is a circuit used to generate the row scanning signal required for the electrochromic material driving sub-circuit 102, and the generated row scanning signal is represented by gate. Vdata represents the data voltage of the data line. Among them, VDD represents the driving voltage of the electrochromic material. For example, VDD is output through the first power supply. VSS represents the ground voltage, VGH represents the gate turn-on voltage, and VGL represents the gate turn-off voltage. The row color-changing module is made of electrochromic material. The electrochromic material can be polythiophene and its derivatives, viologens, tetrathiafulvalene, metal phthalocyanine compounds, etc., without limitation. Among them, each electrochromic material driving sub-circuit can drive the row color-changing module of one row of the target row, or can also drive the row color-changing module from several rows before the target row to the target row, or from several rows before the target row to several rows after the target row, without limitation.

[0028] As Figure 3 is a schematic diagram of progressive scanning with inserted black lines. An inserted black line is added before the target pixel of the target row is refreshed. That is, one or several rows corresponding to the electrochromic material that will be inverted by the liquid crystal in the scanning direction are adjusted to the low transmittance mode, and the high transmittance mode is restored after one row of the target pixel of the target row is refreshed. While improving the pixel response speed and avoiding the ghosting phenomenon, the original effective refresh rate is maintained, improving the visual effect.

[0029] It should be noted that in each embodiment of the present application, the gate and scan signals are exemplified by high-potential pulse signals with a normal low potential. Each electrochromic driving sub-circuit drives the electrochromic material corresponding to one pixel row. The electrochromic material has a low transmittance when powered on and a high transmittance when powered off. The electrochromic material becomes low transmittance one row ahead of the pixel row and becomes high transmittance one row after the pixel row is refreshed. In actual applications, the gate and scan signals can also be low-potential pulse signals with a normal high potential. Each electrochromic driving circuit drives the electrochromic materials corresponding to multiple pixel rows. The electrochromic materials have a high transmittance when powered on and a low transmittance when powered off. The electrochromic materials become low transmittance multiple rows ahead of the pixel row and become high transmittance multiple rows after the pixel row is refreshed, or are synchronously refreshed. The examples in the embodiments of the present application are only for explaining the principle and are not the only reference for actual applications.

[0030] Next, in combination with Figure 2 each component of the black insertion circuit for this row will be described in detail.

[0031] In one embodiment, the pixel driving sub - circuit 101 includes: a first gate driving unit 201, a driving unit 202, and an enabling unit 203.

[0032] The connection relationship is as follows: The first gate driving unit 201 is connected to the gate driving end of the driving unit 202. The output end of the driving unit 202 is connected to the input end of the enabling unit 203. The output end of the enabling unit 203 is connected to the electrochromic material driving sub - circuit 102.

[0033] Among them, the first gate driving unit 201 is used to output the first row - scanning signal Scan(n) to the driving unit 202. The driving unit 202 drives the target pixels of the target row to be refreshed under the action of the first row - scanning signal Scan(n). The enabling unit 203 is used to control the enabling of the electrochromic material driving sub - circuit 102 under the action of the enabling signal EN. It can be configured that when EN is at a low potential, the electrochromic material driving sub - circuit 102 is enabled. If black insertion for the row is not required, EN can be changed to a high potential. If black insertion for the row is required, EN remains at the low - potential state.

[0034] It should be noted that the first row - scanning signal and the second row - scanning signal do not represent the specific row numbers of the scanning signals. They are only used to distinguish the gate(n) signal and the scan(n) signal, and n can be any row in the scanning rows.

[0035] Specifically, the driving unit 202 includes: a first thin - film transistor T1 and a storage capacitor Cst. The enabling unit 203 includes a second thin - film transistor Q1.

[0036] The connection relationship is as follows: The gate of the first thin - film transistor T1 is connected to the first gate driving unit 201. The source of the first thin - film transistor T1 is connected to the data line. The drain of the first thin - film transistor T1 is connected to the first end of the storage capacitor Cst and the first input end of the enabling unit 203. The second end of the storage capacitor Cst is connected to the ground voltage VSS. The gate of the second thin - film transistor Q1 is connected to the enabling signal. When the enabling signal is applied, the electrochromic material driving sub - circuit 102 is enabled. The source of the second thin - film transistor Q1 serves as the first input end of the enabling unit 203 and is connected to the drain of the first thin - film transistor T1. The drain of the second thin - film transistor Q1 serves as the first output end of the enabling unit 203 and is connected to the electrochromic material driving sub - circuit 102.

[0037] In this embodiment, the gate of the second thin-film transistor Q1 is connected to the enable signal EN. When EN is at a low potential, the second thin-film transistor Q1 is turned on. The drain of Q1 is connected to the electrochromic material driving sub-circuit 102. When the first thin-film transistor T1 is turned on, a signal is input to the gate of the sixth thin-film transistor Q5 to turn on Q5. Thus, when Scan(n + 1) is at a high potential, the AND gate module A outputs a high potential, pulling down the row color-changing module to enter the high transmittance mode. When Scan(n + 1) is at a low potential, the AND gate module A outputs a low potential. Thus, when Gate(n) is at a high potential, the row color-changing module enters the low transmittance mode.

[0038] In one embodiment, the enable unit 203 further includes a third thin-film transistor Q2. At this time, the connection relationship is as follows: The gate of the third thin-film transistor Q2 is connected to the drain of the second thin-film transistor Q1. The source of the third thin-film transistor Q2 is connected to the reference voltage VSET. The drain of the third thin-film transistor Q2 is connected to the electrochromic material driving sub-circuit 102.

[0039] In this embodiment, when the third thin-film transistor Q2 is connected to the reference voltage VSET, and VSET is the target gray-scale voltage corresponding to the target gray scale, black insertion for gray-scale rows lower than the target gray scale can be achieved through the third thin-film transistor Q2, further pulling down the gray-scale value to achieve high contrast. This part will be described in detail in the following embodiments.

[0040] In one embodiment, the electrochromic material driving sub-circuit 102 includes: a second gate driving unit 204, an electrochromic unit 205, and an AND gate unit 206.

[0041] The second gate driving unit 204 is connected to the first input terminal of the electrochromic unit 205. The second input terminal of the electrochromic unit 205 is connected to the output terminal of the AND gate unit 206. The AND gate unit 206 is connected to the output terminal of the enable unit 203. The second gate driving unit 204 is configured to output the second row scanning signal Gate(n) to the electrochromic unit 205. Under the combined action of the second row scanning signal and the signal input at the output terminal of the AND gate unit 206, the electrochromic unit 205 drives the electrochromic material of the target row to enter the low transmittance mode or restore the high transmittance mode.

[0042] Specifically, the electrochromic unit 205 includes: a fourth thin-film transistor Q3, a fifth thin-film transistor Q4, a first capacitor C1, and a row color-changing module. The row color-changing module is made of electrochromic material. The AND gate unit 206 includes: an AND gate module (or simply referred to as an AND gate) A, a first resistor R1, a second resistor R2, a third resistor R3, and a sixth thin-film transistor Q5.

[0043] The connection relationship is as follows: The gate of the fourth thin-film transistor Q3 is connected to the second gate driving unit and the first end of the first capacitor C1. The source of the fourth thin-film transistor Q3 is connected to the first power supply VDD. The drain of the fourth thin-film transistor Q3 is connected to the drain of the fifth thin-film transistor Q4 and the first end of the line color change module. The source of the fifth thin-film transistor Q4 is connected to the ground voltage VSS. The gate of the fifth thin-film transistor Q4 is connected to the output end of the AND gate unit 206. The second end of the first capacitor C1 is connected to the gate-off voltage VGL. The second end of the line color change module is connected to the ground voltage VSS. The first input end of the AND gate module A is connected to the first end of the first resistor R1. The second input end of the AND gate module A is connected to the first end of the second resistor R2 and the source of the sixth thin-film transistor Q5. The output end of the AND gate module A is connected to the gate of the fifth thin-film transistor Q4. The second end of the first resistor R1 is connected to the gate-on voltage VGH. The second end of the second resistor R2 is connected to the gate-off voltage VGL. The gate of the sixth thin-film transistor Q5 is connected to the first end of the third resistor R3 and the output end of the pixel driving sub-circuit 101. The drain of the sixth thin-film transistor Q5 is connected to the second end of the third resistor R3 and the first row scan signal Scan(n + 1) of the next row pixel driving sub-circuit.

[0044] In this embodiment, next, taking T1 as an NMOS thin-film transistor (TFT), Q1 and Q2 as PMOS thin-film transistors, and Q3, Q4, and Q5 as NMOS thin-film transistors, the working principles of each stage of the line black insertion circuit will be described in detail.

[0045] In the first stage, Figure 4 is a schematic diagram of the line black insertion circuit in the first stage, Figure 5 is a timing diagram of the scan signal of the line black insertion circuit in the first stage. At this time, Scan(n) and Scan(n + 1) are at a low potential. The first input end of the AND gate A is at a high potential, and the second input end is at a low potential. Then, the AND gate A outputs a low level, and Q4 is cut off. Gate(n) is at a high potential, and Q3 is turned on. VDD drives the electrochromic material of the line color change module into the low transmittance mode and charges C1 to ensure that the potential is maintained during H-Blanking.

[0046] In the second stage, Figure 6 is a schematic diagram of the line black insertion circuit in the second stage, Figure 7This is the timing diagram of the scan signal for the row black insertion circuit in the second stage. At this time, Scan(n) is at a high potential and Scan(n + 1) is at a low potential. At this moment, T1 conducts, the data voltage Vdata enters Cst, and the liquid crystal molecules start to deflect. The first input terminal of AND gate A is at a high potential and the second input terminal is at a low potential, so AND gate A outputs a low level and Q4 is cut off. Gate(n) is at a high potential, Q3 conducts, and VDD drives the electrochromic material of the row color change module into the low transmittance mode and charges C1 to ensure that the potential is maintained during H - Blanking.

[0047] In the third stage, Figure 8 This is the schematic diagram of the row black insertion circuit in the third stage. Figure 9 This is the timing diagram of the scan signal for the row black insertion circuit in the third stage. Scan(n) is at a low potential. At this time, T1 is cut off, Cst maintains the data voltage, and the liquid crystal molecules deflect to the required position. Gate(n) is at a low potential and Q3 is cut off. Scan(n + 1) is at a high potential. The first input terminal of AND gate A is at a high potential and the second input terminal is at a high potential, so AND gate A outputs a high potential and Q4 conducts. VSS drives the electrochromic material of the row color change module to quickly discharge and become transparent.

[0048] Through the above three stages, before the target pixel of the target row is refreshed, the electrochromic material is driven to enter the low transmittance mode for row black insertion of the target row. Then, the target pixel of the target row is refreshed according to the data on the data line, and the high transmittance mode is restored after one row of the target pixel of the target row is refreshed. While improving the pixel response speed and avoiding the ghosting phenomenon, the original effective refresh rate is maintained, improving the visual effect.

[0049] If it is necessary to adjust the response time of the electrochromic material according to the material and the liquid crystal response time, only the advance amount of STV2 (STV2 refers to the frame start signal of GOA2) of GOA2 needs to be adjusted. If it is necessary to adjust the response width of the electrochromic material to each row of pixels, only the number of consecutive pulses of Gate(n), that is, the number of STV2, needs to be adjusted. If it is necessary to adjust the recovery lag time of the electrochromic material, the circuit entity connected to the gate of Q1 needs to be adjusted. If it is necessary to turn off the row black insertion function at a low refresh rate, only STV2 needs to be turned off.

[0050] Next, the specific function of the enable unit 203 will be described in detail. The enable unit can turn on and off the row black insertion function through Q1, and only the enable signal EN needs to be adjusted. And through the reference voltage VSET input at the source of Q2, the working mode in which the electrochromic material is opaque at a specific target gray scale and transparent when higher than this target gray scale can be set to provide a higher contrast, as follows: EN is at a low potential, Q1 conducts, and VSET is set to the target gray scale voltage corresponding to the target gray scale.

[0051] When the Vdata voltage is higher than the reference voltage VSET, the schematic diagram of the row black insertion circuit in the second stage is as follows Figure 10 , the Vgs of Q2 = Vdata - VSET is greater than 0, Q2 is turned off, Q5 is equivalent to a diode, Q5 is turned off when Scan(n + 1) is at a low potential, the AND gate A outputs a low potential, the gate side of Q4 is at a low potential, Q4 is turned off, Gate(n) is at a high potential, Q3 is turned on, and VDD drives the electrochromic material of the row color change module to enter a low transmittance state.

[0052] When the Vdata voltage is higher than the reference voltage VSET, the schematic diagram of the row black insertion circuit in the third stage is as follows Figure 11 , the Vgs of Q2 = Vdata - VSET is greater than 0, Q2 is turned off, Q5 is equivalent to a diode, Q5 is turned on when Scan(n + 1) is at a high potential, the AND gate A outputs a high potential, the gate side of Q4 is at a high potential, Q4 is turned on, and VSS drives the electrochromic material of the row color change module to be in a high transmittance state.

[0053] When the Vdata voltage is lower than the reference voltage VSET, the schematic diagram of the row black insertion circuit in the second stage is as follows Figure 12 , the Vgs of Q2 = Vdata - VSET is less than 0, Q2 is turned on. scan(n + 1) is at a low potential, the first input terminal of the AND gate A is at a high potential, whether Q5 is turned on or not, the second input terminal of the AND gate is at a low potential, that is, the AND gate A outputs a low potential, Q4 is turned off, Gate(n) is at a high potential, Q3 is turned on, and VDD drives the electrochromic material of the row color change module to enter a low transmittance state.

[0054] When the Vdata voltage is lower than the reference voltage VSET, the schematic diagram of the row black insertion circuit in the third stage is as follows Figure 13 , since Vdata is generally less than VGH, the Vgs of Q5 = VSET - Scan(n + 1) is less than 0, Q5 is turned off, the first input terminal of the AND gate A inputs a high potential, the second input terminal inputs a low potential, the AND gate A outputs a low potential, Q4 is turned off. At this time, although Gate(n) switches to a low potential and Q3 is turned off, the electrochromic material of the row color change module still maintains a low transmittance due to its own parasitic capacitance effect in this stage.

[0055] In this embodiment, by setting the target gray-scale voltage corresponding to the target gray-scale for VSET, when the pixel gray-scale is lower than the target gray-scale, the electrochromic material shields the backlight through a low transmittance, further reducing the gray-scale value, achieving a high contrast ratio and improving the display effect.

[0056] In the above embodiments of the present application, since black insertion is performed line by line, while improving the pixel response speed and avoiding the ghosting phenomenon, the original effective refresh rate is maintained, improving the visual effect. Moreover, black insertion is achieved by controlling the transmittance of the electrochromic material, without adding an extra load to the integrated circuit IC.

[0057] Embodiment 2 Based on the same inventive concept, the second embodiment of the present application provides a display panel, and the display panel includes the line black insertion circuit described in any one of Embodiment 1.

[0058] For the display panel applying the line black insertion circuit, before the target pixel of the target row is refreshed, the electrochromic material is driven to enter the low transmittance mode to perform line black insertion on the target row, and then the target pixel of the target row is refreshed according to the data on the data line. After the target pixel of the target row is refreshed, the high transmittance mode is restored after M rows. While improving the pixel response speed and avoiding the ghosting phenomenon, the original effective refresh rate is maintained, improving the visual effect.

[0059] Embodiment 3 The third embodiment of the present application provides a method for driving a line black insertion circuit, which is applied to the line black insertion circuit described in any one of Embodiment 1. The method for driving the line black insertion circuit includes: Under the action of the first row scanning signal of the first gate driving unit, the pixel driving sub - circuit drives the target pixel of the target row to be refreshed according to the data on the data line; Under the action of the second row scanning signal of the second gate driving unit, the electrochromic material driving sub - circuit drives the electrochromic material of the target row to enter the low transmittance mode N rows before the target pixel of the target row is refreshed, and restores the high transmittance mode M rows after the target pixel of the target row is refreshed; wherein, the electrochromic material is disposed between the backlight layer and the pixel.

[0060] This method for driving the line black insertion circuit can drive the electrochromic material to enter the low transmittance mode before the target pixel of the target row is refreshed to perform line black insertion on the target row, and then drive the target pixel of the target row to be refreshed according to the data on the data line. After the target pixel of the target row is refreshed, the high transmittance mode is restored after M rows. While improving the pixel response speed and avoiding the ghosting phenomenon, the original effective refresh rate is maintained, improving the visual effect.

[0061] It should be understood that the terms used herein are for the purpose of describing particular example embodiments only and are not intended to be limiting. Unless the context clearly dictates otherwise, the singular forms "a", "an" and "the" as used herein may also include the plural. The terms "comprising", "including", "containing" and "having" are inclusive and thus specify the presence of the stated features, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring them to be performed in the particular order described or illustrated, unless the order of performance is explicitly stated. It should also be understood that additional or alternative steps may be used.

[0062] It should be understood that the specific embodiments described herein are merely for the purpose of explaining the present application and are not intended to limit the present application. In the description, the suffixes such as "module", "component" or "unit" used to denote elements are only for the convenience of explaining the present application and have no specific meaning in themselves. Therefore, "module", "component" or "unit" can be used interchangeably.

[0063] The above are only specific embodiments of the present application, enabling those skilled in the art to understand or implement the present application. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to these embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features claimed herein.

Claims

1. A black line insertion circuit, characterized in that: The row black insertion circuit includes: a pixel driving subcircuit and an electrochromic material driving subcircuit; The pixel driving subcircuit is used to drive the target pixel in the target row to refresh according to the data of the data line under the action of the first row scanning signal of the first gate driving unit; The electrochromic material driving subcircuit is used to drive the electrochromic material of the target row to enter a low transmittance mode N rows before the target pixel of the target row is refreshed, and to restore the high transmittance mode M rows after the target pixel of the target row is refreshed under the action of the second row scanning signal of the second gate driving unit; wherein, the electrochromic material is arranged between the backlight layer and the pixel.

2. The black line insertion circuit according to claim 1, characterized in that: The pixel driving subcircuit comprises: a first gate driving unit, a driving unit and an enabling unit; The first gate driving unit is connected to the gate driving terminal of the driving unit; the output terminal of the driving unit is connected to the input terminal of the enabling unit; the output terminal of the enabling unit is connected to the electrochromic material driving sub-circuit; The first gate driving unit is used to output the first row scanning signal to the driving unit; the driving unit drives the target pixel in the target row to refresh under the action of the first row scanning signal; the enabling unit is used to control the enabling of the electrochromic material driving sub-circuit under the action of the enabling signal.

3. The black line insertion circuit according to claim 2, characterized in that: The driving unit includes: a first thin film transistor and a storage capacitor; The gate of the first thin film transistor is connected to the first gate driving unit, the source of the first thin film transistor is connected to the data line, the drain of the first thin film transistor is connected to the first end of the storage capacitor and the first input end of the enabling unit; the second end of the storage capacitor is connected to the ground voltage.

4. The black insertion circuit according to claim 3, characterized in that: The enabling unit includes a second thin film transistor; The gate of the second thin film transistor is connected to an enable signal, and the electrochromic material driving subcircuit is enabled under the action of the enable signal; the source of the second thin film transistor serves as the first input end of the enabling unit and is connected to the drain of the first thin film transistor; the drain of the second thin film transistor serves as the first output end of the enabling unit and is connected to the electrochromic material driving subcircuit.

5. The black line insertion circuit according to claim 4, characterized in that: The enabling unit further includes a third thin film transistor; The gate of the third thin film transistor is connected to the drain of the second thin film transistor, the source of the third thin film transistor is connected to a reference voltage, and the drain of the third thin film transistor is connected to the electrochromic material driving sub-circuit.

6. The black line insertion circuit according to claim 2, characterized in that: The electrochromic material driving subcircuit comprises: a second gate driving unit, an electrochromic unit and an AND gate unit; The second gate driving unit is connected to the first input terminal of the electrochromic unit, the second input terminal of the electrochromic unit is connected to the output terminal of the AND gate unit; the AND gate unit is connected to the output terminal of the enabling unit; The second gate driving unit is used to output the second row scanning signal to the electrochromic unit; under the combined action of the second row scanning signal and the signal input at the output end of the AND gate unit, the electrochromic unit drives the electrochromic material of the target row to enter a low transmittance mode or restore a high transmittance mode.

7. The black line insertion circuit according to claim 6, characterized in that: The electrochromic unit comprises: a fourth thin film transistor, a fifth thin film transistor, a first capacitor and a row color changing module; the row color changing module is made of an electrochromic material; The gate of the fourth thin film transistor is connected to the second gate driving unit and the first end of the first capacitor, the source of the fourth thin film transistor is connected to the first power supply, the drain of the fourth thin film transistor is connected to the drain of the fifth thin film transistor and the first end of the row color changing module; the source of the fifth thin film transistor is connected to the ground voltage, and the gate of the fifth thin film transistor is connected to the output end of the AND gate unit; the second end of the first capacitor is connected to the gate closing voltage; the second end of the row color changing module is connected to the ground voltage.

8. The black line insertion circuit according to claim 7, characterized in that: include: The AND gate unit comprises: an AND gate module, a first resistor, a second resistor, a third resistor and a sixth thin film transistor; The first input end of the AND gate module is connected to the first end of the first resistor, the second input end of the AND gate module is connected to the first end of the second resistor and the source of the sixth thin film transistor, and the output end of the AND gate module is connected to the gate of the fifth thin film transistor; The second end of the first resistor is connected to the gate-on voltage; the second end of the second resistor is connected to the gate-off voltage; The gate of the sixth thin film transistor is connected to the first end of the third resistor and the output end of the pixel driving subcircuit, and the drain of the sixth thin film transistor is connected to the second end of the third resistor and the first row scanning signal of the next row pixel driving subcircuit.

9. A display panel, characterized in that: The display panel comprises the row black insertion circuit according to any one of claims 1 to 8.

10. A method for driving a row black insertion circuit, characterized in that: Applied to the row black insertion circuit according to any one of claims 1 to 8, the method comprising: Under the action of the first row scanning signal of the first gate driving unit, the pixel driving subcircuit drives the target pixel in the target row to refresh according to the data of the data line; Under the action of the second row scanning signal of the second gate driving unit, the electrochromic material driving sub-circuit drives the electrochromic material of the target row to enter the low transmittance mode N rows before the target pixel of the target row is refreshed, and restores the high transmittance mode M rows after the target pixel of the target row is refreshed; wherein, the electrochromic material is arranged between the backlight layer and the pixel.

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