Wafer-level chip and computing device

Abstract

The invention discloses a wafer level chip and a preparation method thereof. Belongs to the technical field of reconfigurable chips and comprises a wafer and a plurality of chips interconnected on the wafer. Wherein high-speed interface modules for realizing interconnection between chips are integrated on four sides of the chip; and the high-speed interface module of the chip is electrically connected with the metal wire in the specific area of the wafer so as to realize interconnection between the chips.

Description

Technical Field

[0001] The present invention relates to the technical field of computing chips, and more particularly, to a wafer-level chip and a computing device. Background Art

[0002] With the slowdown of Moore's Law, it has become increasingly difficult to increase the transistor density of a single chip. A single chip is restricted by the exposure limit of the lithography machine, so that the size of the chip obtained by a single exposure cannot be greater than 26mm x 33mm. In order to continuously improve the integration of a single chip, existing solutions include a 2.5D integration solution, that is, multiple dies are integrated on a silicon interposer to improve the integration of a single chip, and there is also a solution of integrating multiple dies on a packaging substrate. Disadvantages of the 2.5D silicon interposer solution: The physical size of a large chip is still difficult to exceed 4 times the photomask limit. Disadvantages of the multi-die integration solution on the packaging substrate: (1) There are limitations on the packaging size, and warping problems will occur when the size is too large; (2) The routing loss of high-speed signals on the packaging substrate is serious; (3) The power consumption is greater for the interconnection of the packaging substrate. Summary of the Invention

[0003] Aiming at the deficiencies of the prior art, the present invention provides a wafer-level chip and a computing device.

[0004] According to one aspect of the present invention, there is provided a wafer-level chip, including: a wafer and a plurality of chips interconnected on the wafer; wherein high-speed interface modules for realizing inter-chip interconnection are integrated on four sides of the chips; and the high-speed interface modules of the chips are electrically connected to the metal lines in a specific area of the wafer to realize inter-chip interconnection.

[0005] Optionally, the specific area of the wafer is a dicing channel area.

[0006] Optionally, the metal line ports in the specific area of the wafer are exposed on the surface of the wafer interconnected with a plurality of chips.

[0007] Optionally, the metal line ports in the specific area of the wafer are exposed in the dicing channel area of the wafer.

[0008] Optionally, the metal lines in the specific area of the wafer are formed by semiconductor back-end processes.

[0009] Optionally, the plurality of chips are fabricated on the wafer by semiconductor processing methods.

[0010] Optionally, the plurality of chips are stacked and interconnected on the wafer.

[0011] Optionally, the high-speed interface modules of the chips and the metal lines in the specific area of the wafer are electrically connected by using hybrid bonding technology; or,

[0012] The high-speed interface module of the chip is electrically connected to the metal wires in a specific area of the wafer using micro-bump technology.

[0013] Optionally, multiple chips are reconfigurable chips.

[0014] According to another aspect of the present invention, there is provided a computing device including the wafer-level chip described in the above aspect of the present invention.

[0015] Thus, the present invention solves the problems of limited single-chip integration and size by interconnecting multiple chips on a wafer, integrating high-speed interface IP for interconnecting reconfigurable chips on four sides of the chips, and electrically connecting the high-speed interface module of the chips to the metal wires in a specific area of the wafer, realizing ultra-large-scale chips at the wafer level; solving the problems of power consumption, latency, and bandwidth in the interconnection part of large-scale computing power systems; and solving the problem of large physical space occupied by large-scale computing power systems. Description of the Drawings

[0016] By referring to the following drawings, the exemplary embodiments of the present invention can be more fully understood:

[0017] Figure 1 is a schematic structural diagram of a wafer-level chip provided by an exemplary embodiment of the present invention. Detailed Embodiments

[0018] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments of the present invention. It should be understood that the present invention is not limited by the exemplary embodiments described herein.

[0019] It should be noted that: unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present invention.

[0020] Those skilled in the art can understand that terms such as "first" and "second" in the embodiments of the present invention are only used to distinguish different steps, devices, or modules, etc., and do not represent any specific technical meaning, nor do they indicate an inevitable logical order between them.

[0021] It should also be understood that in the embodiments of the present invention, "a plurality of" may refer to two or more, and "at least one" may refer to one, two, or more.

[0022] It should also be understood that for any component, data, or structure mentioned in the embodiments of the present invention, without clear limitation or contrary indication in the context, it can generally be understood as one or more.

[0023] In addition, the term "and / or" in the present invention merely describes the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in the present invention generally represents an "or" relationship between the associated objects before and after.

[0024] It should also be understood that the present invention emphasizes the differences between various embodiments in the description of each embodiment. The same or similar parts can be referred to each other. For the sake of brevity, they will not be described one by one.

[0025] Meanwhile, it should be understood that for the convenience of description, the dimensions of each part shown in the drawings are not drawn according to the actual proportional relationship.

[0026] The following description of at least one exemplary embodiment is actually merely illustrative and in no way restricts the present invention and its application or use.

[0027] Techniques, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the techniques, methods, and devices should be regarded as part of the specification.

[0028] It should be noted that similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0029] The wafer-level chip provided in the first aspect of the embodiments of the present invention. Taking the reconfigurable chip as an example, refer to Figure 1 As shown, the wafer-level chip includes: a wafer and a plurality of reconfigurable chips interconnected on the wafer; wherein, high-speed interface modules for realizing the interconnection of reconfigurable chips (D2D) are integrated on four sides of the reconfigurable chips; the high-speed interface modules of the reconfigurable chips are electrically connected to the metal wires in a specific area of the wafer to realize the interconnection of reconfigurable chips. It should be noted that the wafer-level chip provided in the embodiments of the present invention is not only applicable to reconfigurable chips, but also applicable to other types of chips, such as GPU chips, GPGPU chips, TPU chips, and so on.

[0030] The wafer-level chip described in the embodiments of the present invention refers to a chip with wafer-level dimensions. Specifically, the chips are interconnected on an uncut or partially cut wafer to realize a wafer-level chip with a size close to that of the complete wafer, solving the problems of limited single-chip integration and size, improving the integration degree, and realizing ultra-large-scale chips at the wafer level; and solving the problems of power consumption, latency, and bandwidth of the interconnection part of the large-scale computing power system, reducing the system energy consumption; in addition, it also solves the problem of large physical space occupied by the large-scale computing power system.

[0031] In one embodiment of the present invention, the above-mentioned multiple chips are prepared on a wafer, and interconnection channels between chips are set in the scribe line area of ​​the wafer, so that adjacent chips on the wafer can be interconnected across the scribe line. Then, in this embodiment, the above-mentioned specific area of ​​the wafer refers to the scribe line area of ​​the wafer, such as Figure 1 As shown, metal wires can be formed in the dicing area through semiconductor back-end processes as interconnection channels between chips. Adjacent chips are interconnected through metal wires deployed in the dicing area between the dies on the wafer, and multiple reconfigurable chips can be directly interconnected on the uncut wafer, significantly improving the computing power density.

[0032] Taking the reconfigurable chip as an example, the preparation process of the wafer-level chip can also be:

[0033] 1) Design a single reconfigurable chip, whose core computing unit is a reconfigurable computing unit, and the four sides of the chip (east, south, west, and north) are integrated with high-speed interface modules for die-to-die interconnection;

[0034] 2) Through the semiconductor processing process, the reconfigurable chip is prepared on the wafer, and the chips are interconnected through dicing lanes;

[0035] 3) The complete wafer is placed directly on a specific packaging substrate without being cut to form a whole wafer-level chip.

[0036] In addition, after the wafer is cut, the reconfigurable grain dies with quantitative screening functions can be stacked on the wafer to improve the quality of the wafer.

[0037] In another embodiment of the present invention, the designed reconfigurable chip is prepared on a wafer by a semiconductor processing method, such as Figure 1 As shown, the four sides of the reconfigurable chip, namely the southeast, northwest, and northeast, inherit the high-speed interface IP for die-to-die interconnection. After the prepared wafer is cut, each reconfigurable grain die is tested to screen out defective grains. A plurality of metal wires are processed by semiconductors in a specific area on the silicon interposer wafer, wherein the metal wire ports are exposed to the top layer of the wafer, and the selected reconfigurable grain dies with good performance are stacked on the metal wires for interconnection through hybrid bonding technology or micro-bump technology, so as to realize the interconnection between the die2die interface of adjacent reconfigurable grain dies and the metal wires of the silicon interposer, and then realize the interconnection between adjacent reconfigurable grain dies and reconfigurable grain dies. The reconfigurable grain dies are spread all over the silicon interposer wafer to form a silicon interposer wafer. Thus, by cutting the initial reconfigurable chip and testing each reconfigurable grain die separately, defective reconfigurable grains are screened out, and a set of reconfigurable grains with good functions are obtained, and then stacked again to obtain a wafer-level chip, thereby improving the quality of the wafer-level chip.

[0038] Taking a reconfigurable chip as an example, the preparation process of a silicon interposer at the wafer level is as follows:

[0039] 1) Design a single reconfigurable chip, whose core computing unit is a reconfigurable computing unit, and high-speed interface modules for die-to-die interconnection are integrated on the four sides of the chip (east, south, west, and north);

[0040] 2) Through the semiconductor processing process, the designed chip is fabricated on a wafer to form a wafer-level chip;

[0041] 3) Cut the wafer to obtain discrete reconfigurable dies;

[0042] 4) Use testing means to screen out reconfigurable dies with manufacturing defects to obtain reconfigurable dies with good functionality;

[0043] 5) Prepare a silicon interposer wafer, and form multiple metal lines in specific areas on the silicon interposer wafer using semiconductor back-end processes, with the ports of the metal lines exposed on the top layer of the wafer;

[0044] 6) Stack and interconnect the screened reconfigurable dies on one of the above-mentioned silicon interposer wafers. Through hybrid bonding technology or micro-bump technology, the die-to-die interfaces of adjacent reconfigurable dies are interconnected with the metal lines of the silicon interposer, thereby realizing the interconnection between adjacent reconfigurable dies;

[0045] 7) The reconfigurable dies cover the silicon interposer wafer to form a silicon interposer wafer chip with a wafer-level size.

[0046] Thus, by cutting the initial reconfigurable chip and testing each reconfigurable die separately, screening out defective reconfigurable dies, and then re-stacking the obtained set of reconfigurable dies with good functionality to obtain a wafer-level chip, the quality of the wafer-level chip is improved.

[0047] In addition, the wafer can also be directly placed on the packaging substrate of a specific silicon interposer wafer without cutting to form a whole wafer-level silicon interposer wafer chip.

[0048] Thus, through the preparation method of the wafer-level chip proposed by the present invention, by interconnecting multiple reconfigurable chips on a wafer, and high-speed interface IPs for realizing the interconnection between reconfigurable chips are integrated on the four sides of the reconfigurable chips, the problems of limited single-chip integration and size are solved, and a wafer-level ultra-large-scale chip is realized; the problems of power consumption, latency, and bandwidth in the interconnection part of a large-scale computing power system are solved; the problem of large physical space occupied by a large-scale computing power system is solved.

[0049] The second aspect of the present invention provides a computing device, including the wafer-level chip described in the first aspect of the present invention.

[0050] In one embodiment of the present invention, applying the wafer-level chip of the present invention in a computing device can achieve a great improvement in computing power density. The product form of the computing device can be, but is not limited to, a server, such as an AI server. For an AI server applying the wafer-level chip of the present invention, the computing power of a single server can reach more than 20 PFLOP, which is equivalent to 5 to 8 current mainstream eight-graphics-card servers in the market, and the computing power density is greatly improved. Therefore, it can significantly reduce the occupied space and energy consumption of a large-scale computing system.

[0051] The foregoing description has been presented for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of the present invention to the form disclosed herein. Although several example aspects and embodiments have been discussed above, those skilled in the art will recognize some of their variations, modifications, alterations, additions, and sub-combinations.

Claims

1. A wafer-level chip, characterized in that: include: A wafer and a plurality of chips interconnected on the wafer; wherein the four sides of the chip are integrated with high-speed interface modules for interconnecting the chips; the high-speed interface modules of the chips are electrically connected to metal wires in a specific area of ​​the wafer to interconnect the chips.

2. The wafer-level chip according to claim 1, characterized in that: The specific area of ​​the wafer is a scribe line area.

3. The wafer-level chip according to claim 1, characterized in that: The metal line ports in the specific area of ​​the wafer are exposed to the surface of the wafer where the multiple chips are interconnected.

4. The wafer-level chip according to claim 3, characterized in that: The metal line ports in the specific area of ​​the wafer are exposed to the dicing street area of ​​the wafer.

5. The wafer-level chip according to claim 1, characterized in that: The metal lines in the specific area of ​​the wafer are formed by a semiconductor back-end process.

6. The wafer-level chip according to claim 1, characterized in that: The plurality of chips are prepared on the wafer by semiconductor processing.

7. The wafer-level chip according to claim 1, characterized in that: A plurality of the chips are stacked and interconnected on the wafer.

8. The wafer-level chip according to claim 7, characterized in that: The high-speed interface module of the chip is electrically connected to the metal wires in the specific area of ​​the wafer by using hybrid bonding technology; or, The high-speed interface module of the chip and the metal wires in the specific area of ​​the wafer are electrically connected by using micro-bump technology.

9. The wafer-level chip according to any one of claims 1 to 8, characterized in that: The multiple chips are reconfigurable chips.

10. A computing device, characterized in that A wafer-level chip comprising any one of claims 1 to 9.

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