Test structure, test method and test structure layout

Abstract

The invention discloses a test structure, a test method and a test structure layout. The test structure comprises a substrate; the first interconnection layer is arranged above the substrate and comprises a first sub-interconnection layer, a second sub-interconnection layer and a third sub-interconnection layer which is arranged adjacent to the second sub-interconnection layer; the second interconnection layer is arranged above the first interconnection layer and comprises a first signal line, a second signal line and a test line; the interconnection through hole structure is located between the first interconnection layer and the second interconnection layer and comprises a first interconnection through hole structure and a second interconnection through hole structure, the first interconnection through hole structure is electrically connected with the first sub-interconnection layer and the test line, and the second interconnection through hole structure is electrically connected with the second sub-interconnection layer and the test line; the first interconnection through hole structure electrically connected with the second sub-interconnection layer deviates towards one side of the third sub-interconnection layer, and the second interconnection through hole structure is electrically connected with the first sub-interconnection layer and the first signal line and is electrically connected with the third sub-interconnection layer and the second signal line. According to the embodiment of the invention, the reliability of the test result is improved, and the reliability of the test structure is further improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a test structure, a test method, and a test structure layout. Background Art

[0002] With the rapid development of the semiconductor integrated circuit (IC) industry, semiconductor technology has continuously advanced towards smaller process nodes driven by Moore's law, enabling integrated circuits to develop in the direction of smaller volume, higher circuit precision, and higher circuit complexity.

[0003] Affected by factors such as processing technology, defective chips will be produced during the chip manufacturing process. In order to improve the yield of chip manufacturing and reduce the manufacturing cost, the chips will be tested at different stages, and based on the test results, understand the impact of the process on the chip yield, so as to adjust the process during the subsequent batch processing to improve the yield of the chips in the subsequent processing.

[0004] However, the performance of the current test structure still needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a test structure, a test method, and a test structure layout to improve the performance of the test structure.

[0006] To solve the above problem, an embodiment of the present invention provides a test structure, including: a substrate; a first interconnect layer, separately disposed above the substrate, the first interconnect layer extending in a first direction and arranged at intervals in a second direction, the first direction being perpendicular to the second direction, the first interconnect layer including a first sub-interconnect layer, a second sub-interconnect layer, and a third sub-interconnect layer, the third sub-interconnect layer being adjacent to the second sub-interconnect layer; a second interconnect layer, separately disposed above the first interconnect layer, the second interconnect layer extending in the second direction and arranged at intervals in the first direction, the second interconnect layer including a first signal line, a second signal line, and a test line; an interconnect via structure, located between the first interconnect layer and the second interconnect layer, the interconnect via structure including a first interconnect via structure and a second interconnect via structure, the first interconnect via structure electrically connecting the first sub-interconnect layer and the test line, and electrically connecting the second sub-interconnect layer and the test line, and the first interconnect via structure electrically connecting the second sub-interconnect layer is offset towards the third sub-interconnect layer side in the second direction, the second interconnect via structure electrically connecting the first sub-interconnect layer and the first signal line, and electrically connecting the third sub-interconnect layer and the second signal line.

[0007] Optionally, the first through - connection hole structures connecting the same test line form a first group of through - connection hole structures, and the first through - connection hole structure that electrically connects the second sub - interconnect layer and the test line in the first group of through - connection hole structures is an offset through - connection hole structure. The number of the first groups of through - connection hole structures is multiple. The absolute values of the offsets of the offset through - connection hole structures in different first groups of through - connection hole structures are the same, and the offset directions are opposite or the same.

[0008] Optionally, the first group of through - connection hole structures includes a first offset group and a second offset group, and the offset directions of the offset through - connection hole structures in the first offset group and the second offset group are opposite.

[0009] Optionally, the number of both the first offset group and the second offset group is multiple.

[0010] Optionally, in each first group of through - connection hole structures, the first through - connection hole structure that electrically connects the first sub - interconnect layer and the test line is the reference through - connection hole structure of each first group of through - connection hole structures; the reference through - connection hole structures connecting the same first sub - interconnect layer in different first groups of through - connection hole structures are arranged along the first direction; the offset through - connection hole structures connecting the same second sub - interconnect layer in different first groups of through - connection hole structures are arranged along the first direction, and the offset through - connection hole structures electrically connecting the same second sub - interconnect layer have opposite offset directions.

[0011] Optionally, the first through - connection hole structures connecting the same test line form a first group of through - connection hole structures, and the first through - connection hole structure that electrically connects the second sub - interconnect layer and the test line in the first group of through - connection hole structures is an offset through - connection hole structure; the absolute values of the offsets of the offset through - connection hole structures in the same first group of through - connection hole structures are the same.

[0012] Optionally, the test structures are located on the same wafer and the number is multiple. In different test structures, the absolute values of the offsets of the first through - connection hole structures electrically connecting the second sub - interconnect layer are all different.

[0013] Optionally, the first interconnect layer includes an alternately arranged first layout interconnect layer and a second layout interconnect layer; in the adjacent second sub - interconnect layer and third sub - interconnect layer, when the second sub - interconnect layer is the first layout interconnect layer, the third sub - interconnect layer is the second layout interconnect layer; when the second sub - interconnect layer is the second layout interconnect layer, the third sub - interconnect layer is the first layout interconnect layer.

[0014] Correspondingly, an embodiment of the present invention further provides a testing method, which is suitable for being tested by using the testing structure provided by the embodiment of the present invention. The testing method includes: applying a first test signal to a first signal line and a second test signal to a second signal line; detecting an electrical parameter value output by the second signal line, where the electrical parameter value is used to determine whether there is a short circuit between a first through-hole structure for electrically connecting the second sub-interconnection layer and the test line and the third sub-interconnection layer.

[0015] Optionally, the first test signal is a high potential, the second test signal is a zero potential, and the electrical parameter value is a current value.

[0016] Optionally, the method for determining whether there is a short circuit between the first through-hole structure for electrically connecting the second sub-interconnection layer and the test line and the third sub-interconnection layer through the electrical parameter value includes: determining whether the electrical parameter value is greater than a preset electrical parameter value. If so, it is determined that there is a short circuit between the first through-hole structure for electrically connecting the second sub-interconnection layer and the test line and the third sub-interconnection layer; otherwise, it is determined that there is no short circuit between the first through-hole structure for electrically connecting the second sub-interconnection layer and the test line and the third sub-interconnection layer.

[0017] Correspondingly, an embodiment of the present invention further provides a layout of a testing structure, including: a first interconnection layout layer, where the first interconnection layout layer includes discrete first interconnection patterns. The first interconnection patterns extend along a first direction and are arranged at intervals along a second direction. The first direction is perpendicular to the second direction. The first interconnection patterns include a first sub-interconnection pattern, a second sub-interconnection pattern, and a third sub-interconnection pattern. The third sub-interconnection pattern is arranged adjacent to the second sub-interconnection pattern; a second interconnection layout layer, located above the first interconnection layout layer. The second interconnection layout layer includes discrete second interconnection patterns. The second interconnection patterns extend along the second direction and are arranged at intervals along the first direction. The second interconnection patterns include a first signal line pattern, a second signal line pattern, and a test line pattern; a through-hole interconnection layout layer, located between the first interconnection layout layer and the second interconnection layout layer. The through-hole interconnection layout layer includes a first through-hole pattern and a second through-hole pattern. The first through-hole pattern is respectively located on the first sub-interconnection pattern and the second sub-interconnection pattern and is covered by the test line pattern. The first through-hole pattern located on the second sub-interconnection pattern is offset along the second direction toward the side of the third sub-interconnection pattern. The second through-hole pattern is located on the first sub-interconnection pattern and is covered by the first signal line pattern, and is located on the third sub-interconnection pattern and is covered by the second signal line pattern.

[0018] Optionally, the first mutually connected via patterns covered by the same test line pattern form a first group of mutually connected via patterns. The first mutually connected via patterns located on the second sub-interconnection pattern and covered by the test line pattern are offset mutually connected via patterns. The number of the first groups of mutually connected via patterns is multiple. The absolute values of the offsets of the offset mutually connected via patterns in different first groups of mutually connected via patterns are the same, and the offset directions are opposite or the same.

[0019] Optionally, the first group of mutually connected via patterns includes a first offset pattern group and a second offset pattern group. The offset directions of the offset mutually connected via patterns in the first offset pattern group and the second offset pattern group are opposite.

[0020] Optionally, the number of both the first offset pattern group and the second offset pattern group is multiple.

[0021] Optionally, in each first group of mutually connected via patterns, the first mutually connected via patterns located on the first sub-interconnection pattern and covered by the test line pattern are the reference mutually connected via patterns of each first group of mutually connected via patterns; the reference mutually connected via patterns located on the same first sub-interconnection pattern in different first groups of mutually connected via patterns are arranged along the first direction; the offset mutually connected via patterns located on the same second sub-interconnection pattern in different first groups of mutually connected via patterns are arranged along the first direction, and the offset mutually connected via patterns located on the same second sub-interconnection pattern have opposite offset directions.

[0022] Optionally, the first mutually connected via patterns covered by the same test line pattern form a first group of mutually connected via patterns. The first mutually connected via patterns located on the second sub-interconnection pattern and covered by the test line pattern are offset mutually connected via patterns; the absolute values of the offsets of the offset mutually connected via patterns in the same first group of mutually connected via patterns are the same.

[0023] Optionally, the test structure layout is located in the same wafer mask layout and the number is multiple. In different test structure layouts, the absolute values of the offsets of the first mutually connected via patterns located on the second sub-interconnection pattern are all different.

[0024] Optionally, the first interconnect plate layer includes a first sub-plate layer and a second sub-plate layer. The first interconnect pattern in the first sub-plate layer serves as the first layout interconnect layer pattern, and the first interconnect pattern in the second sub-plate layer serves as the second layout interconnect layer pattern. After the first sub-plate layer and the second sub-plate layer are stacked, the first layout interconnect layer patterns and the second layout interconnect layer patterns are alternately arranged. Among the adjacent second sub-interconnect patterns and third sub-interconnect patterns, when the second sub-interconnect pattern is the first layout interconnect layer pattern, the third sub-interconnect pattern is the second layout interconnect layer pattern; when the second sub-interconnect pattern is the second layout interconnect layer pattern, the third sub-interconnect pattern is the first layout interconnect layer pattern.

[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0026] The test structure provided by the embodiment of the present invention includes an interconnection via structure. The interconnection via structure includes a first interconnection via structure and a second interconnection via structure. The first interconnection via structure electrically connects the first sub-interconnect layer and the test line, and electrically connects the second sub-interconnect layer and the test line. And the first interconnection via structure electrically connecting the second sub-interconnect layer is offset toward the third sub-interconnect layer side along the second direction. The second interconnection via structure electrically connects the first sub-interconnect layer and the first signal line, and electrically connects the third sub-interconnect layer and the second signal line. By providing the first interconnection via structure electrically connected to the first sub-interconnect layer, it is ensured that the first signal line can be electrically connected to the first interconnection via structure electrically connected to the second sub-interconnect layer, without being affected by the offset of the first interconnection via structure electrically connected to the second sub-interconnect layer. Since the first interconnection via structure electrically connected to the first sub-interconnect layer and the first interconnection via structure electrically connected to the second sub-interconnect layer are electrically connected to the same test line, even if the first interconnection via structure electrically connected to the second sub-interconnect layer is disconnected from the second sub-interconnect layer due to offset in the second direction, the first signal line can still be electrically connected to the offset first interconnection via structure, forming a test path from the first signal line to the offset first interconnection via structure, ensuring that the electrical parameter value output by the second signal line can reflect the short-circuit condition between the first interconnection via structure electrically connected to the second sub-interconnect layer and the third sub-interconnect layer, thereby improving the reliability of the test result, and further improving the reliability of the test structure.

[0027] In an alternative embodiment, the first group of mutually connected via structures includes a first offset group and a second offset group. The offset directions of the offset mutually connected via structures in the first offset group and the second offset group are opposite, such that in the same test structure, the offset mutually connected via structures have opposite offset directions. That is to say, the offset mutually connected via structures with different offset directions can be located in the same test structure, which is convenient for reducing the area of the test structure. Moreover, test signals can be loaded onto the first signal line and each second signal line end simultaneously, enabling each second signal line to output respective electrical parameter values simultaneously, which is conducive to improving the test efficiency. Correspondingly, the production efficiency of the semiconductor structure and the growth of the wafer per hour (WPH) are also achieved.

[0028] In an alternative embodiment, the reference mutually connected via structures of each first group of mutually connected via structures are arranged along the first direction and connected to the same first sub-interconnect layer. The offset mutually connected via structures of each first group of mutually connected via structures are arranged along the first direction and connected to the same second sub-interconnect layer. Among the offset mutually connected via structures electrically connected to the same second sub-interconnect layer, the offset directions are opposite, such that along the second direction, the third sub-interconnect layer is located on both sides of the second sub-interconnect layer. That is to say, in the offset mutually connected via structures electrically connected to the same second sub-interconnect layer, any short circuit situation between any offset mutually connected via structure and the third sub-interconnect layer on either side can be reflected by the electrical parameter values output by the second signal line. That is, the offset mutually connected via structures electrically connected to the same second sub-interconnect layer have the characteristic of mirror offset. Thus, process monitoring of overlay (OVL), critical dimension uniformity (CDU), etc. can be achieved electrically, making the correlation analysis of process fluctuations more accurate and reliable. Furthermore, it does not completely rely on failure analysis (FA) of slicing, correspondingly shortening the R & D and mass production cycles, saving costs, and improving efficiency. Moreover, the reference mutually connected via structures of each first group of mutually connected via structures are arranged along the first direction and connected to the same first sub-interconnect layer. The offset mutually connected via structures of each first group of mutually connected via structures are arranged along the first direction and connected to the same second sub-interconnect layer, which is also conducive to reducing the number of first signal lines and second signal lines, thus facilitating the simplification of the test structure and improving the robustness of the test structure to adapt to smaller process nodes.

[0029] The test method provided by an embodiment of the present invention is suitable for testing the test structure provided by the embodiment of the present invention, including loading a first test signal on a first signal line, loading a second test signal on a second signal line, and detecting the electrical parameter value output by the second signal line. Since a first via structure electrically connected to the first sub-interconnect layer is provided, it is ensured that the first test signal loaded on the first signal line can be transmitted to the first via structure electrically connected to the second sub-interconnect layer without being affected by the offset of the first via structure electrically connected to the second sub-interconnect layer. Moreover, the first via structure electrically connected to the first sub-interconnect layer and the first via structure electrically connected to the second sub-interconnect layer are electrically connected to the same test line, so that even if the first via structure electrically connected to the second sub-interconnect layer is disconnected from the second sub-interconnect layer due to an offset in the second direction, the first test signal loaded on the first signal line can still be transmitted to the offset first via structure, forming a test path from the first signal line to the offset first via structure, ensuring that the electrical parameter value output by the second signal line can reflect the short-circuit situation between the first via structure electrically connected to the second sub-interconnect layer and the third sub-interconnect layer, thereby improving the reliability of the test result and further improving the reliability of the test structure.

[0030] The layout of the test structure provided by the embodiment of the present invention includes: a first via contact pattern and a second via contact pattern. The first via contact pattern is respectively located on the first sub-interconnect pattern and the second sub-interconnect pattern and is covered by the test line pattern. The first via contact pattern located on the second sub-interconnect pattern is offset toward the third sub-interconnect pattern along the second direction. The second via contact pattern is located on the first sub-interconnect pattern and is covered by the first signal line pattern, and is located on the third sub-interconnect pattern and is covered by the second signal line pattern. By providing the first via contact pattern located on the first sub-interconnect pattern, it is ensured that the first signal line pattern can be connected in series with the first via contact pattern on the second sub-interconnect pattern without being affected by the offset of the first via contact pattern on the second sub-interconnect pattern. Since the first via contact pattern located on the first sub-interconnect pattern and the first via contact pattern located on the second sub-interconnect pattern are covered by the same test line pattern, even if the first via contact pattern located on the second sub-interconnect pattern is not covered by the second sub-interconnect pattern due to offset in the second direction, a series connection can still be formed from the first signal line pattern to the first via contact pattern located on the second sub-interconnect pattern, constituting a series connection path from the first signal line pattern to the first via contact pattern located on the second sub-interconnect pattern, ensuring that the electrical parameter value output by the second signal line can reflect the short-circuit situation between the first via contact structure connecting the second sub-interconnect layer and the third sub-interconnect layer, thereby improving the reliability of the test result, and further improving the reliability of the test structure formed by the layout of the test structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a schematic structural diagram of a test structure;

[0032] Figure 2 is a schematic structural diagram of an embodiment of the test structure of the present invention;

[0033] Figure 3 is a schematic flow diagram corresponding to an embodiment of the test method of the present invention;

[0034] Figure 4 is the layout of the test structure of the present invention Figure 1 schematic diagram of an embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0035] Currently, the performance of the test structure still needs to be improved. In combination with a test structure, the reasons for the performance of the test structure to be improved are analyzed. Figure 1 is a schematic structural diagram of a test structure.

[0036] Reference Figure 1, the test structure includes: a substrate 10; a first interconnect layer 20, separately disposed above the substrate 10, the first interconnect layer 20 extending along a first direction x' and spaced apart along a second direction y', the first direction x' being perpendicular to the second direction y', the first interconnect layer 20 including a first sub-interconnect layer 21 and a second sub-interconnect layer 22, the second sub-interconnect layer 22 being disposed adjacent to the first sub-interconnect layer 21; a second interconnect layer 40, separately disposed above the first interconnect layer 20, the second interconnect layer 40 extending along the second direction y' and spaced apart along the first direction x', the second interconnect layer 40 including a first signal line 41, a second signal line 42, and a test line 43; an interconnect via structure 30, located between the first interconnect layer 20 and the second interconnect layer 40, the interconnect via structure 30 including a first interconnect via structure 31 and a second interconnect via structure 32, the first interconnect via structure 31 electrically connecting the first sub-interconnect layer 21 and the test line 43 and offsetting toward the second sub-interconnect layer 22 along the second direction y', the second interconnect via structure 32 electrically connecting the first sub-interconnect layer 21 and the first signal line 41 and electrically connecting the second sub-interconnect layer 22 and the second signal line 42.

[0037] It has been found through research that when the first interconnect via structure 31 offsets toward the second sub-interconnect layer 22 along the second direction y', that is, along the arrow direction, if the first interconnect via structure 31 is disconnected from the first sub-interconnect layer 21, then a test path cannot be formed from the first signal line 41 to the first interconnect via structure 31, correspondingly making the electrical parameter value output by the second signal line 42 unable to reflect whether there is a short circuit between the first interconnect via structure 31 and the second sub-interconnect layer 22, thus affecting the reliability of the test result, and further making the reliability of the test structure to be improved.

[0038] To solve the above technical problems, an embodiment of the present invention provides a test structure, including: a substrate; a first interconnect layer, separately disposed above the substrate, the first interconnect layer extending in a first direction and arranged at intervals in a second direction, the first direction being perpendicular to the second direction, the first interconnect layer including a first sub-interconnect layer, a second sub-interconnect layer, and a third sub-interconnect layer, the third sub-interconnect layer being disposed adjacent to the second sub-interconnect layer; a second interconnect layer, separately disposed above the first interconnect layer, the second interconnect layer extending in the second direction and arranged at intervals in the first direction, the second interconnect layer including a first signal line, a second signal line, and a test line; an interconnection via structure, located between the first interconnect layer and the second interconnect layer, the interconnection via structure including a first interconnection via structure and a second interconnection via structure, the first interconnection via structure electrically connecting the first sub-interconnect layer and the test line, and electrically connecting the second sub-interconnect layer and the test line, and the first interconnection via structure electrically connecting the second sub-interconnect layer being offset toward the third sub-interconnect layer side in the second direction, the second interconnection via structure electrically connecting the first sub-interconnect layer and the first signal line, and electrically connecting the third sub-interconnect layer and the second signal line.

[0039] The test structure provided by the embodiment of the present invention includes an interconnection via structure, the interconnection via structure including a first interconnection via structure and a second interconnection via structure, the first interconnection via structure electrically connecting the first sub-interconnect layer and the test line, and electrically connecting the second sub-interconnect layer and the test line, and the first interconnection via structure electrically connecting the second sub-interconnect layer being offset toward the third sub-interconnect layer side in the second direction, the second interconnection via structure electrically connecting the first sub-interconnect layer and the first signal line, and electrically connecting the third sub-interconnect layer and the second signal line. By providing the first interconnection via structure electrically connected to the first sub-interconnect layer, it is ensured that the first signal line can be electrically connected to the first interconnection via structure electrically connected to the second sub-interconnect layer, without being affected by the offset of the first interconnection via structure electrically connected to the second sub-interconnect layer. Since the first interconnection via structure electrically connected to the first sub-interconnect layer and the first interconnection via structure electrically connected to the second sub-interconnect layer are electrically connected to the same test line, even if the first interconnection via structure electrically connected to the second sub-interconnect layer is disconnected from the second sub-interconnect layer due to the offset in the second direction, the first signal line can still be electrically connected to the offset first interconnection via structure, forming a test path from the first signal line to the offset first interconnection via structure, ensuring that the electrical parameter value output by the second signal line can reflect the short-circuit situation between the first interconnection via structure electrically connected to the second sub-interconnect layer and the third sub-interconnect layer, thereby improving the reliability of the test result, and further improving the reliability of the test structure.

[0040] In order to make the above objects, features, and advantages of the embodiments of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0041] Figure 2 It is a schematic structural diagram of an embodiment of the test structure of the present invention.

[0042] Referring to Figure 2 , in this embodiment, the test structure includes: a substrate 100; a first interconnect layer 110, separately disposed above the substrate 100, the first interconnect layer 110 extending along a first direction x and arranged at intervals along a second direction y, the first direction x being perpendicular to the second direction y, the first interconnect layer 110 including a first sub-interconnect layer 111, a second sub-interconnect layer 112, and a third sub-interconnect layer 113, the third sub-interconnect layer 113 being disposed adjacent to the second sub-interconnect layer 112; a second interconnect layer 130, separately disposed above the first interconnect layer 110, the second interconnect layer 130 extending along the second direction y and arranged at intervals along the first direction x, the second interconnect layer 130 including a first signal line 131, a second signal line 132, and a test line 133; an interconnection via structure 120, located between the first interconnect layer 110 and the second interconnect layer 130, the interconnection via structure 120 including a first interconnection via structure 121 and a second interconnection via structure 122, the first interconnection via structure 121 electrically connecting the first sub-interconnect layer 111 and the test line 133, and electrically connecting the second sub-interconnect layer 112 and the test line 133, and the first interconnection via structure 121 electrically connecting the second sub-interconnect layer 112 being offset toward the third sub-interconnect layer 113 along the second direction x, the second interconnection via structure 122 electrically connecting the first sub-interconnect layer 111 and the first signal line 131, and electrically connecting the third sub-interconnect layer 113 and the second signal line 132.

[0043] The substrate 100 is used to provide a process platform for the formation of the test structure.

[0044] In this embodiment, the substrate 100 is used to form a field effect transistor.

[0045] The substrate 100 includes a substrate (not labeled), and the material of the substrate can be silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, indium gallium, or other materials, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate or other types of substrates.

[0046] It should be noted that the substrate can be a planar substrate or a substrate with a channel protrusion.

[0047] In this embodiment, according to the actual process conditions, functional structures may be formed within the substrate 100. For example, semiconductor devices such as MOS field effect transistors may be formed within the substrate 100, and a resistance structure may also be formed. In other embodiments, at least one interlayer metal structure (i.e., Mx layer) may also be formed within the substrate, and the interlayer metal structure may have the same structure as the first interconnect layer 110.

[0048] The first interconnect layer 110 is used to electrically lead out each device or achieve electrical connection between devices.

[0049] In this embodiment, the material of the first interconnect layer 110 includes conductive materials such as copper, aluminum, or titanium.

[0050] In this embodiment, the first interconnect layer 110 includes an alternately arranged first layout interconnect layer ca and a second layout interconnect layer cb; in the adjacent second sub-interconnect layer 112 and third sub-interconnect layer 113, when the second sub-interconnect layer 112 is the first layout interconnect layer ca, the third sub-interconnect layer 113 is the second layout interconnect layer cb; when the second sub-interconnect layer 112 is the second layout interconnect layer cb, the third sub-interconnect layer 113 is the first layout interconnect layer ca.

[0051] The first interconnect layer 110 includes an alternately arranged first layout interconnect layer ca and a second layout interconnect layer cb. It can be understood that the first layout interconnect layer ca and the second layout interconnect layer cb are formed by different first interconnect layout layers, which is beneficial to reducing the distance between adjacent first interconnect layers 110 and increasing the pattern density of the first interconnect layer 110.

[0052] Moreover, in the adjacent second sub-interconnect layer 112 and third sub-interconnect layer 113, when the second sub-interconnect layer 112 is the first layout interconnect layer ca, the third sub-interconnect layer 113 is the second layout interconnect layer cb; when the second sub-interconnect layer 112 is the second layout interconnect layer cb, the third sub-interconnect layer 113 is the first layout interconnect layer ca, which is beneficial to determining whether there is a short circuit between the first through-via structure 121 electrically connecting the first layout interconnect layer ca and the third sub-interconnect layer 113 of the second layout interconnect layer cb, and determining whether there is a short circuit between the first through-via structure 121 electrically connecting the second layout interconnect layer cb and the third sub-interconnect layer 113 of the first layout interconnect layer ca.

[0053] The second interconnect layer 130 is used to electrically connect with the first interconnect layer 110.

[0054] The first signal line 131 is used for electrically connecting with the first sub-interconnect layer 111, and a first test signal is loaded on the first signal line 131; the second signal line 132 is used for electrically connecting with the third sub-interconnect layer 113, and a second test signal is loaded on the second signal line 132; the test line 133 is used for electrically connecting with the first sub-interconnect layer 111 and the second sub-interconnect layer 112.

[0055] The second interconnect layer 130 and the first interconnect layer 110 are electrically connected through the interconnect via structure 120.

[0056] As an example, the first interconnect layer 110 is a metal line of a certain layer, that is, Mn, and the second interconnect layer 130 is a metal line on the upper layer of this metal line, that is, Mn + 1.

[0057] By setting the first interconnect via structure 121 electrically connected to the first sub-interconnect layer 111, it is ensured that the first signal line 131 can be electrically connected to the first interconnect via structure 121 electrically connecting the second sub-interconnect layer 112, without being affected by the offset of the first interconnect via structure 121 electrically connecting the second sub-interconnect layer 112. Since the first interconnect via structure 121 electrically connecting the first sub-interconnect layer 111 and the first interconnect via structure 121 electrically connecting the second sub-interconnect layer 112 are electrically connected to the same test line 133, even if the first interconnect via structure 121 electrically connecting the second sub-interconnect layer 112 is offset in the second direction y and disconnected from the second sub-interconnect layer 112, the first signal line 131 can still be electrically connected to the offset first interconnect via structure 121, forming a test path from the first signal line 131 to the offset first interconnect via structure 121, ensuring that the electrical parameter value output by the second signal line 132 can reflect the short-circuit situation between the first interconnect via structure 121 electrically connecting the second sub-interconnect layer 112 and the third sub-interconnect layer 113, thereby improving the reliability of the test result, and further improving the reliability of the test structure.

[0058] Specifically, the material of the interconnect via structure 120 is a conductive material, such as copper, aluminum, etc.

[0059] In this embodiment, the first interconnect via structures 121 connected to the same test line 133 form a first interconnect via structure group 1210, and the first interconnect via structure 121 electrically connecting the second sub-interconnect layer 112 and the test line 133 in the first interconnect via structure group 1210 is an offset interconnect via structure 1215, and the first interconnect via structure 121 electrically connecting the first sub-interconnect layer 111 and the test line 133 in the first interconnect via structure group 1210 is a reference interconnect via structure 1216.

[0060] In this embodiment, the absolute values of the offsets of the offset inter-connecting via structures 1215 in the same first inter-connecting via structure group 1210 are the same.

[0061] The absolute values of the offsets of the offset inter-connecting via structures 1215 in the same first inter-connecting via structure group 1210 are the same. That is to say, in the same first inter-connecting via structure group 1210, the number of the offset inter-connecting via structures 1215 is multiple, which is beneficial to increasing the number of the offset inter-connecting via structures 1215 with the same absolute value of the offset in the second direction y, so that any situation where an offset inter-connecting via structure 1215 is short-circuited with the third sub-interconnecting layer 113 due to process fluctuations can be reflected by the electrical parameter values output by the second signal line 132, thereby being beneficial to further improving the reliability of the test results.

[0062] In this embodiment, the number of the first inter-connecting via structure groups 1210 is multiple, and the absolute values of the offsets of the offset inter-connecting via structures 1215 in different first inter-connecting via structure groups 1210 are the same, and the offset directions are opposite or the same.

[0063] When the absolute values of the offsets of the offset inter-connecting via structures 1215 in different first inter-connecting via structure groups 1210 are the same and the offset directions are the same, that is, the number of the offset inter-connecting via structures 1215 with the same absolute value of the offset and the same offset direction in the first direction x is increased, so that any situation where an offset inter-connecting via structure 1215 is short-circuited with the third sub-interconnecting layer 113 due to process fluctuations can be reflected by the electrical parameter values output by the second signal line 132, thereby being beneficial to further improving the reliability of the test results.

[0064] When the absolute values of the offsets of the offset inter-connecting via structures 1215 in different first inter-connecting via structure groups 1210 are the same and the offset directions are opposite, that is, the offset inter-connecting via structures 1215 with the same absolute value of the offset and opposite offset directions are located in the same test structure. Not only can any situation where an offset inter-connecting via structure 1215 is short-circuited with the third sub-interconnecting layer 113 due to process fluctuations be reflected by the electrical parameter values output by the second signal line 132, but also it is beneficial to increasing the utilization rate of the test structure.

[0065] Specifically, the first inter-connecting via structure group includes a first offset group 1211 and a second offset group 1212, and the offset directions of the offset inter-connecting via structures 1215 in the first offset group 1211 and the second offset group 1212 are opposite.

[0066] Among them, the offset inter-connecting via structures 1215 in the first offset group 1211 and the second offset group 1212 are respectively the offset inter-connecting via structures 1215 in different first inter-connecting via structure groups 1210.

[0067] The first group of mutually connected via structures includes a first offset group 1211 and a second offset group 1212. The offset directions of the offset mutually connected via structures 1215 in the first offset group 1211 and the second offset group 1212 are opposite to each other, increasing the number of the offset mutually connected via structures 1215. Not only can any situation where an offset mutually connected via structure 1215 is short-circuited with the third sub-interconnect layer 113 due to process fluctuations be reflected by the electrical parameter values output by the second signal line 132, but also it is beneficial to make the offset mutually connected via structures have opposite offset directions in the same test structure. That is to say, the offset mutually connected via structures with different offset directions can be located in the same test structure, thereby facilitating the reduction of the area of the test structure. Moreover, test signals can be loaded on the first signal line 131 and each of the second signal lines 132 simultaneously, enabling each of the second signal lines 132 to output respective electrical parameter values simultaneously, which is beneficial to improving the test efficiency. Correspondingly, the production efficiency of the semiconductor structure and the wafer yield per hour are also increased.

[0068] More specifically, the number of both the first offset group 1211 and the second offset group 1212 is multiple.

[0069] The number of both the first offset group 1211 and the second offset group 1212 being multiple is beneficial to further increasing the number of the offset mutually connected via structures 1215 with the same offset vector length and direction in the first direction x, thereby being beneficial to further improving the reliability of the test results.

[0070] In this embodiment, in each of the first groups of mutually connected via structures 1210, the first mutually connected via structure 121 that electrically connects the first sub-interconnect layer 111 and the test line 133 is the reference mutually connected via structure 1216 of each of the first groups of mutually connected via structures 1210; the reference mutually connected via structures 1216 connecting the same first sub-interconnect layer 111 in different first groups of mutually connected via structures 1210 are arranged along the first direction x; the offset mutually connected via structures 1215 connecting the same second sub-interconnect layer 112 in different first groups of mutually connected via structures 1210 are arranged along the first direction x, and the offset mutually connected via structures 1215 connecting the same second sub-interconnect layer 112 have opposite offset directions.

[0071] The reference mutually connected via structures 1216 in different first groups of mutually connected via structures 1210 are arranged along the first direction x and connect the same first sub-interconnect layer 111, that is, the first signal line 131 is electrically connected to each of the reference mutually connected via structures 1216 through the same first sub-interconnect layer 111, which is beneficial to reducing the number of the first signal lines 131, thereby being beneficial to simplifying the test structure and improving the robustness of the test structure to adapt to smaller process nodes.

[0072] The offset inter-connecting vias 1215 in different first groups of inter-connecting via structures 1210 are arranged along the first direction x, and are connected to the same second sub-interconnecting layer 112. The offset directions of the offset inter-connecting vias 1215 that are electrically connected to the same second sub-interconnecting layer 112 are opposite, such that along the second direction y, the third sub-interconnecting layer 113 is located on both sides of the second sub-interconnecting layer 112. That is to say, among the offset inter-connecting vias 1215 that are electrically connected to the same second sub-interconnecting layer 112, any situation where any offset inter-connecting via 1215 is short-circuited to the third sub-interconnecting layer 113 on either side can be reflected by the electrical parameter values output by the second signal line 132. That is, the offset inter-connecting vias 1215 that are electrically connected to the same second sub-interconnecting layer 112 have the characteristic of mirror offset. Thus, process monitoring of overlay accuracy, critical dimension uniformity, etc. can be achieved electrically, making the correlation analysis of process fluctuations more accurate and reliable. Furthermore, it does not completely rely on die failure analysis, correspondingly shortening the R & D and mass production cycles, saving costs, and improving efficiency. Moreover, the offset inter-connecting vias 1215 of each first group of inter-connecting via structures 1210 are arranged along the first direction x and are connected to the same second sub-interconnecting layer 112, which is also beneficial for reducing the number of second signal lines 132, thereby also being beneficial for simplifying the test structure and improving the robustness of the test structure to adapt to smaller process nodes.

[0073] In this embodiment, the material of the inter-connecting via structure 120 is a conductive material, such as copper, aluminum, etc.

[0074] In this embodiment, the test structure further includes: a dielectric layer (not labeled), located between the first interconnecting layer 110 and the second interconnecting layer 130.

[0075] The dielectric layer is an inter-metal dielectric layer (IMD)

[0076] The dielectric layer is used to achieve electrical isolation between the first interconnecting layer 110 and the second interconnecting layer 130.

[0077] Specifically, the material of the dielectric layer is a dielectric material, such as silicon oxide, etc.

[0078] In this embodiment, the test structures are located on the same wafer and the number is multiple. In different test structures, the absolute values of the offsets of the first inter-connecting via structures 121 that are electrically connected to the second sub-interconnecting layer 112 are all different.

[0079] The number of the test structures located on the same wafer is multiple, and in each of the test structures, the absolute value of the offset of the first through-hole interconnection structure 121 electrically connected to the second sub-interconnection layer 112 is different, that is, the absolute value of the offset of the offset through-hole interconnection structure 1215 of each test structure is different, that is, the offset through-hole interconnection structure 1215 with a certain absolute value of the offset is only located in a certain test structure, which is beneficial to simplifying the complexity of the test structure, reducing the process difficulty of the test structure, and also facilitating the analysis of the test results and improving the efficiency during analysis.

[0080] Correspondingly, the present invention further provides a test method, which is suitable for performing tests using the test structure described in the embodiments of the present invention. Figure 3 It is a schematic flowchart corresponding to an embodiment of the test method of the present invention.

[0081] Refer to Figure 3 and in combination with reference to Figure 2 , perform step S1: Apply a first test signal to the first signal line 131 and apply a second test signal to the second signal line 132.

[0082] Since the first through-hole interconnection structure 121 electrically connected to the first sub-interconnection layer 111 is provided, it is ensured that the first test signal applied to the first signal line 131 can be transmitted to the first through-hole interconnection structure 121 electrically connected to the second sub-interconnection layer 112 without being affected by the offset of the first through-hole interconnection structure 121 electrically connected to the second sub-interconnection layer 112. Moreover, the first through-hole interconnection structure 121 electrically connected to the first sub-interconnection layer 111 and the first through-hole interconnection structure 121 electrically connected to the second sub-interconnection layer 112 are electrically connected to the same test line 133, so that even if the first through-hole interconnection structure 121 electrically connected to the second sub-interconnection layer 112 is disconnected from the second sub-interconnection layer 112 due to an offset in the second direction y, the first test signal applied to the first signal line 131 can still be transmitted to the offset first through-hole interconnection structure 121, forming a test path from the first signal line 131 to the offset first through-hole interconnection structure 121, ensuring that the electrical parameter value output by the second signal line 132 can reflect the short-circuit situation between the first through-hole interconnection structure 121 electrically connected to the second sub-interconnection layer 112 and the third sub-interconnection layer 113, thereby improving the reliability of the test results and further improving the reliability of the test structure.

[0083] If there is a short circuit between the first via structure 121 electrically connected to the second sub-interconnect layer 112 and the third sub-interconnect layer 113, a test path will be formed from the first signal line 131 to the third sub-interconnect layer. That is, both the first test signal and the second test signal will affect the third sub-interconnect layer 113. If there is no short circuit between the first via structure 121 electrically connected to the second sub-interconnect layer 112 and the third sub-interconnect layer 113, a test path will not be formed from the first signal line 131 to the third sub-interconnect layer. That is, only the second test signal will affect the third sub-interconnect layer 113. Therefore, when there is a short circuit between the first via structure 121 electrically connected to the second sub-interconnect layer 112 and the third sub-interconnect layer 113, and when there is no short circuit between the first via structure 121 electrically connected to the second sub-interconnect layer 112 and the third sub-interconnect layer 113, the electrical parameter values output by the second signal line 132 are different. That is to say, the electrical parameter values output by the second signal line 132 can be used to determine whether there is a short circuit between the first via structure 121 electrically connected to the second sub-interconnect layer 112 and the third sub-interconnect layer 113.

[0084] As an example, when the first via structure group includes a first offset group 1211 and a second offset group 1212, and the offset directions of the offset via structures 1215 in the first offset group 1211 and the second offset group 1212 are opposite, test signals are loaded on the first signal line 131 and each second signal line 132 simultaneously, so that each second signal line 132 outputs each electrical parameter value simultaneously, which is beneficial to improving the test efficiency. Correspondingly, the production efficiency of the semiconductor structure is improved and the wafer yield per hour is increased.

[0085] In this embodiment, the first test signal is a high potential, the second test signal is a zero potential, and the electrical parameter value is a current value.

[0086] Here, the high potential refers to a state with a higher electric potential, that is, VDD.

[0087] By applying a high potential to the first signal line 131 and a ground potential to the second signal line 132, it is convenient to output a current value at the end of the second signal line 132. It can be understood that if there is a short circuit between the first through-hole connection structure 121 electrically connecting the second sub-interconnect layer 112 and the third sub-interconnect layer 113, the high potential will affect the third sub-interconnect layer 113, that is, there is a potential difference between the two ends of the third sub-interconnect layer 113, resulting in a relatively large current value output by the second signal line 132; if there is no short circuit between the first through-hole connection structure 121 electrically connecting the second sub-interconnect layer 112 and the third sub-interconnect layer 113, the high potential will not affect the third sub-interconnect layer 113, that is, there is no potential difference between the two ends of the third sub-interconnect layer 113, resulting in a relatively small current value output at the end of the second signal line 132, thus facilitating subsequent determination of whether there is a short circuit between the first through-hole connection structure 121 electrically connecting the second sub-interconnect layer 112 and the third sub-interconnect layer 113.

[0088] Reference Figure 3 and in combination with the reference Figure 2 , perform step S2: Detect the electrical parameter value output by the second signal line 132, and the electrical parameter value is used to determine whether there is a short circuit between the first through-hole connection structure 121 electrically connecting the second sub-interconnect layer 112 and the test line 133 and the third sub-interconnect layer 113.

[0089] Since the electrical parameter value output at the end of the second signal line 132 is different when there is a short circuit between the first through-hole connection structure 121 electrically connecting the second sub-interconnect layer 112 and the third sub-interconnect layer 113 and when there is no short circuit between the first through-hole connection structure 121 electrically connecting the second sub-interconnect layer 112 and the third sub-interconnect layer 113, the electrical parameter value output at the end of the second signal line 132 can be used to determine whether there is a short circuit between the first through-hole connection structure 121 electrically connecting the second sub-interconnect layer 112 and the third sub-interconnect layer 113.

[0090] Specifically, the method for determining whether there is a short circuit between the first through-hole connection structure 121 electrically connecting the second sub-interconnect layer 112 and the test line 133 and the third sub-interconnect layer 113 by using the electrical parameter value includes:

[0091] Perform step S3: Determine whether the electrical parameter value is greater than a preset electrical parameter value.

[0092] Perform step S4: If so, determine that there is a short circuit between the first through-hole connection structure 121 electrically connecting the second sub-interconnect layer 112 and the test line 133 and the third sub-interconnect layer 113.

[0093] Execute step S4: Otherwise, it is determined that there is no short circuit between the first through-hole connection structure 121 electrically connecting the second sub-interconnection layer 112 and the test line 133 and the third sub-interconnection layer 113.

[0094] In this embodiment, the first test signal is at a high potential, the second test signal is at a zero potential, and the electrical parameter value is a current value; correspondingly, the preset value can be a preset current value.

[0095] Correspondingly, the present invention also provides a test structure layout. Figure 4 It is a schematic diagram of the test structure layout of the present invention Figure 1 of the embodiment.

[0096] Refer to Figure 4 , in this embodiment, the test structure layout includes: a first interconnection layout layer (not labeled), the first interconnection layout layer includes discrete first interconnection patterns 510, the first interconnection patterns 510 extend along a first direction X and are spaced apart along a second direction Y, the first direction X is perpendicular to the second direction Y, the first interconnection patterns 510 include a first sub-interconnection pattern 511, a second sub-interconnection pattern 512, and a third sub-interconnection pattern 513, and the third sub-interconnection pattern 513 is adjacent to the second sub-interconnection pattern 512; a second interconnection layout layer (not labeled), located above the first interconnection layout layer, the second interconnection layout layer includes discrete second interconnection patterns 530, the second interconnection patterns 530 extend along the second direction Y and are spaced apart along the first direction X, the second interconnection patterns 530 include a first signal line pattern 531, a second signal line pattern 532, and a test line pattern 533; a through-hole connection layout layer (not labeled), located between the first interconnection layout layer and the second interconnection layout layer, the through-hole connection layout layer includes a first through-hole connection pattern 521 and a second through-hole connection pattern 522, the first through-hole connection pattern 521 is respectively located on the first sub-interconnection pattern 511 and the second sub-interconnection pattern 512 and is covered by the test line pattern 533, and the first through-hole connection pattern 521 located on the second sub-interconnection pattern 512 is offset along the second direction Y toward the third sub-interconnection pattern 513, the second through-hole connection pattern 522 is located on the first sub-interconnection pattern 511 and is covered by the first signal line pattern 531, and is located on the third sub-interconnection pattern 513 and is covered by the second signal line pattern 532.

[0097] In the embodiment of the present invention, the test structure layout is suitable for forming the test structure described in the embodiment of the present invention.

[0098] The first interconnection pattern 510 is used to form a first interconnection layer, and the first interconnection layer is used to electrically lead out each device or realize electrical connection between devices.

[0099] In this embodiment, the first interconnect plate layer includes a first sub-plate layer and a second sub-plate layer. The first interconnect pattern 510 in the first sub-plate layer serves as the first layout interconnect layer pattern CA, and the first interconnect pattern 510 in the second sub-plate layer serves as the second layout interconnect layer pattern CB. After the first sub-plate layer and the second sub-plate layer are stacked, the first layout interconnect layer pattern CA and the second layout interconnect layer pattern CB are alternately arranged. Among the adjacent second sub-interconnect patterns 512 and third sub-interconnect patterns 513, when the second sub-interconnect pattern 512 is the first layout interconnect layer pattern CA, the third sub-interconnect pattern 513 is the second layout interconnect layer pattern CB; when the second sub-interconnect pattern 512 is the second layout interconnect layer pattern CB, the third sub-interconnect pattern 513 is the first layout interconnect layer pattern CA.

[0100] The first layout interconnect layer pattern CA is used to form the first layout interconnect layer, and the second layout interconnect layer pattern CB is used to form the second layout interconnect layer.

[0101] The alternate arrangement of the first layout interconnect layer pattern CA and the second layout interconnect layer pattern CB formed by different first interconnect plate layers is conducive to reducing the distance between adjacent first interconnect patterns 510 and increasing the pattern density of the first interconnect patterns 510.

[0102] Moreover, among the adjacent second sub-interconnect patterns 512 and third sub-interconnect patterns 513, when the second sub-interconnect pattern 512 is the first layout interconnect layer pattern CA, the third sub-interconnect pattern 513 is the second layout interconnect layer pattern CB; when the second sub-interconnect pattern 512 is the second layout interconnect layer pattern CB, the third sub-interconnect pattern 513 is the first layout interconnect layer pattern CA, which is conducive to determining whether there is a short circuit between the first interconnect via structure connecting the first layout interconnect layer and the third sub-interconnect layer of the second layout interconnect layer, and determining whether there is a short circuit between the first interconnect via structure connecting the second layout interconnect layer and the third sub-interconnect layer of the first layout interconnect layer.

[0103] The second interconnect plate layer is located above the first interconnect plate layer. Then, in the semiconductor structure manufacturing process, the first interconnect layer is formed first, and then the second interconnect layer is formed.

[0104] The second interconnect pattern 530 is used to form a second interconnect layer for electrically connecting to the first interconnect layer. The first signal line is used to electrically connect to the first sub-interconnect layer, and a first test signal is applied to the first signal line; the second signal line is used to electrically connect to the third sub-interconnect layer, and a second test signal is applied to the second signal line; the test line is used to electrically connect to the first sub-interconnect layer and the second sub-interconnect layer.

[0105] As an example, the first interconnect pattern 510 is used to form a metal line of a certain layer, i.e., Mn, and the second interconnect pattern 530 is used to form a metal line of the layer above the metal line, i.e., Mn+1.

[0106] The via plate layer is located between the first interconnect plate layer and the second interconnect plate layer. Then, in the semiconductor structure manufacturing process, the first interconnect layer, the via structure, and the second interconnect layer are sequentially formed.

[0107] The via pattern is used to form a via structure, and the second interconnect layer is electrically connected to the first interconnect layer through the via structure.

[0108] The first via pattern 521 is used to form a first via structure, and the second via pattern 522 is used to form a second via structure.

[0109] Here, the first via pattern 521 and the second via pattern 522 constitute a via pattern (not labeled).

[0110] By providing a first interconnection via pattern 521 located on the first sub-interconnection pattern 511, it is ensured that the first signal line pattern 531 can be serially connected to the first interconnection via pattern 521 on the second sub-interconnection pattern 512, without being affected by the offset of the first interconnection via pattern 521 on the second sub-interconnection pattern 512. Since the first interconnection via pattern 521 on the first sub-interconnection pattern 511 and the first interconnection via pattern 521 on the second sub-interconnection pattern 512 are covered by the same test line pattern 533, even if the first interconnection via pattern 521 on the second sub-interconnection pattern 512 is offset in the second direction Y and not covered by the second sub-interconnection pattern 512, a serial connection can still be established from the first signal line pattern 531 to the first interconnection via pattern 521 on the second sub-interconnection pattern 512, forming a serial connection path from the first signal line pattern 531 to the first interconnection via pattern 521 on the second sub-interconnection pattern 512. This ensures that the electrical parameter value output by the second signal line can reflect the short-circuit condition between the first interconnection via structure of the second sub-interconnection layer and the third sub-interconnection layer, thereby improving the reliability of the test results and further enhancing the reliability of the test structure formed by the test structure layout.

[0111] In this embodiment, the first interconnection via patterns 521 covered by the same test line pattern 533 form a first interconnection via pattern group 5210. The first interconnection via pattern 521 located on the second sub-interconnection pattern 512 and covered by the test line pattern 533 in the first interconnection via pattern group 5210 is the offset interconnection via pattern 5215, and the first interconnection via pattern 521 located on the first sub-interconnection pattern 511 and covered by the test line pattern 533 in the first interconnection via pattern group 5210 is the reference interconnection via pattern 5216.

[0112] In this embodiment, the absolute values of the offsets of the offset interconnection via patterns 5215 in the same first interconnection via pattern group 5210 are the same.

[0113] The absolute values of the offsets of the offset interconnection via patterns 5215 in the same first interconnection via pattern group 5210 are the same. It can be understood that in the same first interconnection via pattern group 5210, the number of offset interconnection via patterns 5215 is multiple, which is beneficial to increasing the number of offset interconnection via patterns 5215 with the same absolute value of the offset in the second direction X, so that any short-circuit condition between an offset interconnection via structure and the third sub-interconnection layer due to process fluctuations can be reflected by the electrical parameter value output by the second signal line, thereby further improving the reliability of the test results.

[0114] In this embodiment, the number of the first interconnected via pattern groups 5210 is multiple. The absolute values of the offsets of the offset interconnected via patterns 5215 in different first interconnected via pattern groups 5210 are the same, and the offset directions are opposite or the same.

[0115] When the absolute values of the offsets of the offset interconnected via patterns 5215 in different first interconnected via pattern groups 5210 are the same and the offset directions are the same, that is, the number of the offset interconnected via patterns 5215 with the same absolute value of the offset and the same offset direction in the first direction X is increased, so that any situation where an offset interconnected via structure is short-circuited with the third sub-interconnection layer due to process fluctuations can be reflected by the electrical parameter values output by the second signal line, which is beneficial to further improving the reliability of the test results.

[0116] When the absolute values of the offsets of the offset interconnected via patterns 5215 in different first interconnected via pattern groups 5210 are the same and the offset directions are opposite, that is, the offset interconnected via patterns 5215 with the same absolute value of the offset and opposite offset directions are located in the same test structure layout. Not only can any situation where an offset interconnected via structure is short-circuited with the third sub-interconnection layer due to process fluctuations be reflected by the electrical parameter values output by the second signal line, but also it is beneficial to increasing the utilization rate of the test structure formed by this test structure layout.

[0117] Specifically, the first interconnected via pattern group 5210 includes a first offset pattern group 5211 and a second offset pattern group 5212, and the offset directions of the offset interconnected via patterns 5215 in the first offset pattern group 5211 and the second offset pattern group 5212 are opposite.

[0118] Among them, the offset interconnected via patterns 5215 in the first offset pattern group 5211 and the second offset pattern group 5212 are respectively the offset interconnected via patterns 5215 in different first interconnected via pattern groups 5210.

[0119] The first interconnected via pattern group 5210 includes a first offset pattern group 5211 and a second offset pattern group 5212. The offset directions of the offset interconnected via patterns 5215 in the first offset pattern group 5211 and the second offset pattern group 5212 are opposite to each other, increasing the number of offset interconnected via structures. Not only can any situation where an offset interconnected via structure is short-circuited with the third sub-interconnect layer 113 due to process fluctuations be reflected by the electrical parameter values output by the second signal line, but also it is beneficial to have offset interconnected via structures with opposite offset directions in the same test structure. That is to say, offset interconnected via structures with different offset directions can be located in the same test structure, thus facilitating the reduction of the area of the test structure. Moreover, test signals can be loaded onto the first signal line and each second signal line terminal simultaneously, enabling each second signal line to output each electrical parameter value simultaneously, which is conducive to improving the test efficiency. Correspondingly, it also realizes the improvement of the production efficiency of the semiconductor structure and the increase in the number of wafers produced per hour.

[0120] More specifically, the number of both the first offset pattern group 5211 and the second offset pattern group 5212 is multiple.

[0121] The number of both the first offset pattern group 5211 and the second offset pattern group 5212 being multiple is conducive to further increasing the number of offset interconnected via patterns 5215 with the same absolute value of the offset amount and the same offset direction in the first direction X, thereby being conducive to further improving the reliability of the test results.

[0122] In this embodiment, in each first interconnected via pattern group 5210, the first interconnected via pattern 521 located on the first sub-interconnect pattern 511 and covered by the test line pattern 533 is the reference interconnected via pattern 5216 of each first interconnected via pattern group 5210; the reference interconnected via patterns 5216 located on the same first sub-interconnect pattern 511 in different first interconnected via pattern groups 5210 are arranged along the first direction X; the offset interconnected via patterns 5215 located on the same second sub-interconnect pattern 512 in different first interconnected via pattern groups 5210 are arranged along the first direction X, and the offset interconnected via patterns 5215 located on the same second sub-interconnect pattern 512 have opposite offset directions.

[0123] In different first mutually connected via pattern groups 5210, the reference mutually connected via patterns 5216 located on the same first sub-interconnect pattern 511 are arranged along the first direction X. That is, the first signal line pattern 531 is serially connected to each of the reference mutually connected via patterns 5216 through the same first sub-interconnect pattern 511, which is beneficial to reducing the number of first signal line patterns 531 serially connected to the first sub-interconnect pattern 511, thereby facilitating the simplification of the test structure layout, correspondingly simplifying the test structure, improving the robustness of the test structure, and adapting to smaller process nodes.

[0124] In different first mutually connected via pattern groups 5210, the offset mutually connected via patterns 5215 located on the same second sub-interconnect pattern 512 are arranged along the first direction X, and the offset mutually connected via patterns 5215 located on the same second sub-interconnect pattern 512 have opposite offset directions, such that along the second direction Y, the third sub-interconnect pattern 513 is located on both sides of the second sub-interconnect pattern 512. That is to say, among the offset mutually connected via patterns 5215 located on the same second sub-interconnect pattern 512, any short circuit situation between any offset via structure and the third sub-interconnect layer on either side due to process fluctuations can be reflected by the electrical parameter values output by the second signal line. That is, the offset mutually connected via patterns 5215 located on the same second sub-interconnect pattern 512 have the characteristic of mirror offset, so that process monitoring of overlay accuracy, critical dimension uniformity, etc. can be realized electrically, making the correlation analysis of process fluctuations more accurate and reliable, and thus not completely relying on die failure analysis, correspondingly shortening the R & D and mass production cycles, saving costs, and improving efficiency. Moreover, the offset mutually connected via patterns 5215 of each first mutually connected via pattern group 5210 are arranged along the first direction X and are located on the same second sub-interconnect pattern 512, which is also beneficial to reducing the number of second signal line patterns 532 serially connected to the second sub-interconnect pattern 512, thereby also facilitating the simplification of the test structure layout, correspondingly simplifying the test structure, improving the robustness of the test structure, and adapting to smaller process nodes.

[0125] In this embodiment, the test structure layouts are located in the same wafer mask layout and the number is multiple. In different test structure layouts, the absolute values of the offsets of the first mutually connected via patterns 521 located on the second sub-interconnect pattern 512 are all different.

[0126] The number of test structure layouts in the same wafer mask layout is multiple, and the absolute values of the offsets of the offset mutual connection via patterns 5215 of each test structure layout are all different, that is, the offset mutual connection via pattern 5215 with a certain absolute value of offset is only located in a certain test structure, which is beneficial to simplifying the complexity of the test structure, reducing the process difficulty of the test structure, and also facilitating the analysis of test results and improving the efficiency during analysis.

[0127] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A test structure, characterized in that, Comprising: A substrate; A first interconnect layer, separately disposed above the substrate, the first interconnect layer extending in a first direction and arranged at intervals in a second direction, the first direction being perpendicular to the second direction, the first interconnect layer including a first sub-interconnect layer, a second sub-interconnect layer, and a third sub-interconnect layer, the third sub-interconnect layer being disposed adjacent to the second sub-interconnect layer; A second interconnect layer, separately disposed above the first interconnect layer, the second interconnect layer extending in the second direction and arranged at intervals in the first direction, the second interconnect layer including a first signal line, a second signal line, and a test line; An interconnection via structure, located between the first interconnect layer and the second interconnect layer, the interconnection via structure including a first interconnection via structure and a second interconnection via structure, the first interconnection via structure electrically connecting the first sub-interconnect layer and the test line, and electrically connecting the second sub-interconnect layer and the test line, and the first interconnection via structure electrically connecting the second sub-interconnect layer being offset toward the third sub-interconnect layer side in the second direction, the second interconnection via structure electrically connecting the first sub-interconnect layer and the first signal line, and electrically connecting the third sub-interconnect layer and the second signal line.

2. The test structure according to claim 1, wherein The first interconnection via structures connecting the same test line form a first group of interconnection via structures, and the first interconnection via structures in the first group of interconnection via structures that electrically connect the second sub-interconnect layer and the test line are offset interconnection via structures; the number of the first groups of interconnection via structures is multiple, the absolute values of the offsets of the offset interconnection via structures in different first groups of interconnection via structures are the same, and the offset directions are opposite or the same.

3. The test structure according to claim 2, characterized in that, The first group of interconnection via structures includes a first offset group and a second offset group, and the offset directions of the offset interconnection via structures in the first offset group and the second offset group are opposite.

4. The test structure according to claim 3, wherein, The number of both the first offset group and the second offset group is multiple.

5. The test structure according to claim 2, wherein, In each of the first groups of interconnection via structures, the first interconnection via structures that electrically connect the first sub-interconnect layer and the test line are the reference interconnection via structures of each of the first groups of interconnection via structures; The reference interconnection via structures connecting the same first sub-interconnect layer in different first groups of interconnection via structures are arranged in the first direction; The offset interconnection via structures connecting the same second sub-interconnect layer in different first groups of interconnection via structures are arranged in the first direction, and the offset interconnection via structures electrically connecting the same second sub-interconnect layer have opposite offset directions.

6. The test structure according to any one of claims 1 to 5, characterized in that, The first interconnection via structures connecting the same test line form a first group of interconnection via structures, and the first interconnection via structures in the first group of interconnection via structures that electrically connect the second sub-interconnect layer and the test line are offset interconnection via structures; the absolute values of the offsets of the offset interconnection via structures in the same first group of interconnection via structures are the same.

7. The test structure according to any one of claims 1 to 5, characterized in that, The test structures are located on the same wafer and the number is multiple, and in different test structures, the absolute values of the offsets of the first interconnection via structures electrically connecting the second sub-interconnect layer are all different.

8. The test structure according to any one of claims 1 to 5, characterized in that, The first interconnect layer includes alternately arranged first layout interconnect layers and second layout interconnect layers; In the adjacent second sub-interconnection layer and third sub-interconnection layer, when the second sub-interconnection layer is the first layout interconnection layer, the third sub-interconnection layer is the second layout interconnection layer; when the second sub-interconnection layer is the second layout interconnection layer, the third sub-interconnection layer is the first layout interconnection layer.

9. A testing method, characterized in that, Suitable for being tested by using the test structure according to any one of claims 1 to 8, the test method includes: Loading a first test signal on a first signal line and loading a second test signal on a second signal line; Detecting an electrical parameter value output by the second signal line, and the electrical parameter value is used to determine whether there is a short circuit between the first through-hole structure electrically connecting the second sub-interconnection layer and the test line and the third sub-interconnection layer.

10. The test method according to claim 9, wherein The first test signal is a high potential, the second test signal is a zero potential, and the electrical parameter value is a current value.

11. The testing method according to claim 9, characterized in that, The method for determining whether there is a short circuit between the first through-hole structure electrically connecting the second sub-interconnection layer and the test line and the third sub-interconnection layer through the electrical parameter value includes: determining whether the electrical parameter value is greater than a preset electrical parameter value. If so, it is determined that there is a short circuit between the first through-hole structure electrically connecting the second sub-interconnection layer and the test line and the third sub-interconnection layer; otherwise, it is determined that there is no short circuit between the first through-hole structure electrically connecting the second sub-interconnection layer and the test line and the third sub-interconnection layer.

12. A layout of a test structure, characterized in that Including: A first interconnection layout layer, the first interconnection layout layer includes discrete first interconnection patterns, the first interconnection patterns extend along a first direction and are spaced apart along a second direction, the first direction is perpendicular to the second direction, the first interconnection patterns include a first sub-interconnection pattern, a second sub-interconnection pattern and a third sub-interconnection pattern, and the third sub-interconnection pattern is arranged adjacent to the second sub-interconnection pattern; A second interconnection layout layer, located above the first interconnection layout layer, the second interconnection layout layer includes discrete second interconnection patterns, the second interconnection patterns extend along the second direction and are spaced apart along the first direction, the second interconnection patterns include a first signal line pattern, a second signal line pattern and a test line pattern; A through-hole interconnection layout layer, located between the first interconnection layout layer and the second interconnection layout layer, the through-hole interconnection layout layer includes a first through-hole pattern and a second through-hole pattern, the first through-hole pattern is respectively located on the first sub-interconnection pattern and the second sub-interconnection pattern and is covered by the test line pattern, the first through-hole pattern located on the second sub-interconnection pattern is offset along the second direction towards the side of the third sub-interconnection pattern, the second through-hole pattern is located on the first sub-interconnection pattern and is covered by the first signal line pattern, and is located on the third sub-interconnection pattern and is covered by the second signal line pattern.

13. The layout of the test structure according to claim 12, wherein, The first mutually connected via patterns covered by the same test line pattern form a first group of mutually connected via patterns. The first mutually connected via pattern located on the second sub-interconnection pattern and covered by the test line pattern in the first group of mutually connected via patterns is an offset mutually connected via pattern. The number of the first groups of mutually connected via patterns is multiple. The absolute values of the offsets of the offset mutually connected via patterns in different first groups of mutually connected via patterns are the same, and the offset directions are opposite or the same.

14. The layout of the test structure according to claim 13, wherein The first group of mutually connected via patterns includes a first offset pattern group and a second offset pattern group. The offset directions of the offset mutually connected via patterns in the first offset pattern group and the second offset pattern group are opposite.

15. The layout of the test structure according to claim 14, characterized in that, The number of both the first offset pattern group and the second offset pattern group is multiple.

16. The test structure layout according to claim 13, wherein In each first group of mutually connected via patterns, the first mutually connected via pattern located on the first sub-interconnection pattern and covered by the test line pattern is the reference mutually connected via pattern of each first group of mutually connected via patterns; The reference mutually connected via patterns located on the same first sub-interconnection pattern in different first groups of mutually connected via patterns are arranged along the first direction; The offset mutually connected via patterns located on the same second sub-interconnection pattern in different first groups of mutually connected via patterns are arranged along the first direction, and the offset mutually connected via patterns located on the same second sub-interconnection pattern have opposite offset directions.

17. The test structure layout according to any one of claims 12 to 16, wherein The first mutually connected via patterns covered by the same test line pattern form a first group of mutually connected via patterns. The first mutually connected via pattern located on the second sub-interconnection pattern and covered by the test line pattern in the first group of mutually connected via patterns is an offset mutually connected via pattern; the absolute values of the offsets of the offset mutually connected via patterns in the same first group of mutually connected via patterns are the same.

18. The test structure layout according to any one of claims 12 to 16, characterized in that, The test structure layout is located in the same wafer mask layout and the number is multiple. In different test structure layouts, the absolute values of the offsets of the first mutually connected via patterns located on the second sub-interconnection pattern are all different.

19. The test structure layout according to any one of claims 12 to 16, characterized in that, The first interconnection layout layer includes a first sub-layout layer and a second sub-layout layer. The first interconnection patterns in the first sub-layout layer serve as the first layout interconnection layer patterns, and the first interconnection patterns in the second sub-layout layer serve as the second layout interconnection layer patterns. After the first sub-layout layer and the second sub-layout layer are stacked, the first layout interconnection layer patterns and the second layout interconnection layer patterns are alternately arranged; In the adjacent second sub-interconnection pattern and third sub-interconnection pattern, when the second sub-interconnection pattern is a first layout interconnection layer pattern, the third sub-interconnection pattern is a second layout interconnection layer pattern; when the second sub-interconnection pattern is a second layout interconnection layer pattern, the third sub-interconnection pattern is a first layout interconnection layer pattern.

Images