Cross-coupled timing synchronization platform

Abstract

The invention relates to a cross-coupled timing synchronization platform. Apparatuses, devices, and systems for time synchronization are described. The timing circuit may include an analog phase-locked loop (APLL), a plurality of digital phase-locked loops (DPLL), and a plurality of fractional output frequency dividers (FODs). The timing circuit may receive a plurality of reference clock signals. The timing circuit may generate at least one fractional frequency offset signal using a plurality of reference clock signals. The timing circuit may apply at least one operand on the at least one fractional frequency offset signal. The timing circuit may sum the results of the application of the at least one operand on the at least one fractional frequency offset signal to generate a plurality of signals that control the frequency of the plurality of output clock signals that may be synchronized with the plurality of reference clock signals.

Description

Technical Field

[0001] The present disclosure generally relates to integrated circuit devices, and more particularly to clock synchronization circuits having cross-coupled networks for generating multiple clock signals for synchronization. Background Art

[0002] Timing circuits including transceivers and clock circuits can be connected to multiple networks to synchronize the multiple networks. The timing circuit can include multiple phase-locked loops, such as an analog phase-locked loop (APLL) and a digital phase-locked loop (DPLL). The APLL can include an analog phase detector, a charge pump, a loop filter, and a voltage-controlled oscillator (VCO) in a feedback loop. The DPLL can include a digital phase detector and a loop filter, and a numerically controlled oscillator (DCO). Due to including a digital phase detector and a loop filter, digital phase-locked loops are generally smaller than analog PLLs. A combination of an APLL and a DPLL can form a mixed-signal phase-locked loop, thereby reducing jitter in the signals output by the timing circuit. Summary of the Invention

[0003] In one embodiment, a semiconductor device for timing synchronization is generally described. The semiconductor device can include a first timing channel formed by an analog phase-locked loop (APLL), a first digital phase-locked loop (DPLL), and a first summing module. The semiconductor device can further include a second timing channel formed by a fractional output divider (FOD), a second digital phase-locked loop (DPLL), and a second summing module. The first summing module can be configured to apply at least one operand to one or more of a first fractional frequency offset signal output by the first DPLL and a second fractional frequency offset signal output by the second DPLL. The first summing module can further be configured to sum the result of the application of the at least one operand by the first summing module to generate a first signal that controls the frequency of a first clock signal output by the APLL. The second summing module is configured to apply at least one operand to one or more of a first fractional frequency offset signal output by the first DPLL and a second fractional frequency offset signal output by the second DPLL. The second summing module is further configured to sum the result of the application of the at least one operand by the second summing module to generate a second signal that controls the frequency of a second clock signal output by the FOD.

[0004] In one embodiment, a system for time synchronization is generally described. The system can include a first set of transceivers configured to receive input data and output a plurality of reference clock signals. The system can also include a second set of transceivers configured to receive the plurality of output clock signals and output a set of synchronization data. The system can further include a timing circuit that includes at least an analog phase-locked loop (APLL), a plurality of digital phase-locked loops (DPLLs), and a plurality of fractional output dividers (FODs). The timing circuit can be configured to receive the plurality of reference clock signals. The timing circuit can also be configured to generate at least one fractional frequency offset signal using the plurality of reference clock signals. The timing circuit can also be configured to apply at least one operand to the at least one fractional frequency offset signal. The timing circuit can also be configured to sum the result of the application of the at least one operand to the at least one fractional frequency offset signal to generate a plurality of signals that control the frequencies of the plurality of output clock signals. The timing circuit can also be configured to send the plurality of signals to the second set of transceivers.

[0005] In one embodiment, a method for operating a timing circuit is generally described. The method can include receiving a plurality of reference clock signals. The method can also include generating at least one fractional frequency offset signal using the plurality of reference clock signals. The method can also include applying at least one operand to the at least one fractional frequency offset signal. The method can also include determining the sum of the result of the application of the at least one operand to the at least one fractional frequency offset signal to generate a plurality of signals that control the frequencies of the plurality of output clock signals synchronized with the plurality of reference clock signals.

[0006] Various other features as well as the structure and operation of the various embodiments are described in detail below with reference to the accompanying drawings. In the drawings, like reference numerals represent like or functionally similar elements. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a diagram showing an example system of a cross-coupled timing synchronization platform in one embodiment;

[0008] Figure 2 is a diagram showing the timing circuit of a cross-coupled timing synchronization platform that can be implemented in one embodiment;

[0009] Figure 3 is a diagram showing the summing module of a cross-coupled timing synchronization platform that can be implemented in one embodiment;

[0010] Figure 4 is a diagram showing the components in a cross-coupled timing synchronization platform in one embodiment;

[0011] Figure 5 is a diagram showing an example application of a cross-coupled timing synchronization platform in one embodiment;

[0012] Figure 6 is a diagram showing another exemplary implementation of a cross-coupled timing synchronization platform in one embodiment; and

[0013] Figure 7 is a flowchart illustrating a process for implementing a cross-coupled timing synchronization platform in one embodiment. Detailed Description

[0014] In the following description, numerous specific details are set forth, such as specific structures, components, materials, dimensions, processing steps, and techniques, in order to provide an understanding of the various embodiments of the present application. However, those of ordinary skill in the art will understand that the various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail to avoid obscuring the present application.

[0015] Figure 1 is a diagram showing an exemplary system of a cross-coupled timing synchronization platform in one embodiment. System 100 may include a communication device 102 and multiple networks, such as networks 103a, 103b, 104a, 104b. In one embodiment, the communication device 102 may be implemented as a telecommunications network circuit, such as a switch (e.g., a synchronous Ethernet or SyncE switch) or a router. In one embodiment, system 100 may be implemented to synchronize multiple networks (e.g., two or more networks), such as networks 103a, 103b, 104a, 104b. Networks 103a, 103b, 104a, 104b may be, for example, local area networks (LANs), time-division multiplexing (TDM)-based networks (such as SONET / SDH / PDH), and / or Ethernet-based packet networks.

[0016] The communication device 102 may include one or more transceivers 106a, 106b. In one embodiment, the transceivers 106a, 106b, 106c, 106d may be Ethernet physical layer transceiver chips. The transceivers 106a, 106b, 106c, 106d may be configured to send data to or receive data from networks 103a, 103b, 104a, 104b, clock circuit 108, and / or timing circuit 110. The communication device 102 may also include at least one clock circuit 108. The clock circuit 108 may be a Precision Time Protocol (PTP) timing circuit or other timing circuit that can provide a reference clock signal. The communication device 102 may also include a timing circuit 110. In one embodiment, the timing circuit 110 may be a network card. Although Figure 1 the example in shows four networks, four transceivers, and one clock circuit, the communication device 102 may include any number of networks, transceivers, and clock circuits.

[0017] In one embodiment, transceivers 106a, 106b, 106c, 106d, clock circuit 108, and timing circuit 110 may be deployed throughout a telecommunications network, server rack, or other types of communication devices and networks. In one embodiment, system 100 may be implemented as a single semiconductor integrated circuit (or semiconductor package or device). In another embodiment, transceivers 106a, 106b, 106c, 106d, clock circuit 108, and timing circuit 110 may be implemented as individual semiconductor ICs on a printed circuit board.

[0018] Transceiver 106a may be coupled to network 103a and may be configured to send signals to and / or receive signals from network 103a. Transceiver 106a may also be configured to communicate signals with clock circuit 108 and timing circuit 110. Transceiver 106b may be coupled to network 103b and may be configured to send signals to and / or receive signals from network 103b. Transceiver 106b may also be configured to communicate signals with clock circuit 108 and timing circuit 110. Transceiver 106c may be coupled to network 104a and may be configured to send signals to and / or receive signals from network 104a. Transceiver 106c may also be configured to communicate signals with clock circuit 108 and timing circuit 110. Transceiver 106d may be coupled to network 104b and may be configured to send signals to and / or receive signals from network 104b. Transceiver 106d may also be configured to communicate signals with clock circuit 108 and timing circuit 110.

[0019] In one embodiment, clock circuit 108 may implement an IEEE 1588-compliant packet-based timing scheme. Each of at least one clock circuit 108 may be configured as a master clock or a slave clock. When implemented as a master clock, clock circuit 108 may send synchronization messages to other clock circuits implemented as slave clocks.

[0020] In one embodiment, networks 103a, 103b can be transmission networks, and networks 104a, 104b can be receiving networks, such that data 111a, 111b can be transmitted from networks 103a, 103b to networks 104a, 104b via communication device 102, respectively. When networks 103a, 103b are transmission networks, transceivers 106a, 106b can recover corresponding physical reference clock signals 113a, 113b from data 111a, 111b, respectively. In one embodiment, the recovered physical reference clock signals 113a, 113b can be SyncE physical clock signals. Transceivers 106a, 106b can send the recovered physical reference clock signals 113a, 113b to timing circuit 110. When implemented as a slave clock, clock circuit 108 can send reference signal 115 to timing circuit 110. Reference signal 115 can be digital information, such as a PTP phase clock signal of an internal reference clock. Timing circuit 110 can generate output clock signals 117 that are frequency and / or phase locked to the physical reference clock signal 113a, and output clock signals 119 that are frequency and / or phase locked to the physical reference clock signal 113b. Timing circuit 110 can send output clock signals 117, 119 to transceiver 106b and clock circuit 108b, respectively, such that timing circuit 110 can send data 111a, 111b to networks 104a, 104b at a synchronous frequency and phase. In one embodiment, timing circuit 110 can also generate output clock signals that are frequency and / or phase locked to reference signal 115.

[0021] Timing circuit 110 can include a plurality of analog phase-locked loops (APLLs) and digital phase-locked loops (DPLLs) configured to generate frequency-locked and / or phase-locked signals. The combination of APLL and DPLL can form a hybrid signal phase-locked loop (PLL), thereby reducing jitter at the output of timing circuit 110. Timing circuit 110 can also include a fractional output divider (FOD) to divide the high-frequency clock generated by the combination of APLL and DPLL using a fixed fractional division ratio. In one aspect, each DPLL can be connected to an APLL or an FOD to generate a clock signal for a timing channel. Thus, if there are N DPLLs, timing circuit 110 can have N timing channels. However, after configuring N timing channels for a specific timing application, the configuration can remain unchanged because a change in the configuration may disrupt output clock signals 117, 119.

[0022] As will be described in more detail below, in addition to multiple DPLLs (e.g., two or more), an APLL, and an FOD, the timing circuit 110 may further include a configurable cross-coupled network that includes a summing module that can adjust the fractional frequency offset (ffo) signal output by the DPLL. Each of the multiple DPLLs in the timing circuit 110 may be connected to a dedicated summing module that can apply one or more user-programmable operands to the fractional frequency offset signal output by the DPLL. In addition, the configuration of the operands and the enabling or disabling of the DPLLs may be performed dynamically (e.g., at any time, even during operation). By selectively configuring the operands and enabling or disabling the DPLLs in the timing circuit, different output clock signals generated by the timing circuit 110 can be applied to various timing applications.

[0023] Figure 2 is a diagram showing a timing circuit in which a cross-coupled timing synchronization platform can be implemented in one embodiment. Figure 2 The description of can refer to Figure 1 the components shown. The details of the timing circuit 110 are as Figure 2 shown. The timing circuit 110 may include an APLL, N DPLLs, N summing modules, and N - 1 FODs. A particular DPLL may be connected to the APLL 206, and the remaining N - 1 DPLLs may be connected to dedicated FODs among the N - 1 FODs. One summing module may be connected between the particular DPLL and the APLL, and the remaining N - 1 summing modules may be connected to the N - 1 FODs. The APLL or the N - 1 FODs may serve as numerically controlled oscillators for the N DPLLs. In Figure 2 the embodiment shown, N = 4, and the timing circuit 110 may include a local oscillator (LO) 202, an APLL 206, multiple DPLLs 210, 212, 214, 216, multiple FODs 220, 222, 224, and multiple summing modules 230, 232, 234, 236. In one embodiment, the LO 202 may be a crystal oscillator. In one embodiment, the summing modules 230, 232, 234, 236 may be summing circuits. Figure 1 The physical reference clock signals 113a, 113b in may be Figure 2 the reference clock signals ref_clk0, ref_clk1, ref_clk2, ref_clk3 shown. Figure 1 The output clock signals 117, 119 in may be Figure 2 the output clock signals out_clk0, out_clk1, out_clk2, out_clk3 shown. In Figure 2In the illustrated embodiment, DPLL 210 and APLL 206 may form a first timing channel. DPLL 212 and FOD220 may form a second timing channel. DPLL 214 and FOD 222 may form a third timing channel. DPLL 216 and FOD224 may form a fourth timing channel.

[0024] DPLL 210 may be connected to APLL 206 and dedicated summing module 230. Initially, APLL 206 may lock to the LO signal output by LO 202 (e.g., be synchronized therewith), and generate an output clock signal out_clk0 having the same fractional frequency offset as LO 202 before being locked by DPLL 210 (e.g., before DPLL 210 receives the first feedback out_clk0). The output clock signal out_clk0 may be fed back to DPLL 210. DPLL 210 may receive the clock ref_clk0 and generate an ffo0 signal (“ffo0”) for APLL 206. The ffo0 signal may be a fractional frequency offset for guiding APLL 210, and ffo0 may indicate a parts per million (ppm) value (which indicates a relatively small percentage) for adjusting out_clk0. APLL 206 may use ffo0 to adjust out_clk0 such that out_clk0 may be frequency or phase locked to the reference clock ref_clk0. The output clock signal out_clk0 may be continuously fed back to DPLL 210 to implement a feedback loop to maintain out_clk0 frequency or phase locked to ref_clk0. In one embodiment, DPLL 210 may be configured to compare out_clk0 with ref_clk0 to determine the difference (e.g., phase, frequency difference) between out_clk0 and ref_clk0, and these differences may be filtered by DPLL 210 to generate an ffo0 signal that may remove any unwanted frequencies. Additionally, the output clock signal out_clk0 may be assigned to FOD 220, 222, 224 such that FOD 220, 222, 224 may follow the output clock signal out_clk0. FOD 220, 222, 224 may be configured to divide the high-frequency clock generated by APLL 206 and the DPLL in timing circuit 110 using a constant fractional division ratio.

[0025] The DPLL 212 can be connected to the FOD 220 and the dedicated summing module 232. The FOD 220 can output an output clock signal out_clk1, which follows the output clock signal out_clk0 distributed by the APLL 206. The output clock signal out_clk1 can be fed back to the DPLL 212. The DPLL 212 can receive a reference clock ref_clk1 and generate a fractional frequency offset signal ("ffo1") for the FOD 220. The ffo1 signal can be for guiding the fractional frequency offset of the FOD 220, and the ffo1 can indicate a parts per million (ppm) value (which indicates a relatively small percentage) for adjusting out_clk1. The FOD220 can use the ffo1 to generate out_clk1 that is frequency or phase locked to the reference clock ref_clk1. The output clock signal out_clk1 can be continuously fed back to the DPLL 212 to implement a feedback loop to keep out_clk1 frequency or phase locked to ref_clk1. In one embodiment, the DPLL 212 can be configured to compare out_clk1 with ref_clk1 to determine the difference (e.g., phase, frequency difference) between out_clk1 and ref_clk1, and these differences can be filtered by the DPLL 212 to generate the ffo1 signal that can remove any unwanted frequencies. The DPLLs 214, 216 can operate in the same manner as the DPLL 212, and the FODs 222, 224 can operate in the same manner as the FOD 220.

[0026] The summing module 230 can receive the ffo0 signal output from the DPLL 210 and can receive the operand 240. The summing module 230 can apply the operand 240 to the ffo0 signal output from the DPLL 210. In one embodiment, the operand 240 can include addition, subtraction, or block. The addition operand can add the ppm value indicated by the ffo0 to out_clk0. The subtraction operand can subtract the ppm value indicated by the ffo0 from out_clk0. The block operand can hold out_clk0 (e.g., no change). The summing module 230 can output the result of the application of the operand 240 to the ffo0 signal output from the DPLL 210 to the APLL 206. Similar to the summing module 230, the summing module 232 can receive the ffo1 signal output from the DPLL 212 and can receive the operand 242. The summing module 232 can apply the operand 242 to the ffo1 signal output from the DPLL 212. In one embodiment, the operand 242 can include addition, subtraction, or block. The summing module 232 can output the result of the application of the operand 242 to the ffo1 signal output from the DPLL 212 to the FOD 220.

[0027] The operands 240, 242 can be programmably set by a user of the system 100. In addition, the DPLL in the timing circuit 110 can be selectively enabled or disabled by a user of the system 100. The configuration of the operands and the selective enabling or disabling of the DPLL can allow the system 100 to output different clock signals customized for different timing applications. For example, the combination of the DPLL 210 and the APLL 206, as well as the combination of other DPLLs and FODs, can form independent timing channels. In one embodiment, the operands provided to the summing modules 230, 232, 234, 236 can be received from a user interface running on a computing device.

[0028] In one embodiment, a feedback fractional frequency offset (fb_ffo) signal can be provided to one or more DPLLs in the timing circuit 110. The fb_ffo signal can indicate a fractional frequency offset, such as a ppm value. In Figure 2 the example shown, the fb_ffo signal is provided to the DPLL 210 and the summing module 230. When the fb_ffo signal is provided to the DPLL 210, the fb_ffo signal can control the ffo0 signal output from the DPLL 210. The ffo0 signal output from the DPLL 210 can be the sum of the fractional frequency offset of ref_clk0 and the fractional frequency offset indicated by the fb_ffo. For example, if ref_clk0 is a clock signal of +10 ppm and the fb_ffo indicates -30 ppm, then ffo0 can be -20 ppm.

[0029] The fb_ffo signal can also be provided to the summing modules 230, 232, 234, 236 such that the ppm value indicated by the fb_ffo signal can be added to, subtracted from, or block-operated (e.g., no change to ffo0) with the ffo0 signal output from the corresponding DPLL. The fb_ffo signal can provide an additional source (e.g., in addition to the ffo signal output from the DPLL) to control the frequency of the output clock signal of the APLL 206 or the FOD in the timing circuit 110. In addition, the fb_ffo signal can be dynamically configured by a user during the operation of the timing circuit 110.

[0030] Figure 3 is a diagram showing a summing module in which a cross-coupled timing synchronization platform can be implemented in one embodiment. Figure 3 The description of can refer to Figures 1 to 2 the components shown. Figure 3An example implementation of the summing module 300 is shown, which can be one of the summing modules 230, 232, 234, 236. The summing module 300 can receive one or more fractional frequency offset signals ffo0, ffo1, ffo2, ffo3 from the DPLLs 210, 212, 214, 216 respectively. The summing module 300 can also receive the fb_ffo signal. The summing module 300 can also receive different operands 320, 322, 324, 326, 328. The operands 320, 324, 326, 328 can be applied to the fractional frequency offset signals ffo0, ffo1, ffo2, ffo3 respectively, and the operand 322 can be applied to the fb_ffo signal. Depending on the applied operands, the fractional frequency offset signals (including the fb_ffo signal) received at the summing module 300 can be inverted (e.g., subtracted), zeroed (e.g., blocked or ignored), or passed through unchanged (e.g., added).

[0031] The results of the application of the operands can be summed to generate the ffo output 308. In Figure 3 the illustrated embodiment, the fb_ffo signal is also provided to the summing block (with the ∑ label) such that the results of the application of the operands can also be summed with the fb_ffo signal to generate the fractional frequency offset output (ffo output) 308. The ffo output 308 can be a fractional frequency offset signal indicating a ppm value that is used to control the output clock signal of the FOD in the APLL 206 or the timing circuit 110, such as to change the frequency. In one embodiment, the summing module 300 can include a set of registers for storing the operands provided to the summing module 300. The operands can be programmable, such as programmable by a user of the system 100, and can be provided to the set of registers via a serial port.

[0032] In one embodiment, a hold signal 306 can be provided to the summing block to hold the digital word (e.g., the latest value or voltage level) of the ffo output 308 for a specific amount of time. For example, when the operands are dynamically configured during the operation of the timing circuit 110, one operand can be changed at a time (e.g., the operands are changed in sequence). The hold signal 306 can hold the digital word of the ffo output 308 during the sequential change of the operands until all the changes to the operands are complete. In response to completing the change of the operands, the hold applied by the hold signal 306 can be released, and the summing module 300 can sum a new set of results from the application of the new operands to update the ffo output 308. Thus, a change in the fractional frequency offset signal or the operands does not prematurely change the ffo output 308. Additionally, holding the digital word of the ffo output 308 during the change of the operands can avoid phase and frequency transients on the APLL or FOD output clock.

[0033] Figure 4 FIG. is a diagram showing components in a cross-coupled timing synchronization platform in one embodiment. Figure 4 The description of can refer to Figures 1 to 3 the components shown. Figure 4 An example implementation of DPLL 210 and APLL 206 is shown, where the fb_ffo signal is provided to DPLL 210. APLL 206 may include a phase frequency detector (PFD) and charge pump (CP) circuit 412, a low pass filter (LPF) 414, a voltage controlled oscillator (VCO 416), and a multi-mode divider (MMD) 418. A scaler 420 and a sigma-delta modulator (SDM) 422 may be connected between DPLL 210 and APLL 206.

[0034] DPLL 210 may include a phase detector 402, a loop filter 404, an MMD 406, a scaler 408, and an SDM410. The scaler 408 may scale up or down a nominal fractional division value to produce a scaled fractional division value 409. The scaled fractional division value signal 409 may be input to the SDM 410. The SDM 410 may convert the scaled fractional division value signal 409 into a digital signal 411 that alternates between two integer values that on average equal the scaled fractional division value of signal 409. The digital signal 411 may be provided to the MMD 406. The MMD 406 may divide a feedback signal (“fb”) (i.e., the out_clk0 signal output by APLL 206) by the value of the digital signal 411 from the SDM 410, and the result may be another digital signal 407. The digital signal 407 may be provided as a feedback signal to the phase detector 402 in DPLL 210.

[0035] The phase detector 402 may determine the phase difference between ref_ckl0 and the digital signal 407. This difference may be passed through the loop filter 404 to generate a fractional frequency offset signal (e.g., Figure 2in ffo0). The loop filter 404 can provide proportional and integral (PI) control for the difference to correct the error. The fractional frequency offset signal generated by the DPLL 210 can be provided to the scaler 420. The scaler 420 can amplify or reduce the nominal fractional division value to generate a scaled fractional division value signal 421. The scaled fractional division value signal 421 can be input to the SDM 422. The SDM 422 can convert the scaled fractional division value signal 421 into a digital signal 423 that alternates between two integer values that average to the scaled fractional division value of the signal 421. The digital signal 423 can be provided to the MMD 418. The MMD 418 can divide the feedback signal (“fb”) (i.e., the out_clk0 signal output by the APLL 206) by the value of the digital signal 423 from the SDM 422, and the result can be another digital signal 419. The digital signal 419 can be provided to the PFD and CP circuit 412. The nominal fractional division value 424 of the DPLL 210 can be input to the scaler 408. The nominal fractional division value 426 of the APLL 206 can be input to the scaler 420.

[0036] Focusing on the APLL 206, the PFD and CP circuit 412 can determine the phase and frequency difference between the reference clock signal received from the LO 202 and the digital signal 419. The phase and frequency difference can pass through the LPF 414 and then enter the VCO 416 for adjusting and / or generating the output clock signal out_clk0. The output clock signal out_clk0 can be fed back to the DPLL 210. By using the scaler 408 and the SDM 410 to process the fb_ffo signal, the fractional division ratio of the MMD 406 can be variable instead of constant. Since the fb_ffo signal is dynamically programmable during the operation of the timing circuit 110, the frequency of the output clock signal out_clk0 can be controlled by the programmable fb_ffo signal instead of being controlled only based on ref_clk0.

[0037] Figure 5 is a diagram showing an example application of a cross-coupled timing synchronization platform in one embodiment. Figure 5 For the description of Figures 1 to 4 the components shown. An example application of the timing circuit 110 is as Figure 5 shown. In Figure 5Among them, DPLLs 212 and 214 are disabled, and DPLLs 210 and 216 are enabled. When DPLLs 212 and 214 are disabled, the summing module cannot use or access the ffo1 and ffo2 signals. DPLL 210 can be locked to or synchronized with ref_clk0. The summing module 230 can receive the ffo0 signal from DPLL 210, and apply an "addition" operand to the ffo0 signal to generate a signal 502 to drive APLL 206. The signal 502 can be the sum generated by the summing module 230. In Figure 5 In the example shown, since the summing module 230 performs an "addition" operand on the ffo0 signal without any other operations, the signal 502 can indicate the ppm value indicated by the ffo0 signal. The output clock signal out_clk0 from APLL 206 can be locked to or synchronized with ref_clk0 because DPLL 210 is locked to ref_clk0, and the only operand applied in the summing module 230 is the addition of the ffo0 signal, which is also locked to ref_clk0. The output clock signal out_clk0 can be provided to FODs 220, 222, and 224. Figure 5 The operand of the blank box in the summing module shown is an operand set to "block" or "zero out".

[0038] FOD 220 can divide the APLL clock (out_clk0) by a constant fractional division ratio such that out_clk1 is also locked to or synchronized with ref_clk0. As long as the summing module 232 does not receive any fractional frequency offset signals, Out_clk1 can remain locked to ref_clk0. Moving on to the summing module 234, the summing module 234 can receive the ffo0 signal and an associated subtraction operand from DPLL 210. The summing module 234 can apply the "subtraction" operand to the ffo0 signal to generate a signal 504, which can be the sum generated by the summing module 234. In Figure 5 In the example shown, since the summing module 234 performs a "subtraction" operand on the ffo0 signal without any other operations, the signal 504 can indicate the negative value of the ppm value indicated by the ffo0 signal. Since FOD 222 removes ffo0 based on the signal 504, the output clock signal out_clk2 of FOD 222 can be locked to LO 202.

[0039] Continuing to DPLL 216, DPLL 216 can receive the input clock ref_clk3 and output the ffo3 signal that can be locked to ref_clk3. The summing module 236 can receive the ffo3 signal and the associated subtraction operand from DPLL 216, as well as the addition operand associated with the ffo3 signal from DPLL 216. The summing module 236 can apply the "subtraction" operand to the ffo0 signal and the "addition" operand to the ffo3 signal to generate the signal 506, which can be the sum of the ppm values indicated by the ffo0 signal and the ffo3 signal. Since the "subtraction" operand is applied to the ffo0 signal, the signal 506 can be the result of subtracting the ppm value of the ffo0 signal from the ppm value of the ffo3 signal. As a result of removing the ffo0 signal via the subtraction operand, the output clock signal out_clk3 from FOD 224 can be independent of DPLL 210 and can be locked to ref_clk3 or synchronized with ref_clk3.

[0040] Figure 6 FIG. is another example application of the cross-coupled timing synchronization platform in one embodiment. Figure 6 The description of can refer to Figures 1 to 5 the components shown. Figure 6 Another example application of the timing circuit 110 is shown in. In Figure 6 the example shown, LO 202 can be a crystal oscillator, and APLL 206 can initially be locked to the crystal oscillator. In one aspect, the crystal oscillator can provide the lowest jitter on the APLL output clock out_clk0. However, the crystal oscillator may not provide good temperature stability. To overcome the poor temperature stability, DPLL 210 can be locked to a temperature-compensated crystal oscillator (TCXO). The TCXO can provide better temperature stability, but the jitter may be worse than that of the crystal oscillator. However, since the bandwidth of DPLL 210 is much lower than that of APLL 206, the TCXO jitter can be suppressed. The fb_ffo signal can be provided by an external processor through a serial micropore such that the APLL output clock out_clk0 has a fractional frequency offset that is the sum of the TCXO FFO (e.g., ffo0 in this example) and fb_ffo.

[0041] In Figure 6Among them, DPLLs 210, 212, 214, and 216 are enabled. DPLL 210 can receive the TXCO input clock. DPLL 210 can also receive the fb_ffo signal, which can be multiplied by the feedback of out_clk0, and the product can be compared with the TXCO clock to generate the ffo0 signal. The summing module 230 can receive the ffo0 signal from DPLL 210 and apply an "addition" operand to the ffo0 signal to generate a signal 602 to drive APLL 206. The signal 602 can be the sum generated by the summing module 230. In Figure 6 In the example shown, since the summing module 230 performs an "addition" operand on the ffo0 signal without any other operations, the signal 602 can indicate the ppm value indicated by the ffo0 signal. The output clock signal out_clk0 can be provided to FODs 220, 222, and 224. Figure 6 The operand of the blank box in the summing module shown is an operand set to "block" or "zero".

[0042] DPLL 212 can receive the input clock ref_clk1 and output an ffo1 signal locked to ref_clk1. The summing module 232 can receive the ffo1 signal and the associated addition operand from DPLL 212. The summing module 232 can also receive the fb_ffo signal and the associated subtraction operand. The summing module 232 can apply the "subtraction" operand to the fb_ffo signal and the "addition" operand to the ffo1 signal to generate a signal 604, which can be the sum of the ppm values indicated by the fb_ffo signal and the ffo1 signal. Since the "subtraction" operand is applied to the fb_ffo signal, the signal 604 can be the result of subtracting the ppm value of the fb_ffo signal from the ppm value of the ffo1 signal. As a result of removing the fb_ffo signal via the subtraction operand, the output clock signal out_clk1 from FOD 220 can be locked to ref_clk1. Note that by subtracting the fb_ffo signal, the timing channel formed by DPLL 212 and FOD 220 can have additional stability from the TCXO clock (e.g., via the out_clk0 signal), but will not have the modulation from the fb_ffo signal.

[0043] In Figure 6In the example shown, DPLL 214 and DPLL 216 can form a SyncE / PTP pair, where the SyncE fractional frequency offset can be added to the PTP fractional frequency offset to achieve stability. Additionally, both DPLLs 214 and 216 can have additional stability from the TCXO, but will not have modulation from the fb_ffo signal. DPLL 214 can receive the SyncE clock SyncE_clk_in, and the output can be the ffo2 signal locked to SyncE_clk_in. Summing module 234 can receive the ffo2 signal and the associated addition operand from DPLL 214. Summing module 234 can also receive the fb_ffo signal and the associated subtraction operand. Summing module 234 can apply the "subtraction" operand to the fb_ffo signal and the "addition" operand to the ffo2 signal to produce signal 606, which can be the sum of the ppm values indicated by the fb_ffo signal and the ffo2 signal. Since the "subtraction" operand is applied to the fb_ffo signal, signal 606 can be the result of subtracting the ppm value of the fb_ffo signal from the ppm value of the ffo2 signal. As a result of removing the fb_ffo signal via the subtraction operand, the output clock signal SyncE_clk_out from FOD 222 can be locked to SyncE_clk_in.

[0044] DPLL 216 can receive the PTP clock PTP_clk_in, and the output can be the ffo3 signal locked to PTP_clk_in. Summing module 236 can receive the ffo3 signal and the associated addition operand from DPLL 216. Summing module 236 can also receive the ffo2 signal and the associated addition operand from DPLL 214. Summing module 236 can also receive the fb_ffo signal and the associated subtraction operand. Summing module 236 can apply the "subtraction" operand to the fb_ffo signal, the "addition" operand to the ffo2 signal, and the "plus" operand to the ffo3 signal to produce signal 608, which can be the sum of the ppm values indicated by the fb_ffo signal, the ffo2 signal, and the ffo3 signal. Since the "subtraction" operand is applied to the fb_ffo signal, signal 608 can be the result of subtracting the ppm value of the fb_ffo signal from the sum of the ppm values of the ffo2 and ffo3 signals. As a result of removing the fb_ffo signal via the subtraction operand, the output clock signal PTP_ck_out from FOD 224 can be locked to PTP_ck_in.

[0045] Figure 7FIG. 0 is a flow diagram of a process for implementing a cross-coupled timing synchronization platform in one embodiment. Process 700 may include one or more operations, actions, or functions, shown as one or more of blocks 702, 704, 706, and / or 708. Although shown as discrete blocks, various blocks may be divided into additional blocks, combined into fewer blocks, deleted, executed in a different order, or executed in parallel, depending on the desired implementation.

[0046] Process 700 may be executed by a timing circuit, such as timing circuit 110 described herein. Process 700 may begin at block 702. At block 702, the timing circuit may receive a plurality of reference clock signals. Process 700 may proceed from block 702 to block 704. At block 704, the timing circuit may use the plurality of reference clock signals to generate at least one fractional frequency offset signal.

[0047] Process 700 may proceed from block 704 to block 706. At block 706, the timing circuit may apply at least one operand to the at least one fractional frequency offset signal. In one embodiment, the at least one operand may include an addition operand, a subtraction operand, and a block operand. In one embodiment, the timing circuit may multiply a feedback fractional frequency offset signal by a feedback of at least one of the plurality of output clock signals to generate at least one fractional frequency offset signal. In one embodiment, the timing circuit may apply at least one operand to a fractional frequency offset signal generated by a set of digital phase-locked loops (DPLLs) enabled in the timing circuit.

[0048] Process 700 may proceed from block 706 to block 708. At block 708, the timing circuit may determine the sum of the results of the application of the at least one operand to the at least one fractional frequency offset signal to generate a plurality of signals that control the frequencies of the plurality of output clock signals synchronized with the plurality of reference clock signals. In one embodiment, the timing circuit may apply at least one operand to the feedback fractional frequency offset signal and determine the sum of the result of applying the at least one operand to the feedback fractional frequency offset signal and the result of applying at least one operand to at least one fractional frequency offset signal to generate a plurality of signals.

[0049] In one embodiment, the timing circuit may hold the plurality of signals at a constant voltage level. The timing circuit may receive an update to at least one operand. The timing circuit may apply the at least one updated operand to the at least one fractional frequency offset signal. The timing circuit may release the hold on the plurality of signals.

[0050] The flowcharts and block diagrams in the figures illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent an instruction module, segment, or portion that includes one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the blocks may occur out of the order shown in the figures. For example, two blocks shown in succession may, depending on the functionality involved, actually be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order. It will also be noted that each block of the block diagrams and / or flowchart, and combinations of blocks in the block diagrams and / or flowchart, can be implemented by a system based on dedicated hardware that performs the specified functions or acts, or a combination of dedicated hardware and computer instructions.

[0051] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an", and "the" also include the plural forms unless the context clearly dictates otherwise. It should be further understood that when the terms "comprises" and / or "comprising" are used in this specification, they specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0052] The corresponding structures, materials, acts, and equivalents of all means or step plus function elements, if any, in the following claims are intended to include any structure, material, or act that performs the function in combination with other claimed elements as specifically claimed. The embodiments disclosed herein are presented for purposes of illustration and description but are not intended to be exhaustive or to limit the invention to the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.

Claims

1. A semiconductor device, comprising: A first timing channel is formed by an analog phase-locked loop APLL, a first digital phase-locked loop DPLL and a first summing module; as well as The second timing channel is formed by a fractional output divider FOD, a second digital phase-locked loop DPLL and a second summing module, wherein: The first summing module is configured as follows: Applies at least one operand to one or more of the following: a first fractional frequency offset signal output by the first DPLL; and a second fractional frequency offset signal output by the second DPLL; and summing the results of the application of the at least one operand by the first summing module to generate a first signal that controls a frequency of a first clock signal output by the APLL; and The second summing module is configured as: Apply the at least one operand on one or more of: the first fractional frequency offset signal output by the first DPLL; and the second fractional frequency offset signal output by the second DPLL; and Results of the application of the at least one operand by the second summing module are summed to generate a second signal that controls a frequency of a second clock signal output by the FOD.

2. The semiconductor device according to claim 1, wherein the first summing module is further configured as: The at least one operand is applied on a feedback fractional frequency offset signal, wherein summing the result of the applying of the at least one operand comprises a result of applying the at least one operand to the feedback fractional frequency offset signal.

3. The semiconductor device according to claim 1, wherein the first DPLL is configured as: multiplying a feedback fractional frequency offset signal with feedback of the first clock signal output by the APLL to generate a digital signal, wherein the feedback fractional frequency offset signal is variable; determining a difference between the digital signal and an input clock signal; as well as The difference is used to generate the first fractional frequency offset signal.

4. The semiconductor device according to claim 1, wherein the at least one operand comprises: Addition operands; subtraction operand; as well as Block operand.

5. The semiconductor device according to claim 1 , wherein in response to the second DPLL being disabled, the second DPLL is disabled: The first summing module has no access to the second fractional frequency offset signal; and The first summation module is configured to apply the at least one operand on the first fractional frequency offset signal output by the first DPLL.

6. The semiconductor device according to claim 1, wherein the first summing module is configured as: maintaining the first signal at a constant voltage level; receiving an update to the at least one operand; Apply at least one updated operand on one or more of the following: the first fractional frequency offset signal output by the first DPLL; and the second fractional frequency offset signal output by the second DPLL; and releasing the holding of the first signal.

7. The semiconductor device according to claim 1, further comprising: A third timing channel is formed by another FOD, a second DPLL, and a third summing module, wherein the third summing module is configured as: Apply the at least one operand on one or more of: the first fractional frequency offset signal output by the first DPLL; the second fractional frequency offset signal output by the second DPLL; and a third fractional frequency offset signal output by the third DPLL; as well as Results of the application of the at least one operand by the third summing module are summed to generate a third signal that controls a frequency of a third clock signal output by the another FOD.

8. A system comprising: a first set of transceivers configured to receive input data and output a plurality of reference clock signals; a second set of transceivers configured to receive a plurality of output clock signals and output a set of synchronous data; as well as A timing circuit, comprising at least an analog phase-locked loop APLL, a plurality of digital phase-locked loops DPLL and a plurality of fractional output frequency dividers FOD, wherein the timing circuit is configured as follows: receiving the plurality of reference clock signals; generating at least one fractional frequency offset signal using the plurality of reference clock signals; applying at least one operand on the at least one fractional frequency offset signal; summing the results of applying the at least one operand to the at least one fractional frequency offset signal to generate a plurality of signals that control the frequencies of the plurality of output clock signals; as well as The plurality of signals are transmitted to the second group of transceivers.

9. The system of claim 8, wherein the timing circuit is further configured to: applying the at least one operand on the feedback fractional frequency offset signal; and A result of applying the at least one operand to a feedback fractional frequency offset signal and a sum of the result of applying the at least one operand to the at least one fractional frequency offset signal are summed to generate the plurality of signals.

10. The system of claim 8, wherein the timing circuit is configured to: The feedback fractional frequency offset signal is multiplied with feedback of at least one of the plurality of output clock signals to generate the at least one fractional frequency offset signal.

11. The system of claim 8, wherein the at least one operand comprises: Addition operands; subtraction operand; as well as Block operand.

12. The system of claim 8, wherein: The plurality of DPLLs include an enabled DPLL and a disabled DPLL; A fractional frequency offset signal generated by the disabled DPLL is inaccessible; and The applying of the at least one operand to the at least one fractional frequency offset signal comprises applying the at least one operand to a fractional frequency offset signal generated by the enabled DPLL.

13. The system of claim 8, wherein the timing circuit is configured to: maintaining the plurality of signals at a constant voltage level; receiving an update to the at least one operand; applying at least one updated operand on the at least one fractional frequency offset signal; and The holding of the plurality of signals is released.

14. The system of claim 8, wherein the timing circuit comprises a plurality of summing modules configured to apply the at least one operand on the at least one fractional frequency offset signal and sum the results of applying the at least one operand to the at least one fractional frequency offset signal to generate the plurality of signals.

15. A method for operating a timing circuit, the method comprising: receiving a plurality of reference clock signals; generating at least one fractional frequency offset signal using the plurality of reference clock signals; applying at least one operand on the at least one fractional frequency offset signal; as well as A determination is made to sum the results of applying the at least one operand to the at least one fractional frequency offset signal to generate a plurality of signals that control the frequencies of a plurality of output clock signals synchronized with the plurality of reference clock signals.

16. The method according to claim 15, further comprising: applying the at least one operand on the feedback fractional frequency offset signal; as well as A result of applying the at least one operand to a feedback fractional frequency offset signal and a sum of the result of applying the at least one operand to the at least one fractional frequency offset signal are summed to generate the plurality of signals.

17. The method according to claim 15, further comprising: The feedback fractional frequency offset signal is multiplied with feedback of at least one of the plurality of output clock signals to generate the at least one fractional frequency offset signal.

18. The method of claim 15, wherein the at least one operand comprises: Addition operands; subtraction operand; as well as Block operand.

19. The method of claim 15, wherein applying the at least one operand on the at least one fractional frequency offset signal comprises: The at least one operand is applied on a fractional frequency offset signal generated by a set of digital phase locked loops (DPLL) enabled in a timing circuit.

20. The method of claim 15, further comprising: maintaining the plurality of signals at a constant voltage level; receiving an update to the at least one operand; applying at least one updated operand on the at least one fractional frequency offset signal; as well as The holding of the plurality of signals is released.

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