Sampling circuit, analog-to-digital conversion method, analog-to-digital converter, chip and electronic equipment

Abstract

The embodiment of the invention provides a sampling circuit, an analog-to-digital conversion method, an analog-to-digital converter, a chip and electronic equipment, the sampling circuit comprises a sampling module, a common-mode offset module and a sampling control module, the sampling module is used for outputting a first sampling charge signal and a second sampling charge signal, the common-mode offset module is used for outputting a first common-mode offset charge signal and a second common-mode offset charge signal, and the sampling control module is used for controlling the charge quantity range of the first sampling charge signal and the second sampling charge signal and / or controlling the charge quantity of the first common-mode offset charge signal and the second common-mode offset charge signal. According to the invention, the equivalent range of the input signal is matched with the input range of the analog-to-digital converter in a charge common-mode offset mode, so that the conversion precision of the analog-to-digital converter is improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a sampling circuit, an analog-to-digital conversion method, an analog-to-digital converter, a chip and an electronic device. Background Art

[0002] At present, fully differential input analog-to-digital converters are widely used in high-precision measurement scenarios because they can effectively suppress common-mode noise. In related technologies, fully differential input analog-to-digital converters usually have the ability to measure positive half signals and negative half signals, but in some scenarios, if the voltage difference between the actual two differential input signals is fixed to a positive value or a negative value, the measurement capability of the positive half signal or the measurement capability of the negative half signal of the fully differential input analog-to-digital converter will not be utilized.

[0003] For example, the input range of a fully differential input analog-to-digital converter is -5V to +5V. If the input differential voltage range is 0V to 5V, the measurement capability of the negative half signal of the fully differential input analog-to-digital converter will not be utilized, which results in the actual range of the input signal not corresponding to the input range of the analog-to-digital converter and the measurement accuracy cannot be improved. Summary of the invention

[0004] In view of the above problems, the embodiments of the present application provide a sampling circuit, an analog-to-digital conversion method, an analog-to-digital converter, a chip and an electronic device to solve the above technical problems.

[0005] In a first aspect, an embodiment of the present application provides a sampling circuit, the sampling circuit being used to output a first sampling integrated charge signal and a second sampling integrated charge signal to an integration circuit of an analog-to-digital converter, including:

[0006] A sampling module, the sampling module is used to sample the first differential input voltage and the second differential input voltage in a sampling phase, and output a first sampled charge signal and a second sampled charge signal with opposite polarities and equal charge amounts in a conversion phase;

[0007] A common mode offset module, the common mode offset module is used to output a first common mode offset charge signal and a second common mode offset charge signal in a conversion phase;

[0008] A sampling control module, the sampling control module is used to control the charge amount range of the first sampling charge signal and the second sampling charge signal, and / or control the charge amount size of the first common-mode offset charge signal and the second common-mode offset charge signal;

[0009] The charge amount of the first sampling integrated charge signal is equal to the sum of the first common-mode offset charge signal and the first sampling charge signal, and the charge amount of the second sampling integrated charge signal is equal to the sum of the second common-mode offset charge signal and the second sampling charge signal.

[0010] In a second aspect, the present application provides an analog-to-digital conversion method, including:

[0011] Determine the amplification factor of the sampling module and the bias level of the common-mode offset module according to the original voltage difference range of the input signal and the preset voltage difference input range of the analog-to-digital converter;

[0012] Control the sampling module and the common-mode offset module according to the amplification factor of the sampling module and the bias level of the common-mode offset module, so as to change the charge quantity range of the first sampling charge signal and the second sampling charge signal output by the sampling module, and change the charge quantity of the first common-mode offset charge signal and the second common-mode offset charge signal output by the common-mode offset module;

[0013] Perform analog-to-digital conversion based on the first sampling integration charge signal and the second sampling integration charge signal. The charge quantity of the first sampling integration charge signal is equal to the sum of the first common-mode offset charge signal and the first sampling charge signal, and the charge quantity of the second sampling integration charge signal is equal to the sum of the second common-mode offset charge signal and the second sampling charge signal.

[0014] In a third aspect, the present application provides an analog-to-digital converter, including the sampling circuit as in the first aspect.

[0015] In a fourth aspect, an embodiment of the present application further provides a chip, including the sampling circuit as in the third aspect.

[0016] In a fifth aspect, an embodiment of the present application further provides an electronic device, including the chip as in the fourth aspect.

[0017] By adding a common-mode offset module and a sampling control module to the sampling circuit of the analog-to-digital converter in the present application, the sampling control module is used to control the charge quantity range of the first sampling charge signal and the second sampling charge signal, and / or the sampling control module is used to control the magnitudes of the first sampling charge signal and the second sampling charge signal, so as to change the charge quantity range of the first sampling integration charge signal and the second sampling integration charge signal, so that the charge quantity ranges of the first sampling integration charge signal and the second sampling integration charge signal correspond to the charge quantity range of the feedback charge signal of the analog-to-digital converter, which is beneficial to making the equivalent range of the input signal correspond to the input range of the analog-to-digital converter, and finally improving the conversion accuracy of the analog-to-digital converter.

[0018] These aspects or other aspects of the present application will be more clearly understood in the following description of the embodiments. Description of the Drawings

[0019] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0020] Figure 1 Shows a schematic diagram of a Sigma-Delta analog-to-digital converter in the related art.

[0021] Figure 2 Shows a schematic diagram of a sampling circuit in an embodiment of the present application.

[0022] Figure 3 Shows a schematic diagram of a feedback circuit in an embodiment of the present application.

[0023] Figure 4 Shows a schematic diagram of an integration circuit in an embodiment of the present application.

[0024] Figure 5 Shows a schematic diagram of a quantizer in an embodiment of the present application.

[0025] Figure 6 Shows another schematic diagram of a sampling circuit in an embodiment of the present application.

[0026] Figure 7 Shows another schematic diagram of a sampling circuit in an embodiment of the present application.

[0027] Figure 8 Shows another schematic diagram of a sampling circuit in an embodiment of the present application.

[0028] Figure 9 Shows another schematic diagram of a sampling circuit in an embodiment of the present application.

[0029] Figure 10 Shows a schematic flowchart of an analog-to-digital conversion method in an embodiment of the present application.

[0030] Among them, 100 is the sampling circuit, 200 is the feedback circuit, 300 is the integration circuit, 400 is the quantizer, 10 is the sampling module, 20 is the common-mode offset module, and 30 is the sampling control module;

[0031] The first differential input voltage VIP, the second differential input voltage VIN, the first reference voltage VREFP, the second reference voltage VREFN, the first sampled charge signal Qsp, the second sampled charge signal Qsn, the first common-mode offset charge signal Qdp, the second common-mode offset charge signal Qdn, the first sampled integration charge signal Qip, the second sampled integration charge signal Qin, the first feedback charge signal Qrp, the second feedback charge signal Qrn, the first differential integration voltage VOP, the second differential integration voltage VOP;

[0032] The first feedback capacitor Cf1, the second feedback capacitor Cf2, the first feedback switch Sf1, the second feedback switch Sf2, the third feedback switch Sf3, the fourth feedback switch Sf4, the first integration capacitor CI1, the second integration capacitor CI2, the first integration switch SI1, the second integration switch SI2, the third integration switch SI3, the fourth integration switch SI4, the operational amplifier OP, the comparator COMP;

[0033] The first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the first adjustable sampled capacitor Cs1, the second adjustable sampled capacitor Cs2, the fifth switch S5, the sixth switch S6, the seventh switch S7, the eighth switch S8, the first adjustable common-mode offset capacitor Cd1, the second adjustable common-mode offset capacitor Cd2. Detailed implementation manners

[0034] The following details the implementation manners of the present application. Examples of the implementation manners are shown in the accompanying drawings, where the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions throughout. The implementation manners described below with reference to the accompanying drawings are exemplary only for explaining the present application and should not be construed as a limitation to the present application.

[0035] To enable those skilled in the art of this technology to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of protection of the present application.

[0036] In the embodiments of the present application, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0037] Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or apparatus comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or apparatus. Without further limitation, an element qualified by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

[0038] In the description of the embodiments of the present application, words such as "example" or "for example" are used to give examples, explanations or descriptions. Any embodiment or design solution described as "for example" or "for instance" in the embodiments of the present application is not construed as being more preferred or having more advantages than another embodiment or design solution. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner.

[0039] In addition, "a plurality of" in the embodiments of the present application means two or more. In view of this, "a plurality of" in the embodiments of the present application can also be understood as "at least two". "At least one" can be understood as one or more, for example, understood as one, two or more. For example, including at least one means including one, two or more, and it does not limit which ones are included. For example, including at least one of A, B, and C, then what can be included are A, B, C, A and B, A and C, B and C, or A, B, and C.

[0040] It should be noted that in the embodiments of the present application, "and / or" describes the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / ", unless otherwise specified, generally represents an "or" relationship between the associated objects before and after.

[0041] It should be pointed out that "connection" in the embodiments of the present application can be understood as electrical connection, and the connection of two electrical components can be a direct or indirect connection between the two electrical components. For example, when A is connected to B, it can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0042] In the circuit structure provided by the embodiments of the present application, nodes such as the first node and the second node do not represent actually existing components, but represent the convergence points of relevant couplings in the circuit diagram. That is to say, these nodes are nodes equivalent to the convergence points of relevant couplings in the circuit diagram.

[0043] Currently, since fully differential input analog-to-digital converters can effectively suppress common-mode noise, they are widely used in high-precision measurement scenarios. Refer to Figure 1 ,Figure 1 FIG. 1 shows a schematic diagram of a Sigma-Delta analog-to-digital converter in the related art. The Sigma-Delta analog-to-digital converter includes a sampling circuit, a feedback circuit, an integrating circuit, and a quantizer. Among them, the sampling circuit is connected to the differential input signal Vip and the differential input signal Vin, and the feedback circuit is connected to the differential reference voltages Vrefp and Vrefn.

[0044] During the operation of the Sigma-Delta analog-to-digital converter, in the sampling stage of each measurement period, the sampling capacitor Cs in the sampling circuit will be charged based on the differential input signal Vip and the differential input signal Vin. And in the conversion stage of each measurement period after switching the input, the sampling circuit will output two charge signals: -(Vip - Vin)*Cs and -(Vin - Vip)*Cs. The feedback circuit can output two feedback charge signals with a charge amount of ±(Vrefp - Vrefn)*Cf and ±(Vrefn - Vrefp)*Cf. The “±” is determined by the conversion code values “0” and “1” output by the quantizer in the previous measurement period. The integrating circuit can integrate the charges output by the sampling circuit and the feedback circuit in the conversion stage of each measurement period and output the differential integrated voltage Vop and the differential integrated voltage Von. Finally, the quantizer outputs the conversion code value of the current measurement period by comparing the magnitudes of Vop and Von in the current measurement period, so as to make the differential integrated voltage Vop and the differential integrated voltage Von approach each other in multiple measurement periods through feedback control of the feedback circuit.

[0045] For example, taking the case where the sizes of the sampling capacitor in the sampling circuit, the feedback capacitor in the feedback circuit, and the integrating capacitor in the integrating circuit are all equal as an example, assuming Vip = 3.75V, Vin = 2.5V, Vrefp = 5V, and Vrefp = 0V:

[0046] In the first measurement period, the charge amounts output by the sampling circuit to the integrating circuit are respectively -(Vip - Vin)*Cs and -(Vin - Vip)*Cs. The differential integrated voltage Vop output by the integrating circuit is Vip - Vin = 1.25V, and the differential integrated voltage Von is Vin - Vip = -1.25V. Since Vop > Von, the quantizer outputs a conversion code value of 1.

[0047] In the second measurement period, the charge amounts output by the sampling circuit to the integrating circuit are respectively -(Vip - Vin)*Cs,

[0048] -(Vin - Vip)*Cs. At the same time, the feedback circuit feeds back according to the conversion code value “1” in the previous measurement period respectively

[0049] +(Vrefp - Vrefn)*Cf and -(Vrefn - Vrefp)*Cf. The differential integrated voltage Vop output by the integration circuit is Vop = 1.25+(3.75 - 2.5)-5 = -2.5V, and the differential integrated voltage Von is Von = -1.25-(3.75 - 2.5)+5 = 2.5V.

[0050] Since Vop < Von, the conversion code value output by the quantizer is 0.

[0051] In the third measurement period, the amounts of charge output by the sampling circuit to the integration circuit are respectively -(Vip - Vin)*Cs,

[0052] -(Vin - Vip)*Cs. At the same time, according to the conversion code value "0" in the previous measurement period, the feedback circuit respectively feeds back

[0053] -(Vrefp - Vrefn)*Cf and +(Vrefn - Vrefp)*Cf. The differential integrated voltage Vop output by the integration circuit is Vop = -2.5+(3.75 - 2.5)+5 = 3.75V, and the differential integrated voltage Von is Von = 2.5-(3.75 - 2.5)-5 = -3.75V.

[0054] Since Vop > Von, the conversion code value output by the quantizer is 1.

[0055] By analogy, it can be seen that through feedback, the quantizer will make the differential integrated voltage Vop and the differential integrated voltage Von approach each other in multiple measurement periods. Therefore, in multiple measurement periods, the amounts of charge accumulated by the integration capacitor in the integration circuit are close to 0 and can be ignored after feedback control. After multiple measurement periods, the differential input signal Vip, the differential input signal Vin, the differential reference voltage Vrefp, and the differential reference voltage Vrefn satisfy the following relational expression:

[0056] (Vip - Vin)×Cs×(X1 + X2) = (Vrefp - Vrefn)×Cf×X1-(Vrefp - Vrefn)×Cf×X2

[0057] Among them, Cs is the capacitance value of the sampling capacitor in the sampling circuit, Cf is the capacitance value of the feedback capacitor in the feedback circuit, X1 is the number of times of the feedback positive charge signal +(Vrefp - Vrefn)*Cf, and X2 is the number of times of the feedback negative charge signal -(Vrefp - Vrefn)*Cf.

[0058] Therefore, the voltage difference between the differential input signal Vip and the differential input signal Vin can be calculated according to the following formula:

[0059]

[0060] It can be seen that in the code values (such as 011100..1100) output by the quantizer in multiple measurement cycles, 1 represents the number of times the positive charge signal +(Vrefp - Vrefn)*Cf is fed back, and 0 represents the number of times the negative charge signal -(Vrefp - Vrefn)*Cf is fed back. Therefore, finally, the voltage difference between the differential input signal Vip and the differential input signal Vin can be obtained according to the conversion code value output by the quantizer.

[0061] At the same time, it should also be noted that generally, a Sigma-Delta analog-to-digital converter can only perform analog-to-digital conversion on input voltages that meet its input range. For example, assuming Figure 1 the sampling capacitor Cs and the feedback capacitor Cf are of equal size, Vrefp = 5V, and Vrefp = 0V, then the Sigma-Delta analog-to-digital converter can only perform analog-to-digital conversion on the differential input signals Vip and Vin with a voltage difference between -5V and +5V.

[0062] For example, assume Vip = 6V and Vin = 0V. In the first measurement cycle, the differential integrated voltage Vop output by the integration circuit is 6V, the differential integrated voltage Von is -6V, and since Vop > Von, the conversion code value output by the quantizer is 1; in the second measurement cycle, the differential integrated voltage Vop output by the integration circuit is (6 + 6 - 5) = 7V, and the differential integrated voltage Von is (-6 - 6) + 5V = -7V...

[0063] It can be seen that if the voltage difference between the differential input signals Vip and Vin exceeds the input range of the Sigma-Delta analog-to-digital converter, the integrated voltage output by the integration circuit does not approach 0 as the measurement cycle increases, and the conversion code value output by the quantizer in each measurement cycle is always 1. Therefore, the Sigma-Delta analog-to-digital converter cannot perform analog-to-digital conversion on input voltages that exceed its input range.

[0064] At the same time, the above-mentioned fully differential input Sigma-Delta analog-to-digital converter usually has the measurement ability for positive half signals and negative half signals. For example, taking Vrefp = 5V and Vrefp = 0V as an example, the measurement ability of the positive half signal of the Sigma-Delta analog-to-digital converter means that it can perform analog-to-digital conversion on the differential input signals Vip and Vin with a voltage difference between 0 and 5V, and the measurement ability of the negative half signal of the Sigma-Delta analog-to-digital converter means that it can perform analog-to-digital conversion on the differential input signals Vip and Vin with a voltage difference between -5V and 0V.

[0065] However, in some scenarios, if the voltage difference between the differential input signal Vip and the differential input signal Vin is fixed as a positive value or a negative value, the measurement ability of the positive half-signal or the negative half-signal of the fully-differential input Sigma-Delta analog-to-digital converter will not be utilized. For example, in the scenario of measuring the series battery voltage, the voltage of the previous battery must be greater than that of the next battery. Taking the voltage of the previous battery as the differential input signal Vip and the voltage of the next battery as the differential input signal Vin, at this time, the voltage difference between the differential input signal Vip and the differential input signal Vin is fixed as a positive value, so the measurement ability of the negative half-signal of the fully-differential input Sigma-Delta analog-to-digital converter will not be utilized.

[0066] For example, taking the input range of the Sigma-Delta analog-to-digital converter as -5V to 5V and the number of bits N as 5 bits, the quantization level size of the Sigma-Delta analog-to-digital converter is:

[0067]

[0068] At this time, the correspondence between the voltage difference △V between the differential input signal Vip and the differential input signal Vin and the conversion code value is shown in Table 1 below:

[0069] Table 1

[0070] △V Conversion code value -5V ≤ ΔV < -4.6875V 00000 -4.6875V ≤ ΔV < -4.375V 00001 ... ... 0 ≤ ΔV < 0.3125 V 10000 ... ... 4.375V ≤ ΔV < 4.6875V 11110 4.6875V ≤ ΔV < 5V 11111

[0071] It can be seen that if the actual range of the voltage difference △V between the differential input signal Vip and the differential input signal Vin is between 0V and 5V, it only corresponds to half of the input range of the Sigma-Delta analog-to-digital converter. At this time, the range of the conversion code value output by the Sigma-Delta analog-to-digital converter is 10000 to 11111, and the measurement ability of the -5V to 0V negative half-signal of the Sigma-Delta analog-to-digital converter (corresponding to the conversion code value range 00000 to 01111) is not utilized, which will cause the problem that the actual signal range does not match the input range of the Sigma-Delta analog-to-digital converter and the measurement accuracy cannot be improved.

[0072] Therefore, the present application provides a sampling circuit, an analog-to-digital conversion method, an analog-to-digital converter, a chip, and an electronic device, which will be described in detail below.

[0073] First, refer to Figure 2 , Figure 2FIG. 0 shows a schematic diagram of the sampling circuit 100 in an embodiment of the present application. The sampling circuit 100 of the present application can be used as the sampling circuit 100 of an analog-to-digital converter, and the analog-to-digital converter can be, but is not limited to, a Sigma-Delta analog-to-digital converter or a hybrid analog-to-digital converter including a Sigma-Delta analog-to-digital converter. Among them, the analog-to-digital converter includes a sampling circuit 100, a feedback circuit 200, an integration circuit 300, and a quantizer 400. Before introducing the sampling circuit 100 of the present application, the feedback circuit 200, the integration circuit 300, and the quantizer 400 in the analog-to-digital converter will be introduced first.

[0074] Specifically, the feedback circuit 200 can output a first feedback charge signal Qrp and a second feedback charge signal Qrn to the integration circuit 300 during the conversion stage of the measurement period. The polarities of the first feedback charge signal Qrp and the second feedback charge signal Qrn are controlled by the code value output by the quantizer 400 in the previous period, so that the accumulated charge amount of the integration circuit 300 approaches 0 and can be ignored after multiple measurement periods.

[0075] As an example, refer to Figure 3 , Figure 3 FIG. 10 shows a schematic diagram of the feedback circuit 200 in an embodiment of the present application. Among them, the feedback circuit 200 includes a first feedback capacitor Cf1, a second feedback capacitor Cf2, a first feedback switch Sf1, a second feedback switch Sf2, a third feedback switch Sf3, and a fourth feedback switch Sf4.

[0076] If the first feedback switch Sf1 and the fourth feedback switch Sf4 are closed and the second feedback switch Sf2 and the third feedback switch Sf3 are open during the sampling stage, the accumulated charge amounts of the first feedback capacitor Cf1 and the second feedback capacitor Cf2 are respectively:

[0077] QR1 = (VREFP - VCM) * Cf1

[0078] QR2 = (VREFN - VCM) * Cf2

[0079] Where VCM is the common-mode voltage of the operational amplifier OP.

[0080] During the conversion stage, the second feedback switch Sf2 and the third feedback switch Sf3 are closed, and the first feedback switch Sf1 and the fourth feedback switch Sf4 are open. The accumulated charge amounts of the first feedback capacitor Cf1 and the second feedback capacitor Cf2 change to:

[0081] QR3 = (VREFN - VCM) * Cf1

[0082] QR4 = (VREFP - VCM) * Cf2

[0083] Therefore, during the above switch switching process, the first feedback charge signal Qrp output by the first feedback capacitor Cf1 and the second feedback charge signal Qrn output by the second feedback capacitor Cf2 are respectively:

[0084] Qrp = QR3 - QR1 = (VREFN - VREFP) * Cf1

[0085] Qrn = QR4 - QR2 = (VREFP - VREFN) * Cf2

[0086] Assume that the first reference voltage VREFP is greater than the second reference voltage VREFN. Then, the switch switching process in the above sampling stage and conversion stage can make the first feedback charge signal Qrp a negative charge signal and the second feedback charge signal Qrn a positive charge signal.

[0087] Similarly, if the first feedback switch Sf1 and the fourth feedback switch Sf4 are open, and the second feedback switch Sf2 and the third feedback switch Sf3 are closed during the sampling stage, while the first feedback switch Sf1 and the fourth feedback switch Sf4 are closed, and the second feedback switch Sf2 and the third feedback switch Sf3 are open during the conversion stage, then the first feedback charge signal Qrp output by the first feedback capacitor Cf1 and the second feedback charge signal Qrn output by the second feedback capacitor Cf2 are respectively:

[0088] Qrp = QR3 - QR1 = (VREFP - VREFN) * Cf1

[0089] Qrn = QR3 - QR1 = (VREFN - VREFP) * Cf2

[0090] Assume that the first reference voltage VREFP is greater than the second reference voltage VREFN. Then, the switch switching process in the above sampling stage and conversion stage can make the above first feedback charge signal Qrp a positive charge signal and the second feedback charge signal Qrn a negative charge signal.

[0091] Therefore, by changing the switch sequence logic of the first feedback switch Sf1, the second feedback switch Sf2, the third feedback switch Sf3, and the fourth feedback switch Sf4, the polarities of the first feedback charge signal Qrp and the second feedback charge signal Qrn can be changed.

[0092] The integrating circuit 300 can integrate the first feedback charge signal Qrp, the second feedback charge signal Qrn, the first sampled integrating charge signal Qip, and the second sampled integrating charge signal Qin during the conversion stage of each measurement period, and output the first differential integrating voltage VOP and the second differential integrating voltage VOP, so as to facilitate the quantizer 400 to compare the magnitudes of the first differential integrating voltage VOP and the second differential integrating voltage VOP and output the conversion code value of the current measurement period.

[0093] As an example, refer to Figure 4 , Figure 4 which shows a schematic diagram of an integrating circuit in an embodiment of the present application. The integrating circuit 300 includes an operational amplifier OP, a first integrating capacitor CI1, a second integrating capacitor CI2, a first integrating switch SI1, a second integrating switch SI2, a third integrating switch SI3, and a fourth integrating switch SI4.

[0094] In the sampling stage of each measurement period, the second integrating switch SI2 and the fourth integrating switch SI4 are closed, and the first integrating switch SI1 and the third integrating switch SI3 are open. Therefore, the electric charges accumulated in the first integrating capacitor CI1 and the second integrating capacitor CI2 remain unchanged.

[0095] In the conversion stage of each measurement period, the first integrating switch SI1 and the third integrating switch SI3 are closed, and the second integrating switch SI2 and the fourth integrating switch SI4 are open. Therefore, the first integrating capacitor CI1 will integrate the first feedback charge signal Qrp and the first sampled integrating charge signal Qip and output a first differential integrating voltage VOP, and the second integrating capacitor CI2 will integrate the second feedback charge signal Qrn and the second sampled integrating charge signal Qin and output a second differential integrating voltage VOP.

[0096] The quantizer 400 can compare the magnitudes of the first differential integrating voltage VOP and the second differential integrating voltage VOP output by the integrating circuit 300 and output the conversion code value of the current measurement period, so that the feedback circuit 200 can control the polarities of the first feedback charge signal Qrp and the second feedback charge signal Qrn in the next measurement period according to the conversion code value output by the quantizer 400 in the previous measurement period.

[0097] For example, refer to Figure 5 , Figure 5 which shows a schematic diagram of a quantizer in an embodiment of the present application. The quantizer 400 includes a comparator COMP. The non-inverting input terminal of the comparator COMP is connected to the first differential integrating voltage VOP, and the inverting input terminal of the comparator COMP is connected to the second differential integrating voltage VOP. If the first differential integrating voltage VOP is greater than the second differential integrating voltage VOP, the conversion code value output by the comparator in the current measurement period is "1". Therefore, the feedback circuit 200 can output a positive-polarity first feedback charge signal Qrp and a negative-polarity second feedback charge signal Qrn in the next measurement period. After the first integrating capacitor CI1 integrates the first feedback charge signal Qrp and the second integrating capacitor CI2 integrates the second feedback charge signal Qrn, the first differential integrating voltage VOP can be reduced and the second differential integrating voltage VOP can be increased.

[0098] On the contrary, if the first differential integrated voltage VOP is less than the second differential integrated voltage VOP, the conversion code value output by the comparator in the current measurement cycle is "0", so the feedback circuit 200 can output a first feedback charge signal Qrp with a negative polarity and a second feedback charge signal Qrn with a positive polarity in the next measurement cycle. After the first integrating capacitor CI1 integrates the first feedback charge signal Qrp and the second integrating capacitor CI2 integrates the second feedback charge signal Qrn, the first differential integrated voltage VOP can be increased and the second differential integrated voltage VOP can be decreased.

[0099] It can be seen that the quantizer 400 and the feedback circuit 200 can implement negative feedback control on the first differential integration voltage VOP and the second differential integration voltage VOP output by the integration circuit 300, so that the first differential integration voltage VOP and the second differential integration voltage VOP tend to be close in multiple measurement cycles.

[0100] Understandably, the above Figure 5 This is intended to clearly illustrate the exemplary circuit structure of the analog-to-digital converter of the present application and should not be understood as a limitation on the analog-to-digital converter of the present application. The implementation methods of the various circuits of the analog-to-digital converter are not limited thereto. For example, the quantizer 400 may also use a multi-bit comparator or a 1.5bi comparator.

[0101] The sampling circuit 100 of the present application is introduced below. The sampling circuit 100 is used to output a first sampling integrated charge signal Qip and a second sampling integrated charge signal Qin to an integration circuit 300 of an analog-to-digital converter. The sampling circuit 100 includes a sampling module 10, a common-mode offset module 20 and a sampling control module 30.

[0102] Specifically, the sampling module 10 can sample the first differential input voltage VIP and the second differential input voltage VIN in the sampling phase, and output a first sampled charge signal Qsp and a second sampled charge signal Qsn with opposite polarities and equal charge amounts in the conversion phase.

[0103] In some embodiments of the present application, the sampling module 10 may include a signal amplifier (e.g., a programmable gain amplifier), which amplifies the first differential input voltage VIP and the second differential input voltage VIN, so that the sampling control module 30 controls the amplification factor of the signal amplifier on the first differential input voltage VIP and the second differential input voltage VIN, thereby changing the charge range of the first sampling charge signal Qsp and the second sampling charge signal Qsn.

[0104] In some embodiments of the present application, the sampling module 10 may include a variable sampling capacitor with an adjustable capacitance value, so that the sampling control module 30 controls the capacitance value of the variable sampling capacitor, thereby changing the charge range of the first sampling charge signal Qsp and the second sampling charge signal Qsn.

[0105] It is understandable that the sampling module 10 may also include a signal amplifier and a variable sampling capacitor at the same time, so that the sampling control module 30 can simultaneously control the amplification factor of the signal amplifier and the capacitance value of the variable sampling capacitor, thereby changing the charge range of the first sampling charge signal Qsp and the second sampling charge signal Qsn.

[0106] As an example, see Figure 6 , Figure 6 Another schematic diagram of the sampling circuit 100 in the embodiment of the present application is shown, wherein the sampling module 10 includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a first adjustable sampling capacitor Cs1 and a second adjustable sampling capacitor Cs2, wherein the first end of the first switch S1 is used to access the first differential input voltage VIP, and the second end of the first switch S1 is connected to the first end of the first adjustable sampling capacitor Cs1; the first end of the second switch S2 is used to access the second differential input voltage VIN, and the second end of the second switch S2 is connected to the first end of the first adjustable sampling capacitor Cs1; the first end of the third switch S3 is used to access the first differential input voltage VIP, and the second end of the third switch S3 is connected to the first end of the second adjustable sampling capacitor Cs2; the first end of the fourth switch S4 is used to access the second differential input voltage VIN, and the second end of the fourth switch S4 is connected to the first end of the second adjustable sampling capacitor Cs2.

[0107] Specifically, in the sampling phase of each measurement cycle of the analog-to-digital converter, the first switch S1 and the fourth switch S4 are closed, and the second switch S2 and the third switch S3 are opened. At this time, the amount of charge accumulated by the first adjustable sampling capacitor Cs1 and the second adjustable sampling capacitor Cs2 is:

[0108] QS1=(VIP-VCM)*Cs1

[0109] QS2=(VIN-VCM)*Cs2

[0110] In the conversion phase of each measurement cycle, the first switch S1 and the fourth switch S4 are opened, and the second switch S2 and the third switch S3 are closed. At this time, the amount of charge accumulated by the first adjustable sampling capacitor Cs1 and the second adjustable sampling capacitor Cs2 is:

[0111] QS3=(VIN-VCM)*Cs1

[0112] QS4 = (VIP - VCM) * Cs2

[0113] Therefore, during the above switch switching process, the first sampled charge signal Qsp and the second sampled charge signal Qsn output by the sampling module 10 are respectively:

[0114] Qsp = QS3 - QS1 = (VIN - VIP) * Cs1

[0115] Qsn = QS4 - QS2 = (VIP - VIN) * Cs2

[0116] It can be seen that by controlling the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4, the first sampled charge signal Qsp and the second sampled charge signal Qsn representing the voltage difference information between the first differential input voltage VIP and the second differential input voltage VIN can be output.

[0117] Meanwhile, assuming that the actual range of the first differential input voltage VIP is 17.5V - 20V and the actual range of the second differential input voltage VIN is 15V - 17.5V, at this time, the voltage difference range between the first differential input voltage VIP and the second differential input voltage VIN is 0 - 5V. Therefore, the charge amount ranges of the first sampled charge signal Qsp and the second sampled charge signal Qsn are as follows:

[0118] -5V * Cs1 < Qsp < 0

[0119] 0 < Qnp < 5V * Cs1

[0120] It can be seen that when the sampling control module 30 controls the capacitance values of the first adjustable sampling capacitor Cs1 and the second adjustable sampling capacitor Cs2, the charge amount ranges of the first sampled charge signal Qsp and the second sampled charge signal Qsn can be changed.

[0121] The common - mode offset module 20 can sample the first reference voltage VREFP and the second reference voltage VREFN during the sampling stage, and output the first common - mode offset charge signal Qdp and the second common - mode offset charge signal Qdn with opposite polarities and equal charge amounts during the conversion stage.

[0122] Similarly, in some embodiments of the present application, the common - mode offset module 20 may include a signal amplifier (such as a programmable gain amplifier), and the first reference voltage VREFP and the second reference voltage VREFN are amplified by the signal amplifier, so that the sampling control module 30 can control the amplification factors of the signal amplifier for the first reference voltage VREFP and the second reference voltage VREFN, thereby changing the magnitudes of the first common - mode offset charge signal Qdp and the second common - mode offset charge signal Qdn.

[0123] In some embodiments of the present application, the common-mode offset module 20 may include a variable capacitor with an adjustable capacitance value, so that the sampling control module 30 controls the capacitance value of the variable capacitor, thereby changing the magnitude of the first common-mode offset charge signal Qdp and the second common-mode offset charge signal Qdn.

[0124] As an example, see Figure 7 , Figure 7 Another schematic diagram of the sampling circuit 100 in the embodiment of the present application is shown, wherein the sampling module 10 includes a fifth switch S5, a sixth switch S6, a seventh switch S7, an eighth switch S8, a first adjustable common-mode offset capacitor Cd1 and a second adjustable common-mode offset capacitor Cd2; a first end of the fifth switch S5 is used to access the first reference voltage VREFP, and a second end of the fifth switch S5 is connected to a first end of the first adjustable common-mode offset capacitor Cd1; a first end of the sixth switch S6 is used to access the second reference voltage VREFN, and a second end of the sixth switch S6 is connected to a first end of the first adjustable common-mode offset capacitor Cd1; a first end of the seventh switch S7 is used to access the first reference voltage VREFP, and a second end of the seventh switch S7 is connected to a first end of the second adjustable common-mode offset capacitor Cd2; a first end of the eighth switch S8 is used to access the second reference voltage VREFN, and a second end of the eighth switch S8 is connected to a first end of the second adjustable common-mode offset capacitor Cd2.

[0125] Specifically, in the sampling phase of each measurement cycle, the sixth switch S6 and the seventh switch S7 are closed, and the fifth switch S5 and the eighth switch S8 are opened. At this time, the amount of charge accumulated by the first adjustable common-mode offset capacitor Cd1 and the second adjustable common-mode offset capacitor Cd2 is:

[0126] QD1=(VREFN-VCM)*Cd1

[0127] QD2=(VREFP-VCM)*Cd2

[0128] In the conversion phase of each measurement cycle, the sixth switch S6 and the seventh switch S7 are opened, and the fifth switch S5 and the eighth switch S8 are closed. At this time, the amount of charge accumulated by the first adjustable common-mode offset capacitor Cd1 and the second adjustable common-mode offset capacitor Cd2 is:

[0129] QD3=(VREFP-VCM)*Cd1

[0130] QD4=(VREFN-VCM)*Cd2

[0131] Therefore, in the above switching process, the first common-mode offset charge signal Qdp and the second common-mode offset charge signal Qdn output by the sampling module 10 are respectively:

[0132] Qdp=QS3-QS1=(VREFP-VREFN)*Cd1

[0133] Qdn=QS4-QS2=(VREFN-VREFP)*Cd2

[0134] It can be seen that by controlling the fifth switch S5 , the sixth switch S6 , the seventh switch S7 and the eighth switch S8 , a first common-mode offset charge signal Qdp and a second common-mode offset charge signal Qdn with equal charge amounts and opposite polarities can be output.

[0135] Taking VREFP=5V, VREFN=0V as an example, the magnitudes of the first common-mode offset charge signal Qdp and the second common-mode offset charge signal Qdn are as follows:

[0136] Qdp=+5V*Cd1

[0137] Qdn=-5V*Cd2

[0138] Therefore, when the sampling control module 30 controls the capacitance values ​​of the first adjustable common-mode offset capacitor Cd1 and the second adjustable common-mode offset capacitor Cd2 , the charge amounts of the first common-mode offset charge signal Qdp and the second common-mode offset charge signal Qdn can be changed.

[0139] The sampling control module 30 is used to control the charge range of the first sampled charge signal Qsp and the second sampled charge signal Qsn, and / or the sampling control module 30 is used to control the charge size of the first common-mode offset charge signal Qdp and the second common-mode offset charge signal Qdn.

[0140] For example, the sampling control module 30 may control the gain of the signal amplifier in the sampling module 10 and / or the size of the adjustable sampling capacitor, thereby changing the charge range of the first sampling charge signal Qsp and the second sampling charge signal Qsn.

[0141] For another example, the sampling control module 30 can control the gain of the signal amplifier in the common-mode offset module 20 and / or the size of the adjustable capacitor, thereby changing the charge amounts of the first common-mode offset charge signal Qdp and the second common-mode offset charge signal Qdn.

[0142] In the embodiment of the present application, since the charge amount of the first sampled integration charge signal Qip output by the sampling circuit 100 is equal to the sum of the first common-mode offset charge signal Qdp and the first sampled charge signal Qsp, and the charge amount of the second sampled integration charge signal Qin is equal to the sum of the second common-mode offset charge signal Qdn and the second sampled charge signal Qsn, this is equivalent to performing a common-mode offset on the first sampled integration charge signal Qip through the first common-mode offset charge signal Qdp, and performing a common-mode offset on the second sampled integration charge signal Qin through the second common-mode offset charge signal Qdn, which is beneficial to making the charge amount ranges of the first sampled integration charge signal Qip and the second sampled integration charge signal Qin correspond to the charge amount range of the feedback charge signal of the analog-to-digital converter, and finally making the first differential input voltage VIP and the second differential input voltage VIN match the input range of the analog-to-digital converter.

[0143] For example, taking VREFP = 5V and VREFN = 0V as an example, according to the foregoing content, the charge amounts of the first feedback charge signal Qrp, the second feedback charge signal Qrn, the first common-mode offset charge signal Qdp, and the second common-mode offset charge signal Qdn are as follows:

[0144] Qrp = ±5V * Cf1

[0145] Qrn = ±5V * Cf2

[0146] Qdp = +5V * Cd1

[0147] Qdp = -5V * Cd2

[0148] If the actual range of the first differential input voltage VIP is 17.5V to 20V, and the actual range of the second differential input voltage VIN is 15V to 17.5V, at this time, the voltage difference range between the first differential input voltage VIP and the second differential input voltage VIN is 0V to 5V. According to the foregoing content, the charge amount ranges of the first sampled charge signal Qsp and the second sampled charge signal Qsn are as follows:

[0149] -5V * Cs1 < Qsp < 0

[0150] 0 < Qsn < +5V * Cs2

[0151] Assume that under the control of the sampling control module 30, the first adjustable sampling capacitor Cs1, the second adjustable sampling capacitor Cs2, the first adjustable common-mode offset capacitor Cd1, the second adjustable common-mode offset capacitor Cd2, the first feedback capacitor Cf1, and the second feedback capacitor Cf2 satisfy the following relational expressions:

[0152] Cs1 = Cs2 = 2 * Cf1 = 2 * Cf2

[0153] Cf1 = Cf2 = Cd1 = Cd2

[0154] Then, the sum of the first common-mode offset charge signal Qdp and the first sampled charge signal Qsp, and the sum of the second common-mode offset charge signal Qdn and the second sampled charge signal Qsn satisfy the following relational expressions:

[0155] (-5V * 2 * Cf1 + 5V * Cf1) < (Qsp + Qdp) < 0 + 5V * Cf1

[0156] (0 - 5V * Cf1) < (Qsn + Qdn) < (+5V * 2 * Cf1 - 5V * Cf1)

[0157] After simplification, we can obtain:

[0158] -5V * Cf1 < Qsp + Qdp < +5V * Cf1

[0159] -5V * Cf1 < Qsn + Qdn < +5V * Cf1

[0160] That is to say, after the first common-mode offset charge signal Qdp performs a common-mode offset on the first sampled integration charge signal Qip, and the second common-mode offset charge signal Qdn performs a common-mode offset on the second sampled integration charge signal Qin, the charge quantity ranges of the first sampled integration charge signal Qip and the second sampled integration charge signal Qin integrated by the integration circuit 300 are:

[0161] -5V * Cf1 < Qip < +5V * Cf1

[0162] -5V * Cf1 < Qin < +5V * Cf1

[0163] It can be seen that the upper limit value of the charge quantity of the first sampled integration charge signal Qip and the second sampled integration charge signal Qin is +5V * Cf1, and the lower limit value of the charge quantity is -5V * Cf1. And the charge quantity fed back by the first feedback charge signal Qrp and the second feedback charge signal Qrn is +5V * Cf1 or -5V * Cf1. Therefore, at this time, the charge quantity ranges of the first sampled integration charge signal Qip and the second sampled integration charge signal Qin correspond to the charge quantity ranges of the first feedback charge signal Qrp and the second feedback charge signal Qrn, which can make the first differential input voltage VIP and the second differential input voltage VIN match the input range of the Sigma-Delta analog-to-digital converter.

[0164] For example, taking the voltage difference △V between the first differential input voltage VIP and the second differential input voltage VIN as divided at intervals of 0.15625V, the relationship between the voltage difference △V and the first sampled integration charge signal Qip is as shown in Table 2 below:

[0165] Table 2

[0166] △V Qip 0 ≤ ΔV < 0.15625 V -5V*Cf1 ≤ Qip < -4.6875V*Cf1 0.15625V ≤ ΔV < 0.3125 -4.6875V*Cf1 ≤ Qip < -4.375V*Cf1 ... ... 0.234375≤△V<2.5 0 ≤ Qip < 0.3125V * Cf1 ... ... 4.6875V ≤ ΔV < 4.84375V 4.375V*Cf1 ≤ Qip < 4.6875V*Cf1 4.84375V ≤ ΔV < 5V 4.6875VCf1* ≤ Qip < 5V*Cf1

[0167] Similarly, the relationship between the voltage difference △V and the second sampled integration charge signal Qin is shown in the following table:

[0168] Table 3

[0169] △V Qin 0 ≤ ΔV < 0.15625 V 4.6875VCf1* ≤ Qip < 5V*Cf1 0.15625V ≤ ΔV < 0.3125 4.375V*Cf1 ≤ Qip < 4.6875V*Cf1 ... ... 0.234375≤△V<2.5 0 ≤ Qip < 0.3125V * Cf1 ... ... 4.6875V ≤ ΔV < 4.84375V -4.6875V*Cf1 ≤ Qip < -4.375V*Cf1 4.84375V ≤ ΔV < 5V -5V*Cf1 ≤ Qip < -4.6875V*Cf1

[0170] It can be seen from Table 2 and Table 3 that for the voltage difference △V of 0V to 5V, the charge amount ranges of the first sampled integration charge signal Qip and the second sampled integration charge signal Qin correspond to the charge amount range of the feedback charge signal of the analog-to-digital converter. Therefore, the first sampled integration charge signal Qip and the second sampled integration charge signal Qin match the input range of -5V to +5V of the Sigma-Delta analog-to-digital converter.

[0171] Assume that the number of bits of the Sigma-Delta analog-to-digital converter is 5 bits. Then, the relationship between the voltage difference △V between the first differential input voltage VIP and the second differential input voltage VIN and the conversion code value is shown in Table 4 below:

[0172] Table 4

[0173] △V Conversion code value 0 ≤ ΔV < 0.15625V 00000 0.15625V ≤ ΔV < 0.3125 00001 ... ... 0.234375≤△V<2.5 10000 ... ... 4.6875V ≤ ΔV < 4.84375V 111110 4.84375V ≤ ΔV < 5V 111111

[0174] By comparing Table 1 and Table 4, it can be seen that for the voltage difference in the range of 4.6875V ≤ △V < 5V, the solution of the present application can further quantize the voltage difference △V of 4.6875V to 4.84375V as 111110 and the voltage difference △V of 4.84375V to 5V as 111111. Therefore, the conversion accuracy of the analog-to-digital converter is improved.

[0175] In summary, in the present application, a common-mode offset module 20 and a sampling control module 30 are added to the sampling circuit 100 of the analog-to-digital converter. The sampling control module 30 is used to control the charge quantity range of the first sampling charge signal Qsp and the second sampling charge signal Qsn, and / or the sampling control module 30 controls the magnitudes of the first sampling charge signal Qsp and the second sampling charge signal Qsn, thereby changing the charge quantity range of the first sampling integration charge signal Qip and the second sampling integration charge signal Qin, such that the charge quantity ranges of the first sampling integration charge signal Qip and the second sampling integration charge signal Qin correspond to the charge quantity ranges of the first feedback charge signal Qrp and the second feedback charge signal Qrn, which is conducive to matching the equivalent range of the input signal with the input range of the analog-to-digital converter, thereby avoiding the problem that the conversion accuracy of the analog-to-digital converter decreases due to the mismatch between the actual range of the input signal and the input range of the analog-to-digital converter.

[0176] It should be noted that in the above principle description process and in the drawings, the feedback circuit 200 and the common-mode offset module 20 both use the same first reference voltage VREFP and second reference voltage VREFN. This is only to reduce the number of reference voltages to be provided and the corresponding circuits, and should not be construed as a limitation on the feedback circuit 200 and the common-mode offset module 20 of the present application. In some possible embodiments, the feedback circuit 200 and the common-mode offset module 20 may also use different reference voltages. For example, the common-mode offset module 20 is connected to two reference voltages of 0V and 5V, while the feedback circuit 200 is connected to two reference voltages of 0V and 2.5V.

[0177] In some embodiments of the present application, the first differential input voltage VIP is greater than or equal to the second differential input voltage VIN.

[0178] For example, taking the actual range of the first differential input voltage VIP as 15V to 20V and the actual range of the second differential input voltage VIN as 10V to 15V as an example, the voltage difference range between the first differential input voltage VIP and the second differential input voltage VIN is 0V to 10V. It can be seen that the charge quantity ranges of the first sampling charge signal Qsp and the second sampling charge signal Qsn are as follows:

[0179] -10V*Cs1 < Qsp < 0

[0180] 0 < Qsn < +10V*Cs2

[0181] If the first reference voltage VREFP is 5V and the second reference voltage VREFN is 0V, the charge magnitudes of the first feedback charge signal Qrp, the second feedback charge signal Qrn, the first common-mode offset charge signal Qdp, and the second common-mode offset charge signal Qdn are:

[0182] Qrp = ±5V * Cf1

[0183] Qrn = ±5V * Cf2

[0184] Qdp = +5V * Cd1

[0185] Qdp = -5V * Cd2

[0186] Under the control of the sampling control module 30, Cs1 = Cs2 = Cf1 = Cf2 = Cd1 = Cd2. Then, the charge quantity ranges of the first sampled integration charge signal Qip and the second sampled integration charge signal Qin are as follows:

[0187] (-10V * Cf1 + 5V * Cf1) < (Qsp + Qdp) < 0 + 5V * Cf1

[0188] (0 - 5V * 2 * Cf1) < (Qsn + Qdn) < (+10V * Cf1 - 5V * 2 * Cf1)

[0189] That is:

[0190] -5V * Cf1 < Qip < +5V * Cf1

[0191] -5V * Cf1 < Qin < +5V * Cf1

[0192] It can be seen that when the sampling control module 30 controls the capacitance values of the adjustable sampling capacitor, the adjustable common - mode offset capacitor, and the feedback capacitor to be equal, the charge quantity ranges of the first sampled integration charge signal Qip and the second sampled integration charge signal Qin can correspond to the charge quantity range of the feedback charge signal of the analog - to - digital converter. Even if the first differential input voltage VIP is always greater than or equal to the second differential input voltage VIN, the first differential input voltage VIP, the second differential input voltage VIN can also correspond to the input range of the analog - to - digital converter.

[0193] In some embodiments of the present application, the first differential input voltage VIP is less than or equal to the second differential input voltage VIN.

[0194] For example, taking the actual range of the first differential input voltage VIP as - 20V to - 15V and the actual range of the second differential input voltage VIN as - 15V to - 10V as an example, the voltage difference range between the first differential input voltage VIP and the second differential input voltage VIN is - 10V to 0V. It can be known that the charge quantity ranges of the first sampled charge signal Qsp and the second sampled charge signal Qsn are as follows:

[0195] 0 < Qsp < +10V * Cs1

[0196] -10V * Cs2 < Qsn < 0

[0197] If the first reference voltage VREFP is 0V and the second reference voltage VREFN is 5V, the magnitudes of the first feedback charge signal Qrp, the second feedback charge signal Qrn, the first common-mode offset charge signal Qdp, and the second common-mode offset charge signal Qdn are as follows:

[0198] Qrp = ±5V * Cf1

[0199] Qrn = ±5V * Cf2

[0200] Qdp = -5V * Cd1

[0201] Qdp = +5V * Cd2

[0202] Under the control of the sampling control module 30, when Cs1 = Cs2 = Cf1 = Cf2 = Cd1 = Cd2, the charge quantity ranges of the first sampled integration charge signal Qip and the second sampled integration charge signal Qin are as follows:

[0203] (0 - 5V * Cf1) < (Qsp + Qdp) < (10V * Cs1 - 5V * Cf1)

[0204] (5V * Cd2 - 10V * Cf1) < (Qsn + Qdn) < (0 + 5V * Cf1)

[0205] That is:

[0206] -5V * Cf1 < Qip < +5V * Cf1

[0207] -5V * Cf1 < Qin < +5V * Cf1

[0208] It can be seen that when the sampling control module 30 controls the capacitance values of the adjustable sampling capacitor, the adjustable common-mode offset capacitor, and the feedback capacitor to be equal, the charge quantity ranges of the first sampled integration charge signal Qip and the second sampled integration charge signal Qin can correspond to the charge quantity range of the feedback charge signal of the analog-to-digital converter. Even if the first differential input voltage VIP is always less than the second differential input voltage VIN, the actual ranges of the first differential input voltage VIP and the second differential input voltage VIN can still match the input range of the analog-to-digital converter.

[0209] In some embodiments of the present application, for example, in the embodiment where the sampling module 10 includes the first adjustable sampling capacitor Cs1 and the second adjustable sampling capacitor Cs2, refer to Figure 4, the capacitance value of the first adjustable sampling capacitor Cs1 is equal to the capacitance value of the second adjustable sampling capacitor Cs2, and the voltage difference between the first differential input voltage VIP and the second differential input voltage VIN satisfies the original voltage difference range; the first ratio between the first adjustable sampling capacitor Cs1 and the feedback capacitance of the analog-to-digital converter (such as the first feedback capacitance Cf1 or the second feedback capacitance Cf2) is equal to the second ratio between the preset voltage difference input range of the analog-to-digital converter and the original voltage difference range.

[0210] It should be noted that the preset voltage difference input range of the analog-to-digital converter is related to the magnitude of the voltage connected to the feedback circuit 200. Taking Figure 4 the feedback circuit 200 being connected to the first reference voltage VREFP and the second reference voltage VREFN as an example, the preset voltage difference input range of the analog-to-digital converter can be expressed as:

[0211] (VREFN - VRENP)~(VREFP - VREFN)

[0212] For example, assuming the first reference voltage VREFP is 5V and the second reference voltage VREFN is 0V, the preset voltage difference input range of the analog-to-digital converter is -5V~+5V; for another example, assuming the first reference voltage VREFP is 5V and the second reference voltage VREFN is 1V, the preset voltage difference input range of the analog-to-digital converter is -4V~+4V.

[0213] The original voltage difference range refers to the fluctuation range of the voltage difference between the first differential input voltage VIP and the second differential input voltage VIN. The original voltage difference range is related to the actual ranges of the first differential input voltage VIP and the second differential input voltage VIN. Assuming the minimum value of the first differential input voltage is VIP_min, the maximum value of the first differential input voltage is VIP_max, the minimum value of the second differential input voltage is VIN_min, and the maximum value of the second differential input voltage is VIN_max, then the original voltage difference range can be expressed as:

[0214] (VIP_min - VIN_max)~(VIP_max - VIN_min)

[0215] For example, assuming the actual range of the first differential input voltage is 17.5V~20V and the actual range of the second differential input voltage is 15V~17.5V, the original voltage difference range is 0V~+5V; for another example, assuming the actual range of the first differential input voltage is 18V~20V and the actual range of the second differential input voltage is 16V~18V, the original voltage difference range is 0V~+4V.

[0216] In the above embodiments, the first ratio between the first adjustable sampling capacitor Cs1 and the feedback capacitor of the analog-to-digital converter is equal to the second ratio between the preset voltage difference input range of the analog-to-digital converter and the original voltage difference range, that is, it can be expressed by the following formula:

[0217]

[0218] Wherein, Cs is the capacitance value of the first adjustable sampling capacitor Cs1 and the second adjustable sampling capacitor Cs2, and Cf is the capacitance value of the first feedback capacitor Cf1 and the second feedback capacitor Cf2.

[0219] For example, for illustration, if the first reference voltage VREFP is 5V, the second reference voltage VREFN is 0V, the preset voltage difference input range of the analog-to-digital converter is -5V to +5V, and the original voltage difference range is 0V to +5V, then the capacitance values of the first adjustable sampling capacitor Cs1 and the second adjustable sampling capacitor Cs2 are twice that of the feedback capacitor of the analog-to-digital converter, that is, Cs1 = Cs2 = 2*Cf1 = 2*Cf2. At this time, the magnitudes of the first feedback charge signal Qrp and the second feedback charge signal Qrn, and the charge quantity ranges of the first sampling charge signal Qsp and the second sampling charge signal Qsn are as follows:

[0220] Qrp = ±5V * Cf

[0221] Qrn = ±5V * Cf

[0222] -10V * Cf < Qsp < 0

[0223] 0 < Qsn < +10V * Cf

[0224] It can be seen that at this time, the charge quantity ranges of the first sampling charge signal Qsp and the second sampling charge signal Qsn are equal to the charge quantity ranges of the first feedback charge signal Qrp and the second feedback charge signal Qrn. Only by performing a common-mode shift on the first sampling charge signal Qsp and the second sampling charge signal Qsn can their charge quantity ranges correspond to those of the first feedback charge signal Qrp and the second feedback charge signal Qrn.

[0225] For example, taking the charge quantity of the first common-mode shift charge signal Qdp as +5V * Cf and the charge quantity of the second common-mode shift charge signal Qdn as -5V * Cf, the charge quantity ranges of the first sampling integration charge signal Qip and the second sampling integration charge signal Qin are:

[0226] -5V * Cf < Qsp + Qdp < +5V * Cf

[0227] -5V * Cf < Qsn + Qdn < +5V * Cf

[0228] It can be seen that by making the first ratio between the first adjustable sampling capacitor Cs1 and the feedback capacitor of the analog-to-digital converter equal to the second ratio between the preset voltage difference input range of the analog-to-digital converter and the original voltage difference range, it is beneficial to make the charge quantity ranges of the first sampled integral charge signal Qip and the second sampled integral charge signal Qin correspond to the charge quantity range of the feedback charge signal of the analog-to-digital converter after charge common-mode offset.

[0229] In some embodiments of the present application, for example, in the embodiment where the common-mode offset module 20 includes a first adjustable common-mode offset capacitor Cd1 and a second adjustable common-mode offset capacitor Cd2, continue to refer to Figure 4 , the capacitance value of the first adjustable common-mode offset capacitor Cd1 is equal to the capacitance value of the second adjustable common-mode offset capacitor Cd2, and the voltage difference between the first differential input voltage VIP and the second differential input voltage VIN satisfies the original voltage difference range; the middle value of the original voltage difference range and the middle value of the preset voltage difference input range of the analog-to-digital converter differ by a first difference, the ratio between the preset voltage difference input range of the analog-to-digital converter and the original voltage difference range is equal to the first ratio, and the product of the first difference and the first ratio is equal to a first product value; the third ratio between the first adjustable common-mode offset capacitor Cd1 and the feedback capacitor of the analog-to-digital converter is equal to the fourth ratio between the first product value and the magnitude of the preset voltage difference input range.

[0230] Specifically, the first adjustable common-mode offset capacitor Cd1 and the first adjustable common-mode offset capacitor Cd2 can be calculated using the following formula:

[0231]

[0232] where Cd is the capacitance value of the first adjustable common-mode offset capacitor Cd1 and the first adjustable common-mode offset capacitor Cd2.

[0233] In the above formula, the item is the middle value of the preset voltage difference input range, is the middle value of the original voltage difference range, VREFP - VREFN is the magnitude of the preset voltage difference input range, and Cs / Cd is the first ratio.

[0234] For example, assume that the first reference voltage VREFP is 5V, the second reference voltage VREFN is 0V, the actual range of the first differential input voltage is 17.5V to 20V, and the actual range of the second differential input voltage is 15V to 17.5V. According to the foregoing, Cs / Cf = 2, then the capacitance magnitudes of the first adjustable common-mode offset capacitor Cd1 and the first adjustable common-mode offset capacitor Cd2 are:

[0235]

[0236] Wherein, Cd is the capacitance value of the first adjustable common-mode offset capacitor Cd1 and the second adjustable common-mode offset capacitor Cd2.

[0237] It can be seen that the capacitance values of the first adjustable common-mode offset capacitor Cd1, the second adjustable common-mode offset capacitor Cd2 and the feedback capacitors (the first feedback capacitor Cf1 and the second feedback capacitor Cf2) of the analog-to-digital converter are equal. Therefore, the charge amounts of the first common-mode offset charge signal Qdp and the second common-mode offset charge signal Qdn are:

[0238] Qdp = +5V * Cf

[0239] Qdp = -5V * Cf

[0240] Combined with the charge amount ranges of the first sampling charge signal Qsp and the second sampling charge signal Qsn being -10V * Cf < Qsp < 0 and 0 < Qsn < +10V * Cf respectively, it can be known that the charge amount ranges of the first sampling integration charge signal Qip and the second sampling integration charge signal Qin are:

[0241] -5V * Cf < Qsp + Qdp < +5V * Cf

[0242] -5V * Cf < Qsn + Qdn < +5V * Cf

[0243] Therefore, after the charge common-mode offset of the first common-mode offset charge signal Qdp and the second common-mode offset charge signal Qdn, the charge amount ranges of the first sampling integration charge signal Qip and the second sampling integration charge signal Qin can correspond to the charge amount range of the feedback charge signal of the analog-to-digital converter.

[0244] Taking another example, assume that the first reference voltage VREFP is 5V, the second reference voltage VREFN is 0V, the actual range of the first differential input voltage is 16.5V to 20V, and the actual range of the second differential input voltage is 15V to 17.5V. Then the preset voltage difference input range of the analog-to-digital converter is -5V to +5V, the original voltage difference range is -1V to +5V, and at this time Cs / Cf = 10 / 6. Then the capacitance sizes of the first adjustable common-mode offset capacitor Cd1 and the first adjustable common-mode offset capacitor Cd2 are:

[0245]

[0246] Therefore, the capacitance values of the first adjustable common-mode offset capacitor Cd1 and the second adjustable common-mode offset capacitor Cd2 are 2 / 3 times that of the feedback capacitor of the analog-to-digital converter. Therefore, the charge amounts of the first common-mode offset charge signal Qdp and the second common-mode offset charge signal Qdn are:

[0247] Qdp = +5V * 2 / 3 * Cf = 10 / 3V * Cf

[0248] Qdp = -5V * 0.45 * Cf = -10 / 3V * Cf

[0249] Meanwhile, the charge quantity ranges of the first sampled charge signal Qsp and the second sampled charge signal Qsn are respectively:

[0250] -5V * 10 / 6Cf < Qsp < +1V * 10 / 6Cf

[0251] -1V * 10 / 6Cf < Qsn < +5V * 10 / 6Cf

[0252] Therefore, the charge quantity ranges of the first sampled integral charge signal Qip and the second sampled integral charge signal Qin are:

[0253] -5V * 10 / 6Cf + 10 / 3V * Cf < Qsp + Qdp < +1V * 10 / 6Cf + 10 / 3V * Cf

[0254] -1V * 10 / 6Cf - 10 / 3V * Cf < Qsn + Qdn < +5V * 10 / 6Cf - 10 / 3V * Cf

[0255] After simplification, it can be obtained that:

[0256] -5V * Cf < Qip < +5V * Cf

[0257] 5V * Cf < Qin < +5V * Cf

[0258] It can be seen that after the charge common-mode offset of the first common-mode offset charge signal Qdp and the second common-mode offset charge signal Qdn, the charge quantity ranges of the first sampled integral charge signal Qip and the second sampled integral charge signal Qin can also correspond to the charge quantity range of the feedback charge signal of the analog-to-digital converter.

[0259] It should be noted that the above content about the sampling circuit 100 is intended to clearly illustrate the implementation verification process of the present application. Those skilled in the art can also make equivalent modified designs under the guidance of the present application. For example, referring to Figure 8 , Figure 8 shows another schematic diagram of the sampling circuit 100 in the embodiment of the present application. The sampling module 10 includes a signal amplifier, the common-mode offset module 20 includes a signal amplifier, and the sampling control module 30 can change the charge quantity ranges of the first sampled charge signal Qsp and the second sampled charge signal Qsn, and / or the charge quantity magnitudes of the first common-mode offset charge signal Qdp and the second common-mode offset charge signal Qdn by controlling the amplification factor of the signal amplifier.

[0260] For another example, refer to Figure 9 , Figure 9 which shows another schematic diagram of the sampling circuit 100 in an embodiment of the present application. The common-mode offset module 20 may also only include a first adjustable common-mode offset capacitor Cd1 and a second adjustable common-mode offset capacitor Cd2. By respectively inputting a clock signal CLKP and a clock signal CLKN to the first adjustable common-mode offset capacitor Cd1 and the second adjustable common-mode offset capacitor Cd2, when the high-level magnitudes of the clock signal CLKP and the clock signal CLKN are a first reference voltage VREFP, the low-level magnitudes of the clock signal CLKP and the clock signal CLKP are a second reference voltage VREFN, and the timing of the clock signal CLKP and the clock signal CLKP is synchronized with the sampling conversion phase of the analog-to-digital converter, a first common-mode offset charge signal Qdp and a second common-mode offset charge signal Qdn can also be output during the conversion stage.

[0261] Furthermore, in order to better implement the sampling circuit 100 in the embodiment of the present application, based on the sampling circuit 100, the present application also provides an analog-to-digital conversion method. Refer to Figure 10 , Figure 10 which shows a schematic flowchart of an analog-to-digital conversion method in an embodiment of the present application. Among them, the analog-to-digital conversion method includes:

[0262] Step S1001: Determine the amplification factor of the sampling module 10 and the bias level of the common-mode offset module 20 according to the original voltage difference range of the input signal and the preset voltage difference input range of the analog-to-digital converter;

[0263] Specifically, the preset voltage difference input range of the analog-to-digital converter is related to the voltage magnitude connected to the feedback circuit 200. The original voltage difference range of the input signal refers to the fluctuation range of the voltage difference between the first differential input voltage VIP and the second differential input voltage VIN, and the original voltage difference range is related to the actual ranges of the first differential input voltage VIP and the second differential input voltage VIN. For example, taking the first reference voltage VREFP as 5V, the second reference voltage VREFN as 0V, the actual range of the first differential input voltage VIP as 17.5V to 20V, and the actual range of the second differential input voltage VIN as 15V to 17.5V as an example, the preset voltage difference input range of the analog-to-digital converter is -5V to +5V, and the original voltage difference range of the input signal is 0V to +5V.

[0264] The amplification factor of the sampling module 10 is related to the preset voltage difference input range and the size of the original voltage difference range. Exemplarily, the amplification factor of the sampling module 10 can be calculated according to the following formula:

[0265]

[0266] Among them, VIP_max is the maximum value of the first differential input voltage VIP, VIP_min is the minimum value of the first differential input voltage VIP, VIN_max is the maximum value of the second differential input voltage VIN, and VIN_min is the minimum value of the second differential input voltage VIN.

[0267] The bias gear of the common-mode offset module 20 is related to the preset voltage difference input range, the original voltage difference range, and the amplification factor of the sampling module 10. Exemplarily, the bias gear of the common-mode offset module 20 can be calculated according to the following formula:

[0268]

[0269] For example, for the above-mentioned analog-to-digital converter with a preset voltage difference input range of -5V to +5V (i.e., the first reference voltage VREFP is 5V and the second reference voltage VREFN is 0V), and the original voltage difference range of the input signal is 0V to +5V (i.e., VIP_max - VIN_min = 5V, VIP_min - VIN_max = 0V), the amplification factor of the sampling module 10 and the bias gear of the common-mode offset module 20 are:

[0270]

[0271] Step S1002: According to the amplification factor of the sampling module 10 and the bias gear of the common-mode offset module 20, control the sampling module 10 and the common-mode offset module 20 to change the charge amount range of the first sampling charge signal Qsp and the second sampling charge signal Qsn output by the sampling module 10, and change the charge amount of the first common-mode offset charge signal Qdp and the second common-mode offset charge signal Qdn output by the common-mode offset module 20;

[0272] After determining the amplification factor of the sampling module 10 and the bias gear of the common-mode offset module 20, the sampling module 10 and the common-mode offset module 20 can be controlled, so as to change the charge amount range of the first sampling charge signal Qsp and the second sampling charge signal Qsn output by the sampling module 10, and the charge amount of the first common-mode offset charge signal Qdp and the second common-mode offset charge signal Qdn output by the common-mode offset module 20.

[0273] In some embodiments of the present application, according to the amplification factor of the sampling module 10 and the bias gear of the common-mode offset module 20, the charge amount ranges of the first sampling charge signal Qsp and the second sampling charge signal Qsn, and the charge amounts of the first common-mode offset charge signal Qdp and the second common-mode offset charge signal Qdn can be changed by adjusting the capacitance size.

[0274] For example, in an embodiment where the sampling module 10 includes a first adjustable sampling capacitor Cs1 and a second adjustable sampling capacitor Cs2, taking the amplification factor K of the sampling module 10 as 2 as an example, the capacitance values of the first adjustable sampling capacitor Cs1 and the second adjustable sampling capacitor Cs2 can be controlled to be twice the capacitance value of the feedback capacitor of the analog-to-digital converter. According to the charge calculation formula Q = C * U, after changing the capacitance values of the first adjustable sampling capacitor Cs1 and the second adjustable sampling capacitor Cs2, the charge quantity ranges of the first sampled charge signal Qsp and the second sampled charge signal Qsn output by the sampling module 10 can be controlled.

[0275] For another example, in an embodiment where the common-mode offset module 20 includes a first adjustable common-mode offset capacitor Cd1 and a second adjustable common-mode offset capacitor Cd2, taking the bias level of the common-mode offset module 20 as 1 as an example, the capacitance values of the first adjustable common-mode offset capacitor Cd1 and the second adjustable common-mode offset capacitor Cd2 can be controlled to be equal to the capacitance value of the feedback capacitor of the analog-to-digital converter. According to the charge calculation formula Q = C * U, after changing the capacitance values of the first adjustable common-mode offset capacitor Cd1 and the second adjustable common-mode offset capacitor Cd2, the charge quantities of the first common-mode offset charge signal Qdp and the second common-mode offset charge signal Qdn output by the sampling module 10 can be controlled.

[0276] It can be understood that when the sampling module 10 or the common-mode offset module 20 includes a signal amplifier, the charge quantity ranges of the first sampled charge signal Qsp and the second sampled charge signal Qsn, and the charge quantities of the first common-mode offset charge signal Qdp and the second common-mode offset charge signal Qdn can also be changed by changing the amplification factor of the signal amplifier.

[0277] Step S1003: Perform analog-to-digital conversion based on the first sampled integration charge signal Qip and the second sampled integration charge signal Qin. The charge quantity of the first sampled integration charge signal Qip is equal to the sum of the first common-mode offset charge signal Qdp and the first sampled charge signal Qsp, and the charge quantity of the second sampled integration charge signal Qin is equal to the sum of the second common-mode offset charge signal Qdn and the second sampled charge signal Qsn.

[0278] After controlling the sampling module 10 and the common-mode offset module 20 to complete the adjustment (such as capacitance size adjustment or signal amplifier adjustment) according to the amplification factor of the sampling module 10 and the bias level of the common-mode offset module 20, the analog-to-digital conversion of the input signal can be started.

[0279] For example, taking a Sigma-Delta analog-to-digital converter as an example, since the charge amount of the first sampling integrated charge signal Qip is equal to the sum of the first common-mode offset charge signal Qdp and the first sampling charge signal Qsp, and the charge amount of the second sampling integrated charge signal Qin is equal to the sum of the second common-mode offset charge signal Qdn and the second sampling charge signal Qsn, according to the principle of the Sigma-Delta analog-to-digital converter:

[0280] (Qsp+Qdp)*(X1+X2)=Qip*(X1+X2)=Qrp*X1-Qrp*X2

[0281] (Qsn+Qdn)*(X1+X2)=Qin*(X1+X2)=Qrn*X2-Qrn*X1

[0282] Among them, X1 is the number of times the first feedback charge signal Qrp is positive in multiple measurement cycles (that is, the number of times the second feedback charge signal Qrn is negative in multiple measurement cycles), and X2 is the number of times the second feedback charge signal Qrn is negative in multiple measurement cycles (that is, the number of times the second feedback charge signal Qrn is positive in multiple measurement cycles).

[0283] It can be seen that the sampling control module 30 is used to control the charge range of the first sampling charge signal Qsp and the second sampling charge signal Qsn, and / or the sampling control module 30 is used to control the size of the first sampling charge signal Qsp and the second sampling charge signal Qsn, thereby changing the charge range of the first sampling integral charge signal Qip and the second sampling integral charge signal Qin, so that the charge range of the first sampling integral charge signal Qip and the second sampling integral charge signal Qin corresponds to the charge range of the first feedback charge signal Qrp and the second feedback charge signal Qrn, which is beneficial to matching the equivalent range of the input signal with the input range of the analog-to-digital converter, thereby avoiding the problem of reduced conversion accuracy of the analog-to-digital converter due to the mismatch between the actual range of the input signal and the input range of the analog-to-digital converter.

[0284] In some embodiments of the present application, after the step of controlling the sampling module 10 and the common-mode offset module 20 according to the amplification factor of the sampling module 10 and the bias position of the common-mode offset module 20, the analog-to-digital conversion method further includes: determining a current conversion error code value of the analog-to-digital converter, and the current conversion error code value is related to the amplification factor of the sampling module 10 and the bias position of the common-mode offset module 20.

[0285] It should be noted that after controlling the sampling module 10 and the common-mode offset module 20 to complete the adjustment (such as capacitance size adjustment or signal amplifier adjustment) according to the amplification factor of the sampling module 10 and the bias gear of the common-mode offset module 20, the conversion error of the analog-to-digital converter itself is usually changed. If only a fixed conversion error code value is used to correct the conversion code value, it may lead to a problem of reduced conversion accuracy. In the above embodiment, since the current conversion error code value of the analog-to-digital converter is re-determined after the sampling module 10 and the common-mode offset module 20 are adjusted, the updated current conversion error code value can be used to correct the conversion code value, thereby avoiding the problem of reduced analog-to-digital conversion accuracy caused by using a fixed conversion error code value to correct the conversion code value.

[0286] As an example, the two differential input terminals of the analog-to-digital converter can also be short-circuited. At this time, VIP = VIN, and the ideal conversion code value of the analog-to-digital converter should be 00000. If the actual conversion code value of the analog-to-digital converter is 00001 (corresponding to the measured voltage of 0.125V) at this time, the current conversion error code value of the analog-to-digital converter can be determined to be 00001, which means that the conversion error of the analog-to-digital converter is 0.125V.

[0287] As another example, the current conversion error code value of the analog-to-digital converter can be measured by inputting a high-precision known voltage signal to the analog-to-digital converter. For example, the high-precision known voltage signal is 1V (corresponding to the conversion code value of 01000), and the conversion result of the analog-to-digital converter for this high-precision known voltage signal is 01001 (corresponding to the measured voltage of 1.125V), then the current conversion error code value of the analog-to-digital converter can be determined to be 00001, which means that the conversion error of the analog-to-digital converter is 0.125V.

[0288] In some embodiments of the present application, the steps of performing analog-to-digital conversion based on the first sampling integration charge signal Qip and the second sampling integration charge signal Qin include: determining an initial conversion code value according to the first sampling integration charge signal Qip and the second sampling integration charge signal Qin; determining a target conversion code value according to the initial conversion code value and the current conversion error code value.

[0289] Taking the Sigma-Delta analog-to-digital converter as an example, during the process of integrating and feedback controlling the first sampling integration charge signal Qip and the second sampling integration charge signal Qin by the Sigma-Delta analog-to-digital converter in multiple measurement cycles, an initial conversion code value Dout0 can be output after output filtering. If the current conversion error code value is Doffset, then the target conversion code value Dout can be calculated according to the following formula:

[0290] Dout = Doffset - Dout0

[0291] For example, if the Sigma-Delta analog-to-digital converter outputs an initial conversion code value Dout0 of 01110 based on the first sampled and integrated charge signal Qip and the second sampled and integrated charge signal Qin, and the current conversion error code value Doffset is 00010, then the target conversion code value Dout of the analog-to-digital converter is 01100.

[0292] It can be seen that since the current conversion error code value of the analog-to-digital converter is re-determined after the adjustment of the sampling module 10 and the common-mode offset module 20, the updated current conversion error code value can be used to correct the conversion code value, thereby eliminating the conversion error caused by changing the amplification factor of the sampling module 10 and the bias level of the common-mode offset module 20.

[0293] To better implement the sampling circuit 100 in the embodiments of the present application, based on the sampling circuit 100, the present application also provides an analog-to-digital converter. The analog-to-digital converter includes the sampling circuit 100 described in any of the above embodiments. The analog-to-digital converter can be, but is not limited to, a Sigma-Delta analog-to-digital converter or a hybrid analog-to-digital converter including a Sigma-Delta analog-to-digital converter. Since the analog-to-digital converter of the present application has the sampling circuit 100 described in the above embodiments, it has all the beneficial effects of the sampling circuit 100 in the above embodiments, which will not be repeated here.

[0294] The embodiments of the present application also provide a chip, and the chip includes the above analog-to-digital converter. A chip (Integrated Circuit, IC) is also called a chip. The chip can be, but is not limited to, a SOC (System on Chip) chip or a SIP (system in package) chip. Since the analog-to-digital converter in the chip of the present application has the sampling circuit 100 described in the above embodiments, it has all the beneficial effects of the sampling circuit 100 in the above embodiments, which will not be repeated here.

[0295] An embodiment of the present application further provides an electronic device, which includes a device body and a chip as described above disposed in the device body. The electronic device may be, but is not limited to, a weighing scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a vehicle charger, an adapter, a display, a USB (Universal Serial Bus) expansion dock, a stylus, a true wireless earphone, a car center screen, a car, a smart wearable device, a mobile terminal, a smart home device. The smart wearable device includes, but is not limited to, a smart watch, a smart bracelet, and a cervical massager. The mobile terminal includes, but is not limited to, a smart phone, a laptop, a tablet computer, and a POS (point of sales terminal) machine. The smart home device includes, but is not limited to, a smart socket, a smart rice cooker, a smart sweeper, and a smart light.

[0296] The above are only the preferred embodiments of the present application, and do not impose any formal restrictions on the present application. Although the present application has been disclosed above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to equivalent embodiments by using the technical content disclosed above without departing from the technical solution of the present application. However, as long as it does not depart from the content of the technical solution of the present application, any brief modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present application still fall within the scope of the technical solution of the present application.

Claims

1. A sampling circuit, characterized in that: The sampling circuit is used to output a first sampling integrated charge signal and a second sampling integrated charge signal to an integration circuit of an analog-to-digital converter, comprising: A sampling module, the sampling module is used to sample the first differential input voltage and the second differential input voltage in a sampling phase, and output a first sampled charge signal and a second sampled charge signal with opposite polarities and equal charge amounts in a conversion phase; A common mode offset module, the common mode offset module is used to output a first common mode offset charge signal and a second common mode offset charge signal in a conversion phase; A sampling control module, the sampling control module is used to control the charge amount range of the first sampled charge signal and the second sampled charge signal, and / or control the charge amount of the first common-mode offset charge signal and the second common-mode offset charge signal; The charge amount of the first sampling integrated charge signal is equal to the sum of the first common-mode offset charge signal and the first sampling charge signal, and the charge amount of the second sampling integrated charge signal is equal to the sum of the second common-mode offset charge signal and the second sampling charge signal.

2. The sampling circuit according to claim 1, characterized in that: The charge amount ranges of the first sampled integrated charge signal and the second sampled integrated charge signal correspond to the charge amount range of the feedback charge signal of the analog-to-digital converter.

3. The sampling circuit according to claim 1, characterized in that: The sampling module includes a first adjustable sampling capacitor and a second adjustable sampling capacitor; The sampling control module is used to control the capacitance values ​​of the first adjustable sampling capacitor and the second adjustable sampling capacitor to control the charge range of the first sampling charge signal and the second sampling charge signal.

4. The sampling circuit according to claim 3, characterized in that: The capacitance value of the first adjustable sampling capacitor is equal to the capacitance value of the second adjustable sampling capacitor, and the voltage difference between the first differential input voltage and the second differential input voltage satisfies the original voltage difference range; A first ratio between the first adjustable sampling capacitor and the feedback capacitor of the analog-to-digital converter is equal to a second ratio between a preset voltage difference input range of the analog-to-digital converter and the original voltage difference range.

5. The sampling circuit according to claim 3, characterized in that: The sampling module also includes a first switch, a second switch, a third switch and a fourth switch; The first end of the first switch is used to access the first differential input voltage, and the second end of the first switch is connected to the first end of the first adjustable sampling capacitor; The first end of the second switch is used to access the second differential input voltage, and the second end of the second switch is connected to the first end of the first adjustable sampling capacitor; The first end of the third switch is used to access the first differential input voltage, and the second end of the third switch is connected to the first end of the second adjustable sampling capacitor; The first end of the fourth switch is used to access the second differential input voltage, and the second end of the fourth switch is connected to the first end of the second adjustable sampling capacitor.

6. The sampling circuit according to claim 1, characterized in that: The common mode offset module includes a first adjustable common mode offset capacitor and a second adjustable common mode offset capacitor; The sampling control module is used to control the capacitance values ​​of the first adjustable common-mode offset capacitor and the second adjustable common-mode offset capacitor to control the charge amounts of the first common-mode offset charge signal and the second common-mode offset charge signal.

7. The sampling circuit according to claim 6, characterized in that: The capacitance value of the first adjustable common-mode offset capacitor is equal to the capacitance value of the second adjustable common-mode offset capacitor, and the voltage difference between the first differential input voltage and the second differential input voltage satisfies the original voltage difference range; A middle value of the original voltage difference range differs from a middle value of a preset voltage difference input range of the analog-to-digital converter by a first difference, and a ratio between the preset voltage difference input range of the analog-to-digital converter and the original voltage difference range is equal to the first ratio; Among them, the product of the first difference and the first ratio is equal to the first product value, and the third ratio between the first adjustable common-mode offset capacitor and the feedback capacitor of the analog-to-digital converter is equal to the fourth ratio of the first product value to the preset voltage difference input range.

8. The sampling circuit according to claim 6, characterized in that: The common mode offset module further includes a fifth switch, a sixth switch, a seventh switch and an eighth switch; The first end of the fifth switch is used to access the first reference voltage, and the second end of the fifth switch is connected to the first end of the first adjustable common-mode offset capacitor; The first end of the sixth switch is used to access the second reference voltage, and the second end of the sixth switch is connected to the first end of the first adjustable common-mode offset capacitor; The first end of the seventh switch is used to access the first reference voltage, and the second end of the seventh switch is connected to the first end of the second adjustable common-mode offset capacitor; The first end of the eighth switch is used to access the second reference voltage, and the second end of the eighth switch is connected to the first end of the second adjustable common-mode offset capacitor.

9. An analog-to-digital conversion method, characterized in that: include: Determine the amplification factor of the sampling module and the bias position of the common mode offset module according to the original voltage difference range of the input signal and the preset voltage difference input range of the analog-to-digital converter; According to the amplification factor of the sampling module and the bias position of the common-mode offset module, the sampling module and the common-mode offset module are controlled to change the charge range of the first sampling charge signal and the second sampling charge signal output by the sampling module, and to change the charge magnitude of the first common-mode offset charge signal and the second common-mode offset charge signal output by the common-mode offset module; Analog-to-digital conversion is performed based on a first sampled integrated charge signal and a second sampled integrated charge signal, wherein the charge amount of the first sampled integrated charge signal is equal to the sum of the first common-mode offset charge signal and the first sampled charge signal, and the charge amount of the second sampled integrated charge signal is equal to the sum of the second common-mode offset charge signal and the second sampled charge signal.

10. The analog-to-digital conversion method according to claim 9, wherein: The charge amount ranges of the first sampled integrated charge signal and the second sampled integrated charge signal correspond to the charge amount range of the feedback charge signal of the analog-to-digital converter.

11. The analog-to-digital conversion method according to claim 9, wherein: After the step of controlling the sampling module and the common mode offset module according to the amplification factor of the sampling module and the bias position of the common mode offset module, the method further includes: A current conversion error code value of the analog-to-digital converter is determined, wherein the current conversion error code value is related to a current gain of the sampling module and a current bias level of the common-mode offset module.

12. The analog-to-digital conversion method according to claim 11, wherein: The step of performing analog-to-digital conversion based on the first sampled integrated charge signal and the second sampled integrated charge signal comprises: determining an initial conversion code value according to the first sampled integrated charge signal and the second sampled integrated charge signal; A target conversion code value is determined according to the initial conversion code value and the current conversion error code value.

13. An analog-to-digital converter, characterized in that: The method comprises the sampling circuit as claimed in any one of claims 1 to 8.

14. A chip, characterized in that: The analog-to-digital converter comprises the analog-to-digital converter as claimed in claim 13 above.

15. An electronic device, characterized in that: The invention comprises a device body and the chip as claimed in claim 14 arranged in the device body.

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