Vertically embedded components in package substrate

Abstract

In embodiments herein, circuit components are embedded within a core layer of a substrate. The circuit components are vertically oriented within cavities or apertures of the core layer of the substrate, for example, with conductive contacts on edges of the components that are substantially orthogonal to a plane of the core layer. The edge substantially orthogonal to the plane of the core layer may be the longest edge of the component.

Description

BACKGROUND OF THE INVENTION

[0001] Circuit components (e.g., power transfer components such as inductors and capacitors) can be embedded within a core of a package substrate for an integrated circuit package. However, embedding components has proven difficult due to various factors (e.g., thickness mismatches between the core and the components), which can cause the components to tilt or shift within the cavity. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Figure 1 An example package substrate having horizontally embedded components in a core layer is shown.

[0003] Figure 2 An example multi-die integrated circuit package having horizontally embedded components in a core layer is shown.

[0004] Figures 3A - 3B Example problems that may exist for components horizontally embedded within a core of a package substrate are shown.

[0005] Figures 4A - 4G An example process for fabricating a package substrate having vertically embedded circuit components in accordance with embodiments of the present disclosure is shown.

[0006] Figures 5A - 5B An example of a circuit component having a redistribution layer in accordance with embodiments of the present disclosure, where the component is vertically embedded within a core layer of a substrate, is shown.

[0007] Figures 6A - 6D An example of a stacked circuit component having a redistribution layer in accordance with embodiments of the present disclosure, where the component is vertically embedded within a core layer of a substrate, is shown.

[0008] Figures 7A - 7B An example system that can incorporate the architectures described herein is shown.

[0009] Figure 8 A top view of a wafer and dies that can be included in a microelectronic component in accordance with any of the embodiments disclosed herein.

[0010] Figure 9 A cross-sectional side view of an integrated circuit device that can be included in a microelectronic component in accordance with any of the embodiments disclosed herein.

[0011] Figure 10 A block diagram of an example electrical device that can include a microelectronic component in accordance with any of the embodiments disclosed herein. DETAILED DESCRIPTION

[0012] Embodiments of the present disclosure relate to vertically embedding circuit components within a core layer of a packaged substrate, which can help mitigate issues associated with thickness mismatches between circuit components and the core layer, as well as enable higher density of embedded components in the core layer. In particular, these issues can be well mitigated by vertically embedded components because the width of the component (which becomes the height of the component in the core when vertically embedded therein) is more easily controllable / optimizable during its fabrication. Additionally, vertical embedding can achieve stronger coplanarity between the component and the core layer surface. Moreover, since the vertical embedding of passive components can also enable placing several components in one cavity, the achievable capacitance density of the package can be increased, and in some cases, electrical connection through the core via the component itself can also be achieved.

[0013] Typically, passive circuit components (e.g., capacitors) are larger in their x and y directions and relatively thinner in the z direction. As Figures 1 - 2 shown, embedding such components can generally be done in a horizontal orientation (i.e., having longer dimensions in the x and y directions as shown in those figures). However, embodiments herein can orient the component substantially orthogonal thereto such that the longer x and y dimensions of the component are aligned with the thickness of the core layer of the substrate, which can be achieved by controlling the x and y dimensions of the component to achieve a better thickness match between the component and the core layer. In a particular embodiment, for example, the longest dimension of the circuit component can be vertically oriented (e.g., orthogonal or substantially orthogonal to the plane of the core layer).

[0014] In some embodiments, the component to be vertically embedded can have electrical connections (e.g., metal pads) on the same edge as normal (e.g., on the side where the component is normally face-up / face-down in a horizontal embedding scenario), and electrical connections (e.g., pads and vias) can be fabricated in the build-up layers of the substrate to connect to the conductive contacts of the component, e.g., as Figures 4A - 4G shown. In some embodiments, some redistribution layers can be fabricated on the longer surface of the component to enable routing the original contacts of the component to the top or bottom, e.g., as Figures 5A - 5B shown. Vertical embedding can enable multiple components to be embedded inside the core layer, including a set of stacked, vertically oriented components, e.g., as Figures 6A - 6D shown.

[0015] Figure 1FIG. 0 shows an example package substrate 100 having horizontally embedded components in a core layer. Specifically, the example package substrate 100 includes a core layer 102 having build-up layers 106 formed on either side of the core layer 102, i.e., build-up layer 106A on the top side of the core layer 102 and build-up layer 106B on the bottom side of the core layer 102. The build-up layers 106 include metal traces in metallization layers (e.g., 107A-D) and pillars (e.g., 109) between the metallization layers to electrically couple solder bumps 108 at the top of the package substrate 100 to pads 110 at the bottom of the substrate. In some cases, an integrated circuit die, for example, may be coupled to the top side of the package substrate 100 and connected to the solder bumps 108, and the package substrate 100 may be coupled to a circuit board (e.g., a motherboard, a main board, etc.) via pads 110 at the bottom of the package substrate 100. The package substrate 100 also includes a land-side capacitor 112 coupled to the bottom side of the package substrate 100.

[0016] Additionally, the package substrate 100 includes circuit components 116 embedded within the core layer 102 (i.e., within cavity 103 in the core layer 102). In some embodiments, the circuit components 116 may be passive circuit components, such as capacitors or inductors, and may be placed within cavities (e.g., as shown) or holes in the core layer 102. In some embodiments, the components 116 may be encapsulated within the cavity / hole in the core layer 102 using a molding material. Although Figure 1 shown as being horizontally oriented in FIG., the component(s) 116 may be vertically oriented within the core layer 102 in embodiments herein, as further described below.

[0017] Figure 2Shows an example multi-die integrated circuit package 200 having a horizontal embedded component 216 in the core layer of a package substrate. Package 200 includes a core layer 202 and vias 204 passing through the core layer 202. Build-up layers 206 are formed on the top and bottom sides of the core layer 202, i.e., build-up layer 206A on the top side of the core layer 202 and build-up layer 206B on the bottom side of the core layer 202. The build-up layer 206 includes metal traces (e.g., 207A-E) in the metallization layer and pillars (e.g., 209) between the metallization layers, as shown in the figure, to electrically couple components on the top of the package 200 to pads 210 at the bottom of the package. For example, layer 206 can provide a connection between an integrated circuit (IC) die 212 coupled to the top side of the package and a circuit board (e.g., a motherboard, a main board, etc.) via pads 210 at the bottom of the package. Package 200 also includes a bridge circuit system component 214 located in the build-up layer 206A that electrically couples a first IC die 212A to a second IC die 212B. The bridge circuit system component 214 can include passive and / or active components for interconnecting the IC dies 212. In some embodiments, the bridge circuit system component 214 can be an embedded multi-die interconnect bridge (EMIB).

[0018] Additionally, package 200 includes circuit components 216 embedded within the core layer 202 (i.e., within cavity 203 in the core layer 202). Similar to Figure 1 component 116, in some embodiments, the circuit component 216 can be a passive circuit component, such as a capacitor or an inductor, and can be placed within a cavity (e.g., as shown in the figure) or a via in the core layer 202. In some embodiments, the component 216 can be encapsulated within the cavity / via in the core layer 202 using a molding material. Although Figure 2 shown as being horizontally oriented in, the component 216 (or components) can be vertically oriented in the core layer 202 in embodiments herein, e.g., as further described below.

[0019] Figures 3A - 3B Shows an example problem that may exist with components horizontally embedded within the core of a package substrate. In particular, Figure 3A shows a height mismatch between the core layer 310 of the substrate and the component 316, while Figure 3BShows how component 316 can be "tilted" within cavity 303 of core layer 310, i.e., such that its top surface (and thus pad 318) is not aligned with the top surface of core layer 310, which can lead to connectivity issues between component 316 and the pads / traces of the build layer above core layer 310. The thickness mismatch may be attributed to core layer 310 having a thickness of approximately 1 - 2 mm (e.g., approximately 1.5 mm), while the component has a thickness (z - dimension) of approximately 500 - 700 μm (e.g., a thickness of approximately 650 μm). In some cases, the x - dimension and y - dimension can each be on the order of 700 - 1100 μm, closer to the thickness of core layer 310. Thus, vertical alignment of the component can prevent thickness - mismatch issues, while also preventing tilting issues and enabling an increase in the density of the embedded components within the core layer.

[0020] Figures 4A - 4G Illustrates an example process 400 for manufacturing a packaged substrate with vertically embedded circuit components according to embodiments of the present disclosure. The process may include more, fewer, or different operations than those shown or described below. For example, certain operations may be performed in a slightly different order than shown, or may be performed simultaneously (when shown as separate steps). In some embodiments, one or more of the operations shown include multiple operations, sub - operations, etc. It will be understood that the example components shown may not be to scale, and the core layer may be larger than shown (e.g., in the x - direction and y - direction, having more vias, pads, or other components).

[0021] As Figures 4A - 4G shown, circuit component 416 is vertically oriented within core layer 410, i.e., the conductive contacts 418 of component 416 are on a surface or edge (the longer edge oriented vertically in the figure) of the respective component that is substantially orthogonal to the plane of core layer 410 (horizontal in the figure). As used herein, substantially orthogonal may refer to an arrangement in which one term (e.g., the edge of component 416) is oriented within 10 degrees of being orthogonal (e.g., at an angle between 85 - 95 degrees) to another term (e.g., core layer 410). Although oriented on an edge orthogonal to the core layer and build layer, the top conductive contacts 418 can be electrically connected to the conductive contacts of the build layer (e.g., 432) via certain intermediate conductive contacts (e.g., 424 in the example shown). The intermediate contacts can be coplanar with core layer 410, in the first metallization layer of the build layer (e.g., 424), or in another location. For example, in some embodiments, such as those further described below, contacts 418 can be electrically connected to the build layer via a redistribution layer in the edge of the component that is orthogonal to the plane of the core layer (i.e., a redistribution layer that is (in a horizontal orientation) above the conductive contacts 418 or (in a vertical orientation) adjacent to the conductive contacts 418).

[0022] Process 400 begins with the core layer 410 of a substrate. The core layer 410 may include plated through-hole (PTH) vias 404, as Figure 4A shown. The core layer 410 may be an organic material (e.g., a material including carbon, such as a material including silicon and carbon), or it may be a glass or glass-based material that includes silicon (e.g., at least 26% by weight) and oxygen (e.g., at least 26% by weight), potentially having one or more additive elements (e.g., at least 5% by weight), such as aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc. Examples of glass core materials may include aluminosilicate, borosilicate, aluminoborosilicate, silica, or fused quartz, and the material may also include one or more additives, such as Al2O3, B2O3, MgO, CaO, SrO, BaO, SnO2, Na2O, K2O, SrO, P2O3, ZrO2, Li2O, Ti, and Zn.

[0023] Then, as Figure 4B shown, holes 411 (or cavities in other embodiments) are drilled or otherwise formed in the core layer 410, and then components 416 are placed inside the holes, as Figure 4C shown. The components 416 may be placed inside the holes such that they are oriented in a vertical manner as shown. A carrier film 405 may be used to place the components and hold them in place until a build film and / or molding material is placed. In the example shown, there are two components 416A, 416B coupled together via a dielectric material 417. In various embodiments, the dielectric material 417 may be an adhesive material such as a die attach film. Each component 416 in the example shown includes two conductive contacts 418 on one of its longer sides, as shown. However, the component 416 may include additional (e.g., up to eight or more) conductive contacts not shown in this example. When oriented in the vertical position as shown, one contact 418 (or set of contacts) is exposed on the top side of the core layer 410, while the other contact 418 (or set of contacts) is exposed on the bottom side of the core layer 410.

[0024] Then, molding material 419 may be placed in the remaining open portion of the holes 411, and build layers 420 may be formed on either side of the core layer 410, as Figure 4D shown. For example, once the molding material 419 is placed, the carrier film 405 that holds the components 416 in place may also be removed. Then, holes 422 may be drilled in the build layers 420, and via pads 424 may be plated on the contacts respectively, as Figure 4E and Figure 4FAs shown. Then, an additional build layer 430 with vias 432 (and other additional build layers / vias) can be fabricated on either side of the substrate, as Figure 4G shown.

[0025] In the example shown, the top contact 418 of component 416 is connected (via 424, 432) to the upper build layer (e.g., 106A, 206A) of the resulting packaged substrate, while the bottom contact 418 of component 416 is connected to the lower build layer (e.g., 106B, 206B) of the resulting packaged substrate.

[0026] Figures 5A - 5B An example of a circuit component 516 with a redistribution layer 520 according to an embodiment of the present disclosure is shown, where the component is vertically embedded in a core layer 510 of a substrate. In the example shown, each component 516 is placed in a cavity 503 or a hole 513 within the core layer 510 and is vertically oriented (i.e., its longer side is oriented in the thickness direction of the core layer). Although not explicitly shown, the cavities 503 and holes 513 can be filled with a molding material or other dielectric material, for example, before forming build layers on either side of the core layer 510 as described above.

[0027] Each component 516 includes a conductive contact 518 (e.g., a pad) on its longer side ( Figures 5A - 5B the right side of the component in the figure), and also includes a redistribution layer 520 on the longer side, the redistribution layer 520 including traces 521 for connecting the contact 518 to other conductive contacts (e.g., 522, 524) at the top or bottom of the redistribution layer 520, as shown, thereby allowing vias, traces, etc. within the build layers of the substrate above or below the core layer 510 to make electrical contact with the contact 518 on the side of the component 516. Additionally, in Figure 5B the example shown, the redistribution layer 520 includes vias 526 that implement electrical connections through the core layer 510, which may generally be an option in traditional horizontal component embedding techniques.

[0028] Figures 6A - 6D An example of a stacked circuit component 616 with a redistribution layer 620 according to an embodiment of the present disclosure is shown, where the component 616 is vertically embedded in a core layer 610 of a substrate. The component 616 is implemented in a manner similar to that of Figures 5A - 5B those in the figure. That is, each component 616 is placed in a hole 603 within the core layer 610 and is vertically oriented (i.e., its longer side is oriented in the thickness direction of the core layer). The component 616 is encapsulated within the hole 603 by a molding material or other type of dielectric material 604, for example, before forming build layers on either side of the core layer as described above.

[0029] Each component 616 includes conductive contacts 618 (e.g., pads) on its longer side ( Figures 6A - 6D the right side of the component in the figure), and also includes a redistribution layer 620 on the longer side. The redistribution layer 620 includes traces 621 for connecting the contacts 618 to other conductive contacts 622, 624 at the top or bottom of the redistribution layer 620, as shown in the figure, so as to achieve electrical contact between vias, traces, etc. in the build layer of the substrate above or below the core layer 610 and the contacts 618 on the side of the component 616. Specifically, components 616A, 616B respectively include redistribution layers 520A, 520B having traces 521A, 521B, and the traces 521A, 521B achieve connection to the build layer above the core layer 610, and components 616C, 616D respectively include redistribution layers 520C, 520D having traces 521C, 521D, and the traces 521C, 521D achieve connection to the build layer below the core layer 610. Although not shown, in some embodiments, the redistribution layer 520 may also include vias similar to Figure 5B the vias 526 shown in the figure to achieve connection between the build layers above and below the core layer 610.

[0030] Figure 6A The example shown in includes components 616 directly stacked on top of each other, while Figure 6B the example shown in includes an adhesive die attach film 630 that couples the components 616A, 616B on the top to the components 616C, 616D on the bottom. In addition, Figure 6B the example shown in also includes additional redistribution layers 632A, 632B above and below the component stack respectively to redistribute the connections from the components.

[0031] In Figure 6C the example shown, the components with redistribution layers are directly stacked on top of each other, similar to Figure 6A . The top components 616A, 616B include vias in their redistribution layers, which allow the bottom components 616C, 616D to be connected to the top build layer, as shown in the figure. Figure 6D The example shown in is similar to Figure 6B the example shown in, where the top components 616A, 616B are respectively stacked on the bottom components 616C, 616D. However, compared with Figure 6C the example where the components have their own corresponding redistribution layers, Figure 6D in the example shown, the components are stacked on top of each other, and then a redistribution layer is formed across the two components, as shown in the figure. Therefore, in Figure 6C the example shown, the components can be stacked on top of each other during the embedding process, while in Figure 6D the example shown, the components can be stacked on top of each other and have a redistribution layer formed before being embedded in the core layer.

[0032] Although Figures 6A - 6D a stack of two components is shown, embodiments herein may stack any suitable number of components with respect to each other in the vertical orientation shown and described above. The components may include their own respective redistribution layers similar to Figure 6C or may include a shared redistribution layer for the stack, e.g., as Figure 6D shown.

[0033] In some embodiments, the embedded components (e.g., 416, 516, 616) may be deep trench capacitors, which are becoming increasingly important in the semiconductor industry. Orienting these components in a stack and rotating them can address the issue of partial / incomplete fill for substrate core thicknesses greater than 700 μm, while also achieving density scaling of the capacitors that benefits from the core thickness in cases where the design is moved to a larger fill ratio or active silicon is moved to inactive or bulk silicon. In some embodiments, the embedded components (e.g., 416, 516, 616) may be magnetic inductor arrays (MIAs).

[0034] In a horizontal orientation, the components may have a footprint of several square millimeters. However, by vertically embedding the components as described herein, the footprint of the components will be related to the effective thickness of the device, which is on the order of 20 - 100 μm, and then either axis for the previous lateral footprint. This means that vertical embedding can scale with the growth of the core thickness (e.g., from 700 μm to 1040 μm or 1480 μm or greater) since additional capacitive bodies can be embedded within the core without affecting the required cross-sectional area. The stack as Figures 6A - 6B shown can also help achieve further densification, thus enabling more efficient area utilization within the core of the substrate.

[0035] Figures 7A - 7B Examples of systems 700, 710 are shown that may incorporate the architectures described herein. Figure 7A Example system 700 includes a circuit board 702, which in some embodiments may be implemented as a motherboard or main board of a computer system. Example system 700 also includes a package substrate 704 having an integrated circuit die 706 attached to the package substrate 704. Die 706 may be a packaged or unpackaged integrated circuit product that includes one or more integrated circuit dies (e.g., Figure 8 die 802 of Figure 9an integrated circuit device 900) and / or one or more other suitable components. Die 706 may include one or more computing system components, such as one or more processor units (e.g., system-on-chip (SoC), processor cores, graphics processing unit (GPU), accelerators, chipset processors), I / O controllers, memories, or network interface controllers. In some embodiments, die 706 may include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. In addition to including one or more processor units, die 706 may also include additional components, such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memory, input / output (I / O) controller, or memory controller. Any of these additional components may be located on the same integrated circuit die as the processor unit, or on one or more integrated circuit dies separate from the integrated circuit die including the processor unit. These separate integrated circuit dies may be referred to as "dielets". Package substrate 704 may provide electrical connections between die 706 and circuit board 702.

[0036] Similar to system 700, system 710 also includes a circuit board 712, which may be implemented as a motherboard or main board of a computer system in some embodiments. System 710 also includes a multi-die package 714, which includes a plurality of integrated circuits / dies (e.g., 706) and interconnections between the dies in one or more metallization layers. The multi-die package 714 may include, for example, one or more silicon interposers, one or more silicon bridges (e.g., embedded multi-die interconnect bridge (EMIB)) embedded in the package substrate, or a combination thereof.

[0037] The main circuit boards 702, 712 may provide electrical connections to other components of the computer system (e.g., memories, storage devices, network interfaces, peripheral devices, power supplies, etc.). The main circuit board may include one or more traces and circuit components to provide interconnections between such computer system components.

[0038] Figure 8is a top view of a wafer 800 and die 802 that can be combined with any of the embodiments disclosed herein. The wafer 800 can be composed of semiconductor material and can include one or more die 802 having integrated circuit structures formed on the surface of the wafer 800. Each die 802 can be a repeating unit of an integrated circuit product that includes any suitable integrated circuit. After the manufacture of the semiconductor product is complete, the wafer 800 can undergo a singulation process in which the die 802 are separated from one another to provide discrete "chips" of the integrated circuit product. The die 802 can include one or more transistors (e.g., some of the transistors 940 discussed below Figure 9 ), support circuitry for transmitting electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit components. In some embodiments, the wafer 800 or die 802 can include memory devices (e.g., random access memory (RAM) devices such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive-bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple of these devices can be combined on a single die 802. For example, a memory array formed of multiple memory devices can be formed on the same die 802 as a processor unit (e.g., Figure 10 's processor unit 1002) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

[0039] Figure 9 is a cross-sectional side view of an integrated circuit device 900 that can be included in any of the embodiments disclosed herein. One or more of the integrated circuit devices 900 can be included in one or more die 802 ( Figure 8 ). The integrated circuit device 900 can be formed on a die substrate 902 (e.g., Figure 8 's wafer 800), and can be included in a die (e.g., Figure 8into the die 802). The die substrate 902 can be a semiconductor substrate composed of a semiconductor material system, the semiconductor material system including, for example, an n-type or p-type material system (or a combination of both). The die substrate 902 can include, for example, a crystalline substrate formed using bulk silicon or silicon-on-insulator (SOI) substructures. In some embodiments, alternative materials that may or may not be combined with silicon can be used to form the die substrate 902, the alternative materials including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Group II-VI, III-V, or IV can also be used to form the die substrate 902. Although several examples of materials that can form the die substrate 902 are described herein, any material that can serve as a basis for the integrated circuit device 900 can be used. The die substrate 902 can be a singulated die (e.g., Figure 8 the die 802) or a portion of a wafer (e.g., Figure 8 the wafer 800).

[0040] The integrated circuit device 900 can include one or more device layers 904 disposed on the die substrate 902. The device layer 904 can include features formed by one or more transistors 940 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs) or ferroelectric field-effect transistors (FeFETs), such as those described herein) formed on the die substrate 902. The transistors 940 can include, for example, one or more source and / or drain (S / D) regions 920, a gate 922 for controlling the current flow between the S / D regions 920, and one or more S / D contacts 924 for transmitting electrical signals to / from the S / D regions 920. The transistors 940 can include additional features not depicted for clarity, such as device isolation regions, gate contacts, etc. The transistors 940 are not limited to Figure 9 the types and configurations depicted therein, and can include a wide variety of other types and configurations, e.g., such as planar transistors, non-planar transistors, or a combination of both. Non-planar transistors can include FinFET transistors such as double-gate or triple-gate transistors, and surround or all-around gate transistors such as nanoribbon, nanosheet, or nanowire transistors.

[0041] Return Figure 9 , for example, the exemplary transistor 940 can include a gate 922 formed of at least two layers, a gate dielectric, and a gate electrode. The gate dielectric can include a single layer or a stack of layers. One or more layers can include silicon oxide, silicon dioxide, silicon carbide, and / or high-k dielectric materials.

[0042] High-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used for gate dielectrics include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when a high-k material is used, an annealing process may be performed on the gate dielectric to improve its quality.

[0043] The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 940 is a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some embodiments, the gate electrode may be composed of a stack of two or more metal layers, where one or more of the metal layers are work function metal layers and at least one metal layer is a fill metal layer. For other purposes, other metal layers may be included, such as a barrier layer.

[0044] For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to NMOS transistors (e.g., for work function tuning). For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to PMOS transistors (e.g., for work function tuning).

[0045] In some embodiments, when considered as a cross-section of the transistor 940 along the source-channel-drain direction, the gate electrode may be composed of a U-shaped structure that includes a bottom portion that is substantially parallel to the surface of the die substrate 902 and two sidewall portions that are substantially perpendicular to the top surface of the die substrate 902. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the die substrate 902 and does not include sidewall portions that are substantially perpendicular to the top surface of the die substrate 902. In other embodiments, the gate electrode may be composed of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be composed of one or more U-shaped metal layers formed on top of one or more flat non-U-shaped layers.

[0046] In some embodiments, a pair of sidewall spacers may be formed on opposite sides of the gate stack to support the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, multiple spacer pairs may be used; for example, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0047] The S / D regions 920 may be formed in the die substrate 902 adjacent to the gates 922 of the respective transistors 940. For example, an implantation / diffusion process or an etching / deposition process may be used to form the S / D regions 920. In the former process, dopant ions such as boron, aluminum, antimony, phosphorus, or arsenic may be implanted into the die substrate 902 to form the S / D regions 920. An annealing process to activate the dopants and further diffuse them into the die substrate 902 may be performed after the ion implantation process. In the latter process, the die substrate 902 may first be etched to form a recess at the location of the S / D regions 920. Then, an epitaxial deposition process may be performed to fill the recess with a material for fabricating the S / D regions 920. In some embodiments, a silicon alloy such as silicon germanium or silicon carbide may be used to fabricate the S / D regions 920. In some embodiments, the epitaxially deposited silicon alloy may be in-situ doped with a dopant such as boron, arsenic, or phosphorus. In some embodiments, one or more alternative semiconductor materials such as germanium or III-V materials or alloys may be used to form the S / D regions 920. In other embodiments, one or more layers of metal and / or metal alloy may be used to form the S / D regions 920.

[0048] Electrical signals such as power and / or input / output (I / O) signals may be transmitted to and / or from the devices (e.g., transistors 940) of the device layer 904 through one or more interconnect layers (shown as interconnect layers 906 - 910 in Figure 9 ) disposed on the device layer 904. For example, the conductive features (e.g., gates 922 and S / D contacts 924) of the device layer 904 may be electrically coupled to the interconnect structures 928 of the interconnect layers 906 - 910. One or more interconnect layers 906 - 910 may form the metallization stack (also referred to as the "ILD stack") 919 of the integrated circuit device 900.

[0049] The interconnect structures 928 may be arranged within the interconnect layers 906 - 910 to transmit electrical signals according to various designs; in particular, the arrangement is not limited to Figure 9 the specific configuration of the interconnect structures 928 depicted in Figure 9A specific number of interconnect layers 906 - 910 are depicted, but embodiments of the present disclosure include integrated circuit devices having more or fewer interconnect layers than those depicted.

[0050] In some embodiments, the interconnect structure 928 may include wires 928a and / or vias 928b filled with a conductive material such as metal. The wires 928a may be arranged to transmit electrical signals in a direction in a plane substantially parallel to the surface of the device layer 904 of the die substrate 902. For example, the wires 928a may transmit electrical signals in a direction into and out of the page and / or across the page from the Figure 9 perspective. The vias 928b may be arranged to transmit electrical signals in a direction in a plane substantially perpendicular to the surface of the device layer 904 of the die substrate 902. In some embodiments, the vias 928b may electrically couple the wires 928a of different interconnect layers 906 - 910 together.

[0051] As Figure 9 shown, the interconnect layers 906 - 910 may include dielectric materials 926 disposed between the interconnect structures 928. In some embodiments, the dielectric materials 926 disposed between the interconnect structures 928 in different interconnect layers 906 - 910 may have different compositions; in other embodiments, the compositions of the dielectric materials 926 between different interconnect layers 906 - 910 may be the same. The device layer 904 may also include dielectric materials 926 disposed between the transistors 940 and the bottom layer of the metallization stack. The dielectric materials 926 included in the device layer 904 may have a different composition from the dielectric materials 926 included in the interconnect layers 906 - 910; in other embodiments, the composition of the dielectric materials 926 in the device layer 904 may be the same as the dielectric materials 926 included in any of the interconnect layers 906 - 910.

[0052] The first interconnect layer 906 (referred to as metal 1 or "M1") may be formed directly on the device layer 904. In some embodiments, as shown, the first interconnect layer 906 may include wires 928a and / or vias 928b. The wires 928a of the first interconnect layer 906 may be coupled to the contacts (e.g., S / D contacts 924) of the device layer 904. The vias 928b of the first interconnect layer 906 may be coupled to the wires 928a of the second interconnect layer 908.

[0053] The second interconnect layer 908 (referred to as metal 2 or "M2") can be formed directly on the first interconnect layer 906. In some embodiments, the second interconnect layer 908 can include vias 928b to couple the lines 928 of the second interconnect layer 908 to the lines 928a of the third interconnect layer 910. Although, for clarity, the lines 928a and vias 928b are depicted structurally as lines within a single interconnect layer, in some embodiments, the lines 928a and vias 928b can be structurally and / or materially continuous (e.g., filled simultaneously during a dual-damascene process).

[0054] According to similar techniques and configurations described in connection with the second interconnect layer 908 or the first interconnect layer 906, a third interconnect layer 910 (referred to as metal 3 or "M3") (and additional interconnect layers as needed) can be formed continuously on the second interconnect layer 908. In some embodiments, the "higher" (i.e., farther from the device layer 904) interconnect layers in the metallization stack 919 in the integrated circuit device 900 can be thicker than the lower interconnect layers in the metallization stack 919, where the lines 928a and vias 928b in the higher interconnect layers are thicker than the lines and vias in the lower interconnect layers.

[0055] The integrated circuit device 900 can include a solder mask material 934 (e.g., polyimide or a similar material) and one or more conductive contacts 936 formed on the interconnect layers 906 - 910. In Figure 9 , the conductive contacts 936 are shown as taking the form of bond pads. The conductive contacts 936 can be electrically coupled to the interconnect structure 928 and are configured to transmit electrical signals of the transistors 940 to external devices. For example, a solder bond can be formed on one or more of the conductive contacts 936 to mechanically and / or electrically couple the integrated circuit die including the integrated circuit device 900 to another component (e.g., a printed circuit board). The integrated circuit device 900 can include additional or alternative structures for transmitting electrical signals from the interconnect layers 906 - 910; for example, the conductive contacts 936 can include other similar features (e.g., pillars) for transmitting electrical signals to external components.

[0056] In some embodiments where the integrated circuit device 900 is a double-sided die, the integrated circuit device 900 can include another metallization stack (not shown) on the opposite side of the device layer 904. This metallization stack can include multiple interconnect layers as discussed above with reference to the interconnect layers 906 - 910 to provide a conductive path (e.g., including conductive lines and vias) between the device layer 904 and additional conductive contacts (not shown) on the side of the integrated circuit device 900 opposite the conductive contacts 936.

[0057] In other embodiments where the integrated circuit device 900 is a double-sided die, the integrated circuit device 900 may include one or more through-silicon vias (TSVs) that pass through the die substrate 902; these TSVs may contact the device layer 904 and may provide a conductive path between the device layer 904 and additional conductive contacts (not shown) on the side of the integrated circuit device 900 opposite the conductive contact 936. In some embodiments, the TSVs extending through the substrate may be used to transfer power and ground signals from the conductive contacts on the opposite side of the integrated circuit device 900 to the transistor 940 and any other components integrated within the die 900, and the metallization stack 919 may be used to transfer I / O signals from the conductive contact 936 to the transistor 940 and any other components integrated within the die 900.

[0058] Multiple integrated circuit devices 900 may be stacked with one or more TSVs in each of the stacked devices, thereby providing a connection between any one of the devices to any of the other devices in the stack. For example, one or more high bandwidth memory (HBM) integrated circuit dies may be stacked on top of a base integrated circuit die, and the TSVs in the HBM dies may provide a connection between each HBM and the base integrated circuit die. Conductive contacts may provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts may be fine pitch solder bumps (microbumps).

[0059] Figure 10 is a block diagram of an example electrical device 1000 that may include one or more of the embodiments disclosed herein. For example, any suitable component of the electrical device 1000 may include one or more of the integrated circuit device 900 or integrated circuit die 802 disclosed herein. Multiple components are shown as being included in the electrical device 1000 in Figure 10 but any one or more of these components may be omitted or replicated depending on the application requirements. In some embodiments, some or all of the components included in the electrical device 1000 may be attached to one or more motherboards, mainboards, or system boards. In some embodiments, one or more of these components are fabricated onto a single system-on-chip (SoC) die.

[0060] Additionally, in various embodiments, the electrical device 1000 may not include Figure 10One or more of the components shown in [description], but the electrical device 1000 may include interface circuitry for coupling to one or more components. For example, the electrical device 1000 may not include the display device 1006, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which the display device 1006 may be coupled. In another set of examples, the electrical device 1000 may not include the audio input device 1024 or the audio output device 1008, but may include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which the audio input device 1024 or the audio output device 1008 may be coupled.

[0061] The electrical device 1000 may include one or more processor units 1002 (e.g., one or more processing units). As used herein, the terms "processor unit", "processing unit", or "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that may be stored in registers and / or memory. The processor unit 1002 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general purpose GPUs (GPGPUs), accelerated processing units (APUs), field programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller cryptographic processors (specialized processors that execute cryptographic algorithms in hardware), server processors, controllers, or any other suitable type of processor unit. Thus, the processor unit may be referred to as an XPU (or xPU).

[0062] The electrical device 1000 may include a memory 1004, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), non-volatile memory (e.g., read only memory (ROM), flash memory, chalcogenide-based phase change non-volatile memory), solid state memory, and / or hard disk drives. In some embodiments, the memory 1004 may include memory located on the same integrated circuit die as the processor unit 1002. This memory may be used as cache memory (e.g., level 1 (L1), level 2 (L2), level 3 (L3), level 4 (L4), last level cache (LLC)), and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0063] In some embodiments, the electrical device 1000 may include one or more processor units 1002 that are heterogeneous or asymmetric with respect to another processor unit 1002 in the electrical device 1000. With respect to a series of quality factors including architecture, microarchitecture, thermal, power consumption characteristics, etc., there may be various differences between the processor units 1002 in the system. These differences can effectively manifest themselves as the asymmetry and heterogeneity between the processor units 1002 in the electrical device 1000.

[0064] In some embodiments, the electrical device 1000 may include a communication component 1012 (e.g., one or more communication components). For example, the communication component 1012 may manage wireless communication for transmitting data to and from the electrical device 1000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, technologies, communication channels, etc. that are capable of transmitting data by using modulated electromagnetic radiation via a non-solid medium. The term "wireless" does not imply that the associated device does not contain any wires, although in some embodiments they may not contain any wires.

[0065] The communication component 1012 can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards (including WiFi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendment)), Long Term Evolution (LTE) program along with any amendments, updates, and / or revisions (e.g., LTE-Advanced program, Ultra Mobile Broadband (UMB) program (also known as "3GPP2"), etc.). IEEE 802.16 compliant broadband wireless access (BWA) networks are generally referred to as WiMAX networks. WiMAX is an acronym representing Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed the IEEE 802.16 standard compliance and interoperability tests. The communication component 1012 can operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. The communication component 1012 can operate according to Enhanced Data Rate for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component 1012 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), its derivative standards, and any other wireless protocols designated as 3G, 4G, 5G, and higher standards. In other embodiments, the communication component 1012 can operate according to other wireless protocols. The electrical device 1000 can include an antenna 1022 to facilitate wireless communication and / or receive other wireless communications (e.g., AM or FM radio transmissions).

[0066] In some embodiments, the communication component 1012 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., IEEE 802.3 Ethernet standard). As described above, the communication component 1012 can include multiple communication components. For example, a first communication component 1012 can be dedicated to short-range wireless communications such as Wi-Fi or Bluetooth, and a second communication component 1012 can be dedicated to long-range wireless communications such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communication component 1012 can be dedicated to wireless communications, and the second communication component 1012 can be dedicated to wired communications.

[0067] The electrical device 1000 may include a battery / power circuit system 1014. The battery / power circuit system 1014 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of the electrical device 1000 to an energy source separate from the electrical device 1000 (e.g., an AC line power source).

[0068] The electrical device 1000 may include a display device 1006 (or corresponding interface circuitry, as described above). The display device 1006 may include one or more embedded or wired or wirelessly connected external visual indicators, such as a head-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0069] The electrical device 1000 may include an audio output device 1008 (or corresponding interface circuitry, as described above). The audio output device 1008 may include any embedded or wired or wirelessly connected external device that generates an audible indicator, e.g., a speaker, headphones, or earbuds.

[0070] The electrical device 1000 may include an audio input device 1024 (or corresponding interface circuitry, as discussed above). The audio input device 1024 may include any embedded or wired or wirelessly connected device that generates a signal representative of sound, e.g., a microphone, a microphone array, or a digital instrument (e.g., an instrument having a Musical Instrument Digital Interface (MIDI) output). The electrical device 1000 may include a Global Navigation Satellite System (GNSS) device 1018 (or corresponding interface circuitry, as discussed above), e.g., a Global Positioning System (GPS) device. The GNSS device 1018 may communicate with a satellite-based system and may determine the geographical location of the electrical device 1000 based on information received from one or more GNSS satellites, as is known in the art.

[0071] The electrical device 1000 may include other output devices 1010 (or corresponding interface circuitry, as discussed above). Examples of other output devices 1010 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage devices.

[0072] The electrical device 1000 may include other input devices 1020 (or corresponding interface circuitry, as discussed above). Examples of other input devices 1020 may include accelerometers, gyroscopes, compasses, image capture devices (e.g., single field of view or stereo field of view cameras), trackballs, trackpads, touchpads, keyboards, cursor control devices such as mice, styli, touchscreens, proximity sensors, microphones, barcode readers, quick response (QR) code readers, electrocardiogram (ECG) sensors, PPG (photoplethysmography) sensors, electrocutaneous response sensors, any other sensors, or radio frequency identification (RFID) readers.

[0073] The electrical device 1000 may have any desired form factor, e.g., a portable or mobile electrical device (e.g., a cellular phone, smartphone, mobile Internet device, music player, tablet computer, laptop computer, 2-in-1 convertible computer, portable all-in-one computer, notebook computer, ultrabook computer, personal digital assistant (PDA), ultra-mobile personal computer, portable gaming console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., a blade, tray, or sled computing system), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a stationary gaming console, a smart TV, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device, or an embedded computing system (e.g., a computing system that is part of a vehicle, smart appliance, consumer electronics or device, manufacturing equipment). In some embodiments, the electrical device 1000 may be any other electronic device that processes data. In some embodiments, the electrical device 1000 may include a plurality of discrete physical components. Given the range of devices that the electrical device 1000 can embody in various embodiments, in some embodiments, the electrical device 1000 may be referred to as a computing device or computing system.

[0074] Exemplary examples of the techniques described throughout this disclosure are provided below. Embodiments of these techniques may include any one or more of the examples described below and any combination thereof. In some embodiments, at least one of the systems or components illustrated in one or more of the foregoing figures may be configured to perform one or more of the operations, techniques, processes, and / or methods set forth in the examples below.

[0075] Example 1 is an integrated circuit package substrate, comprising: a core layer; circuit components within the core layer; and a build-up layer on a first side of the core layer, the build-up layer including a plurality of metallization layers connected by metal posts; wherein the circuit components include conductive contacts on an edge of the circuit components that is substantially orthogonal to the plane of the core layer, and the conductive contacts of the circuit components are connected to conductive contacts in the build-up layer.

[0076] Example 1.1 is an integrated circuit package substrate, comprising: a core layer; a build-up layer on the core layer, the build-up layer comprising a plurality of metallization layers; and circuit components within the core layer, the circuit components comprising conductive contacts on an edge of the circuit components that is substantially orthogonal to a plane of the core layer, the conductive contacts of the circuit components being connected to at least one metallization layer.

[0077] Example 1.2 is an integrated circuit package substrate, comprising: a core layer; a build-up layer on a first side of the core layer, the build-up layer comprising a plurality of metallization layers; and circuit components oriented within the core layer such that a longest edge of the circuit components is substantially orthogonal to a plane of the core layer, wherein the circuit components comprise conductive contacts connected to a metallization layer on the longest edge.

[0078] Example 2 includes the subject matter of any of the foregoing examples, wherein the circuit components comprise one or more redistribution layers, the one or more redistribution layers comprising conductive traces for connecting the conductive contacts of the circuit components to the conductive contacts in the build-up layer.

[0079] Example 3 includes the subject matter of Example 2, wherein the redistribution layer is on the edge that is substantially orthogonal to the plane of the core layer.

[0080] Example 4 includes the subject matter of Example 2 or 3, wherein the edge that is substantially orthogonal to the plane of the core layer is a first edge, and the redistribution layer further comprises an electrical trace between a second edge of the circuit components and a third edge of the circuit components that is opposite the second edge, the second edge and the third edge being substantially orthogonal to the first edge.

[0081] Example 4.1 includes the subject matter of Example 4, wherein the length of the first edge is greater than the lengths of the second edge and the third edge.

[0082] Example 5 includes the subject matter of any of the foregoing examples, wherein the build-up layer is a first build-up layer, the conductive contacts of the circuit components are first conductive contacts of the circuit components, and the substrate further comprises a second build-up layer on a second side of the core layer that is opposite the first side, the second build-up layer comprising a plurality of metallization layers connected by metal posts, wherein the circuit components further comprise second conductive contacts on the first edge, the second conductive contacts being connected to conductive contacts in the second build-up layer.

[0083] Example 6 includes the subject matter of any of the foregoing examples, wherein the circuit component is a first circuit component, and the substrate further includes a second circuit component within the core layer, the second circuit component including conductive contacts on an edge of the second circuit component that is substantially orthogonal to the plane of the core layer, and the conductive contacts of the second circuit component are connected to conductive contacts in the build layer.

[0084] Example 7 includes the subject matter of Example 6, wherein the conductive contacts of the second circuit component and the conductive contacts of the first circuit component are connected to the same conductive contacts in the build layer.

[0085] Example 8 includes the subject matter of Example 6, wherein the second circuit component includes a redistribution layer that includes conductive traces to connect the conductive contacts of the second circuit component to the conductive contacts in the build layer.

[0086] Example 9 includes the subject matter of any of the foregoing examples, wherein the circuit component is a first circuit component, and the substrate further includes a second circuit component within the core layer below the first circuit component.

[0087] Example 10 includes the subject matter of Example 9, wherein the second circuit component includes conductive contacts on an edge of the second circuit component that is substantially orthogonal to the plane of the core layer, and the conductive contacts of the second circuit component are connected to conductive contacts in the build layer.

[0088] Example 11 includes the subject matter of Example 9, and further includes a second build layer on a second side of the core layer opposite the first side, the second build layer including a plurality of metallization layers connected by metal pillars, wherein the second circuit component includes conductive contacts on an edge of the second circuit component that is substantially orthogonal to the plane of the core layer, and the conductive contacts of the second circuit component are connected to conductive contacts in the second build layer.

[0089] Example 12 includes the subject matter of any of the foregoing examples, wherein the core layer includes an organic material.

[0090] Example 13 includes the subject matter of any of the foregoing examples, wherein the core layer includes glass.

[0091] Example 14 includes the subject matter of any of the foregoing examples, wherein the circuit component is a capacitor or an inductor.

[0092] Example 15 includes the subject matter of Example 14, wherein the circuit component is a deep trench capacitor.

[0093] Example 16 is an integrated circuit package, comprising: an integrated circuit package substrate according to any of the foregoing examples; and an integrated circuit die coupled to the package substrate.

[0094] Example 17 is a system, comprising: a circuit board; and an integrated circuit package coupled to the circuit board, the integrated circuit package being according to Example 16.

[0095] In the foregoing description, various aspects of the illustrative embodiments have been described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present disclosure may be practiced using only some of the described aspects. For explanatory purposes, specific numbers, materials, and configurations have been set forth to provide a thorough understanding of the illustrative embodiments. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without all of the specific details. In other instances, well-known features have been omitted or simplified so as not to obscure the illustrative embodiments.

[0096] For purposes of the present disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of the present disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0097] As used herein, the terms "above", "below", "between", "over", and "on" may refer to the relative position of one material layer or component with respect to other layers or components. For example, a layer disposed above or below another layer may be in direct contact with the other layer or may have one or more intermediate layers. Additionally, a layer disposed between two layers may be in direct contact with the two layers or may have one or more intermediate layers. In contrast, a first layer "on" a second layer is in direct contact with the second layer. Similarly, unless expressly stated otherwise, a feature disposed between two features may be in direct contact with an adjacent feature or may have one or more intervening features.

[0098] The above description may use the phrases "in an embodiment" or "in embodiments", which may each refer to one or more of the same or different embodiments. Additionally, the terms "comprising", "including", "having", etc., used with respect to embodiments of the present disclosure are synonymous.

[0099] The term "coupled to" and its derivatives may be used herein. "Coupled" may mean one or more of the following. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are in contact with each other indirectly, but still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements referred to as being coupled to each other. The term "directly coupled" may mean that two or more elements are in direct contact.

[0100] In various embodiments, the phrase "a first feature formed, deposited, or otherwise disposed on a second feature" may mean that the first feature is formed, deposited, or disposed above the second feature, and at least a portion of the first feature may be in direct contact (e.g., direct physical and / or electrical contact) or indirect contact (e.g., having one or more other features between the first feature and the second feature) with at least a portion of the second feature.

[0101] In various embodiments, the phrase "located on" in the context of a first layer or component located on a second layer or component means that the first layer or component is directly physically attached to the second layer or component (no layer or component between the first and second layers or components) or physically attached to the second layer or component through one or more intervening layers or components.

[0102] In various embodiments, the term "adjacent" refers to layers or components that are in physical contact with each other. That is, there is no layer or component between the adjacent layers or components described. For example, layer X adjacent to layer Y refers to the layer that is in physical contact with layer Y.

[0103] In instances where the present disclosure recites "a" or "a first" element or the like, such disclosure includes one or more such elements, neither requiring nor precluding two or more such elements. Further, ordinal indicators (e.g., first, second, or third) used for the identified elements are used to distinguish the elements and do not indicate or imply a required or limited number of such elements, and unless otherwise expressly stated, they also do not indicate a particular location or order of such elements.

Claims

1. An integrated circuit packaging substrate, comprising: Core layer; Circuit components within the core layer; as well as a build-up layer on a first side of the core layer, the build-up layer comprising a plurality of metallization layers; Wherein, the circuit component includes conductive contacts on edges of the circuit component that are substantially orthogonal to the plane of the core layer, the conductive contacts of the circuit component being connected to conductive contacts in the building layer.

2. The integrated circuit package substrate according to claim 1, wherein: The circuit component includes one or more redistribution layers including conductive traces for connecting the conductive contacts of the circuit component with the conductive contacts in the build-up layers.

3. The integrated circuit package substrate according to claim 2, wherein: The redistribution layer is on the edge that is substantially orthogonal to the plane of the core layer.

4. The integrated circuit package substrate according to claim 2, wherein: The edge substantially orthogonal to the plane of the core layer is a first edge, and the redistribution layer further includes an electrical trace between a second edge of the circuit component and a third edge of the circuit component opposite the second edge, the second edge and the third edge being substantially orthogonal to the first edge.

5. The integrated circuit package substrate according to claim 4, wherein: The length of the first edge is greater than the length of the second edge and the length of the third edge.

6. The integrated circuit package substrate according to claim 1, wherein: The building layer is a first building layer, the conductive contact of the circuit component is a first conductive contact of the circuit component, and the substrate further includes a second building layer on a second side of the core layer opposite to the first side, the second building layer including a plurality of metallization layers connected by metal pillars, wherein the circuit component further includes a second conductive contact on the first edge, the second conductive contact connected to the conductive contact in the second building layer.

7. The integrated circuit package substrate according to claim 1, wherein: The circuit component is a first circuit component, and the substrate further includes a second circuit component inside the core layer, the second circuit component including conductive contacts on edges of the second circuit component that are substantially orthogonal to the plane of the core layer, the conductive contacts of the second circuit component connected to conductive contacts in the building layer.

8. The integrated circuit package substrate according to claim 7, wherein: The conductive contacts of the second circuit component and the conductive contacts of the first circuit component are connected to the same conductive contacts in the build-up layer.

9. The integrated circuit package substrate according to claim 7, wherein: The second circuit component includes a redistribution layer including conductive traces for connecting the conductive contacts of the second circuit component with the conductive contacts in the build-up layer.

10. The integrated circuit package substrate according to claim 1, wherein: The circuit component is a first circuit component, and the substrate further includes a second circuit component inside the core layer below the first circuit component.

11. The integrated circuit package substrate according to claim 10, wherein: The second circuit component includes conductive contacts on edges of the second circuit component that are substantially orthogonal to the plane of the core layer, the conductive contacts of the second circuit component connecting to conductive contacts in the build-up layer.

12. The integrated circuit package substrate according to claim 10, further comprising: a second build-up layer on a second side of the core layer opposite the first side, the second build-up layer comprising a plurality of metallization layers connected by metal pillars, wherein the second circuit component comprises a conductive contact on an edge of the second circuit component that is substantially orthogonal to the plane of the core layer, the conductive contact of the second circuit component connected to a conductive contact in the second build-up layer.

13. The integrated circuit package substrate according to any one of claims 1 to 12, wherein: The circuit component is a capacitor or an inductor.

14. The integrated circuit package substrate according to claim 13, wherein: The circuit components are deep trench capacitors or magnetic inductor arrays.

15. An integrated circuit package, comprising: An integrated circuit packaging substrate, the integrated circuit packaging substrate comprising: Core layer; A build-up layer on the core layer, the build-up layer comprising a plurality of metallization layers; and A circuit component within the core layer, the circuit component including conductive contacts on edges of the circuit component substantially orthogonal to the plane of the core layer, the conductive contacts of the circuit component connected to at least one metallization layer; and an integrated circuit die coupled to the packaging substrate.

16. The integrated circuit package of claim 15, wherein: The edge of the circuit component including the conductive contact has the longest dimension of the circuit component.

17. The integrated circuit package of claim 15, wherein: The circuit component includes one or more redistribution layers including conductive traces for connecting the conductive contacts of the circuit component with the at least one metallization layer.

18. The integrated circuit package of claim 15, wherein: The circuit component is a first circuit component, and the substrate further includes a second circuit component inside the core layer, the second circuit component including conductive contacts on an edge of the second circuit component that is substantially orthogonal to the plane of the core layer.

19. The integrated circuit package according to any one of claims 15 to 18, wherein: The circuit components are deep trench capacitors or magnetic inductor arrays.

20. An apparatus comprising: Circuit boards; as well as an integrated circuit package coupled to the circuit board, the integrated circuit package comprising: A substrate, comprising: Core layer; a build-up layer on a first side of the core layer, the build-up layer comprising a plurality of metallization layers; and a circuit component oriented within the core layer such that a longest edge of the circuit component is substantially orthogonal to a plane of the core layer, wherein the circuit component includes a conductive contact connected to a metallization layer on the longest edge; and An integrated circuit die is coupled to the package substrate.

21. The apparatus according to claim 20, wherein: The circuit component includes one or more redistribution layers including conductive traces for connecting the conductive contacts of the circuit component with the metallization layer.

22. The apparatus of claim 20, wherein: The circuit component is a first circuit component, and the substrate further includes a second circuit component inside the core layer, the second circuit component including conductive contacts on an edge of the second circuit component that is substantially orthogonal to the plane of the core layer.

23. The apparatus according to any one of claims 20 to 22, wherein: The circuit components are deep trench capacitors or magnetic inductor arrays.

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