Power semiconductor device and manufacturing method thereof
By introducing a local buffer layer at the mesa terminal of the power semiconductor device, the carrier injection efficiency is reduced, the problem of insufficient flow capacity in the prior art is solved, and higher flow capacity and junction temperature are achieved.
Patent Information
- Application Number
- CN202311774902.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-21
- Publication Date
- 2025-06-27
AI Technical Summary
The flow capacity of existing power semiconductor devices still needs to be improved, especially under high power and high voltage conditions.
By introducing a first buffer layer and a second buffer layer at the mesa terminal, the design of the local buffer layer can effectively reduce carrier injection efficiency, thereby improving the flow throughput of the device.
The current gain of equivalent PNP transistors at the mesa terminal of the power semiconductor device is reduced, blocked leakage is reduced, and the junction temperature throughput capacity of the device is improved.
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Figure CN120224712A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the technical field of semiconductor devices, and in particular, to a power semiconductor device and a manufacturing method thereof. Background Art
[0002] Power semiconductor devices are high-power electronic devices in the power conversion and control circuits of electrical equipment, and are widely used in various fields including the power field. At present, the flexible DC transmission system in the world has a high voltage level and a large power capacity. Some key devices require main turn-off devices to have working characteristics such as a relatively high single-tube turn-off power capacity, a long-term short-circuit failure mode, a reverse blocking ability, and easy series connection and heat dissipation. Among them, taking the reverse-blocking gate-commutated thyristor as an example, it has the advantages of high bidirectional blocking voltage, large power capacity, low on-state loss, short-circuit failure mode, easy series and parallel connection, and high robustness. Therefore, it is very suitable for the application of ultra-high-power power electronic devices in the power grid. However, taking the reverse-blocking gate-commutated thyristor as an example, the current-carrying capacity of the current power semiconductor device still needs to be improved.
[0003] It should be noted that the information distinguishing the invention in the above background art is only configured to strengthen the understanding of the background of the present invention, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention
[0004] The embodiments of the present application provide a power semiconductor device and a manufacturing method thereof, aiming to improve the current-carrying capacity of the power semiconductor device while taking into account the blocking characteristics of the power semiconductor.
[0005] In one aspect, the embodiments of the present application provide a power semiconductor device, including: a first-conductivity-type anode emission region, a first-conductivity-type anode region, a second-conductivity-type base region, a first-conductivity-type first base region, a first-conductivity-type second base region, and a second-conductivity-type cathode emission region partially embedded in the first-conductivity-type second base region, which are stacked in sequence from bottom to top;
[0006] A first mesa terminal is formed at the edge of the first-conductivity-type anode emission region and the first-conductivity-type anode region, and a first buffer layer is provided between the first mesa terminal and the second-conductivity-type base region; a second mesa terminal is formed at the edge of the first-conductivity-type first base region and the first-conductivity-type second base region, and a second buffer layer is provided between the second mesa terminal and the second-conductivity-type base region;
[0007] Wherein, along the direction perpendicular to the edge of the plane where the second-conductivity-type base region is located, the positive projection of the first buffer layer on the second-conductivity-type base region extends beyond the positive projection of the first mesa terminal on the second-conductivity-type base region, and the extended length is not greater than 2 / 3 of the positive projection length of the first mesa terminal on the second-conductivity-type base region; along the direction perpendicular to the edge of the plane where the second-conductivity-type base region is located, the positive projection of the second buffer layer on the second-conductivity-type base region extends beyond the positive projection of the second mesa terminal on the second-conductivity-type base region, and the extended length is not greater than 2 / 3 of the positive projection length of the second mesa terminal on the second-conductivity-type base region.
[0008] Optionally, along the direction away from the edge of the plane where the second-conductivity-type base region is located, the positive projection lengths of the first mesa terminal and the second mesa terminal on the second-conductivity-type base region are not greater than 5000 μm;
[0009] Along the direction away from the edge of the plane where the second-conductivity-type base region is located, the length by which the positive projection of the first buffer layer on the second-conductivity-type base region extends beyond the positive projection of the first mesa terminal on the second-conductivity-type base region and the length by which the positive projection of the second buffer layer on the second-conductivity-type base region extends beyond the positive projection of the second mesa terminal on the second-conductivity-type base region are between 10 μm and 3000 μm.
[0010] Optionally, the first buffer layer and the second buffer layer are embedded in the second-conductivity-type base region, and the surfaces of the first buffer layer and the second buffer layer away from the second-conductivity-type base region are flush with the surface of the second-conductivity-type base region.
[0011] Optionally, the second-conductivity-type base region includes a first charge region at the first mesa terminal, and the second-conductivity-type base region includes a second charge region at the second mesa terminal;
[0012] The first buffer layer or the second buffer layer is embedded in the second-conductivity-type base region, and the first buffer layer has a first preset distance from the first charge region, and the second buffer layer has a second preset distance from the second charge region.
[0013] Optionally, the doping concentrations of the first buffer layer and the second buffer layer are less than any one of the following:
[0014] The doping concentration of the second-conductivity-type cathode emission region, the doping concentration of the first-conductivity-type second base region, and the doping concentration of the first-conductivity-type anode emission region.
[0015] Optionally, the doping concentration of the first buffer layer or and the second buffer layer is 5E13 cm -3 ~5E16 cm -3 ;
[0016] The doping concentration of the cathode emission region of the second conductivity type is 1E19 cm -3 ~2E20 cm -3 ;
[0017] The doping concentration of the second base region of the first conductivity type is 5E17 cm -3 ~5E18 cm -3 ;
[0018] The doping concentration of the first base region of the first conductivity type is 5E14 cm -3 ~2E16 cm -3 ;
[0019] The doping concentration of the anode region of the first conductivity type is 5E14 cm -3 ~2E16 cm -3 ;
[0020] The doping concentration of the anode emission region of the first conductivity type is 5E17 cm -3 ~8E18 cm -3 .
[0021] Optionally, the first buffer layer and the second buffer layer are formed by N-type impurity implantation and annealing, and the thickness of the first buffer layer and the second buffer layer is between 5 μm and 60 μm;
[0022] The cathode emission region of the second conductivity type is formed by N-type impurity diffusion, and the junction depth is 15 μm to 30 μm;
[0023] The second base region of the first conductivity type is formed by P-type impurity implantation and diffusion, and the diffusion junction depth is 50 μm to 80 μm;
[0024] The first base region of the first conductivity type is formed by P-type impurity implantation and diffusion with a diffusion coefficient greater than a preset diffusion coefficient threshold, and the junction depth is determined according to the blocking voltage and the terminal structure of the power semiconductor device;
[0025] The doping concentration and thickness of the second base region of the second conductivity type are determined according to the blocking voltage level of the power semiconductor device;
[0026] The anode region of the first conductivity type is formed by P-type impurity implantation and diffusion with a diffusion coefficient greater than a preset diffusion coefficient threshold, and the junction depth is determined according to the blocking voltage and the terminal structure of the power semiconductor device;
[0027] The first-conductivity-type anode emission region is formed by P-type impurity implantation and diffusion, and the diffusion junction depth is 20 μm to 80 μm.
[0028] Optionally, the first-conductivity-type base region includes: a first-conductivity-type outer region, a first-conductivity-type inner region located on a side of the first-conductivity-type outer region away from the edge of the power semiconductor device, and a first-conductivity-type step region located between the first-conductivity-type outer region and the first-conductivity-type inner region;
[0029] The first-conductivity-type anode region includes: a first-conductivity-type anode outer region, a first-conductivity-type anode inner region located on a side of the first-conductivity-type outer region away from the edge of the power semiconductor device, and a first-conductivity-type anode step region located between the first-conductivity-type anode outer region and the first-conductivity-type anode inner region;
[0030] Wherein, the thickness of the first-conductivity-type inner region is less than the thickness of the first-conductivity-type outer region, and the thickness of the first-conductivity-type anode inner region is less than the thickness of the first-conductivity-type anode outer region, and the thicknesses of the first-conductivity-type step region and the first-conductivity-type anode step region gradually increase in a direction away from the edge of the power semiconductor device.
[0031] Optionally, the power semiconductor device includes: a reverse-blocking gate-commutated thyristor;
[0032] The maximum value of the current rise rate of the reverse-blocking gate-commutated thyristor is greater than a preset current rise rate threshold;
[0033] The high-temperature leakage current of the reverse-blocking gate-commutated thyristor is lower than a preset leakage current threshold;
[0034] The chip junction temperature of the reverse-blocking gate-commutated thyristor is higher than a preset temperature threshold;
[0035] The low on-state loss of the reverse-blocking gate-commutated thyristor is lower than a preset loss threshold;
[0036] The maximum on-state current of the reverse-blocking gate-commutated thyristor is greater than a preset on-state current threshold.
[0037] Compared with the prior art, the advantages of the embodiments of the present application are as follows:
[0038] Through the above embodiments, a first buffer layer and a second buffer layer are introduced at the mesa terminal of the present application. The design of such local buffer layers can effectively reduce the carrier injection efficiency at the mesa terminal, that is, it can reduce the current gain of the equivalent PNP transistor at the mesa terminal of the power semiconductor device, thereby reducing the blocking leakage and thus increasing the device junction temperature. Moreover, due to the length limitation of the projection relationship between the first buffer layer and the mesa terminal, it will not affect the active region of the power semiconductor device, so that the active region of the power semiconductor device can still maintain a standard design, that is, the current gain of the equivalent PNP transistor in the active region remains unchanged. Because the operating junction temperature of the power semiconductor device increases, the current-carrying capacity of the power semiconductor device is improved. In addition, since the carrier concentration distribution at the mesa terminal during the reverse blocking recovery process of the power semiconductor device as a reverse blocking gate commutated thyristor is reduced, the maximum tolerable current rise rate of the reverse blocking gate commutated thyristor can be effectively increased.
[0039] In yet another aspect, an embodiment of the present application further provides a manufacturing method of a power semiconductor device, including:
[0040] Successively fabricating a first-conductivity-type anode emitter region, a first-conductivity-type anode region, a second-conductivity-type base region, a first-conductivity-type first base region, a first-conductivity-type second base region, and a second-conductivity-type cathode emitter region partially embedded in the first-conductivity-type second base region, which are stacked from bottom to top;
[0041] A first mesa terminal is formed at the edges of the first-conductivity-type anode emitter region and the first-conductivity-type anode region, and a first buffer layer is disposed between the first mesa terminal and the second-conductivity-type base region; a second mesa terminal is formed at the edges of the first-conductivity-type first base region and the first-conductivity-type second base region, and a second buffer layer is disposed between the second mesa terminal and the second-conductivity-type base region;
[0042] Wherein, along the direction perpendicular to the edge of the plane where the second-conductivity-type base region is located, the positive projection of the first buffer layer on the second-conductivity-type base region exceeds the positive projection of the first mesa terminal on the second-conductivity-type base region, and the exceeding length is not greater than 2 / 3 of the positive projection length of the first mesa terminal on the second-conductivity-type base region; along the direction perpendicular to the edge of the plane where the second-conductivity-type base region is located, the positive projection of the second buffer layer on the second-conductivity-type base region exceeds the positive projection of the second mesa terminal on the second-conductivity-type base region, and the exceeding length is not greater than 2 / 3 of the positive projection length of the second mesa terminal on the second-conductivity-type base region.
[0043] Optionally, the first buffer layer and the second buffer layer are formed by N-type impurity implantation and annealing.
[0044] Compared with the prior art, the method for manufacturing a semiconductor device provided by the embodiment of the present application can obtain a first buffer layer and a second buffer layer through an implantation annealing process, manufacture the power semiconductor device in the above embodiment at a lower cost, and the manufactured power semiconductor device has all the advantages of the above power semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS
[0045] The drawings are only for reference and illustration purposes and are not intended to limit the protection scope of the present application. The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.
[0046] Figure 1 FIG. shows a schematic cross-sectional structure diagram of a part of a power semiconductor device in an embodiment provided by the present application.
[0047] Figure 2 FIG. shows a schematic cross-sectional structure diagram of a part of another power semiconductor device in an embodiment provided by the present application.
[0048] Figure 3 FIG. shows a schematic cross-sectional structure diagram of a part of another power semiconductor device in an embodiment provided by the present application.
[0049] Figure 4 FIG. shows a doping schematic diagram of a power semiconductor device in an embodiment provided by the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0050] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0051] Taking the reverse blocking gate-commutated thyristor in the related art as an example, due to the high anode concentration and relatively deep junction depth, the anode carrier injection efficiency is very high, resulting in a reduction in the high-temperature blocking characteristics of the device. Compared with the asymmetric gate-commutated thyristor, the operating junction temperature of the reverse blocking gate-commutated thyristor with a symmetric structure property is reduced, further reducing its current-carrying capacity. The inventor considered using the double-doping technology to balance between the current-carrying capacity and the blocking characteristics of the device. Therefore, how to improve the current-carrying capacity of a power semiconductor device taking the reverse blocking gate-commutated thyristor as an example while ensuring the blocking characteristics of the power semiconductor device as much as possible is an urgent problem to be solved by those skilled in the art.
[0052] Related technologies propose to use local irradiation technology. By means of non-uniform irradiation, local irradiation is performed on the local area of the thyristor terminal, so that the local carrier lifetime is reduced, the anode injection efficiency in the terminal area is reduced, and the blocking ability of the device is improved while ensuring the current-carrying capacity of the device. However, excessive irradiation will increase the blocking leakage current of the device.
[0053] Related technologies also propose to improve the method of doping the buffer layer. By reducing the device chip thickness, the current-carrying loss of the device is reduced and the blocking junction temperature of the device is increased. However, since the anode injection efficiency of the device is greatly reduced, the influence of reducing the chip thickness on the on-state loss is weakened. Therefore, in fact, the improvement of the current-carrying capacity is limited.
[0054] In view of the analysis of the above problems, the embodiments of the present application provide a power semiconductor device and a manufacturing method thereof, aiming to efficiently realize the local erasing function of the semiconductor device.
[0055] The embodiments of the present application will be described below with reference to the accompanying drawings.
[0056] Refer to Figure 1 , Figure 1 which shows a schematic diagram of a partial cross-sectional structure of a power semiconductor device in an embodiment provided by the present application. As Figure 1 shown, the embodiments of the present application provide a power semiconductor device, including: a first-conductivity-type anode emission region 1, a first-conductivity-type anode region 17, a second-conductivity-type base region 2, a first-conductivity-type first base region 3, a first-conductivity-type second base region 4, and a second-conductivity-type cathode emission region 5 partially embedded in the first-conductivity-type second base region 4, which are stacked in sequence from bottom to top.
[0057] Among them, the power semiconductor device may include a reverse-blocking power semiconductor device.
[0058] In some alternative embodiments, the first conductivity type may be P type, and the second conductivity type may be N type.
[0059] In the embodiments of the present application, the power semiconductor device may further include: an anode 6 disposed on the first-conductivity-type anode emission region 1 away from the first-conductivity-type anode region 17, a gate located above the first-conductivity-type third base region, and a cathode 8 located above the second-conductivity-type cathode region.
[0060] Among them, the number of gates may be multiple. Exemplarily, it may include a first gate 7 and a second gate 9.
[0061] The edge of the first-conductivity-type anode emission region 1 and the first-conductivity-type anode region 17 forms a first mesa terminal 13, and a first buffer layer 15 is disposed between the first mesa terminal 13 and the second-conductivity-type base region 2. The edge of the first-conductivity-type first base region 3 and the first-conductivity-type second base region 4 forms a second mesa terminal 14, and a second buffer layer 16 is disposed between the second mesa terminal 14 and the second-conductivity-type base region 2.
[0062] Wherein, the first buffer layer 15 and the second buffer layer 16 may be local buffer layers, which do not cover the entire plane of the power semiconductor device, but are only located at the mesa terminals.
[0063] Wherein, the first mesa terminal 13 may be connected to the upper edge of the side surface of the second-conductivity-type base region 2 and the upper surface edge of the first-conductivity-type second base region 4. The second mesa terminal 14 may be connected to the lower edge of the side surface of the second-conductivity-type base region 2 and the lower surface edge of the first-conductivity-type anode emission region 1.
[0064] Wherein, along the direction perpendicular to the edge in the plane where the second-conductivity-type base region 2 is located, the positive projection of the first buffer layer 15 on the second-conductivity-type base region 2 extends beyond the positive projection of the first mesa terminal 13 on the second-conductivity-type base region 2, and the extended length is not greater than 2 / 3 of the positive projection length of the first mesa terminal 13 on the second-conductivity-type base region 2; along the direction perpendicular to the edge in the plane where the second-conductivity-type base region 2 is located, the positive projection of the second buffer layer 16 on the second-conductivity-type base region 2 extends beyond the positive projection of the second mesa terminal 14 on the second-conductivity-type base region 2, and the extended length is not greater than 2 / 3 of the positive projection length of the second mesa terminal 14 on the second-conductivity-type base region 2.
[0065] In some alternative embodiments, along the direction perpendicular to the edge in the plane where the second-conductivity-type base region 2 is located, the positive projection lengths of the first mesa terminal 13 and the second mesa terminal 14 on the second-conductivity-type base region 2 may be equal, both being L1, and the positive projection lengths of the first buffer layer 15 and the second buffer layer 16 on the second-conductivity-type base region 2 may be equal, both being L1 + L2, then the extended projection lengths are both L2.
[0066] Through the above embodiments, the present application introduces a first buffer layer 15 and a second buffer layer 16 at the mesa terminal. The design of such local buffer layers can effectively reduce the carrier injection efficiency at the mesa terminal, that is, it can reduce the current gain of the equivalent PNP transistor at the mesa terminal of the power semiconductor device, thereby reducing the blocking leakage and thus increasing the device junction temperature. Moreover, due to the limitation of the length of the projection relationship between the first buffer layer 15 and the mesa terminal, it will not affect the active region of the power semiconductor device, so that the active region of the power semiconductor device can still maintain a standard design, that is, the current gain of the equivalent PNP transistor in the active region remains unchanged. Due to the increase in the operating junction temperature of the power semiconductor device, the current-carrying capacity of the power semiconductor device is improved. In addition, since the carrier concentration distribution at the mesa terminal during the reverse blocking recovery process of the power semiconductor device as a reverse blocking gate commutated thyristor is reduced, the maximum tolerable current rise rate of the reverse blocking gate commutated thyristor can also be effectively improved.
[0067] In an alternative embodiment, the present application further provides a power semiconductor device, wherein, along the direction away from the edge of the plane where the second-conductivity-type base region 2 is located, the positive projection lengths of the first mesa terminal 13 and the second mesa terminal 14 on the second-conductivity-type base region 2 are not greater than 5000 μm.
[0068] Along the direction away from the edge of the plane where the second-conductivity-type base region 2 is located, the length by which the positive projection of the first buffer layer 15 on the second-conductivity-type base region 2 exceeds the positive projection of the first mesa terminal 13 on the second-conductivity-type base region 2, and the length by which the positive projection of the second buffer layer 16 on the second-conductivity-type base region 2 exceeds the positive projection of the second mesa terminal 14 on the second-conductivity-type base region 2 are between 10 μm and 3000 μm.
[0069] Exemplarily, the positive projections of the first mesa terminal 13 and the second mesa terminal 14 on the second-conductivity-type base region 2 can be 100 μm, and the positive projections of the first buffer layer 15 and the second buffer layer 16 on the second-conductivity-type base region 2 can be 130 μm, then the exceeded length is 30 μm.
[0070] As Figure 1 shown, in an alternative embodiment, the present application further provides a power semiconductor device, wherein the first buffer layer 15 and the second buffer layer 16 are embedded in the second-conductivity-type base region 2, and the surfaces of the first buffer layer 15 and the second buffer layer 16 away from the second-conductivity-type base region 2 are flush with the surface of the second-conductivity-type base region 2.
[0071] Referring to Figure 2 , Figure 2 shows a schematic diagram of a partial cross-sectional structure of another power semiconductor device in an embodiment provided by the present application. As Figure 2As shown, in yet another alternative embodiment, the present application further provides a power semiconductor device, wherein the second-conductivity-type base region 2 includes at the first mesa terminal 13: a first charge region 10, and the second-conductivity-type base region 2 includes at the second mesa terminal 14: a second charge region 11.
[0072] Wherein, the first charge region 10 may be located on the upper surface of the second-conductivity-type base region 2, and the second charge region 11 may be located on the lower surface of the second-conductivity-type base region 2.
[0073] In some alternative embodiments, a third charge region 12 may further be included. The third charge region 12 may include a J3 junction, that is, a gate-cathode junction.
[0074] Wherein, the first charge region 10 may include a J1 junction, that is, a reverse-blocking main junction. The second charge region 11 may include a J2 junction, that is, a forward-blocking main junction.
[0075] Specifically, the first charge region 10 may be disposed on the surface of the positive projection of the first mesa terminal 13 on the second conductivity type, and the second charge region 11 may be disposed on the surface of the positive projection of the second mesa terminal 14 on the second conductivity type.
[0076] The first buffer layer 15 or the second buffer layer 16 is embedded in the second-conductivity-type base region 2, and the first buffer layer 15 has a first preset distance from the first charge region 10, and the second buffer layer 16 has a second preset distance from the second charge region 11.
[0077] In some alternative embodiments, the first preset distance and the second preset distance may be equal.
[0078] In some alternative embodiments, the first preset distance and the second preset distance may be less than 200 μm.
[0079] Furthermore, the first preset distance and the second preset distance may be determined according to the carrier injection efficiency at the mesa terminal.
[0080] Through the above embodiments, an electric field can be made to form a punch-through structure to achieve the purpose of increasing the effective base region width of the mesa terminal, thereby reducing the carrier injection efficiency at the mesa terminal, and then further improving the blocking characteristics of the power semiconductor device. This structural design helps to further achieve the best balance between the current-carrying capacity and the blocking characteristics of the device through multi-dimensional technical means.
[0081] In an alternative embodiment, the present application further provides a power semiconductor device, wherein the doping concentrations of the first buffer layer 15 and the second buffer layer 16 are less than any one of the following:
[0082] The doping concentration of the cathode emission region 5 of the second conductivity type, the doping concentration of the second base region 4 of the first conductivity type, and the doping concentration of the anode emission region 1 of the first conductivity type.
[0083] Referring to Figure 4 , Figure 4 FIG. shows a doping schematic diagram of a power semiconductor device in an embodiment provided by the present application. As Figure 4 shown, further, in an alternative embodiment, the present application also provides a power semiconductor device, wherein the doping concentration N of the first buffer layer 15 or the second buffer layer 16 Buf is 5E13 cm -3 ~5E16 cm -3 .
[0084] The doping concentration N of the cathode emission region 5 of the second conductivity type E is 1E19cm -3 ~2E20cm -3 .
[0085] The doping concentration N of the second base region 4 of the first conductivity type P+ is 5E17cm -3 ~5E18cm -3 .
[0086] The doping concentration N of the first base region 3 of the first conductivity type P is 5E14cm -3 ~2E16cm -3 .
[0087] The doping concentration N of the anode region 17 of the first conductivity type PA is 5E14cm -3 ~2E16cm -3 .
[0088] The doping concentration N of the anode emission region 1 of the first conductivity type PA+ is 5E17cm -3 ~8E18 cm -3 .
[0089] In an alternative embodiment, the present application also provides a power semiconductor device, wherein,
[0090] As Figure 1 shown, the first buffer layer 15 and the second buffer layer 16 are formed by N-type impurity implantation and annealing, and the thickness W of the first buffer layer 15 and the second buffer layer 16 N is between 5μm and 60μm.
[0091] Wherein, in the embodiments of the present application, unless otherwise specified, "thickness" refers to the distance between the two ends along the stacking direction of the stack.
[0092] In some alternative embodiments, the first buffer layer 15 and the second buffer layer 16 are formed by light N-type impurity implantation and annealing.
[0093] Exemplarily, the first buffer layer 15 and the second buffer layer 16 may be formed by hydrogen (H) impurity implantation and annealing.
[0094] As Figure 4 shown, the cathode emission region 5 of the second conductivity type is formed by N-type impurity diffusion, and the junction depth X j3 is 15 μm to 30 μm.
[0095] Exemplarily, the cathode emission region 5 of the second conductivity type may be formed by phosphorus (P) impurity diffusion.
[0096] The second base region 4 of the first conductivity type is formed by P-type impurity implantation and diffusion, and the diffusion junction depth X jP+ is 50 μm to 80 μm.
[0097] Exemplarily, the second base region 4 of the first conductivity type may be formed by boron (B) impurity implantation and diffusion.
[0098] The first base region 3 of the first conductivity type is formed by P-type impurity implantation and diffusion with a diffusion coefficient greater than a preset diffusion coefficient threshold, and the junction depth X j2 is determined according to the blocking voltage and the terminal structure of the power semiconductor device.
[0099] Exemplarily, the first base region 3 of the first conductivity type may be formed by aluminum (Al) or gallium (Ga) impurity implantation and diffusion.
[0100] The doping concentration N D and the thickness W D of the second base region 2 of the second conductivity type are determined according to the blocking voltage level of the power semiconductor device.
[0101] Wherein, the second base region 2 of the second conductivity type may also serve as a substrate.
[0102] The anode region 17 of the first conductivity type is formed by P-type impurity implantation and diffusion with a diffusion coefficient greater than a preset diffusion coefficient threshold, and the junction depth X j1 is determined according to the blocking voltage and the terminal structure of the power semiconductor device.
[0103] Exemplarily, the anode region 17 of the first conductivity type may be formed by aluminum (Al) or gallium (Ga) impurity implantation and diffusion.
[0104] The anode emission region 1 of the first conductivity type is formed by P-type impurity implantation and diffusion, and the diffusion junction depth X jPA+ is 20 μm to 80 μm.
[0105] Exemplarily, the first-conductive-type anode emission region 1 may be formed by boron (B) impurity implantation and diffusion.
[0106] Referring to Figure 3 , Figure 3 FIG. shows a schematic partial cross-sectional structure diagram of another power semiconductor device in an embodiment provided by the present application. As Figure 3 shown, considering that the blocking voltage of the power semiconductor device needs to be further improved, the present application also proposes to add a stepped structure to the first-conductive-type base region at one end of the first buffer layer and / or the first-conductive-type anode region at one end of the second buffer layer based on the above embodiment. To this end, in an optional embodiment, the present application also provides a power semiconductor device, wherein the first-conductive-type base region includes: a first-conductive-type outer region, a first-conductive-type inner region located on the side of the first-conductive-type outer region away from the edge of the power semiconductor device, and a first-conductive-type stepped region located between the first-conductive-type outer region and the first-conductive-type inner region.
[0107] The first-conductive-type anode region includes: a first-conductive-type anode outer region, a first-conductive-type anode inner region located on the side of the first-conductive-type outer region away from the edge of the power semiconductor device, and a first-conductive-type anode stepped region located between the first-conductive-type anode outer region and the first-conductive-type anode inner region.
[0108] Wherein, the thickness of the first-conductive-type inner region is less than the thickness of the first-conductive-type outer region, and the thickness of the first-conductive-type anode inner region is less than the thickness of the first-conductive-type anode outer region, and the thicknesses of the first-conductive-type stepped region and the first-conductive-type anode stepped region gradually increase in the direction away from the edge of the power semiconductor device.
[0109] In the embodiment of the present application, the edge of the power semiconductor device may be the scribe circle edge of the chip.
[0110] In the above embodiment, along the direction from the edge of the power semiconductor device towards the inside of the chip, the length of the first-conductive-type outer region may be substantially the same as the length of the first buffer layer. Specifically, the difference ratio may not exceed 10%. The length of the first-conductive-type anode outer region may be substantially the same as the length of the second buffer layer. Specifically, the difference ratio may not exceed 10%.
[0111] In some optional embodiments, the length of the first-conductive-type outer region may be equal to the length of the first-conductive-type anode outer region.
[0112] Exemplarily, along the direction towards the inside of the chip at the edge of the power semiconductor device, the length of the outer region of the first conductivity type and / or the length of the outer anode region of the first conductivity type can be less than 5000 μm.
[0113] In some alternative embodiments, the height step difference between the outer region of the first conductivity type and the inner region of the first conductivity type can be 10 - 40 μm, and the height step difference between the outer anode region of the first conductivity type and the inner anode region of the first conductivity type can be 10 - 40 μm, or can be equal to the height step difference between the outer region of the first conductivity type and the inner region of the first conductivity type. The high step difference can be regarded as the step height.
[0114] Through the above embodiments, the closer the step region of the first conductivity type and / or the anode step region of the first conductivity type is to the inner side of the chip, that is, the farther away from the scribe line edge of the chip, the more conducive it is to the surface electric field expansion of the mesa and the reduction of the terminal peak electric field. Moreover, the blocking voltage increases with the increase of the step height. The above embodiments help to improve the blocking voltage of the power semiconductor device. Among them, when the step height increases to a certain value, the blocking voltage begins to increase slightly, and the deeper the terminal junction depth, the greater the leakage current.
[0115] In an alternative embodiment, the present application also provides a power semiconductor device, wherein,
[0116] The power semiconductor device includes: a reverse blocking gate-commutated thyristor.
[0117] The maximum value of the current rise rate of the reverse blocking gate-commutated thyristor is greater than a preset current rise rate threshold.
[0118] The high-temperature leakage current of the reverse blocking gate-commutated thyristor is lower than a preset leakage current threshold.
[0119] The chip junction temperature of the reverse blocking gate-commutated thyristor is higher than a preset temperature threshold.
[0120] The low on-state loss of the reverse blocking gate-commutated thyristor is lower than a preset loss threshold.
[0121] The maximum on-state current of the reverse blocking gate-commutated thyristor is greater than a preset on-state current threshold.
[0122] Through the above embodiments, it can help to increase the maximum value of the current rise rate of the reverse blocking gate-commutated thyristor, reduce the high-temperature leakage current, increase the chip junction temperature, reduce the low on-state loss, and increase the maximum on-state current.
[0123] Based on the same inventive concept, the embodiments of the present application also provide a manufacturing method of a power semiconductor device, including:
[0124] The first conductive type anode emission region 1, the first conductive type anode region 17, the second conductive type base region 2, the first conductive type first base region 3, the first conductive type second base region 4, and the second conductive type cathode emission region 5 partially embedded in the first conductive type second base region 4 are sequentially fabricated from bottom to top.
[0125] The edges of the first conductive type anode emission region 1 and the first conductive type anode region 17 form a first mesa terminal 13, and a first buffer layer 15 is disposed between the first mesa terminal 13 and the second conductive type base region 2; the edges of the first conductive type first base region 3 and the first conductive type second base region 4 form a second mesa terminal 14, and a second buffer layer 16 is disposed between the second mesa terminal 14 and the second conductive type base region 2.
[0126] Wherein, along the direction perpendicular to the edge in the plane where the second conductive type base region 2 is located, the positive projection of the first buffer layer 15 on the second conductive type base region 2 exceeds the positive projection of the first mesa terminal 13 on the second conductive type base region 2, and the exceeding length is not greater than 2 / 3 of the positive projection length of the first mesa terminal 13 on the second conductive type base region 2; along the direction perpendicular to the edge in the plane where the second conductive type base region 2 is located, the positive projection of the second buffer layer 16 on the second conductive type base region 2 exceeds the positive projection of the second mesa terminal 14 on the second conductive type base region 2, and the exceeding length is not greater than 2 / 3 of the positive projection length of the second mesa terminal 14 on the second conductive type base region 2.
[0127] In an alternative embodiment, the first buffer layer 15 and the second buffer layer 16 are formed by N-type impurity implantation and annealing.
[0128] The manufacturing method of the semiconductor device provided by the embodiments of the present application can obtain the first buffer layer and the second buffer layer through an implantation annealing process, fabricate the power semiconductor device in the above embodiments at a lower cost, and the fabricated power semiconductor device has all the advantages of the above power semiconductor device.
[0129] For the method embodiments, since they are basically similar to the device structure embodiments, the description is relatively simple, and for the relevant parts, refer to the partial description of the device structure embodiments.
[0130] Each embodiment in this specification is described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts among the embodiments can be referred to each other.
[0131] It should be noted that unless otherwise clearly specified and limited, the drawings in the specification of the present application are only used for schematic illustration and help understanding, and the dimensions in the drawings cannot be used as a limitation to the content of the present application.
[0132] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is the difference from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other.
[0133] In the description of this application, it should be understood that the orientation or positional relationship indicated by terms such as "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to this application. In addition, the terms "first" and "second" are only configured for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of this application, "a plurality" means two or more, unless otherwise specifically defined.
[0134] In the description of this application, it should be noted that unless otherwise clearly specified and limited, the terms "installed", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a connection that can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0135] In this application, unless otherwise clearly specified and limited, the fact that the first feature is "on" or "under" the second feature may include the direct contact between the first and second features, or may include the situation where the first and second features are not in direct contact but in contact through other features between them. Moreover, the fact that the first feature is "above", "over" and "on" the second feature includes that the first feature is directly above and obliquely above the second feature, or merely means that the horizontal height of the first feature is higher than that of the second feature. The fact that the first feature is "under", "beneath" and "under" the second feature includes that the first feature is directly below and obliquely below the second feature, or merely means that the horizontal height of the first feature is lower than that of the second feature.
[0136] In this application, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article or terminal device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or terminal device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or terminal device comprising the element.
[0137] It should be noted that in the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of words such as "exemplary" or "for example" is intended to present relevant concepts in a specific manner.
[0138] In the description of this application, unless otherwise specified, the meaning of "same layer" means that two or more defined objects are in the same layer position in the stacking relationship, or are entirely or partially in the same horizontal plane in the thickness direction of the stacking relationship.
[0139] Finally, it should also be noted that specific examples are used in this article to elaborate on the principles and implementation manners of this application. The descriptions of the above embodiments are only configured to help understand the technical solutions and their core ideas of this application. Although the preferred embodiments of the embodiments of this application have been described, those skilled in the art can make additional changes and modifications to these embodiments once they know the basic creative concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of this application.
Claims
1. A power semiconductor device, characterized in that, Including: A first-conductivity-type anode emission region, a first-conductivity-type anode region, a second-conductivity-type base region, a first-conductivity-type first base region, a first-conductivity-type second base region, and a second-conductivity-type cathode emission region partially embedded in the first-conductivity-type second base region, which are stacked in sequence from bottom to top; A first mesa terminal is formed at the edge of the first-conductivity-type anode emission region and the first-conductivity-type anode region, and a first buffer layer is provided between the first mesa terminal and the second-conductivity-type base region; a second mesa terminal is formed at the edge of the first-conductivity-type first base region and the first-conductivity-type second base region, and a second buffer layer is provided between the second mesa terminal and the second-conductivity-type base region; Wherein, along the direction perpendicular to the edge of the plane where the second-conductivity-type base region is located, the positive projection of the first buffer layer on the second-conductivity-type base region exceeds the positive projection of the first mesa terminal on the second-conductivity-type base region, and the exceeding length is not greater than 2 / 3 of the positive projection length of the first mesa terminal on the second-conductivity-type base region; Along the direction perpendicular to the edge of the plane where the second-conductivity-type base region is located, the positive projection of the second buffer layer on the second-conductivity-type base region exceeds the positive projection of the second mesa terminal on the second-conductivity-type base region, and the exceeding length is not greater than 2 / 3 of the positive projection length of the second mesa terminal on the second-conductivity-type base region.
2. The power semiconductor device according to claim 1, wherein Along the direction away from the edge of the plane where the second-conductivity-type base region is located, the positive projection length of the first mesa terminal and the second mesa terminal on the second-conductivity-type base region is not greater than 5000 μm; Along the direction away from the edge of the plane where the second-conductivity-type base region is located, the length by which the positive projection of the first buffer layer on the second-conductivity-type base region exceeds the positive projection of the first mesa terminal on the second-conductivity-type base region, and the length by which the positive projection of the second buffer layer on the second-conductivity-type base region exceeds the positive projection of the second mesa terminal on the second-conductivity-type base region are between 10 μm and 3000 μm.
3. The power semiconductor device according to claim 1, wherein, The first buffer layer and the second buffer layer are embedded in the second-conductivity-type base region, and the surfaces of the first buffer layer and the second buffer layer away from the second-conductivity-type base region are flush with the surface of the second-conductivity-type base region.
4. The power semiconductor device according to claim 1, characterized in that, The second-conductivity-type base region includes a first charge region at the first mesa terminal, and the second-conductivity-type base region includes a second charge region at the second mesa terminal; The first buffer layer or the second buffer layer is embedded in the second-conductivity-type base region, and the first buffer layer has a first preset distance from the first charge region, and the second buffer layer has a second preset distance from the second charge region.
5. The power semiconductor device according to claim 1, characterized in that, The doping concentration of the first buffer layer and the second buffer layer is less than any one of the following: The doping concentration of the second-conductivity-type cathode emission region, the doping concentration of the first-conductivity-type second base region, and the doping concentration of the first-conductivity-type anode emission region.
6. The power semiconductor device according to claim 5, characterized in that, The doping concentration of the first buffer layer or and the second buffer layer is 5E13 cm -3 ~5E16 cm -3 ; The doping concentration of the second-conductive-type cathode emission region is 1E19 cm -3 ~2E20 cm -3 ; The doping concentration of the second base region of the first conduction type is 5E17 cm -3 ~5E18 cm -3 ; The doping concentration of the first base region of the first conduction type is 5E14 cm -3 ~2E16 cm -3 ; The doping concentration of the anode region of the first conduction type is 5E14 cm -3 ~2E16 cm -3 ; The doping concentration of the first-conductivity-type anode emission region is 5E17 cm -3 ~8E18 cm -3 .
7. The power semiconductor device according to claim 6, wherein The first buffer layer and the second buffer layer are formed by N-type impurity implantation and annealing, and the thickness of the first buffer layer and the second buffer layer is between 5 μm and 60 μm; The second-conductivity-type cathode emission region is formed by N-type impurity diffusion, and the junction depth is 15 μm to 30 μm; The first-conductivity-type second base region is formed by P-type impurity implantation and diffusion, and the diffusion junction depth is 50 μm to 80 μm; The first-conductivity-type first base region is formed by P-type impurity implantation and diffusion with a diffusion coefficient greater than a preset diffusion coefficient threshold, and the junction depth is determined according to the blocking voltage and the terminal structure of the power semiconductor device; The doping concentration and thickness of the second-conductivity-type base region are determined according to the blocking voltage level of the power semiconductor device; The first-conductivity-type anode region is formed by P-type impurity implantation and diffusion with a diffusion coefficient greater than a preset diffusion coefficient threshold, and the junction depth is determined according to the blocking voltage and the terminal structure of the power semiconductor device; The first-conductivity-type anode emission region is formed by P-type impurity implantation and diffusion, and the diffusion junction depth is 20 μm to 80 μm.
8. The power semiconductor device according to claim 1, wherein The first-conductivity-type base region includes: a first-conductivity-type outer region, a first-conductivity-type inner region located on a side of the first-conductivity-type outer region away from the edge of the power semiconductor device, and a first-conductivity-type step region located between the first-conductivity-type outer region and the first-conductivity-type inner region; The first-conductivity-type anode region includes: a first-conductivity-type anode outer region, a first-conductivity-type anode inner region located on a side of the first-conductivity-type outer region away from the edge of the power semiconductor device, and a first-conductivity-type anode step region located between the first-conductivity-type anode outer region and the first-conductivity-type anode inner region; Wherein, the thickness of the first-conductivity-type inner region is less than the thickness of the first-conductivity-type outer region, and the thickness of the first-conductivity-type anode inner region is less than the thickness of the first-conductivity-type anode outer region, and the thicknesses of the first-conductivity-type step region and the first-conductivity-type anode step region gradually increase in a direction away from the edge of the power semiconductor device.
9. The power semiconductor device according to any one of claims 1 to 8, characterized in that, The power semiconductor device includes: a reverse blocking gate-commutated thyristor; The maximum value of the current rise rate of the reverse blocking gate-commutated thyristor is greater than a preset current rise rate threshold; The high-temperature leakage current of the reverse blocking gate-commutated thyristor is lower than a preset leakage current threshold; The chip junction temperature of the reverse blocking gate-commutated thyristor is higher than a preset temperature threshold; The low on-state loss of the reverse blocking gate-commutated thyristor is lower than a preset loss threshold; The maximum on-state current of the reverse blocking gate-commutated thyristor is greater than a preset on-state current threshold.
10. A method for manufacturing a power semiconductor device, characterized in that, Including: A first conductivity type anode emission region, a first conductivity type anode region, a second conductivity type base region, a first conductivity type first base region, a first conductivity type second base region, and a second conductivity type cathode emission region partially embedded in the first conductivity type second base region are sequentially formed from bottom to top. A first mesa terminal is formed at the edge of the first conductivity type anode emission region and the first conductivity type anode region, and a first buffer layer is provided between the first mesa terminal and the second conductivity type base region; a second mesa terminal is formed at the edge of the first conductivity type first base region and the first conductivity type second base region, and a second buffer layer is provided between the second mesa terminal and the second conductivity type base region. Wherein, along the direction perpendicular to the edge of the plane where the second conductivity type base region is located, the positive projection of the first buffer layer on the second conductivity type base region exceeds the positive projection of the first mesa terminal on the second conductivity type base region, and the exceeding length is not greater than 2 / 3 of the positive projection length of the first mesa terminal on the second conductivity type base region. Along the direction perpendicular to the edge of the plane where the second conductivity type base region is located, the positive projection of the second buffer layer on the second conductivity type base region exceeds the positive projection of the second mesa terminal on the second conductivity type base region, and the exceeding length is not greater than 2 / 3 of the positive projection length of the second mesa terminal on the second conductivity type base region.
11. The manufacturing method of the power semiconductor device according to claim 10, characterized in that, The first buffer layer and the second buffer layer are formed by N-type impurity implantation and annealing.