Efficient thermal management planar gate silicon carbide VDMOS and preparation method thereof

Abstract

The invention provides an efficient thermal management planar gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; forming a barrier layer, etching, performing ion implantation, and respectively forming a first P-type source region, a second P-type source region, a P-type well region, a gate protection region and an N-type source region; a barrier layer is formed again, and metal is etched and deposited to form a Schottky metal layer; forming a barrier layer again, etching and depositing to form an insulating medium layer; forming a barrier layer again, etching and depositing metal, and forming a gate metal layer; the method comprises the following steps: forming a barrier layer again, etching, depositing metal, forming a source electrode metal layer, removing the barrier layer, completing preparation, and designing a Schottky metal layer in contact with an N-type source region, thereby reducing the source electrode contact resistance of the device, reducing heat production, and improving the thermal management capability of the device.

Description

Technical Field

[0001] The present invention relates to a high-efficiency thermal management planar-gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Due to the wide bandgap and high thermal conductivity of silicon carbide VDMOS devices, the risk of thermal management is lower. However, the mainstream gate metal is aluminum, and the thermal conductivity of the gate metal alloy is generally 180–190 W / (m·K), which is similar to that of doped silicon carbide materials (120–270 W / (m·K)). Therefore, the gate metal has a limited effect on the thermal management of silicon carbide VDMOS devices. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a high-efficiency thermal management planar-gate silicon carbide VDMOS and a preparation method thereof. The Schottky metal in lateral contact with the N-type source region is designed to reduce the source contact resistance of the device, reduce heat generation, and improve the thermal management ability of the device.

[0004] In a first aspect, the present invention provides a preparation method of a high-efficiency thermal management planar-gate silicon carbide VDMOS, including the following steps: Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially grow on the upper side of the silicon carbide substrate to form a drift layer; Step 2: Form a blocking layer above the drift layer, etch the blocking layer to form a through hole, and perform ion implantation to form a first P-type source region and a second P-type source region respectively; Step 3: Remove the blocking layer in Step 2, reform the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form a P-type well region and a gate protection region respectively; Step 4: Remove the blocking layer in Step 3, reform the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form an N-type source region; Step 5: Remove the blocking layer in Step 4, reform the blocking layer, etch the blocking layer to form a through hole, etch the drift layer to the upper side of the first P-type source region, and deposit metal to form a Schottky metal layer; Step 6: Remove the blocking layer in Step 5, reform the blocking layer, etch the blocking layer to form a through hole, and deposit to form an insulating dielectric layer; Step 7: Remove the blocking layer in Step 6, reform the blocking layer, etch the blocking layer to form a through hole, and deposit metal to form a gate metal layer; Step 8: Remove the blocking layer in Step 7, reform the blocking layer, etch the blocking layer to form a through hole, deposit metal to form a source metal layer, and remove the blocking layer to complete the preparation.

[0005] In a second aspect, the present invention provides an efficient thermal management planar gate silicon carbide VDMOS, which is prepared by using the preparation method of an efficient thermal management planar gate silicon carbide VDMOS described in the first aspect.

[0006] The advantages of the present invention are as follows: 1. The present invention constructs a Schottky metal layer in contact with the N-type source region, realizing metal contact in both the top and lateral directions of the N-type source region, which can effectively reduce the source ohmic contact resistance of the device, reduce the on-resistance of the device, and reduce the heat source of the device. The Schottky metal layer is in direct contact with the drift layer, the first P-type source region, and the second P-type source region inside the device, reducing the conduction impedance from the source metal layer of the device to the body diode and reducing the heat source of the device; 2. The Schottky metal layer in contact with the N-type source region in the present invention constructs a low thermal resistance path from the inside of the device to the source metal layer. The parasitic body diodes of the device can all dissipate heat through the low thermal resistance channel of the Schottky metal layer, increasing the metal contact area between the N-type source region and the surface of the device, reducing the source thermal resistance of the device, and thus improving the thermal management ability of the device; 3. In the body diode region of the present invention, a composite diode structure is constructed in which the Schottky metal layer is on the top, and the first P-type source region, the second P-type source region, and the drift region are arranged side by side at the bottom of the Schottky metal layer. On the basis of ensuring the freewheeling ability of the device body diode, the freewheeling loss is reduced. When the drain bears a large voltage, the drift layer will form a space charge region with the first P-type source region and the second P-type source region, which can improve the breakdown voltage ability of the parasitic Schottky diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention will be further described below with reference to the accompanying drawings in conjunction with embodiments.

[0008] Figure 1 is the schematic diagram of an efficient thermal management planar gate silicon carbide VDMOS of the present invention.

[0009] Figure 2 is the process cross-section of an efficient thermal management planar gate silicon carbide VDMOS of the present invention Figure 1 .

[0010] Figure 3 is the process cross-section of an efficient thermal management planar gate silicon carbide VDMOS of the present invention Figure 2 .

[0011] Figure 4 is the process cross-section of an efficient thermal management planar gate silicon carbide VDMOS of the present invention Figure 3 .

[0012] Figure 5 is the process cross-section of an efficient thermal management planar gate silicon carbide VDMOS of the present inventionFigure 4 。

[0013] Figure 6 Process cross-section of an efficient thermal management planar-gate silicon carbide VDMOS of the present invention Figure 5 。

[0014] Figure 7 Process cross-section of an efficient thermal management planar-gate silicon carbide VDMOS of the present invention Figure 6 。

[0015] Figure 8 Process cross-section of an efficient thermal management planar-gate silicon carbide VDMOS of the present invention Figure 7 。

[0016] Figure 9 Process cross-section of an efficient thermal management planar-gate silicon carbide VDMOS of the present invention Figure 8 。

[0017] Figure 10 Process cross-section of an efficient thermal management planar-gate silicon carbide VDMOS of the present invention Figure 9 。 Detailed implementation manners

[0018] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0020] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "in contact with", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although terms such as first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or portions, these elements, components, regions, layers, doping types and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or portion from another element, component, region, layer, doping type or portion. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be referred to as a second element, component, region, layer or portion.

[0021] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientation depicted in the figures, spatial relationship terms also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under", "beneath" or "underneath" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. Additionally, the device may also have other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0022] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / having" etc. specify the presence of the stated features, integers, steps, operations, components, parts or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0023] As Figures 1 to 10 shown, an embodiment of the present application provides a method for preparing an efficient thermal management planar gate silicon carbide VDMOS, including the following steps: Step 1: Deposit metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 9; epitaxially grow on the upper side of the silicon carbide substrate 1 to form a drift layer 2; Step 2: Form a blocking layer 100 above the drift layer 2, etch the blocking layer 100 to form a through hole, and perform ion implantation to respectively form a first P-type source region 22 and a second P-type source region 23; Step 3: Remove the blocking layer 100 in Step 2, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, and perform ion implantation to respectively form a P-type well region 5 and a gate protection region 211; Step 4: Remove the blocking layer 100 in Step 3, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, and perform ion implantation to form an N-type source region 4; Step 5: Remove the blocking layer 100 in Step 4, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, etch the drift layer 2 to the upper side of the first P-type source region 22, and deposit metal to form a Schottky metal layer 3; Step 6: Remove the blocking layer 100 in Step 5, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, and deposit to form an insulating dielectric layer 6; Step 7: Remove the blocking layer 100 in Step 6, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, and deposit metal to form a gate metal layer 7; Step 8: Remove the blocking layer 100 in Step 7, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, deposit metal to form a source metal layer 8, and remove the blocking layer 100 to complete the preparation.

[0024] In this embodiment, preferably, the Schottky metal layer 3, the N-type source region 4, the P-type well region 5, and the gate protection region 211 have the same thickness.

[0025] In this embodiment, preferably, the width of the first P-type source region 22 is smaller than the width of the second P-type source region 23.

[0026] In this embodiment, preferably, the doping concentration of the P-type well region 5 is smaller than the doping concentration of the drift layer 2.

[0027] In this embodiment, preferably, the doping concentration of the P-type well region 5 is smaller than the doping concentration of the N-type source region 4; the doping concentration of the P-type well region 5 is smaller than the doping concentration of the second P-type source region 23.

[0028] In this embodiment, preferably, both the silicon carbide substrate 1 and the drift layer 2 are N-type, and the gate protection region 211 is P-type.

[0029] As Figure 1 shown, the planar gate silicon carbide VDMOS obtained by the above manufacturing method includes: Silicon carbide substrate 1 Drift layer 2, the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1, a convex portion 21 is provided on the drift layer 2, and a gate protection region 211 is provided in the convex portion 21; a first P-type source region 22 and a second P-type source region 23 are provided on the drift layer 2, and the second P-type source region 23 is located inside the first P-type source region 22; Schottky metal layer 3, the lower side of the Schottky metal layer 3 is connected to the upper side of the drift layer 2, the upper side of the first P-type source region 22, and the second P-type source region 23; N-type source region 4, the lower side of the N-type source region 4 is connected to the upper side of the second P-type source region 23, and the outer side of the N-type source region 4 is connected to the inner side of the Schottky metal layer 3; P-type well region 5, the lower side of the P-type well region 5 is connected to the upper side of the second P-type source region 23, the outer side of the P-type well region 5 is connected to the N-type source region 4, and the inner side of the P-type well region 5 is connected to the outer side of the convex portion 21; Insulating dielectric layer 6, the lower side of the insulating dielectric layer 6 is respectively connected to the P-type well region 5, the convex portion 21, and the gate protection region 211; Gate metal layer 7, the lower side of the gate metal layer 7 is connected to the upper side of the insulating dielectric layer 6; Source metal layer 8, the source metal layer 8 is respectively connected to the Schottky metal layer 3 and the N-type source region 4; And a drain metal layer 9, the drain metal layer 9 is connected to the lower side of the silicon carbide substrate 1.

[0030] In another embodiment of the present invention, the doping concentration of the silicon carbide substrate 1 is 2 - 8e18 cm -3 , the doping concentration of the drift layer 2 is 1 - 8e17 cm -3 , the doping concentration of the P-type well region 5 is 1 - 5e15 cm -3 , the doping concentrations of the first P-type source region 22 and the second P-type source region 23 are both 5 - 9e18 cm -3 , the material of the insulating dielectric layer 6 can be silicon dioxide, the doping concentration of the N-type source region 4 is 2 - 8e18 cm -3 , the materials of the Schottky metal layer 3 and the source metal layer 8 are the same, which is nano silver, its thermal conductivity is 429 W / (m·K), embedded inside the device structure, it can improve the heat conduction efficiency from the inside of the device to the source metal, improve the thermal management ability of the device, improve the source heat conduction efficiency of the device, and form a more firm contact with the bonding wire during device packaging, forming heat conduction from the device pad to the device packaging structure; The doping concentration of the silicon carbide substrate 1 is to ensure a low-resistance ohmic contact with the drain metal layer 9 and reduce the overall on-resistance of the device; the doping concentration of the drift layer 2 is a trade-off between the reverse breakdown voltage and on-resistance of the device. Due to the doping concentrations of the first P-type source region 22 and the second P-type source region 23 and the structural distribution of the Schottky metal layer 3, the doping concentration of the drift layer 2 can be increased under the condition of ensuring the device breakdown voltage. There are two considerations in the design of the doping concentrations of the first P-type source region 22 and the second P-type source region 23: First, it is to reduce the contact resistance between the first P-type source region 22 and the second P-type source region 23 and the Schottky metal layer 3, thereby reducing the conduction loss of the parasitic pn junction body diode of the device; Second, when the drain is at a high voltage, it is to reduce the diffusion speed of the space charge region located in the first P-type source region 22 and the second P-type source region 23 towards the gate and source of the device; the doping concentration of the P-type well region 5 is to reduce the gate control charge of the device gate and improve the switching speed of the device. The thickness of the silicon carbide substrate 1 of the device is 1 μm, and the thickness of the drift layer 2 is 50 - 80 μm, which is adjusted within the above range according to different requirements for the device breakdown voltage characteristics. The thicknesses of both the first P-type source region 22 and the second P-type source region 23 are 300 nm, and the thicknesses of the Schottky metal layer 3, the N-type source region 4, the P-type well region 5, and the gate protection region 211 are all 600 nm. This is to increase the longitudinal contact area between the Schottky metal layer 3 and the N-type source region 4, thereby reducing the ohmic contact resistance between the N-type source region 4 of the device and the source metal layer 8, reducing the on-resistance of the device, and increasing the contact area between the internal structure of the device and the high-thermal-conductivity metal to improve the thermal management efficiency; the thickness of the gate protection region 211 is equal to the thickness and doping concentration of the P-type well region 5, which is to complete the fabrication of the P-type well region 5 and the gate protection region 211 in one step process, reduce the process steps, and reduce the device manufacturing cost; the Schottky metal layer 3 forms a Schottky junction with the drift layer 2, but the Schottky metal layer 3 forms an ohmic contact with the N-type source region 4. The thickness of the insulating dielectric layer 6 is 50 nm, which ensures the switching characteristics of the device and controls the gate charge. The width of the first P-type source region 22 is 1 μm, the width of the drift layer 2 between the first P-type source region 22 and the second P-type source region 23 is 500 nm, the width of the second P-type source region is 2 μm, the width of the Schottky metal layer 3 is 2 μm, and the width of the N-type source region 4 is 1 μm. This design is to form an ohmic contact of the Schottky metal layer 3 above the second P-type source region 23 and avoid forming an ohmic conduction channel from the N-type source region 4 to the drift layer 2. The drift layer 2 between the first P-type source region 22 and the second P-type source region 23 is to construct a Schottky body diode and form a space charge region when the device is reverse-biased to ensure the breakdown voltage characteristics of the device. The width of the P-type well region 5 is 500 nm, the width of the insulating dielectric layer 6 is 4 μm, the width of the gate metal layer 7 is 3 μm, and the width of the gate protection region 211 is 1 μm. This is to improve the gate reliability of the device, shield the gate-drain capacitance, and increase the switching speed of the device. The distance from the P-type well region 5 to the gate protection region 211 is 500 nm, which ensures that the conductive channel of the device is not affected while improving the gate reliability of the device.

[0031] Although the specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments we described are illustrative rather than limiting the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered by the scope of the claims of the present invention.

Claims

1. A preparation method of an efficient thermal management planar-gate silicon carbide VDMOS, characterized in that: It includes the following steps: Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially grow on the upper side of the silicon carbide substrate to form a drift layer; Step 2: Form a blocking layer above the drift layer, etch the blocking layer to form a through hole, and perform ion implantation to respectively form a first P-type source region and a second P-type source region; Step 3: Remove the blocking layer in Step 2, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to respectively form a P-type well region and a gate protection region; Step 4: Remove the blocking layer in Step 3, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form an N-type source region; Step 5: Remove the blocking layer in Step 4, re-form a blocking layer, etch the blocking layer to form a through hole, etch the drift layer to the upper side of the first P-type source region, and deposit metal to form a Schottky metal layer; Step 6: Remove the blocking layer in Step 5, re-form a blocking layer, etch the blocking layer to form a through hole, and deposit to form an insulating dielectric layer; Step 7: Remove the blocking layer in Step 6, re-form a blocking layer, etch the blocking layer to form a through hole, and deposit metal to form a gate metal layer; Step 8: Remove the blocking layer in Step 7, re-form a blocking layer, etch the blocking layer to form a through hole, deposit metal to form a source metal layer, and remove the blocking layer to complete the preparation.

2. The manufacturing method of an efficient thermal management planar gate silicon carbide VDMOS according to claim 1, characterized in that: The thicknesses of the Schottky metal layer, the N-type source region, the P-type well region, and the gate protection region are equal.

3. The manufacturing method of a high-efficiency thermal management planar-gate silicon carbide VDMOS according to claim 1, characterized in that: The width of the first P-type source region is smaller than the width of the second P-type source region.

4. The manufacturing method of a high-efficiency thermal management planar-gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the P-type well region is smaller than the doping concentration of the drift layer.

5. The manufacturing method of an efficient thermal management planar-gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the P-type well region is smaller than the doping concentration of the N-type source region; the doping concentration of the P-type well region is smaller than the doping concentration of the second P-type source region.

6. The manufacturing method of an efficient thermal management planar gate silicon carbide VDMOS as claimed in claim 1, wherein: The silicon carbide substrate and the drift layer are both N-type, and the gate protection region is P-type.

7. An efficient thermal management planar-gate silicon carbide VDMOS, characterized in that, The silicon carbide VDMOS is prepared by the preparation method according to any one of claims 1 to 6.

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