Josephson junction with reduced stray inductance

Abstract

Methods, systems, and devices for forming Josephson junctions with reduced stray inductance. In one aspect, a device includes: a substrate; a first superconductor layer on the substrate; an insulator layer on the first superconductor layer; a second superconductor layer on the insulator layer, wherein the first superconductor layer, the insulator layer, and the second superconductor layer form a Josephson junction; and a third superconductor layer directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide the first contact to the superconductor tunnel junction and the second contact to the superconductor tunnel junction, respectively.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 201980010108.X, with an international filing date of July 25, 2019, an entry date into the Chinese national phase of July 24, 2020, and an invention title of "Josephson Junction with Reduced Stray Inductance". Technical Field

[0002] The present disclosure relates to forming a tunnel junction for a Josephson junction. Background Art

[0003] Quantum computing is a relatively new computing method that utilizes quantum effects such as superposition of ground states and entanglement to perform certain calculations more efficiently than classical digital computers. Compared with digital computers that store and manipulate information in the form of bits (e.g., "1" or "0"), quantum information processing devices can use qubits to manipulate information. A qubit can refer to a quantum device capable of achieving superposition of multiple states (e.g., data in both the "0" state and the "1" state) and / or to the superposition of data itself in multiple states. Example physical implementations of qubits include qubits implemented using Josephson junctions. Summary of the Invention

[0004] Generally, one innovative aspect of the subject matter described in this specification can be implemented in a method that includes the following actions: providing a substrate including a first resist layer, the first resist layer being patterned to expose an opening region, where the opening region includes a central opening portion, a first elongated opening portion, and a second elongated portion, the first elongated opening portion having a length extending from a first side of the central opening portion in a first direction, the second elongated portion having a length extending from a second side of the central opening portion in a second direction different from the first direction, where the width of the first elongated portion is less than the length of the first side of the central opening, and the width of the second elongated portion is less than the length of the second side of the central opening; depositing a first superconductor material on the patterned resist layer at a first non-normal angle with respect to the substrate to form a first superconductor layer within the central opening portion and the first elongated opening portion of the opening region; forming an insulator layer on a portion of the first superconductor layer; depositing a second superconductor material on the insulator layer and the patterned resist layer at a second non-normal angle with respect to the substrate to form a second superconductor layer within the central opening portion and the second elongated portion of the opening region, where the first superconductor layer, the insulator layer, and the second superconductor layer within the central opening portion provide a superconductor tunnel junction; and forming a third superconductor layer directly on the surface of the first superconductor layer and directly on the surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a separate second contact to the superconductor tunnel junction, respectively.

[0005] The foregoing embodiments and other embodiments may each optionally include, individually or in combination, one or more of the following features. In some embodiments, a first superconducting layer is formed in a first section of the central opening portion, a second superconducting layer is formed in a second section of the central opening portion, and the first section and the second section of the central opening portion only partially overlap.

[0006] In some embodiments, a superconducting tunnel junction is formed at a position where the first section and the second section of the central opening portion partially overlap.

[0007] In some embodiments, a first contact is formed on the surface of the first superconducting layer at a position outside the position where the first section and the second section of the central opening portion partially overlap, and a second contact is formed on the surface of the second superconducting layer at a position outside the position where the first section and the second section of the central opening portion partially overlap.

[0008] In some embodiments, a first contact is formed on the surface of the first superconducting layer within the first elongated opening portion, and a second contact is formed on the surface of the second superconducting layer within the second elongated opening.

[0009] In some embodiments, the width of the first contact is greater than the width of the first superconducting layer within the first elongated portion, and the width of the second contact is greater than the width of the second superconducting layer within the second elongated portion.

[0010] In some embodiments, forming the third superconducting layer includes: forming a second resist layer on the first superconducting layer and the second superconducting layer; patterning the second resist layer to form a first contact opening and a second contact opening; and depositing a third superconductor on the patterned second resist layer and removing the second resist layer to form the first contact and the second contact.

[0011] In some embodiments, the method further includes: performing ion milling on the surface of the first superconducting layer exposed in the first contact opening and the surface of the second superconducting layer exposed in the second contact opening before depositing the third superconducting layer.

[0012] In some embodiments, the first resist layer is patterned using optical lithography.

[0013] In some embodiments, the aspect ratio between the height of the first resist layer and the width of the first elongated opening portion or the width of the second elongated opening portion is between 1:1 and 10:1.

[0014] In some embodiments, the height of the resist layer is between approximately 0.1 micrometer and approximately 4 micrometers.

[0015] In some embodiments, the superconducting tunnel junction forms part of an analog circuit element or a single-flux quantum logic circuit element.

[0016] Generally, another innovative aspect of the subject matter described in this specification can be implemented in a method that includes the following actions: providing a substrate including a first resist layer, the first resist layer being patterned to include an opening region that exposes the surface of the substrate, wherein the opening region is laterally surrounded by the first resist layer on all sides; depositing a first superconducting material on the patterned resist layer at a first non-normal angle with respect to the substrate in a first direction to form a first superconducting layer within the opening region, wherein the patterned resist layer prevents the first superconducting layer from forming in at least a first portion of the opening region; forming an insulator layer on a portion of the first superconducting layer; depositing a second superconducting material on the insulator layer and the patterned resist layer at a second non-normal angle with respect to the substrate in a second direction to form a second superconducting layer within the opening region, wherein the patterned resist layer prevents the second superconducting layer from forming in at least a second portion of the opening region, and wherein the first superconducting layer, the insulator layer, and the second superconducting layer within the opening region provide a superconducting tunnel junction; and forming a third superconducting layer directly on the surface of the first superconducting layer and directly on the surface of the second superconducting layer to provide a first contact to the superconducting tunnel junction and a separate second contact to the superconducting tunnel junction, respectively.

[0017] The foregoing embodiments and other embodiments can each optionally individually include or combinatorially include one or more of the following features. In some embodiments, the first superconducting layer is formed in a first section of the opening region, the second superconducting layer is formed in a second section of the opening region, and the first section and the second section of the opening region only partially overlap.

[0018] In some embodiments, the superconducting tunnel junction is formed at a location where the first section and the second section of the opening region partially overlap.

[0019] In some embodiments, the first contact is formed on the surface of the first superconducting layer at a location outside the location where the first section and the second section of the opening region partially overlap, and the second contact is formed on the surface of the second superconducting layer at a location outside the location where the first section and the second section of the opening region partially overlap.

[0020] In some embodiments, the first contact extends away from a first side of the opening region, and the second contact extends away from a different second side of the opening region.

[0021] In some embodiments, the first contact and the second contact extend in orthogonal directions.

[0022] In some embodiments, forming the third superconductor layer includes: forming a second resist layer on the first superconductor layer and the second superconductor layer; patterning the second resist layer to form a first contact opening and a second contact opening; and depositing a third superconductor on the patterned second resist layer and removing the second resist layer to form a first contact and a second contact.

[0023] In some embodiments, the method further includes: performing ion milling on the surface of the first superconductor layer exposed in the first contact opening and the surface of the second superconductor layer exposed in the second contact opening before depositing the third superconductor layer.

[0024] In some embodiments, the first resist layer is patterned using optical lithography.

[0025] In some embodiments, the height of the resist layer is between about 0.1 micrometer and about 4 micrometers.

[0026] In some embodiments, the superconducting tunnel junction forms part of an analog circuit element or a single flux quantum logic circuit element.

[0027] Generally, another innovative aspect of the subject matter described in this specification can be implemented in a device that includes: a substrate; a first superconductor layer on the substrate; an insulator layer on the first superconductor layer; a second superconductor layer on the insulator layer, wherein the first superconductor layer, the insulator layer, and the second superconductor layer form a superconducting tunnel junction; and a third superconductor layer that is directly on the surface of the first superconductor layer and directly on the surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a second contact to the superconducting tunnel junction, respectively.

[0028] The foregoing embodiments and other embodiments can each optionally include, alone or in combination, one or more of the following features. In some embodiments, the first superconductor layer includes a first portion that forms a bottom electrode to the superconducting tunnel junction and includes a second portion that is directly adjacent to the bottom electrode, wherein the first contact is directly formed on the second portion of the first superconductor layer, the second superconductor layer includes a first portion that forms a top electrode to the superconducting tunnel junction and includes a second portion that is directly adjacent to the top electrode, wherein the second contact is directly formed on the second portion of the second superconductor layer.

[0029] In some embodiments, the second portion of the first superconductor layer includes a corresponding wide section and a corresponding narrow section, the narrow section having a length extending outward from the wide section of the first superconductor layer, the second portion of the second superconductor layer includes a corresponding wide section and a corresponding narrow section, the narrow section having a length extending outward from the wide section of the second superconductor layer.

[0030] In some embodiments, the superconductor tunnel junction forms part of an amplifier circuit element.

[0031] In some embodiments, the superconductor tunnel junction forms part of an analog circuit element.

[0032] In some embodiments, the superconductor tunnel junction forms part of a single flux quantum logic circuit element.

[0033] The subject matter described in this specification can be implemented in a particular manner so as to achieve one or more of the following advantages.

[0034] For example, in some embodiments, the processes disclosed herein can be used to fabricate Josephson junctions having junction leads with reduced stray series inductance. Alternatively or additionally, due to an increase in the size of the overlapping regions between the superconductor material layers, the techniques disclosed herein can be used to increase the critical current of the Josephson junction. In some cases, the fabrication processes described herein reduce the number of patterning steps required to form the junction. Fewer patterning steps can result in fewer wafer removals from the deposition chamber, which in turn can reduce the risk of defects and simplify the fabrication process.

[0035] Josephson junctions fabricated using the two-angle deposition technique described in this specification can have any size (independent of the electrode width) without causing an accidental short circuit. This is in contrast to Josephson junctions fabricated using other known two-angle deposition techniques, in which the side arms of the junction cannot be arbitrarily increased due to the sidewalls of the resist layer or due to an increased risk of short circuits.

[0036] Because photolithography can be used instead of electron beam lithography to perform junction patterning, Josephson junctions fabricated using the techniques described in this specification can be fabricated in parallel. Electron beam lithography requires sequential exposure of each individual junction feature on the wafer, whereas with optical lithography, all features are exposed simultaneously. Depending on the specific device and wafer size, each wafer can have ~1e6 junctions.

[0037] In some embodiments, because the junction can be electrically connected to the circuit, for example via regions 104a and 104b, before each deposition step is completed, Josephson junctions fabricated using the techniques described in this specification allow the junction to be probed and characterized during the fabrication process for in-line metrology. Figure 1A of the junction to be probed and characterized during the fabrication process for in-line metrology.

[0038] In some embodiments, Josephson junctions fabricated using the techniques described in this specification have improved reproducibility of the junction critical current because area differences do not dominate resistance variations (as is the case for smaller junctions).

[0039] Details of one or more embodiments of the subject matter of this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the specification, the drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1A is a schematic diagram of an example state of a prior art double-angle Josephson junction.

[0041] Figure 1B is a schematic diagram of an example deposition angle relative to a wafer.

[0042] Figure 2 is a flowchart of a first example process for fabricating a low stray inductance Josephson junction.

[0043] Figures 3A - 3D is a schematic diagram of a top view and a cross-sectional view of an example substrate during a first example process for forming a Josephson junction with reduced stray inductance.

[0044] Figure 4 is a flowchart of a second example process for fabricating a low stray inductance Josephson junction.

[0045] Figures 5A - 5D is a schematic diagram of a top view of an example substrate during a second process for forming a Josephson junction with reduced stray inductance. DETAILED DESCRIPTION

[0046] Quantum computing requires the coherent processing of quantum information stored in qubits of a quantum computer. Superconducting quantum computing is an embodiment of quantum computing technology, where the quantum information processing device is partially formed of superconducting materials. The fabrication of an integrated quantum information processing device with superconducting components typically involves depositing and patterning superconducting materials, dielectrics, and metal layers. Josephson junctions can be used to construct some quantum information processing devices such as qubits.

[0047] A Josephson junction can be made by sandwiching a layer of non-superconducting material or a "barrier" of non-superconducting material between two layers of superconducting material. The non-superconducting material layer is thin enough to allow electrons to tunnel quantum mechanically from one superconducting layer through the non-superconducting material to the other superconducting layer. That is, until the critical current is reached, a supercurrent can flow through the barrier, and electron pairs can tunnel through the barrier without any resistance. For superconducting logic applications in quantum computing, the barrier material is an insulator, such as aluminum oxide.

[0048] One technique for fabricating Josephson junctions is the dual-angle deposition lift-off process. During this process, a first superconductor layer is deposited on a wafer at a first angle relative to the patterned resist features, the first superconductor layer is then oxidized, and then a second superconductor is deposited at a second angle relative to the patterned resist. The two deposition angles result in two offset images of the resist pattern. This technique relies on masking from the resist stack to cover sections of the pattern to create two electrically distinct metal regions that are connected by a junction oxide in a well-defined overlap region in the pattern.

[0049] Josephson Junction with Reduced Stray Inductance

[0050] The present disclosure provides methods and apparatus for fabricating Josephson junctions with reduced stray series inductance of the junction leads using a dual-angle deposition process.

[0051] Figure 1A is a schematic diagram of an example dual-angle Josephson junction. Regions 102a, 102b represent etched-defined portions of the circuit. Regions 104a, 104b, 104c represent superconductors deposited in two angle steps described below. The region enclosed by the dashed line 108 represents the overlap region where the junction is formed, and region 106 represents the portion of the pattern that is masked by the resist during the two deposition steps. Figure 1B is a schematic diagram of an example deposition angle relative to the wafer. Different from other dual-angle deposition techniques, the first deposition is represented by the arrow 152 along the negative x-axis (as opposed to deposition along the + axis). The first deposition is at 45° to the upper surface of the wafer (the surface on which the components are formed), however, in some cases, the first deposition angle can take other values. The second deposition is represented by the arrow 154 along the positive y-axis (as opposed to deposition along the – axis). The second deposition is also at 45° to the upper surface of the wafer, however, this is only an example, and in some cases, the second deposition angle can take other values.

[0052] The dual-angle deposition technique used in this specification requires that the leads connecting the junction to the rest of the circuit be long and narrow. The width of these leads must be small enough to be masked by the resist stack, and their length is typically constrained by the minimum pitch design rules of the process. For example, even though the junction itself spans several micrometers, the length of the leads can be 2 μm and the width can be 0.3 - 0.7 μm.

[0053] As a result of the geometry of the junction leads, the leads exhibit a large series inductance leading to the junction, which is unacceptable in applications such as Josephson logic, Josephson amplifiers, and microwave components. Additionally, due to the high aspect ratio of the leads, their inductance may be more difficult to control relative to variations in the manufacturing process.

[0054] Refer to the following Figure 2 andFigures 3A - 3D Describe an exemplary process for fabricating a Josephson junction with reduced stray inductance.

[0055] Figure 2 FIG. 5 is a flowchart of a first exemplary process 200 for forming a Josephson junction with reduced stray inductance. For example, process 200 may be used to form the Josephson junction shown in the present application. Figure 3D as shown.

[0056] Provide a substrate including a first resist layer that has been patterned to expose an opening region (step 202). Figure 3A FIG. 6 shows a schematic diagram of the provided substrate.

[0057] The first resist layer may have been patterned using optical lithography and may have a height between about 0.1 micrometer and about 4 micrometers. In some embodiments, the first resist layer may include a bilayer resist stack, where the bottom of the stack is an undercut layer and the top is an imaging layer.

[0058] The opening region includes: a central opening portion; a first elongated opening portion having a length extending from a first side of the central opening portion in a first direction; and a second elongated portion having a length extending from a second side of the central opening portion in a second direction, the second direction being different from the first direction, e.g., orthogonal to the first direction.

[0059] The width of the first elongated portion is less than the width of the first side of the central opening. Additionally, the width of the second elongated portion is less than the length of the second side of the central opening. In some embodiments, the aspect ratio between the height of the first resist layer and the width of the first elongated opening portion or the second elongated opening portion may be between 1:1 and 10:1.

[0060] Deposit a first superconductor material on the patterned resist layer relative to the substrate at a first non-normal angle to form a first superconductor layer within the central opening portion and the first elongated opening portion of the opening region (step 204). Figure 3B FIG. 7 shows a schematic diagram of the substrate after the first superconductor material is deposited on the first resist layer.

[0061] Form an insulator layer on a portion of the first superconductor layer (step 206). Figure 3C FIG. 8 shows a schematic diagram of the substrate with the insulator layer formed on a portion of the first superconducting layer.

[0062] A second superconductor material is deposited at a second non-normal angle with respect to the substrate on the insulator layer and the patterned resist layer to form a second superconductor layer within the central opening portion and the second elongated opening portion of the opening region (step 208). The first superconductor layer, the insulator layer, and the second superconductor layer within the central opening portion provide a superconductor tunnel junction.

[0063] In some embodiments, the first superconductor layer may be formed in a first section of the central opening portion, and the second superconductor layer may be formed in a second section of the central opening portion, wherein the first section of the central opening portion and the second section of the central opening portion only partially overlap. In these embodiments, a superconductor tunnel junction may be formed at the position where the first section of the central opening portion and the second section of the central opening portion partially overlap.

[0064] A third superconductor layer is formed directly on the surface of the first superconductor layer and directly on the surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a separate second contact to the superconductor tunnel junction, respectively (step 212). Figure 3D A schematic view of the substrate is shown after the third superconductor layer has been formed directly on a portion of the surface of the first superconductor layer and a portion of the surface of the second superconductor layer.

[0065] Forming the third superconductor layer may include forming a second resist layer on the first superconductor layer and on the second superconductor layer (step 210), patterning the second resist layer to form a first contact opening and a second contact opening (step 210), and depositing a third superconductor material on the patterned second resist layer. The third superconductor material may be deposited at an angle perpendicular to the substrate. Forming the third superconductor layer may then further include removing the second resist layer to form the first contact and the second contact. Optionally, prior to depositing the third superconductor layer, ion milling may be performed on the surface of the first superconductor layer exposed in the first contact opening and on the surface of the second superconductor layer exposed in the second contact opening.

[0066] In embodiments where the superconductor tunnel junction is formed at the position where the first section of the central opening portion and the second section of the central opening portion partially overlap, the first contact may be formed on the surface of the first superconductor layer located outside the position where the first section of the central opening portion and the second section of the central opening portion partially overlap. Similarly, the second contact may be formed on the surface of the second superconductor layer located outside the position where the first section of the central opening portion and the second section of the central opening portion partially overlap.

[0067] In some embodiments, a first contact may be formed on a surface of a first superconductor layer located within a first elongated opening portion. In some embodiments, a second contact may be formed on a surface of a second superconductor layer located within a second elongated opening portion. The width of the first contact may be greater than the width of the first superconductor layer within the first elongated portion. Additionally, the width of the second contact may be greater than the width of the second superconductor layer within the second elongated portion.

[0068] For convenience, process 200 has been described with reference to forming a single Josephson junction using a first resist layer that has been patterned to expose a single opening region. However, in some embodiments, the first resist layer may include multiple opening regions such that process 200 can be used to form multiple Josephson junctions in parallel.

[0069] Devices formed by process 200, such as the devices shown below in Figure 3D may be provided for various applications. For example, the device may be provided for use as an element in a quantum circuit, a Josephson amplifier, or as a microwave component. As another example, the device may be provided for use as an element in an analog circuit, e.g., a microwave component such as a switch, mixer, phase shifter, resonator, filter, or detector.

[0070] Figures 3A - 3D is a schematic diagram of a top view and cross-sectional views of an example substrate 302 during a first example process 200 for forming a Josephson junction with reduced stray inductance.

[0071] Figure 3A shows a schematic diagram of the provided substrate 302 in a top view 300a, a cross-sectional view 300b taken along axis A - A', and a cross-sectional view 300c taken along axis B - B'. The provided substrate 302 corresponds to the substrate provided at Figure 2 step 202 of

[0072] The substrate 302 includes a first resist layer 304 for defining a Josephson junction. In some embodiments, the height of the first resist layer 304 may be, for example, between about 0.1 micrometer and about 4 micrometers. The first resist layer 304 is patterned to expose an opening region 306 defined by the dashed line. The area size of the opening 306 depends on the process and the circuit to which the junction will be connected. However, the area size of the opening 306 may be limited by factors such as defect rate, stray capacitance of the junction, and manufacturing considerations. As an example, the area size of the opening 306 may be less than 5.0 μm by 5.0 μm. In some embodiments, the first resist layer 304 may be patterned using optical lithography.

[0073] The opening region 306 includes a central opening portion 306a, a first elongated opening portion 306b, and a second elongated opening portion 306c.

[0074] The first elongated opening portion 306b has a length extending from a first side 308a of the central opening portion 306a in a first direction. The width 310 of the first elongated opening portion 306b is less than the length 312 of the first side 308a of the central opening 306a (or equivalently, narrower than the width of the central opening portion 306a). In some embodiments, the width 310 may be approximately equal to 0.3 μm. In some embodiments, the length L1 of the first elongated opening portion 306b may be approximately equal to 2 μm. In some embodiments, the aspect ratio between the height of the first resist layer 304 and the width 310 of the first elongated opening portion 306b is between 1:1 and 10:1.

[0075] The second elongated portion 306c has a length extending from a second side 308b of the central opening portion 306a in a second direction different from the first direction. For example, the first direction and the second direction are orthogonal. The width 314 of the second elongated portion 306c is less than the length of the second side 308b of the central opening portion 306a (or equivalently, narrower than the height 316 of the central opening portion 306a). In some embodiments, the width 314 may be approximately equal to 0.3 μm and / or the height 316 of the central opening portion 306a may be approximately equal to 3.5 μm. In some embodiments, the aspect ratio between the height of the first resist layer 304 and the width 314 of the second elongated opening portion 306c may be between 1:1 and 10:1.

[0076] Each of the elongated portions 306b, 306c may be coupled to first and second devices or components 318b, 318c formed on the substrate 302, respectively. For example, the devices or components 318b, 318c may include a ground connection, a capacitor, an inductor, another Josephson junction, a coplanar waveguide, a qubit, a qubit readout resonator, a qubit control element (such as a qubit Z control or a qubit XY control element), and other circuit elements.

[0077] Figure 3B A schematic view of the substrate 302 is shown in a top view 300d, a cross-sectional view 300e taken along axis C-C', and a cross-sectional view 300f taken along axis D-D' after the first superconducting material 320 is deposited on Figure 3A the first resist layer 304 shown. For example, Figure 3B the schematic view of the substrate 302 shown corresponds to Figure 2 step 204. In some embodiments, the first superconducting material 320 may be aluminum.

[0078] The first superconducting material 320 may be deposited on the first resist layer 304 at a first non-normal angle with respect to the upper surface of the substrate 302, as described above with reference to Figure 1B that. In some embodiments, the first non-normal angle may be 45 degrees. Depositing the first superconducting material 320 at a first non-normal angle with respect to the substrate surface 302 forms a first superconducting layer 322 (defined by the dashed line) within the central opening portion 306a and the first elongated opening portion 306b of the opening region 306.

[0079] Figure 3C Illustrated is a schematic view of the substrate 302 in a top view 300g, a cross-sectional view 300h taken along axis E-E', and a cross-sectional view 300i taken along axis F-F' after an insulator layer 360 (e.g., an oxide layer) is formed on a portion of the first superconducting layer 322 shown in Figure 3B and the second superconducting material 326 is deposited on the insulator layer 360 and the first resist layer 304 shown in Figure 3A . For example, the schematic view of the substrate 302 shown in Figure 3C may correspond to step 206 of Figure 2 . In some embodiments, the second superconducting material 326 may be aluminum.

[0080] The second superconducting material 326 may be deposited on the insulator layer 360 and the first resist layer 304 at a second non-normal angle with respect to the substrate 302, as described above with reference to Figure 1B that. In some embodiments, the second non-normal angle may be 45 degrees. Depositing the second superconducting material 326 at a second non-normal angle with respect to the substrate surface 302 forms a second superconducting layer 328 (defined by the dashed line) within the central opening portion 306a and the second elongated opening portion 306c of the opening region 306.

[0081] The portions of the first superconducting layer 322, the insulator layer 360, and the second superconducting layer 328 that are located within and overlap in the central opening portion 306a provide a superconducting tunnel junction. In some embodiments, the first section of the central opening portion 306a in which the first superconducting layer 322 is formed and the second section of the central opening portion 306a in which the second superconducting layer 328 is formed may only partially overlap in the region 330. In the Figure 3C example shown, the superconducting tunnel junction is defined within the region surrounded by the dashed line 324.

[0082] Figure 3D Illustrated is a schematic view of the substrate 302 after a third superconducting layer has been directly formed on a portion of the surface of the first superconducting layer 322 shown in Figure 3C and a portion of the surface of the second superconducting layer 328 shown in Figure 3C . For example, Figure 3DThe schematic diagram of the substrate 302 shown may correspond to Figure 2 step 212.

[0083] The third superconductor layer provides a first contact 332a to the superconducting tunnel junction 330 and a separate second contact 332b to the superconducting tunnel junction 330, respectively. The deposition of the third superconductor layer provides electrical contact to the superconducting tunnel junction 330 and to the remainder of the circuit (e.g., etched-defined portions 318a and 318b) to provide a current path.

[0084] In some embodiments, the first contact 332a may be formed on the surface of the first superconductor layer 322 outside of the position where a first section of the central opening portion 306a and a second section of the central opening portion 306a partially overlap (e.g., outside of region 330). In these embodiments, the first contact 332a may be formed on the surface of the first superconductor layer 322 within the first elongated opening portion 306b.

[0085] Similarly, in some embodiments, the second contact 332b may be formed on the surface of the second superconductor layer 328 outside of the position where a first section of the central opening portion 306a and a second section of the central opening portion 306a partially overlap (e.g., outside of region 330). In these embodiments, the second contact 332b may be formed on the surface of the second superconductor layer 328 within the second elongated opening portion 306c.

[0086] The width 334a of the first contact 332a is greater than the width of the first superconductor layer 322 within the first elongated portion 306b (e.g., Figure 3A width 310). Similarly, the width 334b of the second contact 332b is greater than the width of the second superconductor layer 328 within the second elongated portion 306b (e.g., Figure 3A width 314). In some embodiments, the width 334a of the first contact 332a and / or the width 334b of the second contact 332b may be approximately equal to 2 μm, or equal to a value between 2 μm and 5 μm. Such widths can reduce the stray inductance of the leads of the Josephson junction to approximately 2 pH per lead. In cases where wider contacts are needed, additional width can be achieved by extending other elements such as etched-defined portions 318a and 318b.

[0087] Next, with reference to Figure 4 and Figures 5A - 5C another exemplary process for manufacturing a Josephson junction with reduced stray inductance will be described.

[0088] Figure 4is a flow chart of a second exemplary process 400 for forming a Josephson junction with reduced stray inductance. For example, process 400 can be used to form the Josephson junction shown in Figure 5D this application.

[0089] Provide a substrate including a first resist layer, the first resist layer being patterned to include an opening area exposing the substrate surface (step 402). In some embodiments, the first resist layer can be a bilayer, i.e., a layer suitable for angled deposition techniques. In some embodiments, the first resist layer can have been patterned using optical lithography and can have a height between approximately 0.1 micrometers and approximately 4 micrometers.

[0090] The opening area can be, for example, in the shape of a rectangle (such as a square), which is laterally surrounded by the first resist layer on all sides. For example, the opening area is a central opening area that does not have any elongated opening portions extending outward from the central opening area. The area size of the central opening area depends on the deposition angle and the resist thickness. For example, for a 1 μm thick resist and a 45-degree deposition angle, the area of the central opening area can be at least 1 μm by 1 μm. A schematic diagram of the substrate provided in step 402 is shown in Figure 5A this figure.

[0091] Deposit a first superconductor material on the patterned resist layer at a first non-normal angle relative to the substrate in a first direction to form a first superconductor layer within the opening area (step 404). The patterned resist layer prevents the first superconductor layer from forming in at least a first portion of the opening area. Figure 5B A schematic diagram of the substrate after the first superconductor material is deposited on the first resist layer is shown in

[0092] Form an insulator layer on a portion of the first superconductor layer (step 406).

[0093] Deposit a second superconductor material on the insulator layer and the patterned resist layer at a second non-normal angle relative to the substrate in a second direction to form a second superconductor layer within the opening area (step 408). The patterned resist layer prevents the second superconductor layer from forming in at least a second portion of the opening area, and the first superconductor layer, insulator layer, and second superconductor layer within the opening area provide a superconductor tunnel junction. Figure 5C A schematic diagram of the substrate after the insulator layer is formed on a portion of the first superconducting layer and the second superconductor material is deposited on the insulator layer and the first resist layer is shown in

[0094] In some embodiments, a first superconducting layer may be formed in a first section of the opening region, and a second superconducting layer may be formed in a second section of the opening region. The first section of the opening region and the second section of the opening region may only partially overlap. In these embodiments, a superconducting tunnel junction may be formed at a location where the first section of the opening region and the second section of the opening region partially overlap.

[0095] (After the second patterning step described below) A third superconducting layer is formed directly on the surface of the first superconducting layer and directly on the surface of the second superconducting layer to provide a first contact to the superconducting tunnel junction and a separate second contact to the superconducting tunnel junction, respectively (step 410). The first contact may be formed on the surface of the first superconducting layer at a location outside the location where the first section of the opening region and the second section of the opening region partially overlap. Similarly, the second contact may be formed on the surface of the second superconducting layer at a location outside the location where the first section of the opening region and the second section of the opening region partially overlap. Figure 5D A schematic view of the substrate after the third superconducting layer has been directly formed on a portion of the surface of the first superconducting layer and a portion of the surface of the second superconducting layer is shown.

[0096] In some embodiments, the first contact extends away from a first side of the opening region, and the second contact extends away from a different second side of the opening region. In these embodiments, the first contact and the second contact may extend in orthogonal directions.

[0097] Forming the third superconducting layer may include: forming a second resist layer on the first superconducting layer and the second superconducting layer; patterning the second resist layer to form a first contact opening and a second contact opening; and depositing the third superconducting layer on the patterned second resist layer and removing the second resist layer to form the first contact and the second contact. Optionally, before depositing the third superconducting layer, ion milling may be performed on the surface of the first superconducting layer exposed in the first contact opening and the surface of the second superconducting layer exposed in the second contact opening.

[0098] For convenience, process 400 has been described with reference to forming a single Josephson junction using a first resist layer that has been patterned to expose a single opening region. However, in some embodiments, the first resist layer may include multiple opening regions such that process 400 can be used to form multiple Josephson junctions in parallel.

[0099] Devices formed by process 400, such as the following Figure 5DThe device shown can be provided for various applications. For example, the device can be provided as an element in a quantum circuit, a Josephson amplifier, or as a microwave component. As another example, the device can be provided as an element in an analog circuit, such as a microwave component, such as a switch, mixer, phase shifter, resonator, filter, or detector.

[0100] Figures 5A - 5D FIG. is a schematic top view of an example substrate 502 during a second example process 400 for forming a Josephson junction with reduced stray inductance.

[0101] Figure 5A A schematic view of the provided substrate 502 is shown. The substrate 502 includes a first resist layer 504 for defining a Josephson junction. In some embodiments, the height of the first resist layer 504 can be between about 0.1 micrometer and about 4 micrometers. The first resist layer 504 is patterned to include an opening region 506 that exposes the surface of the substrate 502. For example, the first resist layer 504 can be patterned using optical lithography. The opening region 506 includes, for example, a rectangular opening region (such as a square opening region) that is laterally surrounded by the first resist layer 504 on all sides. For example, the opening region 506 is a central opening region that does not have any elongated opening portions (such as Figure 3A the elongated portions 306c, 306b shown) extending outward from the central opening region 506. Figure 5A The schematic view of the substrate 502 shown corresponds to Figure 4 step 402.

[0102] Figure 5B A schematic view of the substrate 502 is shown after a first superconducting material 508 is deposited on Figure 5A the first resist layer 504 shown. Figure 5B The schematic view of the substrate 502 shown corresponds to Figure 4 step 404. In some embodiments, the first superconducting material 508 can be aluminum.

[0103] The first superconducting material 508 can be deposited on the first resist layer 504 at a first non-normal angle with respect to the upper surface of the substrate 502 in a first direction, as described above with reference to Figure 1B FIG. In some embodiments, the first non-normal angle can be 45 degrees. Depositing the first superconducting material 508 at a first non-normal angle with respect to the substrate 502 in a first direction forms a first superconducting layer 510 (defined by the dashed line) within the opening region 506. As Figure 5BAs shown, patterning of the resist layer 504 prevents the first superconductor layer 510 from forming in at least a first portion of the opening region 506, e.g., in the top section of the opening region 506. An insulator layer, such as an oxide layer, can be formed on a portion of the first superconducting layer 510, and this insulator layer can serve as a barrier layer for a superconductor tunnel junction or a Josephson junction.

[0104] Figure 5C Shown is a schematic of the substrate 502 after an insulator layer, such as an oxide layer, has been formed on Figure 5B a portion of the first superconducting layer 510 and the second superconductor material 512 has been deposited on the insulator layer and Figure 5A the first resist layer 504 as shown. Figure 5C The schematic of the substrate 502 shown corresponds to Figure 4 step 406. In some embodiments, the second superconductor material 512 can be aluminum.

[0105] The second superconductor material 512 can be deposited on the insulator layer and the first resist layer 504 at a second non-normal angle with respect to the upper surface of the substrate 502 along a second direction, as referred to above with reference to Figure 1B described. In some embodiments, the second non-normal angle can be 45 degrees. Depositing the second superconductor material 512 at a second non-normal angle with respect to the substrate 502 along the second direction forms a second superconductor layer 514 (defined by the shaded region) within the opening region 506. As Figure 5C shown, patterning of the resist layer 504 prevents the second superconductor layer 514 from forming in at least a second portion of the opening region 506, e.g., in the rightmost section of the opening region 506, leaving the top right corner that does not have a superconductor layer formed on the exposed portion of the substrate.

[0106] The first superconductor layer 510, the insulator layer, and the second superconductor layer 514 within the opening region 506 provide a superconductor tunnel junction. In some embodiments, a first section of the opening portion 506 where the first superconductor layer 510 is formed and a second section of the opening portion 506 where the second superconductor layer 514 is formed can only partially overlap, e.g., in region 516. In these embodiments, the superconductor tunnel junction can be formed at the location where the first section and the second section of the opening portion 506 partially overlap. In Figure 5C the example shown, the superconductor tunnel junction is defined within the region surrounded by the dashed line 518.

[0107] Figure 5D Shown is after a third superconductor layer has been directly formed on Figure 5B a portion of the surface of the first superconducting layer 510 and Figure 5CSchematic of the substrate 502 after on a portion of the surface of the second superconducting layer 514. The third superconducting layer provides a first contact 520a to the superconducting tunnel junction 518 and a separate second contact 520b to the superconductor tunnel junction 518, respectively. Figure 5D The schematic of the substrate 502 shown corresponds to Figure 4 step 410.

[0108] In some embodiments, the first contact 520a may be formed on the surface of the first superconducting layer 510 outside of a position where a first section of the opening portion 506 and a second section of the opening portion 506 partially overlap (e.g., outside of Figure 5C region 516). Similarly, in some embodiments, the second contact 520b may be formed on the surface of the second superconducting layer 514 outside of a position where a first section of the opening portion 506 and a second section of the opening portion 506 partially overlap (e.g., outside of Figure 5C region 516).

[0109] As Figure 5D shown, the first contact 520a may extend away from the first side 522a of the opening region 506, and the second contact 520b may extend away from a different second side 522b of the opening region. In some embodiments, the first contact 520a and the second contact 520b may extend in orthogonal directions, i.e., the first side 522a and the second side 522b may be orthogonal.

[0110] Depositing the third superconducting layer in this manner provides electrical contact to the superconducting tunnel junction 518 and to the remainder of the circuit (e.g., circuit elements 524a and 524b) to provide a low inductance current path. The circuit elements 524a and 524b may include, for example, other components formed on the substrate, including, for example, ground connections, inductors, capacitors, other Josephson junctions, qubits, coplanar waveguides, qubit readout resonators, qubit control elements (e.g., qubit Z control elements or qubit XY control elements), and other circuit elements. Although not shown in Figure 5D it, in some embodiments, the circuit elements 520a, 520b, 524a, and 524b may be wider than the junction leads 514 and 510 (if desired, e.g., to reduce inductance).

[0111] An example of a superconducting material that can be used to form quantum circuit elements is aluminum. Aluminum can be used in combination with a dielectric to create Josephson junctions, which are common components of quantum circuit elements. Examples of quantum circuit elements that can be formed with aluminum include circuit elements such as superconducting coplanar waveguides, quantum LC oscillators, qubits (e.g., flux qubits or charge qubits), superconducting quantum interference devices (SQUIDs) (e.g., RF-SQUIDs or DC-SQUIDs), inductors, capacitors, transmission lines, ground planes, and the like. Other superconducting materials can include, for example, niobium or titanium nitride.

[0112] Aluminum can also be used to form superconducting classical circuit elements that can interoperate with superconducting quantum circuit elements and other classical circuit elements based on complementary metal oxide semiconductor (CMOS) circuits. Examples of classical circuit elements that can be formed with aluminum include rapid single flux quantum (RSFQ) devices, reciprocal quantum logic (RQL) devices, and ERSFQ devices (which are energy-efficient versions of RSFQ that do not use bias resistors). Other classical circuit elements can also be formed with aluminum. The classical circuit elements can be configured to jointly execute the instructions of a computer program by performing basic arithmetic, logical, and / or input / output operations on data, where the data is represented in analog or digital form.

[0113] Another example of a superconducting material that can be used to form quantum circuit elements is niobium. Niobium can be used to form wiring, waveguides, inductors, or capacitors. In some embodiments, different types of superconducting materials can be used in the same circuit element. For example, a first type of superconducting material (e.g., niobium) can be used for wiring, waveguides, inductors, capacitors, etc., and a second type of superconductor (e.g., aluminum) can be used to form Josephson junctions.

[0114] The processes described herein may require depositing one or more materials, such as superconductors, dielectrics, and / or metals. Depending on the materials selected, these materials can be deposited using deposition processes such as chemical vapor deposition, physical vapor deposition (e.g., evaporation or sputtering), or epitaxial techniques and other deposition processes. The processes described herein may also require removing one or more materials from the device during fabrication. Depending on the materials to be removed, the removal processes can include, for example, wet etching techniques, dry etching techniques, lift-off processes, or chemical mechanical polishing.

[0115] The described subject matter and the implementations of the operations herein can be implemented in digital electronic circuitry, in analog electronic circuitry, in suitable quantum circuitry (or more generally, a quantum computing system), in tangibly embodied software or firmware, in computer hardware including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. The term "quantum computing system" can include, but is not limited to, a quantum computer, a quantum information processing system, a quantum cryptography system, or a quantum simulator.

[0116] The terms quantum information and quantum data refer to information or data carried, held, or stored in a quantum system, where the smallest non-trivial system is a qubit, i.e., the system that defines the unit of quantum information. It is to be understood that the term "qubit" encompasses all quantum systems that can be appropriately approximated as two-level systems in the corresponding context. Such quantum systems can include, for example, multi-level systems having two or more energy levels. By way of example, such systems can include atoms, electrons, photons, ions, or superconducting qubits. In many implementations, the computational basis states are identified as the ground state and the first excited state, however, it is to be understood that other settings where the computational states are identified with higher energy excited states are possible.

[0117] Quantum circuit elements (also referred to as quantum computing circuit elements) include circuit elements for performing quantum processing operations. That is, quantum circuit elements are configured to utilize quantum mechanical phenomena such as superposition and entanglement to perform operations on data in a non-deterministic manner. Some quantum circuit elements (such as qubits) can be configured to represent information in more than one state simultaneously and operate on the information. Examples of superconducting quantum circuit elements include circuit elements such as quantum LC oscillators, qubits (e.g., flux qubits, phase qubits, or charge qubits), and superconducting quantum interference devices (SQUIDs) (e.g., RF-SQUIDs or DC-SQUIDs).

[0118] In contrast, classical circuit elements generally process data in a deterministic manner. Classical circuit elements can be configured to jointly execute the instructions of a computer program by performing basic arithmetic, logical, and / or input / output operations on data, where the data is represented in analog or digital form. In some implementations, classical circuit elements can be used to send data to and / or receive data from quantum circuit elements via electrical connections or electromagnetic connections. Examples of classical circuit elements include circuit elements based on CMOS circuits, rapid single flux quantum (RSFQ) devices, reciprocal quantum logic (RQL) devices, and ERSFQ devices (which are an energy-efficient version of RSFQ that do not use bias resistors).

[0119] In some cases, some or all of the quantum and / or classical circuit elements can be implemented using, for example, superconducting qubits and / or classical circuit elements. Fabrication of superconducting circuit elements may require deposition of one or more materials, such as superconductors, dielectrics, and / or metals. Depending on the materials selected, these materials can be deposited using deposition processes such as chemical vapor deposition, physical vapor deposition (e.g., evaporation or sputtering), or epitaxial techniques and other deposition processes. The processes for fabricating circuit elements described herein may require removal of one or more materials from the device during fabrication. Depending on the materials to be removed, the removal processes can include, for example, wet etching techniques, dry etching techniques, lift-off processes, or chemical mechanical polishing. Known etching techniques (e.g., photolithography or electron beam lithography) can be used to pattern the materials forming the circuit elements described herein.

[0120] During operation of a quantum computing system using superconducting quantum circuit elements and / or superconducting classical circuit elements (such as the circuit elements described herein), the superconducting circuit elements are cooled within a cryostat to a temperature that allows the superconducting material to exhibit superconducting properties. A superconductor (alternatively, superconducting) material can be understood as a material that exhibits superconducting properties at or below the superconducting critical temperature. Examples of superconducting materials include aluminum (superconducting critical temperature of 1.2 Kelvin) and niobium (superconducting critical temperature of 9.3 Kelvin). Thus, superconducting structures such as superconducting traces and superconducting ground planes are formed from materials that exhibit superconducting properties at or below the superconducting critical temperature.

[0121] In some embodiments, classical circuit elements that are electrically and / or electromagnetically coupled to the quantum circuit elements can be used to provide control signals for the quantum circuit elements (e.g., qubits and qubit couplers). The control signals can be provided in digital and / or analog form.

[0122] Although this specification contains many specific implementation details, these should not be construed as limitations on the scope of what is claimed, but rather as descriptions of features specific to particular embodiments. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented separately in multiple embodiments or in any suitable sub-combination. Moreover, although the features may be described above as acting in certain combinations and even initially claimed as such, in some cases one or more features from the claimed combination can be removed from the combination, and the claimed combination can be directed to a sub-combination or a variation of the sub-combination.

[0123] Similarly, although the operations are depicted in the drawings in a particular order, this should not be construed as requiring that the operations be performed in the particular order shown or in a sequential order, or that all of the illustrated operations be performed to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Additionally, the separation of various system modules and components in the above-described embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems generally may be integrated together in a single software product or packaged into multiple software products.

[0124] Particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the acts recited in the claims may be performed in a different order and still achieve the desired result. As one example, the processes depicted in the figures do not necessarily require the particular order shown or sequential order to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous.

Claims

1. A device, comprising: a substrate; a first superconductor layer on a top surface of the substrate; an insulator layer on a top surface of the first superconductor layer; a second superconductor layer on a top surface of the insulator layer, wherein the first superconductor layer, the insulator layer, and the second superconductor layer form a Josephson junction; and a third superconductor layer, wherein a first portion of the third superconductor layer is in direct contact with the top surface of the first superconductor layer and extends along a first direction to provide a first contact to the Josephson junction, and a second portion of the third superconductor layer is in direct contact with the top surface of the second superconductor layer and extends along a second direction to provide a separate second contact to the Josephson junction, wherein an edge of the first contact is separated and laterally spaced from an edge of the second contact, wherein the first superconductor layer includes forming a bottom electrode to a first portion of the Josephson junction, wherein the second superconductor layer includes forming a top electrode to a first portion of the Josephson junction.

2. The device according to claim 1, wherein the Josephson junction forms part of an analog circuit element.

3. The device according to claim 1, wherein the Josephson junction forms part of a single flux quantum logic circuit element.

4. The device according to claim 1, wherein the first contact is formed on a portion of the surface of the first superconductor layer that does not overlap with the Josephson junction.

5. The device according to claim 1, wherein the second contact is formed on a portion of the surface of the second superconductor layer that does not overlap with the Josephson junction.

6. The device according to claim 1, wherein, The first contact provides a first low-inductance current path to a first circuit element, and the second contact provides a second low-inductance current path to a second circuit element.

7. The device according to claim 6, wherein each of the first low-inductance current path and the second low-inductance current path includes an inductance of less than 2 picohenries (pH).

8. The device according to claim 1, wherein the first superconductor layer, the second superconductor layer, and the third superconductor layer include aluminum.

9. The device according to claim 1, wherein the insulator layer includes aluminum oxide.

10. The device according to claim 1, wherein the first contact and the second contact extend laterally to contact respective circuit elements that are laterally separated from a second portion of the first superconductor layer and a second portion of the second superconductor layer.

11. A device, comprising: a substrate; a first superconductor layer on a top surface of the substrate; an insulator layer on a top surface of the first superconductor layer; a second superconductor layer on a top surface of the insulator layer, wherein the first superconductor layer, the insulator layer, and the second superconductor layer form a Josephson junction; and A third superconducting layer, wherein a first portion of the third superconducting layer is in direct contact with the top surface of the first superconducting layer to provide a first contact to the Josephson junction, and a second portion of the third superconducting layer is in direct contact with the top surface of the second superconducting layer to provide a separate second contact to the Josephson junction, wherein the first contact is separated from and laterally spaced apart from the second contact, wherein the first superconducting layer includes a first portion that forms a bottom electrode to the Josephson junction, wherein the second superconducting layer includes a first portion that forms a top electrode to the Josephson junction, and wherein a second portion of the first superconducting layer extends in a first direction away from the bottom electrode of the Josephson junction, and a second portion of the second superconducting layer extends in a second direction away from the top electrode of the Josephson junction, wherein the first direction is orthogonal to the second direction.

12. The device according to claim 11, wherein, The first contact extends in the first direction away from the bottom electrode of the Josephson junction, and the second contact extends in the second direction away from the top electrode of the Josephson junction.

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