Semiconductor memory device

Abstract

A semiconductor memory device according to an embodiment of the present invention includes a first sub-word line driver and a second sub-word line driver. The first sub word line driver includes a first pull-down transistor and a first holding transistor. The second sub word line driver includes a second pull-down transistor and a second holding transistor. The source region of the first pull-down transistor and the source region of the second retention transistor are disposed to share a first doped region on the semiconductor substrate, and the source region of the second pull-down transistor and the source region of the first retention transistor are disposed to share a second doped region on the semiconductor substrate.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices, and more particularly, to semiconductor memory devices. Background Art

[0002] Semiconductor memory devices can be classified as volatile semiconductor memory devices or non-volatile semiconductor memory devices. In volatile memory devices such as dynamic random access memories (DRAMs), data is stored by charging / discharging a cell capacitor, and the stored data remains during the application of power, but is lost when power is not applied.

[0003] As the capacity of DRAMs increases, the number of memory cells connected to one word line increases, and the interval between word lines decreases. To drive the word lines, a method of dividing the word lines into a plurality of sub-word lines and driving each sub-word line using a sub-word line driver is adopted. To increase the integration degree of DRAMs, a method for reducing the area occupied by the sub-word line driver is required. Summary of the Invention Technical Problem

[0004] An object of the present disclosure is to provide a semiconductor memory device that reduces the chip size by reducing the area occupied by a sub-word line driver on a semiconductor substrate.

[0005] An object of the present disclosure is to provide a semiconductor memory device that allows various patterns included in a sub-word line driver to be finely formed by adjusting the layout of transistors included in the sub-word line driver. Technical Solution

[0006] A semiconductor memory device for achieving the above object according to an embodiment of the present disclosure includes a first sub-word line driver and a second sub-word line driver. The first sub-word line driver includes a first pull-down transistor and a first holding transistor. The first pull-down transistor pulls down a first word line during a deactivation interval of the first word line. The first holding transistor maintains the voltage level of the pulled-down first word line during the deactivation interval of the first word line. The second sub-word line driver includes a second pull-down transistor and a second holding transistor. The second pull-down transistor pulls down a second word line during a deactivation interval of the second word line. The second holding transistor maintains the voltage level of the pulled-down second word line during the deactivation interval of the second word line. A source region of the first pull-down transistor and a source region of the second holding transistor are provided to share a first doped region on a semiconductor substrate, and a source region of the second pull-down transistor and a source region of the first holding transistor are provided to share a second doped region on the semiconductor substrate.

[0007] A semiconductor memory device for achieving the above object according to an embodiment of the present disclosure includes a memory cell array and first to fourth sub - word line drivers. The memory cell array includes a plurality of memory cells connected to a plurality of word lines. The first to fourth sub - word line drivers respectively activate first to fourth word lines that extend to one side of the memory cell array and are adjacent to each other among the plurality of word lines. The first sub - word line driver includes a first pull - down transistor and a first holding transistor. The first pull - down transistor pulls down the first word line during the de - activation interval of the first word line. The first holding transistor maintains the voltage level of the pulled - down first word line during the de - activation interval of the first word line. The second sub - word line driver includes a second pull - down transistor and a second holding transistor. The second pull - down transistor pulls down the second word line during the de - activation interval of the second word line. The second holding transistor maintains the voltage level of the pulled - down second word line during the de - activation interval of the second word line. The source region of the first pull - down transistor and the source region of the second holding transistor are set to share a first doped region on the semiconductor substrate, and the source region of the second pull - down transistor and the source region of the first holding transistor are set to share a second doped region on the semiconductor substrate.

[0008] A semiconductor memory device for achieving the above object according to an embodiment of the present disclosure includes a first sub - word line driver, a second sub - word line driver, a first metal line, a second metal line, and a third metal line. The first sub - word line driver includes a first pull - down transistor and a first holding transistor. The first pull - down transistor pulls down the first word line during the de - activation interval of the first word line. The first holding transistor maintains the voltage level of the pulled - down first word line during the de - activation interval of the first word line. The second sub - word line driver includes a second pull - down transistor and a second holding transistor. The second pull - down transistor pulls down the second word line during the de - activation interval of the second word line. The second holding transistor maintains the voltage level of the pulled - down second word line during the de - activation interval of the second word line. The first metal line is electrically connected to the gates of the first pull - down transistor and the second pull - down transistor. The second metal line is electrically connected to the gate of the first holding transistor. The third metal line is electrically connected to the gate of the second holding transistor. The source region of the first pull - down transistor and the source region of the second holding transistor are set to share a first doped region on the semiconductor substrate, and the source region of the second pull - down transistor and the source region of the first holding transistor are set to share a second doped region on the semiconductor substrate. The drain region of the first holding transistor and the drain region of the first pull - down transistor are set to share a third doped region on the semiconductor substrate, and the drain region of the second holding transistor and the drain region of the second pull - down transistor are set to share a fourth doped region on the semiconductor substrate. Beneficial effects

[0009] The semiconductor memory device according to an embodiment of the present disclosure can reduce the chip size by reducing the area occupied by the sub - word line driver on the semiconductor substrate.

[0010] A semiconductor memory device according to an embodiment of the present disclosure can allow various patterns included in a sub - word line driver to be finely formed by adjusting the layout of transistors included in the sub - word line driver. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 and Figure 2 is a block diagram showing a semiconductor memory device including a sub - word line driver according to an embodiment of the present disclosure.

[0012] Figure 3 is showing Figure 1 and Figure 2 a circuit diagram of some sub - word line drivers shown in

[0013] Figure 4 is for describing Figure 1 the operation of the sub - word line driver

[0014] Figure 5 and Figure 6 is for describing Figure 3 an embodiment of the layout of transistors included in the sub - word line driver

[0015] Figure 7 and Figure 8 is for describing Figure 1 an embodiment of the layout of doped regions or metal lines included in the sub - word line driver

[0016] Figure 9 and Figure 10 is for describing Figure 1 an embodiment of the layout of transistors, doped regions or metal lines included in the sub - word line driver

[0017] Figure 11 is for describing Figure 1 the layout of the sub - word line driver

[0018] Figure 12 is a diagram for describing an embodiment of the layout of transistors, doped regions or metal lines included in a sub - word line driver according to an embodiment of the present disclosure.

[0019] Figure 13 is for describing Figure 12 the layout of the sub - word line driver

[0020] Figure 14 is a diagram showing an embodiment of the layout of a sub - word line driver according to an embodiment of the present disclosure.

[0021] Figure 15 is a block diagram showing a semiconductor memory device including a sub - word line driver according to an embodiment of the present disclosure.

[0022] Figure 16 is a flowchart showing a method for designing and manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0023] Figure 17a 、 17b and 17c are diagrams of photomasks depicting patterns included in a sub - word line driver for forming Figure 12 .

[0024] Figure 18 is a block diagram showing a computing system including a sub - word line driver according to an embodiment of the present disclosure.

[0025] Figure 19 is a diagram showing a data center applying a semiconductor memory device including a sub - word line driver according to an embodiment of the present disclosure. Detailed Description of the Invention

[0026] Figure 1 is a diagram representing the best mode for implementing the present disclosure.

[0027] Hereinafter, embodiments of the present disclosure will be described in detail and clearly so that those skilled in the art can easily implement the present disclosure.

[0028] Figure 1 and Figure 2 are block diagrams showing a semiconductor memory device including a sub - word line driver according to an embodiment of the present disclosure.

[0029] Referring to Figure 1 , the semiconductor memory device 100 may be a volatile memory device. Hereinafter, it is assumed that the volatile memory device is a dynamic random access memory (DRAM), but this is only an example. In an embodiment, the semiconductor memory device 100 may be any semiconductor memory device having the same or similar structure as a DRAM.

[0030] The semiconductor memory device 100 may include a memory cell array 101 and a plurality of sub - word line drivers, and the memory cell array 101 may include a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines and arranged in rows and columns. The plurality of sub - word line drivers may activate the plurality of word lines respectively.

[0031] In an embodiment, an activation interval and a deactivation interval may be defined for each of a plurality of word lines. The activation interval may be an interval during which each of the plurality of word lines maintains a first voltage level to drive selected memory cells in an operation mode of the semiconductor memory device 100 (e.g., a write operation mode, a read operation mode, and a self-refresh operation mode). The deactivation interval may be an interval during which each of the plurality of word lines maintains a second voltage level lower than the first voltage level to not drive unselected memory cells in each operation mode of the semiconductor memory device 100. The activation interval and the deactivation interval may be specific time intervals and may be referred to as a "driving time interval" and a "non-driving time interval", respectively. The activation interval and the deactivation interval will be described with reference to Figure 4 the activation interval and the deactivation interval are described.

[0032] The plurality of sub-word line drivers may include a first sub-word line driver 105 and a second sub-word line driver 109. The first sub-word line driver 105 and the second sub-word line driver 109 may activate a first word line WL1 and a second word line WL2 among the plurality of word lines, respectively, and may drive corresponding memory cells (or rows of memory cells) among the plurality of memory cells.

[0033] The first sub-word line driver 105 may include a first pull-down transistor PDTR1 and a first hold transistor KPTR1, and the second sub-word line driver 109 may include a second pull-down transistor PDTR2 and a second hold transistor KPTR2. Although Figure 1 not shown in the figure, each of the first sub-word line driver 105 and the second sub-word line driver 109 may further include a pull-up transistor for pulling up a corresponding word line and may further include one or more other transistors.

[0034] The first pull-down transistor PDTR1 may pull down the first word line WL1 during the deactivation interval of the first word line WL1, while the first hold transistor KPTR1 may maintain the voltage level of the first word line WL1 pulled down thereby. For example, during the deactivation interval of the first word line WL1, the first pull-down transistor PDTR1 may be turned on such that the first word line WL1 is pulled down to a negative voltage VBB2 corresponding to the second voltage level, and the first hold transistor KPTR1 may be turned on such that the voltage level of the pulled-down first word line WL1 is maintained at the negative voltage VBB2.

[0035] The second pull-down transistor PDTR2 can pull down the second word line WL2 during the deactivation interval of the second word line WL2, while the second holding transistor KPTR2 can maintain the voltage level of the second word line WL2 pulled down thereby. For example, during the deactivation interval of the second word line WL2, the second pull-down transistor PDTR2 can be turned on so that the second word line WL2 is pulled down to a negative voltage VBB2 corresponding to the second voltage level, and the second holding transistor KPTR2 can be turned on so that the voltage level of the pulled-down second word line WL2 is maintained at the negative voltage VBB2.

[0036] Each of the first pull-down transistor PDTR1, the first holding transistor KPTR1, the second pull-down transistor PDTR2, and the second holding transistor KPTR2 may include a drain region and a source region, and may include a channel region formed between the drain region and the source region at the time when each transistor is turned on. The drain region may be referred to as a "drain active region", and the source region may be referred to as a "source active region". A direct contact portion for electrical connection to an external circuit may be provided on the drain region and the source region.

[0037] In an embodiment, the first pull-down transistor PDTR1, the first holding transistor KPTR1, the second pull-down transistor PDTR2, and the second holding transistor KPTR2 may be formed on a semiconductor substrate.

[0038] The source regions of the first pull-down transistor PDTR1 and the second holding transistor KPTR2 may be provided on the semiconductor substrate to share a doped region SHRD_DPR1 on the semiconductor substrate. For example, the source regions of the first pull-down transistor PDTR1 and the second holding transistor KPTR2 may be formed on the doped region SHRD_DPR1 on the semiconductor substrate. For example, the doped region SHRD_DPR1 on the semiconductor substrate may include the source regions of the first pull-down transistor PDTR1 and the second holding transistor KPTR2.

[0039] The source regions of the second pull-down transistor PDTR2 and the first holding transistor KPTR1 may be provided on the semiconductor substrate to share a doped region SHRD_DPR2 on the semiconductor substrate. For example, the source regions of the second pull-down transistor PDTR2 and the first holding transistor KPTR1 may be formed on the doped region SHRD_DPR2 on the semiconductor substrate. For example, the doped region SHRD_DPR2 on the semiconductor substrate may include the source regions of the second pull-down transistor PDTR2 and the first holding transistor KPTR1.

[0040] Although Figure 1Although not shown, the drain regions of the first pull-down transistor PDTR1 and the first holding transistor KPTR1 may be disposed on the semiconductor substrate to share another doping region different from the doping regions SHRD_DPR1 and SHRD_DPR2. The drain regions of the second pull-down transistor PDTR2 and the second holding transistor KPTR2 may be disposed on the semiconductor substrate to share another doping region different from the doping regions SHRD_DPR1 and SHRD_DPR2.

[0041] Reference Figure 2 , the semiconductor memory device 100a may include memory cells (or “memory cell arrays”) 111, 113, and 115, sub-word line drivers 131 and 133, sense amplifier blocks 151, 152, 153, 154, 155, and 156, connection circuits 171, 172, 173, and 174, and a row decoder 190. The row decoder 190 may include a control signal generator 191.

[0042] The row decoder 190 may receive a row address RADO and may generate signals for driving the selected memory cells among the memory cells 111, 113, and 115. For example, based on the row address RADO, the row decoder 190 may generate one or more word line enable signals NWEIB<0>, NWEIB<1>, etc., and one or more sub-word line driver control signals PXID<0>, …, PXID<7>, …, PXIB<0>, …, PXIB<7>, etc., and may drive the selected memory cells.

[0043] In an embodiment, the row decoder 190 may generate one or more word line enable signals NWEIB<0>, NWEIB<1>, etc. based on the first bit of the row address RADO, and the control signal generator 191 included in the row decoder 190 may generate one or more sub-word line driver control signals PXID<0>, …, PXID<7>, …, PXIB<0>, …, PXIB<7>, etc. based on the second bit of the row address RADO. For example, when the results of decoding the first and second bits of the row address RADO indicate driving one or more of the memory cells MC0, MC1, MC2, MC3, MC4, MC5, MC6, and MC7, the row decoder 190 may generate the word line enable signal NWEIB<0>. In the case of driving one or more of the memory cells (e.g., MC0, MC2, MC4, and MC6), the control signal generator 191 may generate one or more of the sub-word line driver control signals PXID<0>, …, PXID<7>, …, PXIB<0>, …, PXIB<7>, etc. (e.g., PXID<0>, PXIB<0>, PXID<2>, PXIB<2>, PXID<4>, PXIB<4>, PXID<6>, and PXIB<6>). In this case, the sub-word line drivers SWD0, SWD2, SWD4, and SWD6 may activate the word lines WL<0>, WL<2>, WL<4>, and WL<6> based on the word line enable signal NWEIB<0> and the sub-word line driver control signals PXID<0>, PXIB<0>, PXID<2>, PXIB<2>, PXID<4>, PXIB<4>, PXID<6>, and PXIB<6>.

[0044] The connection circuits 171 to 174 may include metal lines for supplying power to or providing electrical signals generated from the sense amplifier blocks 151 to 156, the sub-word line drivers 131 and 133, and the memory cells 111, 113, and 115, and may include various circuits for any other operations of the semiconductor memory device 100a.

[0045] Each of the sub-word line drivers SWD0, SWD1, SWD2, SWD3, SWD4, SWD5, SWD6, and SWD7 may include a pull-down transistor and a hold transistor. The source region of the pull-down transistor included in one sub-word line driver and the source region of the hold transistor included in another sub-word line driver may share a doped region on the semiconductor substrate. The drain regions of the pull-down transistor and the hold transistor included in one sub-word line driver may share another doped region on the semiconductor substrate. The shared doped regions may be disposed separately from each other on the semiconductor substrate, and some of the shared doped regions may be symmetrically disposed. The shared doped regions will be described with reference to Figure 7 and Figure 9 describe the shared doped regions.

[0046] According to the above configuration, the semiconductor memory device according to an embodiment of the present disclosure can reduce the area occupied by the sub-word line driver on the semiconductor substrate, thereby reducing the chip size. In addition, by adjusting the layout of the transistors included in the sub-word line driver, various patterns included in the sub-word line driver can be formed finely.

[0047] Figure 3 is a diagram showing Figure 1 and Figure 2 a circuit diagram of some of the sub-word line drivers shown in.

[0048] In Figures 1 to 3 some components with the same reference numerals / symbols can perform substantially the same functions. Referring to Figure 3 , some 133a of the sub-word line drivers may include sub-word line drivers SWD0, SWD2, SWD4, and SWD6, and each of the sub-word line drivers SWD0, SWD2, SWD4, and SWD6 may include a pull-up transistor, a pull-down transistor, and a holding transistor. The pull-up transistor may be formed of a MOS transistor of a first conduction type, and each of the pull-down transistor and the holding transistor may be formed of a MOS transistor of a second conduction type.

[0049] For example, the sub-word line driver SWD0 may include a pull-up transistor PM0 formed of a PMOS transistor SWD0-P, and a pull-down transistor NM0 and a holding transistor KP0 formed of NMOS transistors SWD0-N, respectively. Accordingly, the PMOS transistor SWD0-P of the sub-word line driver SWD0 may refer to the pull-up transistor PM0, and the NMOS transistors SWD0-N of the sub-word line driver SWD0 may refer to the pull-down transistor NM0 and the holding transistor KP0.

[0050] The pull-up transistor PM0 included in the sub-word line driver SWD0 may be connected between a terminal to which a sub-word line driver control signal PXID<0> is applied and a corresponding word line (e.g., WL<0>), and the pull-down transistor NM0 and the holding transistor KP0 included in the sub-word line driver SWD0 may be connected in parallel between the corresponding word line and a terminal to which a negative voltage VBB2 is applied. For example, the sub-word line driver control signal PXID<0> may be applied to the source region of the pull-up transistor PM0, and the negative voltage VBB2 may be applied to the source region of each of the pull-down transistor NM0 and the holding transistor KP0. The drain region of each of the pull-up transistor PM0, the pull-down transistor NM0, and the holding transistor KP0 may be connected to the corresponding word line.

[0051] The remaining sub - word line drivers SWD2, SWD4, and SWD6 can also be implemented to be the same as or similar to the sub - word line driver SWD0.

[0052] In an embodiment, the sub - word line driver SWD2 may include a pull - up transistor PM2 formed by a PMOS transistor SWD2 - P, a pull - down transistor NM2 and a hold transistor KP2 formed by NMOS transistors SWD2 - N respectively, and the sub - word line driver control signal PXID<2> and a negative voltage VBB2 may be applied to the sub - word line driver SWD2. The sub - word line driver SWD4 may include a pull - up transistor PM4 formed by a PMOS transistor SWD4 - P, a pull - down transistor NM4 and a hold transistor KP4 formed by NMOS transistors SWD4 - N respectively, and the sub - word line driver control signal PXID<4> and the negative voltage VBB2 may be applied to the sub - word line driver SWD4. The sub - word line driver SWD6 may include a pull - up transistor PM6 formed by a PMOS transistor SWD6 - P, a pull - down transistor NM6 and a hold transistor KP6 formed by NMOS transistors SWD6 - N respectively, and the sub - word line driver control signal PXID<6> and the negative voltage VBB2 may be applied to the sub - word line driver SWD6.

[0053] In this case, each of the pull - up transistors PM0, PM2, PM4, and PM6 and the pull - down transistors NM0, NM2, NM4, and NM6 included in the sub - word line drivers SWD0, SWD2, SWD4, and SWD6 may include a gate terminal configured to receive the word line enable signal NWEIB<0>. Each of the hold transistors KP0, KP2, KP4, and KP6 included in the sub - word line drivers SWD0, SWD2, SWD4, and SWD6 may include a gate terminal configured to receive the corresponding control signal among the sub - word line driver control signals PXIB<0>, PXIB<2>, PXIB<4>, and PXIB<6>. The sub - word line driver control signals applied to the hold transistors KP0, KP2, KP4, and KP6 respectively may be referred to as "hold control signals".

[0054] The sub - word line drivers SWD0, SWD2, SWD4, and SWD6 can activate the word lines WL<0>, WL<2>, WL<4>, and WL<6> respectively.

[0055] In an embodiment, the word lines WL<0>, WL<2>, WL<4>, and WL<6> may correspond to the sub - word line drivers SWD0, SWD2, SWD4, and SWD6 respectively. In an embodiment, the word lines WL<0>, WL<2>, WL<4>, and WL<6> may be word lines that extend to one side of the memory cell array and are adjacent to each other.

[0056] Figure 4 is a timing diagram for describing the operation of a sub - word line driver. Figure 1 Among the sub - word line drivers SWD0, SWD2, SWD4, and SWD6 shown in Figure 2 and Figure 3 , only the components related to the sub - word line driver SWD0 are described, but this is only for example. The operations of the remaining sub - word line drivers can be substantially the same as that of the sub - word line driver SWD0. In Figure 4 , the signal levels of the word line enable signal NWEIB<0>, the sub - word line driver control signals PXID<0> and PXIB<0> applied to the sub - word line driver SWD0 as time passes through time points t1, t2, and t3 are shown, and the voltage level of the word line WL<0> activated by the sub - word line driver SWD0 is shown.

[0057] Referring to Figure 3 and Figure 4 , the word line enable signal NWEIB<0> can have one of a high level (H) and a low level (L), and the sub - word line driver control signals PXID<0> and PXIB<0> can have one of a voltage level VSS and a voltage level VPP. The high level can be a signal level sufficient to turn off the pull - up transistor PM0 and turn on the pull - down transistor NM0, and the low level can be a signal level sufficient to turn on the pull - up transistor PM0 and turn off the pull - down transistor NM0. The voltage level VPP can be a high voltage level sufficient to activate the word line WL<0>, and the voltage level VSS can be a low voltage level sufficient to de - activate the word line WL<0>.

[0058] The word line enable signal NWEIB<0> can have a high level before t1, can transition to a low level at t1, and remain at the low level until t2. In addition, the word line enable signal NWEIB<0> can transition to a high level at t2 and can remain at the high level until t3.

[0059] The sub - word line driver control signal PXID<0> can have a voltage level VSS before t1, can transition to a voltage level VPP at t1, and remain at the voltage level VPP until t2. In addition, the sub - word line driver control signal PXID<0> can transition to a voltage level VSS at t2 and remain at the voltage level VSS until t3. When the sub - word line driver control signal PXID<0> has a voltage level VSS, the sub - word line driver control signal PXIB<0> can have a voltage level VPP; when the sub - word line driver control signal PXID<0> has a voltage level VPP, the sub - word line driver control signal PXIB<0> can have a voltage level VSS.

[0060] Before t1 or between t2 and t3, since the word line enable signal NWEIB<0> has a high level and the sub-word line driver control signal PXIB<0> has a voltage level of VPP, the pull-down transistor NM0 and the hold transistor KP0 can be turned on, and the voltage level of the word line WL<0> can indicate the negative voltage VBB2.

[0061] Between t1 and t2 or after t3, since the word line enable signal NWEIB<0> has a low level and the sub-word line driver control signal PXIB<0> has a voltage level of VSS, the pull-up transistor PM0 can be turned on, and the voltage level of the word line WL<0> can indicate the voltage level VPP, which is the voltage level of the sub-word line driver control signal PXID<0>.

[0062] Between t1 and t2, the word line WL<0> can be activated. Before t1 or between t2 and t3, the word line WL<0> can be deactivated.

[0063] As referenced Figure 1 it is possible to define the activation interval and the deactivation interval of the word line WL<0>. The time interval from t1 to t2 can correspond to the activation interval of the word line WL<0>, and the time interval from t2 to t3 can correspond to the deactivation interval of the word line WL<0>.

[0064] Figure 5 and Figure 6 are diagrams for describing Figure 3 the layout of the transistors included in the sub-word line driver.

[0065] Referenced Figure 3 and Figure 5 Some 133b in the sub-word line driver can include sub-word line drivers SWD0, SWD2, SWD4, and SWD6, and each of the sub-word line drivers SWD0, SWD2, SWD4, and SWD6 can include a pull-up transistor, a pull-down transistor, and a hold transistor.

[0066] In an embodiment, the sub-word line drivers SWD0, SWD2, SWD4, and SWD6 can be formed on a semiconductor substrate.

[0067] The source region of the pull-down transistor included in one sub-word line driver and the source region of the hold transistor included in another sub-word line driver can be arranged on the semiconductor substrate to share a doped region on the semiconductor substrate.

[0068] In an embodiment, the sub - word line driver SWD0 may include a pull - down transistor NM0 and a holding transistor KP0, and the sub - word line driver SWD2 may include a pull - down transistor NM2 and a holding transistor KP2. For example, the source regions of the pull - down transistor NM2 and the holding transistor KP0 may be set as a common doping region SHRD_DPR1 - 1, and the source regions of the pull - down transistor NM0 and the holding transistor KP2 may be set as a common doping region SHRD_DPR2 - 1.

[0069] In an embodiment, the sub - word line driver SWD4 may include a pull - down transistor NM4 and a holding transistor KP4, and the sub - word line driver SWD6 may include a pull - down transistor NM6 and a holding transistor KP6. For example, the source regions of the pull - down transistor NM6 and the holding transistor KP4 may be set as a common doping region SHRD_DPR1 - 2, and the source regions of the pull - down transistor NM4 and the holding transistor KP6 may be set as a common doping region SHRD_DPR2 - 2.

[0070] Reference Figure 5 and Figure 6 , an active region ACT located between device isolation layers STI1 and STI2 may be defined on the semiconductor substrate SUB.

[0071] In the active region ACT, doping regions DPR1, DPR2, and DPR3 may be formed, and the pull - down transistor NM0 included in the sub - word line driver SWD0 and the holding transistor KP2 included in the sub - word line driver SWD2 may be formed.

[0072] The pull - down transistor NM0 may receive a word - line enable signal NWEIB<0> through a gate terminal, and may include a drain region NM0_DR connected to the word line WL<0> through a direct contact portion DC1, and a source region NM0_SR connected to a terminal providing a negative voltage VBB2 through a direct contact portion DC2. The holding transistor KP2 may receive a sub - word line driver control signal PXIB<2> through a gate terminal, and may include a drain region KP2_DR connected to the word line WL<2> through a direct contact portion DC3, and a source region KP2_SR connected to a terminal providing a negative voltage VBB2 through a direct contact portion DC2.

[0073] As Figure 6 shown, the source regions of the pull - down transistor NM0 and the holding transistor KP2 may be set to share a doping region (e.g., DPR2). Although Figure 6 not shown in Figure 6Similar to the example shown, the source regions of the pull-down transistor NM2 and the holding transistor KP0, the source regions of the pull-down transistor NM6 and the holding transistor KP4, and the source regions of the pull-down transistor NM4 and the holding transistor KP6 can be set to share a doped region.

[0074] Figure 7 and Figure 8 are diagrams for describing Figure 1 the layout of the doped regions or metal wires included in the sub-word line driver.

[0075] Figure 7 It shows a plan view of the semiconductor substrate observed in the vertical direction with reference to Figure 1 , Figure 2 , Figure 5 and Figure 6 described, and Figure 7 the semiconductor substrate of may only contain regions corresponding to the pull-down transistors NM0 and NM2 and the holding transistors KP0 and KP2 of some (e.g., SWD0 and SWD2) of the sub-word line drivers SWD0, SWD2, SWD4, and SWD6 of Figure 5 . Directions D1, D2, and D3 may be orthogonal, and direction D4 may indicate the direction between D1 and D2. Directions D1, D2, D3, and D4 can be jointly used to describe the semiconductor memory device according to an embodiment of the present disclosure.

[0076] Referring to Figure 7 , doped regions DPR11, DPR13, DPR15, and DPR17 and metal wires ML1, ML2, and ML3 can be formed in the semiconductor substrate, and direct contact portions DC11, DC13, DC15, and DC17 for applying a given signal or voltage can be formed in the doped regions DPR11, DPR13, DPR15, and DPR17.

[0077] In an embodiment, the doped regions DPR11, DPR13, DPR15, and DPR17 can be arranged on the semiconductor substrate to be separated from each other.

[0078] In an embodiment, drain regions can be formed in the doped regions DPR11 and DPR15, and source regions can be formed in the doped regions DPR13 and DPR17. For example, the drain regions of the pull-down transistor NM0 and the holding transistor KP0 can be formed in the doped region DPR11, and the source regions of the pull-down transistor NM0 and the holding transistor KP2 can be formed in the doped region DPR13. The drain regions of the holding transistor KP2 and the pull-down transistor NM2 can be formed in the doped region DPR15, and the source regions of the pull-down transistor NM2 and the holding transistor KP0 can be formed in the doped region DPR17.

[0079] ​Metal lines ML1, ML2, and ML3 can be electrically connected to the gates of pull - down transistors NM0 and NM2 and holding transistors KP0 and KP2. For example, metal line ML1 can be electrically connected to the gates of pull - down transistors NM0 and NM2, metal line ML2 can be electrically connected to the gate of holding transistor KP2, and metal line ML3 can be electrically connected to the gate of holding transistor KP0.

[0080] In an embodiment, gate signals (e.g., NWEIB<0>, PXIB<0>, and PXIB<2>) can be provided to pull - down transistors NM0 and NM2 and holding transistors KP0 and KP2 through metal lines ML1, ML2, and ML3. For example, a word - line enable signal (e.g., NWEIB<0>) can be applied to pull - down transistors NM0 and NM2 through metal line ML1, a sub - word - line driver control signal (e.g., PXIB<2>) can be applied to holding transistor KP2 through metal line ML2, and a sub - word - line driver control signal (or holding control signal) (e.g., PXIB<0>) can be applied to holding transistor KP0 through metal line ML3.

[0081] Direct contact parts DC11, DC13, DC15, and DC17 can be disposed on doped regions DPR11, DPR13, DPR15, and DPR17. For example, direct contact part DC11 can be disposed on doped region DPR11, direct contact part DC13 can be disposed on doped region DPR13, direct contact part DC15 can be disposed on doped region DPR15, and direct contact part DC17 can be disposed on doped region DPR17.

[0082] In an embodiment, a negative voltage (e.g., VBB2 in Figure 1 ) can be provided to pull - down transistors NM0 and NM2 and holding transistors KP0 and KP2 through direct contact parts DC13 and DC17. For example, pull - down transistor NM0 and holding transistor KP2 can receive the negative voltage through direct contact part DC13, and pull - down transistor NM2 and holding transistor KP0 can receive the negative voltage through direct contact part DC17.

[0083] Figure 8 Only metal lines ML1, ML2, and ML3 are shown in Figure 8 , metal line ML1 can extend a first length L1 (e.g., from point P1 to point P2) along a first direction D1, then can extend a second length L2 (e.g., from point P2 to point P3) along a second direction D4 different from the first direction D1, and then can extend a third length L3 (e.g., from point P3 to point P4) along the first direction D1.

[0084] In an embodiment, the first direction D1 may be the direction in which the word lines WL<0> and WL<2> driven by the sub - word line drivers SWD0 and SWD2 extend, and the second direction D4 may form a given angle θ1 with the first direction D1. For example, the angle θ1 may be 45 degrees, or may have a value close to 45 degrees.

[0085] The metal lines ML2 and ML3 may be arranged symmetrically with respect to the metal line ML1 extending along the second direction D4.

[0086] In an embodiment, the metal lines ML2 and ML3 may be arranged on a virtual line VL1 perpendicular to the second direction D4.

[0087] In an embodiment, the metal lines ML2 and ML3 may be arranged on another virtual line that forms a given angle θ2 with the line VL1. For example, the angle θ2 may be 0 degrees, or may have a value close to 0 degrees. Reference will be made Figure 10 to the point P23 where the metal line ML1 extending along the second direction D4 intersects the line VL1. The point P23 may be used as a standard for forming a gate region of a metal line or a given holding transistor.

[0088] Figure 9 and Figure 10 are diagrams for describing Figure 1 the layout of transistors, doped regions, or metal lines included in the sub - word line drivers.

[0089] Figure 9 shows a plan view of a semiconductor substrate substantially the same as the semiconductor substrate of Figure 7 and the semiconductor substrate of Figure 9 may only include regions corresponding to the pull - down transistors NM0 and NM2 and the holding transistors KP0 and KP2 of some (e.g., SWD0 and SWD2) of the sub - word line drivers SWD0, SWD2, SWD4, and SWD6 of Figure 5 . In Figure 7 and Figure 9 , components with the same reference numerals / symbols may perform substantially the same functions.

[0090] Referring to Figure 9 , the doped regions DPR11, DPR13, DPR15, and DPR17 and the metal lines ML1, ML2, and ML3 may be formed on the semiconductor substrate, and transistor regions NM0R and NM2R where the pull - down transistors NM0 and NM2 are respectively formed, and transistor regions KP0R and KP2R where the holding transistors KP0 and KP2 are respectively formed may be further formed on the semiconductor substrate.

[0091] In an embodiment, a source region NM0_SR of a pull-down transistor NM0 and a source region KP2_SR of a holding transistor KP2 may be formed in a doped region DPR13. For example, the source regions NM0_SR and KP2_SR of the pull-down transistor NM0 and the holding transistor KP2 may be arranged to share the doped region DPR13.

[0092] In an embodiment, a source region NM2_SR of a pull-down transistor NM2 and a source region KP0_SR of a holding transistor KP0 may be formed in a doped region DPR17. For example, the source regions NM2_SR and KP0_SR of the pull-down transistor NM2 and the holding transistor KP0 may be arranged to share the doped region DPR17.

[0093] In an embodiment, a drain region NM0_DR of a pull-down transistor NM0 and a drain region KP0_DR of a holding transistor KP0 may be formed in a doped region DPR11. For example, the drain regions NM0_DR and KP0_DR of the pull-down transistor NM0 and the holding transistor KP0 may be arranged to share the doped region DPR11.

[0094] In an embodiment, a drain region NM2_DR of a pull-down transistor NM2 and a drain region KP2_DR of a holding transistor KP2 may be formed in a doped region DPR15. For example, the drain regions NM2_DR and KP2_DR of the pull-down transistor NM2 and the holding transistor KP2 may be arranged to share the doped region DPR15.

[0095] In an embodiment, the doped region DPR13 may be referred to as a "first doped region", the doped region DPR17 may be referred to as a "second doped region", the doped region DPR11 may be referred to as a "third doped region", and the doped region DPR15 may be referred to as a "fourth doped region". In this case, the first doped region to the fourth doped region may be arranged in a clockwise order with respect to a virtual central axis perpendicular to the semiconductor substrate: the first doped region, the fourth doped region, the second doped region, and the third doped region. In this case, the first doped region and the third doped region may be arranged to be point-symmetrical with the second doped region and the fourth doped region.

[0096] In an embodiment, the pull-down transistor NM0 and the holding transistor KP0 may be arranged on the semiconductor substrate to be point-symmetrical with the pull-down transistor NM2 and the holding transistor KP2.

[0097] The gate region NM0_GR forming the gate of the pull-down transistor NM0 can be disposed in a region where the metal line ML1 and the transistor region NM0R overlap each other, and the gate region NM2_GR forming the gate of the pull-down transistor NM2 can be disposed in a region where the metal line ML1 and the transistor region NM2R overlap each other. The gate region KP2_GR forming the gate of the holding transistor KP2 can be disposed in a region where the metal line ML2 and the transistor region KP2R overlap each other, and the gate region KP0_GR forming the gate of the holding transistor KP0 can be disposed in a region where the metal line ML3 and the transistor region KP0R overlap each other.

[0098] Reference Figure 9 and Figure 10 , virtual lines VL2-1 and VL2-2 passing through the point P23 and intersecting each other perpendicularly can be defined on the semiconductor substrate. For example, as described in reference Figure 8 , the point P23 can be a point where the metal line ML1 extending along the second direction D4 intersects the line VL1.

[0099] The semiconductor substrate can be divided into four regions based on the lines VL2-1 and VL2-2, and the gate regions NM0_GR, NM2_GR, KP0_GR, and KP2_GR of the pull-down transistor NM0, the pull-down transistor NM2, the holding transistor KP0, and the holding transistor KP2 can be disposed in these four regions respectively.

[0100] In an embodiment, the gate region NM0_GR and the gate region NM2_GR can be disposed separately from each other and can be symmetrically disposed with respect to the point P23. The gate region KP0_GR and the gate region KP2_GR can be disposed separately from each other and can be symmetrically disposed with respect to the point P23.

[0101] In an embodiment, the gate regions NM0_GR and KP0_GR and the gate regions KP2_GR and NM2_GR can be disposed separately from each other and can be symmetrically disposed with respect to the point P23. The gate regions NM0_GR and KP2_GR and the gate regions KP0_GR and NM2_GR can be disposed separately from each other and can be symmetrically disposed with respect to the point P23.

[0102] Figure 11 is a diagram for describing the layout of the sub-word line driver for Figure 1 .

[0103] Figure 11 The transistor regions NM0R, KP0R, NM2R, and KP2R are shown in. The transistor regions NM0R, KP0R, NM2R, and KP2R are substantially the same as the transistor regions NM0R, KP0R, NM2R, and KP2R described in reference Figure 9 .

[0104] Reference Figure 9 and Figure 11 The transistor regions included in the sub - word line driver according to an embodiment of the present disclosure can be implemented by changing the layout of the transistor regions according to the prior art. For example, the layout of the transistor regions NM2R and KP2R among the transistor regions NM0R, KP0R, NM2R, and KP2R can be implemented by changing the layout according to the prior art (e.g., 301) to any other layout (e.g., 305).

[0105] In an embodiment, each of the layouts 301 and 305 may include a transistor region NM2R forming a pull - down transistor NM2 and a transistor region KR2R forming a holding transistor KP2. As Figure 11 shown, the layout 305 can be implemented by rotating the layout 301 by 180 degrees around a virtual line passing through the drain region of the pull - down transistor NM2.

[0106] As the layout 301 changes to the layout 305, the line symmetry formed by the transistor regions NM0R and KP0R and the transistor regions NM2R and KP2R can be changed to point symmetry formed by the transistor regions NM0R and KP0R and the transistor regions NM2R and KP2R. In this case, the shortest distance between the transistor region NM2R and the transistor region KR0R can be reduced, and the shortest distance between the transistor region KP2R and the transistor region NM0R can be reduced.

[0107] As the layout 301 changes to the layout 305, the source region NM0_SR of the pull - down transistor NM0 and the source region KP2_SR of the holding transistor KP2 can be set to share a doped region, and the source region NM2_SR of the pull - down transistor NM2 and the source region KP0_SR of the holding transistor KP0 can be set to share a doped region. In this case, the area occupied by the part of the sub - word line driver on the semiconductor substrate can be reduced by as much as the size of the region 309 (e.g., w1×h1).

[0108] As the layout 301 changes to the layout 305, the metal lines can be formed as Figure 8 shown.

[0109] Figure 12 is a diagram for describing an embodiment of the layout of transistors, doped regions, or metal lines included in a sub - word line driver according to an embodiment of the present disclosure.

[0110] Figure 12 shows Figure 7 a plan view of a semiconductor substrate substantially the same as the semiconductor substrate of Figure 12 The semiconductor substrate of Figure 5The regions corresponding to the pull-down transistors NM0, NM2, NM4, and NM6 and the holding transistors KP0, KP2, KP4, and KP6 of the sub-word line drivers SWD0, SWD2, SWD4, and SWD6, and may also include Figure 5 the regions corresponding to the pull-down transistors NM8, NM10, NM12, and NM14 and the holding transistors KP8, KP10, KP12, and KP14 of the sub-word line drivers SWD8, SWD10, SWD12, and SWD14 not shown in Figure 12 . Although not shown in Figure 5 , Figure 6 and Figure 9 , in a manner the same as or similar to that described in

[0111] , the doping regions can be shared between the pull-down transistors NM0, NM2, NM4, NM6, NM8, NM10, NM12, and NM14 and the holding transistors KP0, KP2, KP4, KP6, KP8, KP10, KP12, and KP14 of the sub-word line drivers SWD0, SWD2, SWD4, SWD6, SWD8, SWD10, SWD12, and SWD14.

[0111] Referring to Figure 2 , Figure 3 and Figure 12 , the sub-word line drivers SWD8, SWD10, SWD12, and SWD14 can activate the word lines WL<8>, WL<10>, WL<12>, and WL<14> respectively, and the word lines WL<8>, WL<10>, WL<12>, and WL<14> can be word lines that extend in the same direction to one side of the memory cell array and are adjacent to each other as the word lines WL<0>, WL<2>, WL<4>, and WL<6>.

[0112] In an embodiment, in a semiconductor substrate, it is possible to define: a sub-word line driver region SWD0-NR, including transistor regions NM0R and KP0R where a pull-down transistor NM0 and a holding transistor KP0 are formed; and a sub-word line driver region SWD2-NR, including transistor regions NM2R and KP2R where a pull-down transistor NM2 and a holding transistor KP2 are formed. The sub-word line driver regions SWD4-NR, SWD6-NR, SWD8-NR, SWD10-NR, SWD12-NR, and SWD14-NR can be defined as described above. The sub-word line driver regions SWD0-NR, SWD2-NR, SWD4-NR, SWD6-NR, SWD8-NR, SWD10-NR, SWD12-NR, and SWD14-NR can respectively include NMOS transistors SWD0-N, SWD2-N, SWD4-N, SWD6-N, SWD8-N, SWD10-N, SWD12-N, and SWD14-N of sub-word line drivers SWD0, SWD2, SWD4, SWD6, SWD8, SWD10, SWD12, and SWD14. In this case, all the sub-word line driver regions SWD0-NR and SWD2-NR can be set to be line-symmetric with all the sub-word line driver regions SWD4-NR and SWD6-NR. All the sub-word line driver regions SWD8-NR and SWD10-NR can be set to be line-symmetric with all the sub-word line driver regions SWD12-NR and SWD14-NR. All the sub-word line driver regions SWD0-NR, SWD2-NR, SWD4-NR, and SWD6-NR can be set to be line-symmetric with all the sub-word line driver regions SWD8-NR, SWD10-NR, SWD12-NR, and SWD14-NR.

[0113] In an embodiment, since the sub-word line driver regions SWD0-NR and SWD2-NR are adjacent to the sub-word line driver regions SWD8-NR and SWD10-NR, it may additionally cause the doping regions to be shared. For example, the source region of the pull-down transistor NM0 included in the sub-word line driver region SWD0-NR and the source region of the holding transistor KP2 included in the sub-word line driver region SWD2-NR may share a doping region. The source region of the pull-down transistor NM8 included in the sub-word line driver region SWD8-NR and the source region of the holding transistor KP10 included in the sub-word line driver region SWD10-NR may share a doping region. In addition, all the source regions of the pull-down transistors NM0 and NM8 and the holding transistors KP2 and KP10 may share a doping region. For example, the source region of the holding transistor KP4 included in the sub-word line driver region SWD4-NR and the source region of the pull-down transistor NM6 included in the sub-word line driver region SWD6-NR may share a doping region. The source region of the holding transistor KP12 included in the sub-word line driver region SWD12-NR and the source region of the pull-down transistor NM14 included in the sub-word line driver region SWD14-NR may share a doping region. In addition, all the source regions of the pull-down transistors NM6 and NM14 and the holding transistors KP4 and KP12 may share a doping region.

[0114] In an embodiment, the NMOS transistors of the first to fourth sub-word line drivers may be respectively disposed in the sub-word line driver regions SWD0-NR, SWD2-NR, SWD4-NR, and SWD6-NR. The first sub-word line driver may include a first pull-down transistor and a first holding transistor, and the second sub-word line driver may include a second pull-down transistor and a second holding transistor. The third sub-word line driver may include a third pull-down transistor and a third holding transistor, and the fourth sub-word line driver may include a fourth pull-down transistor and a fourth holding transistor.

[0115] In an embodiment, the first metal line may be electrically connected to the gates of the first to fourth pull-down transistors, and the second metal line may be electrically connected to the gate of the first holding transistor. The third metal line may be electrically connected to the gate of the second holding transistor, the fourth metal line may be electrically connected to the gate of the third holding transistor, and the fifth metal line may be electrically connected to the gate of the fourth holding transistor.

[0116] In an embodiment, the third metal line and the fourth metal line may be formed of one metal line and may provide the same sub-word line driver control signal to the gates of the second and third holding transistors. For example, the same sub-word line driver control signal (e.g.,Figure 5 in the PXIB <2>). For example, the same sub - word line driver control signal can be provided to the gates of the holding transistors included in the transistor regions KP4R and KP12R (e.g., Figure 5 in the PXIB <4>).

[0117] In an embodiment, the first metal line can extend a first length in a first direction, then extend a second length in a second direction different from the first direction, and then extend a third length in the first direction. After the first metal line extends the third length in the first direction, the first metal line can extend the second length in a third direction different from the first direction, and then extend a fifth length in the first direction. In this case, the first direction can be the direction in which the word line extends towards one side of the memory cell array. The second direction can form a 45 - degree angle with the first direction, and the third direction can form a 45 - degree angle with the first direction and a 90 - degree angle with the second direction.

[0118] Figure 13 is for describing Figure 12 the layout of the sub - word line driver.

[0119] Refer to Figure 11 , Figure 12 and Figure 13 , the transistor regions included in the sub - word line driver according to an embodiment of the present disclosure can be implemented by partially changing the layout of the transistor regions according to the prior art. For example, the layout of the sub - word line driver region can be implemented by changing the layout according to the prior art (e.g., 311) to any other layout (e.g., 315). In this case, the area occupied by the sub - word line driver on the semiconductor substrate can be reduced by as much as the size of region 319 (e.g., w2×h2).

[0120] As the layout 311 is changed to the layout 315, the metal line can be formed as shown in Figure 8 .

[0121] Figure 14 is a diagram showing an embodiment of the layout of the sub - word line driver according to an embodiment of the present disclosure.

[0122] Figure 14 shows Figure 7 a plan view of a semiconductor substrate substantially the same as the semiconductor substrate of Figure 14The semiconductor substrate can include regions corresponding to the NMOS transistors SWD0-N, SWD2-N, SWD4-N, SWD6-N, SWD8-N, SWD10-N, SWD12-N, and SWD14-N of the sub-word line drivers SWD0, SWD2, SWD4, SWD6, SWD8, SWD10, SWD12, and SWD14, and can also include regions corresponding to the PMOS transistors SWD0-P, SWD2-P, SWD4-P, SWD6-P, SWD8-P, SWD10-P, SWD12-P, and SWD14-P of the sub-word line drivers SWD0, SWD2, SWD4, SWD6, SWD8, SWD10, SWD12, and SWD14.

[0123] Reference Figure 2 , Figure 3 , Figure 12 and Figure 14 , the sub-word line drivers SWD8, SWD10, SWD12, and SWD14 can activate the word lines WL<8>, WL<10>, WL<12>, and WL<14> respectively, and the word lines WL<8>, WL<10>, WL<12>, and WL<14> can be word lines that extend in the same direction to one side of the memory cell array and are adjacent to each other along with the word lines WL<0>, WL<2>, WL<4>, and WL<6>. Although Figure 14 is not shown in Figure 5 , Figure 6 , Figure 9 and Figure 12 described, the doped regions can be shared between the pull-down transistors NM0, NM2, NM4, NM6, NM8, NM10, NM12, and NM14 and the hold transistors KP0, KP2, KP4, KP6, KP8, KP10, KP12, and KP14 of the sub-word line drivers SWD0, SWD2, SWD4, SWD6, SWD8, SWD10, SWD12, and SWD14 in the same or similar manner as described in

[0124] In an embodiment, in a semiconductor substrate, a sub-word line driver region SWD0-PR including a transistor region forming a pull-up transistor PM0 and a sub-word line driver region SWD2-PR including a transistor region forming a pull-up transistor PM2 may be defined. The sub-word line driver regions SWD4-PR, SWD6-PR, SWD8-PR, SWD10-PR, SWD12-PR, and SWD14-PR may be defined as described above. The sub-word line driver regions SWD0-PR, SWD2-PR, SWD4-PR, SWD6-PR, SWD8-PR, SWD10-PR, SWD12-PR, and SWD14-PR may respectively include PMOS transistors SWD0-P, SWD2-P, SWD4-P, SWD6-P, SWD8-P, SWD10-P, SWD12-P, and SWD14-P of sub-word line drivers SWD0, SWD2, SWD4, SWD6, SWD8, SWD10, SWD12, and SWD14. In this case, all the sub-word line driver regions SWD4-PR, SWD6-PR, SWD8-PR, SWD10-PR, SWD12-PR, and SWD14-PR may be disposed on a first side of all the sub-word line driver regions SWD0-NR, SWD2-NR, SWD4-NR, SWD6-NR, SWD8-NR, SWD10-NR, and SWD12-NR. All the sub-word line driver regions SWD0-PR, SWD2-PR, SWD4-PR, and SWD6-PR may be disposed to be line-symmetric with all the sub-word line driver regions SWD8-PR, SWD10-PR, SWD12-PR, and SWD14-PR.

[0125] In Figure 14 this case, the setting order of each of the sub-word line driver regions SWD0-PR, SWD2-PR, SWD4-PR, SWD6-PR, SWD8-PR, SWD10-PR, SWD12-PR, SWD14-PR, SWD0-NR, SWD2-NR, SWD4-NR, SWD6-NR, SWD8-NR, SWD10-NR, SWD12-NR, and SWD14-NR is provided only as an example.

[0126] In an embodiment, when the order of the sub-word line driver regions SWD0-NR, SWD2-NR, SWD4-NR, SWD6-NR, SWD8-NR, SWD10-NR, SWD12-NR, and SWD14-NR is changed, the order of the sub-word line driver regions SWD0-PR, SWD2-PR, SWD4-PR, SWD6-PR, SWD8-PR, SWD10-PR, SWD12-PR, and SWD14-PR respectively corresponding thereto may also be changed together.

[0127] Figure 15 is a block diagram showing a semiconductor memory device including a sub - word line driver according to an embodiment of the present disclosure.

[0128] Referring Figure 15 , the semiconductor memory device 500 may include a control logic circuit 510, a row decoder 520, a bank array 530, sense amplifiers 531, an input / output strobe circuit 540, a column decoder 550, an ECC engine 560, a data input / output buffer 570, and an on - die termination (ODT) circuit 580. The control logic circuit 510 may include a command decoder 511, a sense amplifier control logic 512, a mode register 513, a refresh counter 515, an address register 517, and a bank control logic 519. For example, the semiconductor memory device 500 may be a volatile memory device, and specifically, may be a DRAM.

[0129] The bank array 530 may include a plurality of bank arrays. The row decoder 520 may include a plurality of bank row decoders respectively connected to the plurality of bank arrays, the column decoder 550 may include a plurality of bank column decoders respectively connected to the plurality of bank arrays, and the sense amplifiers 531 may include a plurality of bank sense amplifiers respectively connected to the plurality of bank arrays. The plurality of bank arrays, the plurality of bank row decoders, the plurality of bank column decoders, and the plurality of bank sense amplifiers may constitute a plurality of banks. Each of the plurality of bank arrays may include a plurality of memory cells MC formed at intersections of a plurality of word lines WL and a plurality of bit lines BL. The row decoder 520 may correspond to Figure 2 the row decoder 190 of Figure 2 and sub - word line drivers SWD1, SWD2, SWD3, SWD4, SWD5, SWD6, SWD7, etc. of

[0130] The address register 517 may receive an address ADDR including a bank address, a row address, and a column address from a memory controller. The address register 517 may provide the bank address to the bank control logic 519, may provide the row address to the row decoder 520, and may provide the column address to the column decoder 550.

[0131] The bank control logic 519 may generate bank control signals in response to the bank address. Based on the bank control signals, the bank row decoder and the bank column decoder corresponding to the bank address may be activated.

[0132] The refresh counter 515 can generate a refresh row address that sequentially increments or decrements under the control of the control logic circuit 510. The activated bank column decoder among the multiple bank column decoders can activate the sense amplifiers 531 corresponding to the bank address, row address, and column address by using the input / output strobe circuit 540.

[0133] The codeword CW read from one of the multiple bank arrays can be sensed by the sense amplifier corresponding to the one bank array. The ECC engine 560 can perform ECC decoding on the sensed codeword CW, and the DQ signal can be provided to the memory controller through the data input / output buffer 570 as the ECC decoding result. The data DAT transmitted from the input / output pad 590 to the data input / output buffer 570 can be multi-level data. The data input / output buffer 570 can include a receive driver for encoding the multi-level data and can receive a reference voltage for encoding.

[0134] The data DAT to be written to one of the multiple bank arrays can be provided to the ECC engine 560. The ECC engine 560 can generate parity bits based on the data DAT and provide a codeword including the data DAT and the parity bits to the input / output strobe circuit 540. The input / output strobe circuit 540 can write the codeword to the one bank array.

[0135] The ODT circuit 580 can be connected to the data input / output pad 590 and the data input / output buffer 570 and can perform impedance matching.

[0136] The control logic circuit 510 can control the operation of the memory device 500. For example, the control logic circuit 510 can generate control signals such that the memory device 500 performs a write operation or a read operation. The control logic circuit 510 can include: a command decoder 511 that decodes the command CMD received from the memory controller; and a mode register 513 for setting the operation mode of the memory device 500. For example, the command decoder 511 can decode a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, etc., and can generate control signals corresponding to the command CMD.

[0137] Figure 16 is a flowchart showing a method for designing and manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0138] Reference Figure 16, a computer system can be used to perform high-level design of semiconductor integrated circuits (S110). High-level design may refer to describing the integrated circuit to be designed in a high-level language of a computer language. For example, a high-level language such as the C language can be used. The circuit designed by the high-level design can be more specifically expressed by register transfer level (RTL) coding or simulation. In addition, the code generated by the register transfer level coding can be converted into a netlist and can be synthesized into an entire semiconductor device. The synthesized schematic circuit can be verified by a simulation tool and can be adjusted according to the verification result.

[0139] Layout design for implementing a logically complete semiconductor integrated circuit on a silicon substrate can be performed (S120). For example, the layout design can be referred to the synthesized schematic circuit in the high-level design or its corresponding netlist. The layout design can include a wiring process for placing and connecting various cells provided in the cell library according to specified design rules. In designing the layout associated with the embodiments of the present disclosure, designing multiple metal lines can be included. The multiple metal lines can correspond to multiple metal layers sequentially stacked on the silicon substrate. Wiring for connecting the data path can be performed while each metal line is set.

[0140] The cell library for layout design can also include information about the operation, speed, and power consumption of the cells. The cell library for representing a specific gate-level circuit as a layout is defined in most layout design tools. The layout can be a process for defining the shape or size of the patterns of transistors, doped regions, and metal lines actually to be formed on the silicon substrate. For example, layout patterns such as PMOS, NMOS, N-WELL, gate lines, and metal lines to be placed can be appropriately set to actually form an inverter circuit on the silicon substrate. For this purpose, a suitable inverter can be searched for and selected from the inverters predefined in the cell library. In addition, wiring can be performed on the selected and placed cells. Most of the series of processes can be automatically or passively performed by the layout design tool.

[0141] After wiring, layout verification can be performed to determine whether there are parts that violate the design rules. The items to be verified can include: design rule check (DRC) to verify whether the layout complies with the design rules; electrical rule check (ERC) to verify whether the internal electrical connections are correct and without disconnection; and layout versus schematic (LVS) to verify whether the layout matches the gate-level netlist.

[0142] An optical proximity correction (OPC) process (S130) may be performed. A layout pattern obtained by layout design may be implemented on a silicon substrate by using a photolithography process. In this case, optical proximity correction may be a technique for correcting distortion phenomena that may occur in the photolithography process. That is, through optical proximity correction, distortion phenomena such as refraction or process effects caused by light characteristics during exposure using such a layout pattern may be corrected. The shape and position of the designed layout pattern may be slightly changed during the optical proximity correction.

[0143] A photomask may be manufactured based on the layout changed by the optical proximity correction (S140). In general, a photomask may be manufactured by drawing a layout pattern using a chrome thin layer coated on a glass substrate.

[0144] A semiconductor device may be manufactured by using the generated photomask (S150). In the process of manufacturing the semiconductor device using the photomask, various types of exposure and etching processes may be repeated. Through these processes, a pattern implemented in the process of designing the layout may be sequentially formed on the silicon substrate.

[0145] Figure 17a , Figure 17b and Figure 17c It is used to describe the formation Figure 12 FIG. 1 is a diagram of a photomask having a pattern included in a sub-word line driver.

[0146] exist Figure 17a , Figure 17b and Figure 17c The Figure 13 The layouts 311 and 315 correspond to the layouts 711 and 715 .

[0147] Figure 17a Photomasks MSKP11 - 1 , MSKP11 - 2 , and MSKP11 - 3 used to manufacture the layout 711 , and photomasks MSKP15 - 1 , MSKP15 - 2 , MSKP15 - 3 , and MSKP15 - 4 used to manufacture the layout 715 are also shown. Figure 17b Photomasks MSKP21-1, MSKP21-2, MSKP21-3, MSKP21-4, MSKP21-5 and MSKP21-6 used to manufacture layout 711 and photomasks MSKP25-1, MSKP25-2, MSKP25-3, MSKP25-4 and MSKP25-5 used to manufacture layout 715 are also shown. Figure 17c Photomasks MSKP31 - 1 and MSKP31 - 2 used to manufacture layout 711 , and photomask MSKP35 - 1 used to manufacture layout 715 are also shown.

[0148] In an embodiment, Figure 17a The photomasks MSKP11-1, MSKP11-2, MSKP11-3, MSKP15-1, MSKP15-2, MSKP15-3, and MSKP15-4 can be used to form the source regions of the pull-down transistors of a sub-word line driver (e.g., Figure 12 SWD0, SWD2, SWD4, SWD6, SWD8, SWD10, SWD12, and SWD14).

[0149] In an embodiment, Figure 17b The photomasks MSKP21-1, MSKP21-2, MSKP21-3, MSKP21-4, MSKP21-5, MSKP21-6, MSKP25-1, MSKP25-2, MSKP25-3, MSKP25-4, and MSKP25-5 can be used to form the drain regions of the pull-down transistors and the holding transistors of a sub-word line driver (e.g., Figure 12 SWD0, SWD2, SWD4, SWD6, SWD8, SWD10, SWD12, and SWD14).

[0150] In an embodiment, Figure 17c The photomasks MSKP31-1, MSKP31-2, and MSKP35-1 can be used to form the source regions of the pull-down transistors of a sub-word line driver (e.g., Figure 12 SWD0, SWD2, SWD4, SWD6, SWD8, SWD10, SWD12, and SWD14).

[0151] Referring to Figure 17a , Figure 17b and Figure 17c , the photomasks used to fabricate layout 715 can be superior in performance to the photomasks used to fabricate layout 711. For example, according to the design rules or layout described in reference Figure 16 , the various patterns included in the sub-word line driver can be formed to be closer to the ideal pattern in shape.

[0152] In an embodiment, the performance of a photomask can be evaluated based on the photomask pitch (including the average pitch, maximum pitch, and minimum pitch between photomasks), the discrete values and standard deviation of the photomask pitch, and the height and width of each photomask.

[0153] In an embodiment, as the performance of the photomask improves, the various patterns included in the sub-word line driver can be formed more precisely. For example, the various patterns included in the sub-word line driver can include the transistors, doped regions, and metal lines described in reference Figures 7 to 12 .

[0154] Figure 18is a block diagram showing a computing system including a sub - word line driver according to an embodiment of the present disclosure.

[0155] Referring Figure 18 , the computing system 1000 includes a processor 1100, an input / output hub 1200, an input / output controller hub 1300, at least one DRAM module 1400, and a graphics card 1500. Herein, the computing system 1000 can be any one of a PC (personal computer), a server computer, a workstation, a laptop computer, a mobile phone, a smart phone, a PDA (personal digital assistant), a PMP (portable multimedia player), a digital camera, a digital TV, a set - top box, a music player, a portable game console, and a navigation system.

[0156] The processor 1100 can perform various computing functions, such as specific calculations or tasks. For example, the processor 1100 can be a microprocessor or a central processing unit (CPU). The processor 1100 can include one processor core (i.e., single - core), or can include multiple processor cores (i.e., multi - core). For example, the processor 1100 can include multi - cores, such as dual - core, quad - core, or six - core. In addition, Figure 18 the illustrated computing system 1000 includes one processor 1100, but the computing system 1000 can also include multiple processors. In addition, the processor 1100 can also include a cache memory located inside or outside of it.

[0157] The processor 1100 can include a memory controller 1150, which controls the operation of the DRAM module 1400. The memory controller 1150 included in the processor 1100 can be referred to as an integrated memory controller (IMC). The memory interface between the memory controller 1150 and the DRAM module 1400 can be implemented by one channel including multiple signal lines, or can be implemented by multiple channels. In addition, one or more DRAM modules 1400 can be connected to each channel. The memory controller 1150 can be placed in the input / output hub 1200. The input / output hub 1200 including the memory controller 1150 can be referred to as a memory controller hub (MCH).

[0158] The DRAM module 1400 can include multiple DRAM devices, which store data provided from the memory controller 1150. Each of the DRAM devices can be implemented by Figure 15 a semiconductor memory device 500. That is, each DRAM device can include a semiconductor memory device according to an embodiment of the present disclosure, which reduces the chip size and allows the patterns included in the sub - word line driver to be formed finely.

[0159] The input / output hub 1200 can manage data transmission between the processor 1100 and devices such as the graphics card 1500. The input / output hub 1200 can be connected to the processor 1100 through various interface methods. For example, the input / output hub 1200 and the processor 1100 can be connected through various standard interfaces, such as FSB (Front Side Bus), system bus, HyperTransport, LDT (Lightning Data Transport), QPI (QuickPath Interconnect), and CSI (Common System Interface). Figure 18 The illustrated computing system 1000 includes one input / output hub 1200, but the computing system 1000 can include multiple input / output hubs.

[0160] The input / output hub 1200 can provide various interfaces to devices. For example, the input / output hub 1200 can provide an AGP (Accelerated Graphics Port) interface, PCIe (Peripheral Component Interconnect Express), CSA (Communication Stream Architecture) interface, etc.

[0161] The graphics card 1500 can be connected to the input / output hub 1200 through AGP or PCIe. The graphics card 1500 can control a display device (not shown) for displaying images. The graphics card 1500 can include an internal semiconductor storage device and an internal processor for image data processing. According to an embodiment, the input / output hub 1200 can include a graphics device within the input / output hub 1200, which works together with or replaces the graphics card 1500 placed outside the input / output hub 1200. The graphics device included in the input / output hub 1200 can be referred to as an integrated graphics card. In addition, the input / output hub 1200 including a memory controller and a graphics device can be referred to as a Graphics Memory Controller Hub (GMCH).

[0162] The input / output controller hub 1300 can perform data buffering and interface arbitration to enable efficient operation of various system interfaces. The input / output controller hub 1300 can be connected to the input / output hub 1200 through an internal bus. For example, the input / output hub 1200 and the input / output controller hub 1300 can be connected through DMI (Direct Media Interface), hub interface, ESI (Enterprise South Bridge Interface), PCIe, etc.

[0163] The input / output controller hub 1300 can provide various interfaces to peripheral devices. For example, the input / output controller hub 1300 can provide Universal Serial Bus (USB) ports, Serial Advanced Technology Attachment (SATA) ports, General Purpose Input / Output (GPIO), Low Pin Count (LPC) bus, Serial Peripheral Interface (SPI), PCI, PCIe, etc.

[0164] In an embodiment, the processor 1100, the input / output hub 1200, and the input / output controller hub 1300 may be implemented using separate chip sets or integrated circuits, or two or more components among the processor 1100, the input / output hub 1200, or the input / output controller hub 1300 may be implemented using one chip set.

[0165] Figure 19 FIG. is a diagram of a data center to which a semiconductor memory device including a sub-word line driver according to an embodiment of the present disclosure is applied.

[0166] Referring Figure 19 , the data center 3000 is a facility that collects various types of data and provides services, and may be referred to as a "data storage center". The data center 3000 may be a system for operating a search engine and a database, and may be a computing system used by a company (such as a bank) or a government agency. The data center 3000 may include application servers 3100 to 3100n and storage servers 3200 to 3200m. The number of application servers 3100 to 3100n and the number of storage servers 3200 to 3200m may be selected differently according to embodiments, and the number of application servers 3100 to 3100n may be different from the number of storage servers 3200 to 3200m.

[0167] The application server 3100 or the storage server 3200 may include at least one of processors 3110 and 3210 and memories 3120 and 3220. Taking the storage server 3200 as an example for description. The processor 3210 may control all operations of the storage server 3200, may access the memory 3220, and may execute instructions and / or data loaded in the memory 3220. The memory 3220 may be implemented with DDR SDRAM (Double Data Rate Synchronous DRAM), HBM (High Bandwidth Memory), HMC (Hybrid Memory Cube), DIMM (Dual In-line Memory Module), Optane DIMM, and / or NVMDIMM (Non-Volatile DIMM). In some embodiments, the number of processors 3210 included in the storage server 3200 and the number of memories 3220 included in the storage server 3200 may be selected differently. In an embodiment, the processor 3210 and the memory 3220 may provide a processor-memory pair. In an embodiment, the number of processors 3210 may be different from the number of memories 3220. The processor 3210 may include a single-core processor or a multi-core processor. The above description of the storage server 3200 may be similarly applied to the application server 3100. According to an embodiment, the application server 3100 may not include a storage device 3150. The storage server 3200 may include at least one storage device 3250. The number of storage devices 3250 included in the storage server 3200 may be selected differently according to embodiments.

[0168] The application servers 3100 to 3100n may communicate with the storage servers 3200 to 3200m via the network 3300. The network 3300 may be implemented by using Fibre Channel (FC) or Ethernet. In this case, FC may be a medium for relatively high-speed data transmission, and a high-performance and high-availability optical switch may be used. The storage servers 3200 to 3200m may be provided as file storage, block storage, or object storage according to the access method of the network 3300.

[0169] In an embodiment, the network 3300 may be a storage dedicated network, such as a Storage Area Network (SAN). For example, the SAN may be an FC-SAN implemented using an FC network and according to the FC protocol (FCP). As another example, the SAN may be an IP-SAN implemented using a TCP / IP network and according to iSCSI (SCSI over TCP / IP or Internet SCSI). In another embodiment, the network 3300 may be a general network, such as a TCP / IP network. For example, the network 3300 may be implemented according to protocols such as Fibre Channel over Ethernet (FCoE), Network Attached Storage (NAS), and NVMe over Fabrics (NVMe-oF).

[0170] The application server 3100 and the storage server 3200 will be mainly described below. The description of the application server 3100 can be applied to other application servers 3100n, and the description of the storage server 3200 can be applied to other storage servers 3200m.

[0171] The application server 3100 can store the data requested by a user or a client through the network 3300 in one of the storage servers 3200 to 3200m. In addition, the application server 3100 can obtain the data requested by a user or a client to be read from one of the storage servers 3200 to 3200m through the network 3300. For example, the application server 3100 can be implemented as a web server or a database management system (DBMS).

[0172] The application server 3100 can access the memory 3120n or the storage device 3150n included in other application servers 3100n through the network 3300. Alternatively, the application server 3100 can access the memories 3220 to 3220m or the storage devices 3250 to 3250m included in the storage servers 3200 to 3200m through the network 3300. According to the above description, the application server 3100 can perform various operations on the data stored in the application servers 3100 to 3100n and / or the storage servers 3200 to 3200m. For example, the application server 3100 can execute instructions to move or copy data between the application servers 3100 to 3100n and / or the storage servers 3200 to 3200m. In this case, the data can be directly moved from the storage devices 3250 to 3250m of the storage servers 3200 to 3200m to the memories 3120 to 3120n of the application servers 3100 to 3100n, or moved to the memories 3120 to 3120n of the application servers 3100 to 3100n through the memories 3220 to 3220m of the storage servers 3200 to 3200m. The data moved through the network 3300 can be data encrypted for security or privacy.

[0173] The storage server 3200 will be described as an example. The interface 3254 can provide a physical connection between the processor 3210 and the controller 3251 and a physical connection between the NIC 3240 and the controller 3251. For example, the interface 3254 can be implemented by using a direct-attached storage (DAS) scheme, where the storage device 3250 is directly connected to a dedicated cable. In addition, for example, the interface 3254 can be implemented in various interface manners, such as ATA (Advanced Technology Attachment), SATA (Serial ATA), e-SATA (External SATA), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), PCI (Peripheral Component Interconnect), PCIe (PCI Express), NVMe (NVM Express), IEEE1394, USB (Universal Serial Bus), SD (Secure Digital) card, MMC (MultiMedia Card), eMMC (Embedded MultiMedia Card), UFS (Universal Flash Storage), eUFS (Embedded Universal Flash Storage), and / or CF (CompactFlash) card.

[0174] The storage server 3200 may further include a switch 3230 and a NIC 3240. Under the control of the processor 3210, the switch 3230 can selectively connect the processor 3210 to the storage device 3250 or can selectively connect the NIC 3240 of the storage device 3250.

[0175] In an embodiment, the NIC 3240 can include a network interface card, a network adapter, etc. The NIC 3240 can be connected to the network 3300 through a wired interface, a wireless interface, a Bluetooth interface, or an optical interface. The NIC 3240 can include an internal memory, a digital signal processor (DSP), a host bus interface, etc., and can be connected to the processor 3210 and / or the switch 3230 through the host bus interface. The host bus interface can be implemented by one of the examples of the above interface 3254. In an embodiment, the NIC 3240 can be integrated with at least one of the processor 3210, the switch 3230, and the storage device 3250.

[0176] In the storage servers 3200 to 3200m or the application servers 3100 to 3100n, the processor can send commands to the storage devices 3150 to 3150n and 3250 to 3250m or the memories 3120 to 3120n and 3220 to 3220m and can program or read data. In this case, the data can be data whose errors are corrected by an ECC engine. The data can be data on which a data bus inversion (DBI) operation or a data masking (DM) operation is performed and can include cyclic redundancy code (CRC) information. The data can be data encrypted for security or privacy.

[0177] The storage devices 3150 to 3150n and 3250 to 3250m may send control signals and command / address signals to the NAND flash memory devices 3252 to 3252m in response to read commands received from the processor. In this case, when reading data from the NAND flash memory devices 3252 to 3252m, a read enable (RE) signal may be input as a data output control signal, so that data can be output to the DQ bus. The data strobe DQS may be generated using the RE signal. The command and address signals may be latched into the page buffer according to the rising or falling edge of the write enable (WE) signal.

[0178] The controller 3251 may control all operations of the storage device 3250. In an embodiment, the controller 3251 may include SRAM. The controller 3251 may write data to the NAND flash 3252 in response to a write command, or may read data from the NAND flash 3252 in response to a read command. For example, the write command and / or the read command may be provided from the processor 3210 of the storage server 3200, the processor 3210m of another storage server 3200m, or the processors 3110 and 3110n of the application servers 3100 and 3100n. The DRAM 3253 may temporarily store (or buffer) the data to be written to the NAND flash 3252 or the data read from the NAND flash 3252. In addition, the DRAM 3253 may store metadata. Herein, the metadata is user data or data generated by the controller 3251 for managing the NAND flash 3252. The storage device 3250 may include a security element (SE) for security or privacy.

[0179] The entire DRAM 3253 or a part of the DRAM 3253 may include a semiconductor memory device according to an embodiment of the present disclosure. Accordingly, each DRAM 3253 may include a semiconductor memory device according to an embodiment of the present disclosure that reduces the chip size and allows a pattern included in the sub-word line driver to be finely formed.

[0180] As described above, the semiconductor memory device according to an embodiment of the present disclosure may reduce the chip size by reducing the area occupied by the sub-word line driver on the semiconductor substrate, and may allow a pattern included in the sub-word line driver to be finely formed by adjusting the layout of the transistors included in the sub-word line driver.

[0181] The above description relates to embodiments for implementing the present disclosure. In addition to the above embodiments, the present disclosure may also include embodiments in which the design is simply changed or easily changed. In addition, technologies that can be easily changed and implemented by using the above embodiments are also included in the present disclosure. Accordingly, the scope of the present disclosure should not be limited to the above embodiments, and should be determined by equivalents of the claims of the present invention and the following claims. Industrial Applicability

[0182] Embodiments of the present disclosure can be usefully used in any electronic devices and systems including semiconductor memory devices. For example, embodiments of the present disclosure can be more usefully applied to electronic systems such as PCs (personal computers), server computers, data centers, workstations, laptop computers, cellular phones, smartphones, MP3 players, PDAs (personal digital assistants), PMPs (portable multimedia players), digital TVs, digital cameras, portable game consoles, navigation systems, wearable devices, IoT (Internet of Things) devices, IoE (Internet of Everything) devices, e-books, VR (virtual reality) devices, AR (augmented reality) devices, and drones.

Claims

1. A semiconductor memory device, comprising: A first sub - word line driver, including a first pull - down transistor and a first holding transistor. During a de - activation interval of a first word line, the first pull - down transistor pulls down the first word line and the first holding transistor maintains the voltage level of the pulled - down first word line; And A second sub - word line driver, including a second pull - down transistor and a second holding transistor. During a de - activation interval of a second word line, the second pull - down transistor pulls down the second word line and the second holding transistor maintains the voltage level of the pulled - down second word line, Wherein, a source region of the first pull - down transistor and a source region of the second holding transistor are set to share a first doped region on a semiconductor substrate, and Wherein, a source region of the second pull - down transistor and a source region of the first holding transistor are set to share a second doped region on the semiconductor substrate.

2. The semiconductor memory device according to claim 1, wherein, A drain region of the first holding transistor and a drain region of the first pull - down transistor are set to share a third doped region on the semiconductor substrate, and Wherein, a drain region of the second holding transistor and a drain region of the second pull - down transistor are set to share a fourth doped region on the semiconductor substrate.

3. The semiconductor memory device according to claim 2, wherein, The first doped region to the fourth doped region are arranged separately from each other on the semiconductor substrate, and are arranged clockwise in the order of the first doped region, the fourth doped region, the second doped region, and the third doped region with respect to a virtual central axis perpendicular to the semiconductor substrate.

4. The semiconductor memory device according to claim 2, wherein, The first doped region and the third doped region are set to be point - symmetric with the second doped region and the fourth doped region.

5. The semiconductor memory device according to claim 1, wherein, The first pull - down transistor and the first holding transistor are arranged on the semiconductor substrate to be point - symmetric with the second pull - down transistor and the second holding transistor.

6. The semiconductor memory device according to claim 1, further comprising: A first metal line electrically connected to gates of the first pull - down transistor and the second pull - down transistor; A second metal line electrically connected to the gate of the first holding transistor; And A third metal line electrically connected to the gate of the second holding transistor.

7. The semiconductor memory device according to claim 6, wherein, The first metal line extends a first length in a first direction, then extends a second length in a second direction different from the first direction, and then extends a third length in the first direction again.

8. The semiconductor memory device according to claim 7, wherein, The first direction is the direction in which the first word line extends, and Wherein, the second direction forms a 45 - degree angle with the first direction.

9. The semiconductor memory device according to claim 7, wherein, The second metal line and the third metal line are symmetrically arranged with respect to the first metal line extending in the second direction.

10. The semiconductor memory device according to claim 9, wherein, The second metal line and the third metal line are arranged on a virtual line perpendicular to the second direction.

11. The semiconductor memory device according to claim 7, wherein, The first metal line is configured to provide a first word - line enable signal to the first pull - down transistor and the second pull - down transistor, and Wherein, the second metal line and the third metal line are configured to provide a first holding control signal and a second holding control signal to the first holding transistor and the second holding transistor, respectively.

12. The semiconductor memory device according to claim 1, further comprising: A first direct contact portion disposed on the first doped region; And A second direct contact portion disposed on the second doped region, Wherein the first pull - down transistor and the second holding transistor are configured to receive a negative voltage through the first direct contact portion, and Wherein the second pull - down transistor and the first holding transistor are configured to receive the negative voltage through the second direct contact portion.

13. The semiconductor memory device according to claim 1, wherein, The first pull - down transistor, the second pull - down transistor, the first holding transistor, and the second holding transistor are metal - oxide - semiconductor (MOS) transistors of a first conduction type.

14. The semiconductor memory device according to claim 1, wherein, The first word line and the second word line extend to one side of the memory cell array and are adjacent to each other.

15. A semiconductor memory device, comprising: A memory cell array including a plurality of memory cells connected to a plurality of word lines; And A first sub - word - line driver to a fourth sub - word - line driver, Wherein the first sub - word - line driver to the fourth sub - word - line driver respectively activate a first word line to a fourth word line that extend to one side of the memory cell array and are adjacent to each other among the plurality of word lines, Wherein the first sub - word - line driver includes: A first pull - down transistor that pulls down the first word line during a de - activation interval of the first word line; and A first holding transistor that maintains the voltage level of the pulled - down first word line during the de - activation interval of the first word line, Wherein the second sub - word - line driver includes: A second pull - down transistor that pulls down the second word line during a de - activation interval of the second word line; and A second holding transistor that maintains the voltage level of the pulled - down second word line during the de - activation interval of the second word line, Wherein the source region of the first pull - down transistor and the source region of the second holding transistor are provided as a first doped region on a common semiconductor substrate, and Wherein the source region of the second pull - down transistor and the source region of the first holding transistor are provided as a second doped region on the common semiconductor substrate.

16. The semiconductor memory device according to claim 15, wherein, The third sub - word - line driver includes: A third pull - down transistor that pulls down the third word line during a de - activation interval of the third word line; and A third holding transistor that maintains the voltage level of the pulled - down third word line during the de - activation interval of the third word line, and Wherein the fourth sub - word - line driver includes: A fourth pull - down transistor that pulls down the fourth word line during a de - activation interval of the fourth word line; and A fourth holding transistor that maintains the voltage level of the pulled - down fourth word line during the de - activation interval of the fourth word line.

17. The semiconductor memory device according to claim 16, further comprising: A first metal line electrically connected to the gates of the first pull - down transistor to the fourth pull - down transistor; A second metal line electrically connected to the gate of the first holding transistor; A third metal line electrically connected to the gate of the second holding transistor; A fourth metal line electrically connected to the gate of the third holding transistor; And A fifth metal line electrically connected to the gate of the fourth holding transistor.

18. The semiconductor memory device according to claim 17, wherein, The first metal line extends a first length in a first direction, then extends a second length in a second direction different from the first direction, and then extends a third length in the first direction again. Wherein, after the first metal line extends the third length in the first direction, the first metal line extends a fourth length in a third direction different from the first direction and then extends a fifth length in the first direction again.

19. The semiconductor memory device according to claim 18, wherein, The first direction is the direction in which the first word line extends. Wherein, the second direction forms a 45-degree angle with the first direction, and Wherein, the third direction forms a 45-degree angle with the first direction and a 90-degree angle with the second direction.

20. A semiconductor memory device, comprising: A first sub-word line driver including a first pull-down transistor and a first holding transistor. During a deactivation interval of the first word line, the first pull-down transistor pulls down the first word line and the first holding transistor maintains the voltage level of the pulled-down first word line. A second sub-word line driver including a second pull-down transistor and a second holding transistor. During a deactivation interval of the second word line, the second pull-down transistor pulls down the second word line and the second holding transistor maintains the voltage level of the pulled-down second word line. A first metal line electrically connected to the gates of the first pull-down transistor and the second pull-down transistor. A second metal line electrically connected to the gate of the first holding transistor. And A third metal line electrically connected to the gate of the second holding transistor. Wherein, the source region of the first pull-down transistor and the source region of the second holding transistor are set as a first doped region on a common semiconductor substrate. Wherein, the source region of the second pull-down transistor and the source region of the first holding transistor are set as a second doped region on the semiconductor substrate. Wherein, the drain region of the first holding transistor and the drain region of the first pull-down transistor are set as a third doped region on the semiconductor substrate, and Wherein, the drain region of the second holding transistor and the drain region of the second pull-down transistor are set as a fourth doped region on the semiconductor substrate.

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