Magnetic memory element and memory system

Abstract

The present invention improves crystallinity of a magnetic layer in a magnetic memory element while preventing a reduction in efficiency of magnetic anisotropy modulation. The magnetic memory element includes: a memory layer having a voltage-controlled magnetic anisotropy effect and a variable magnetization direction; the reference layer has a constant magnetization direction; a tunnel barrier layer disposed between the memory layer and the reference layer; and a bottom layer arranged as a layer below the storage layer. The memory layer of the magnetic memory element is formed so as to have a B content of 10 at% or less. The bottom layer of the magnetic storage element is formed in an amorphous state or is formed to have an orientation different from that of the tunnel barrier layer.

Description

Technical Field

[0001] The present disclosure relates to a magnetic storage element and a storage system. Background Art

[0002] In a magnetic resistance random access memory (MRAM) that uses a magnetic storage element as a non-volatile storage element, a voltage-driven magnetic storage element that writes data by applying a pulse voltage has been proposed. For such an MRAM, a magnetic storage element having a magnetic tunnel junction (MTJ) structure in which a tunnel barrier layer is sandwiched between two magnetic layers (a storage layer and a reference layer) is used.

[0003] This magnetic storage element is in a high-resistance state when the magnetization directions of the two magnetic layers are different, and is in a low-resistance state when the magnetization directions are the same. The MRAM stores data using this resistance change, and the higher the resistance ratio, the more stably data can be written and read. To increase the resistance ratio, the crystal structure of the magnetic layer is an important factor. By forming the magnetic layer into a crystal structure with a (001) orientation, a high resistance ratio can be obtained.

[0004] Generally, MgO and FeCoB are used for the tunnel barrier layer and the magnetic layer, respectively (see, for example, Patent Document 1). When B is included in the FeCo alloy of the magnetic layer, an amorphous magnetic layer can be formed. When MgO as the tunnel barrier layer is formed into an amorphous state and stacked on the magnetic layer, MgO is configured to have a (001) orientation. Thereafter, by performing annealing, B in the magnetic layer diffuses, and FeCo undergoes solid-phase epitaxial growth using the MgO of the tunnel barrier layer as a template. As a result, the crystal structure of the magnetic layer can be configured to have a (001) orientation.

[0005] Citation List

[0006] Patent Document

[0007] Patent Document 1: JP 2019-057601 A Summary of the Invention

[0008] Technical Problem

[0009] However, the problem with the above conventional technology is that the performance deteriorates when applied to a voltage-driven magnetic storage element. This is because a voltage-driven magnetic storage element requires a magnetic layer having a voltage-controlled magnetic anisotropy (VCMA) effect, but when the content of B is large, the magnetic anisotropy voltage modulation efficiency decreases. In this case, a high write voltage is required, and the convenience deteriorates.

[0010] Therefore, the present disclosure provides a magnetic storage element that prevents a decrease in magnetic anisotropy modulation efficiency, improves the crystallinity of the magnetic layer, and maintains a high resistance ratio, and a storage system using the magnetic storage element.

[0011] Solution to the problem

[0012] A magnetic storage element according to the present disclosure includes: a storage layer having a variable magnetization direction and a voltage-controlled magnetic anisotropy effect; a reference layer having a constant magnetization direction; a tunnel barrier layer disposed between the storage layer and the reference layer; and a bottom layer disposed below the storage layer, wherein the storage layer is configured to have a B content of 10 at% or less, and the bottom layer is configured to have an orientation different from that of the tunnel barrier layer or to be in an amorphous state.

[0013] Furthermore, a storage system according to the present disclosure includes: a magnetic storage element including: a storage layer having a variable magnetization direction and a voltage-controlled magnetic anisotropy effect, a reference layer having a constant magnetization direction, a tunnel barrier layer disposed between the storage layer and the reference layer, and a bottom layer disposed below the storage layer; and a storage control unit that controls writing and reading of data in the magnetic storage element, wherein the storage layer is configured to have a B content of 10 at% or less, and the bottom layer is configured to have an orientation different from that of the tunnel barrier layer or to be in an amorphous state. Description of the Drawings

[0014] Figure 1 is a diagram showing a configuration example of a storage system according to an embodiment of the present disclosure.

[0015] Figure 2 is a diagram showing a configuration example of a storage cell according to an embodiment of the present disclosure.

[0016] Figure 3 is a diagram showing a configuration example of a magnetic storage element according to a first embodiment of the present disclosure.

[0017] Figure 4 is a diagram showing another configuration example of a magnetic storage element according to a first embodiment of the present disclosure.

[0018] Figure 5 is a diagram showing an example of writing in a magnetic storage element according to an embodiment of the present disclosure.

[0019] Figure 6 is a diagram showing an example of a method for manufacturing a magnetic storage element according to an embodiment of the present disclosure.

[0020] Figure 7 is a diagram showing an example of a processing procedure of a writing process of a magnetic storage element according to an embodiment of the present disclosure.

[0021] Figure 8 is a diagram showing an example of a writing process of a magnetic storage element according to an embodiment of the present disclosure.

[0022] Figure 9 is a diagram showing a configuration example of a magnetic storage element according to a second embodiment of the present disclosure.

[0023] Figure 10 is a diagram showing a configuration example of a magnetic storage element according to a second embodiment of the present disclosure.

[0024] Figure 11 is a diagram showing another configuration example of a magnetic storage element according to a second embodiment of the present disclosure.

[0025] Figure 12 is a diagram showing another configuration example of a magnetic storage element according to a second embodiment of the present disclosure.

[0026] Figure 13 is a diagram showing another configuration example of a magnetic storage element according to a second embodiment of the present disclosure.

[0027] Figure 14 is a diagram showing another configuration example of a magnetic storage element according to a second embodiment of the present disclosure. Detailed Embodiments

[0028] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The description will be given in the following order. Note that in the following embodiments, the same components are denoted by the same reference numerals, and redundant descriptions will be omitted.

[0029] 1. First Embodiment

[0030] 2. Second Embodiment

[0031] (1. First Embodiment)

[0032] [Configuration of Storage System]

[0033] Figure 1 is a diagram showing a configuration example of a storage system according to an embodiment of the present disclosure. Figure 1 is a block diagram showing a configuration example of the storage system 1. The storage system 1 includes an interface unit 2, a storage control unit 3, a storage unit array 10, a word line address decoder 60, a word line control circuit 20, a bit line address decoder 50, a bit line control circuit 30, and a sense amplifier 40. In addition, the storage system 1 further includes a voltage generation circuit 90. Note that in the present embodiment, an example in which a memory interface connected to a main system is provided is described, but the storage system 1 can also be applied to an embedded memory, a hybrid memory, and a hybrid storage medium having an I / O connected to a system-on-chip (SoC) hybrid internal bus or a logic circuit.

[0034] The interface unit 2 uses the storage system 1 to perform exchanges with the main system and the like.

[0035] The storage control unit 3 performs exchanges with the main system and the like. The storage control unit 3 receives commands from the main system and the like, and controls the writing and reading of data based on the received commands. Figure 1 The storage control unit 3 in outputs write and read addresses to the word line address decoder 60 and the bit line address decoder 50. In addition, the storage control unit 3 outputs control signals to the word line control circuit 20 and the voltage generation circuit 90. Further, the storage control unit 3 sends write data to the sense amplifier 40 and acquires read data from the sense amplifier 40.

[0036] The memory cell array 10 is configured by arranging memory cells 100 for storing data in a two-dimensional matrix. The memory cell 100 includes a magnetic memory element 120 and a selection element 110.

[0037] For example, as the magnetic memory element 120, a magnetoresistive effect element such as an MTJ element can be used. The MTJ element is an element in which a nonmagnetic insulating layer is provided between two ferromagnetic layers, and is an element whose resistance value changes according to the magnetization directions of the two ferromagnetic layers. When the magnetization directions of the two ferromagnetic layers are different, the MTJ element is in a high-resistance state, and when the magnetization directions are the same, the MTJ element is in a low-resistance state. Note that the state where the magnetization directions are the same is called the parallel state, and the state where the magnetization directions are different is called the antiparallel state. The magnetization direction can be changed by applying a write voltage to the MTJ element. For example, 1-bit data can be stored by associating the values "0" and "1" with the low-resistance state and the high-resistance state of the MTJ element, respectively. Note that the values "0" and "1" can also be referred to as a low-level voltage (L) and a high-level voltage (H).

[0038] The selection element 110 is an element that is connected to one end of the magnetic memory element 120 and controls the application of voltage to the magnetic memory element 120. For example, an n-channel MOS transistor can be applied to the selection element 110.

[0039] The word line 11 (WL) and the bit line 12 (BL) for transmitting control signals are connected to the memory cell 100. In addition, in the memory cell 100, a source line 13 (SL) for transmitting signals from the magnetic memory element 120 is also provided. In the memory cell array 10, a plurality of word lines are wired in the row direction, and a plurality of bit lines and source lines are wired in the column direction.

[0040] The word line address decoder 60 selects the word lines of the memory cell array 10 based on the control signal from the storage control unit 3.

[0041] The word line control circuit 20 outputs a control signal to the word line selected by the word line address decoder 60.

[0042] The bit line address decoder 50 selects a bit line of the memory cell array 10 based on a control signal from the memory control unit 3.

[0043] The bit line control circuit 30 outputs a control signal to the bit line selected by the bit line address decoder 50.

[0044] The sense amplifier 40 reads data by detecting a current flowing through the memory cell 100 during a read operation. The read data is output to the memory control unit 3. Further, the sense amplifier 40 applies a write voltage to the memory cell 100 during a write operation.

[0045] The voltage generation circuit 90 is a circuit that generates voltages to be applied during write and read operations of the memory cell 100.

[0046] Writing to the memory cell 100 is performed when the stored data in the memory cell 100 is different from the data to be written. That is, data is read from the memory cell 100, and the read data and the write data are compared. As a result of this comparison, writing is performed when they are different. In this case, writing can be performed by inverting the stored data in the memory cell 100. That is, writing can be performed by inverting the storage state of the magnetic storage element 120. The storage state of the magnetic storage element 120 can be inverted by applying a predetermined write voltage to the magnetic storage element 120. Details of writing to the magnetic storage element 120 will be described later.

[0047] Reading can be performed by applying a predetermined read voltage to the magnetic storage element 120 of the memory cell 100 and detecting the current flowing through the memory cell 100. Note that the read voltage is preferably a voltage having a polarity different from that of the write voltage.

[0048] [Memory Cell]

[0049] Figure 2 is a diagram showing a configuration example of a memory cell according to an embodiment of the present disclosure. Figure 2 is a schematic diagram showing a configuration example of the memory cell 100. As described above, the memory cell 100 includes a magnetic storage element 120 and a selection element 110.

[0050] The magnetic storage element 120 is connected to the wiring 101 etc. via the contact layers 103 and 104. As will be described later, the magnetic storage element 120 is configured by stacking a storage layer 122, a reference layer 125, etc. The configuration of the magnetic storage element 120 will be described later.

[0051] The drain of the selection element 110 is connected to the contact layer 104 of the magnetic storage element 120, and the source of the selection element is connected to the source line 13 (SL). Further, the gate of the selection element 110 is connected to the word line 11 (WL). Note that the contact layer 103 on the reference layer 111 side of the magnetic storage element 120 is connected to the wiring 101 that constitutes the bit line 12 (BL). By applying a conduction voltage to the word line 11 (WL), the selection element 110 is turned on, and a current according to the voltage applied to the magnetic storage element 120 can flow.

[0052] As described above, the word line 11 (WL) is connected to the word line control circuit 20. The bit line 12 (BL) is connected to the bit line control circuit 30. The source line 13 (SL) is connected to the sense amplifier 40. By applying a voltage between the bit line 12 (BL) and the source line 13 (SL) and applying a conduction voltage for turning on the selection element 110 to the word line 11 (WL), a voltage for writing or reading can be applied to the magnetic storage element 120.

[0053] Further, a magnetic field generating layer 109 is provided in Figure 2 the magnetic storage element 120 in. The magnetic field generating layer 109 applies a magnetic field in a direction ( Figure 2 the horizontal direction in) perpendicular to the stacking direction of the storage layer 122 etc. of the magnetic storage element 120.

[0054] Note that the configuration of the storage cell 100 is not limited to this example. For example, the positions of the magnetic field generating layer 109 and the magnetic storage element 120 can be interchanged. Further, for example, either of the contact layers 103 and 104 can be configured as the magnetic field generating layer. In this case, the magnetic field generating layer 109 can be omitted. Further, a magnetic layer can be formed above or below the magnetic storage element 120, and a magnetic field can be applied using the leakage magnetic field. Further, by inserting an antiferromagnetic layer into the magnetic storage element 120, an exchange bias magnetic field from the antiferromagnetic layer can be applied. Further, a magnetic field generated by arranging a wiring parallel to the horizontal direction of the magnetic storage element 120 above the wiring 101 or below the magnetic storage element 120 and causing a current to flow can also be used. Further, a method of applying a magnetic field by arranging a permanent magnet around the storage cell array 10 can also be adopted.

[0055] [Magnetic storage element]

[0056] Figure 3 is a diagram showing a configuration example of a magnetic storage element according to the first embodiment of the present disclosure. Figure 3 is a cross-sectional view showing a configuration example of the magnetic storage element 120. Figure 3The magnetic storage element 120 therein includes a bottom layer 121, a storage layer 122, a tunnel barrier layer 124, a reference layer 125, a spacer layer 127, a pinned layer 128, and a capping layer 129. In addition, Figure 3 The magnetic storage element 120 therein is configured by sequentially stacking a bottom layer 121, a storage layer 122, a tunnel barrier layer 124, a reference layer 125, a spacer layer 127, a pinned layer 128, and a capping layer 129.

[0057] The bottom layer 121 is a layer that serves as a substrate for the storage layer 122. The bottom layer 121 can be configured to have an orientation different from (001). Specifically, the bottom layer 121 can be formed as a body-centered cubic lattice (bcc), a face-centered cubic lattice (fcc), a hexagonal close-packed lattice (hcp), or an amorphous state. The bottom layer 121 can be made of a metal such as Cr, Ta, Ru, Au, Ag, Cu, Al, Ti, V, Mo, Zr, Hf, Re, W, Pt, Pd, Ir, or Rh, or an alloy containing these metals. In addition, the bottom layer 121 can also be configured by stacking these metals. In addition, the bottom layer 121 can also be made of a conductive nitride such as TiN. For example, Figure 3 The bottom layer 121 therein can be formed of Ta (thickness: 5 nm) and Ru (thickness: 10 nm) formed sequentially.

[0058] The storage layer 122 is a ferromagnetic layer having magnetic anisotropy and an energy-variable magnetization direction. The state where the magnetization direction of the storage layer 122 is the same as the magnetization direction of the reference layer 125 and the state where the magnetization direction of the storage layer is different from the magnetization direction of the reference layer 125 correspond to the parallel state and the antiparallel state, respectively. The magnetic storage element 120 is in a low-resistance state in the parallel state and in a high-resistance state in the antiparallel state. As described above, by applying a voltage to the magnetic storage element 120, the magnetization direction of the storage layer 122 can be reversed.

[0059] As described above, the storage layer 122 can be made of CoFe. In addition, in addition to CoFe, the storage layer 122 can include a ferromagnetic material containing at least one of Fe, Co, Ni, and Mn. In addition, another element can be added to the storage layer 122 to improve the VCMA efficiency, control the interface magnetic anisotropy energy, adjust the saturation magnetization, control the magnetocrystalline anisotropy energy, and adjust the grain size and intergranular bonding. As an element added to the storage layer 122, for example, at least one of Ir, Os, Pt, Rh, Hf, Zr, Ti, Ta, W, Re, Au, Mo, Ru, Pd, Y, V, Sc, Gd, Tb, La, Mg, Al, Ag, Cu, and Cr can be applied. Figure 3 The storage layer 122 therein can be made of, for example, CoFe (thickness: 0.8 nm).

[0060] The thickness of the desired storage layer 122 is 3 nm or less. This is because the magnetization direction caused by the interface magnetic anisotropy during the standby period can be controlled in the direction perpendicular to the film surface. In addition, it is more preferable to adjust the film thickness of the storage layer 122 to 1.5 nm or less. This is because the anisotropy modulation effect can be improved by the applied voltage.

[0061] In addition, a substrate cooling process can be added before or during the formation of the storage layer 122. At this time, the temperature reached by the wafer (substrate) can be, for example, 0°C or less. Since the storage layer 122 can be configured to be in an amorphous state without being affected by the orientation of the underlying layer 121 by adding the cooling process, the MgO of the tunnel barrier layer to be described later can grow in the (001) orientation. For example, cooling sputtering can be applied to the cooling process.

[0062] Thereafter, by applying an annealing process, the CoFe of the storage layer 122 can be configured to have the (001) orientation using MgO as a template. The temperature reached by the wafer (substrate) during annealing can be, for example, in the range of 250°C or more and 500°C or less. Through these steps, the CoFe of the storage layer 122 and the MgO of the tunnel barrier layer can be in the (001) orientation. As a result, a high magnetoresistance ratio can be obtained, and the read margin can be increased. In addition, the magnetic anisotropy energy can be improved, and the holding force can be increased. In addition, the VCMA efficiency can be improved, and the write voltage can be reduced.

[0063] As described above, even without the inclusion of B, the CoFe of the storage layer 122 can be formed in an amorphous state. Note that a configuration including multiple storage layers as shown later can also be adopted. Figure 9 Even in this case, CoFe with a B content of approximately 0% can be used for the storage layer adjacent to the tunnel barrier layer 124. Note that in the case where multiple storage layers are provided, it is desirable that the B concentration in all the storage layers including the storage layer 122 is 7 at% or less. This is to prevent a decrease in the VCMA efficiency. In addition, it is more desirable that the B concentration in all the storage layers including the storage layer 122 is 5 at% or less. This is to reduce the thermal diffusion in the case of applying a heat load through wafer processing or annealing.

[0064] The tunnel barrier layer 124 is provided adjacent to the storage layer 122, and an electric field is applied to the storage layer 122 to impart a voltage-controlled magnetic anisotropy effect. In addition, the tunnel barrier layer 124 is a layer that separates the storage layer 122 from the reference layer 125. Figure 3 The tunnel barrier layer 124 in [reference] can be made of, for example, MgO (thickness: 2.0 nm).

[0065] Note that the tunnel barrier layer 124 can be made of an oxide of at least one element selected from the group consisting of Mg, Al, Ti, Si, Zn, Zr, Hf, Ta, Bi, Cr, Ga, La, Gd, Sr, and Ba, or a nitride of at least one element selected from the group consisting of Mg, Al, Ti, Si, Zn, Zr, Hf, Ta, Bi, Cr, Ga, La, Gd, Sr, and Ba. In addition, insulators, dielectrics, and semiconductors such as MgF2, CaF, SrTiO2, AlLaO3, or AlNO can also be used for configuration. Note that the tunnel barrier layer 124 is also referred to as an insulating layer.

[0066] The reference layer 125 is a ferromagnetic layer having magnetic anisotropy and a constant magnetization direction. The magnetization direction of the reference layer 125 is controlled in a direction perpendicular to the film surface by the magnetic anisotropy. The reference layer 125 may include a ferromagnetic layer containing at least one of Fe, Co, Ni, and Mn. Similar to the storage layer 122, it is desirable that the reference layer 125 does not include B. This is to enhance the VCMA effect at the interface. Figure 3 The reference layer 125 in [reference] can be made of, for example, CoFe (thickness: 1.0 nm).

[0067] The fixed layer 128 is a ferromagnetic layer having magnetic anisotropy and a fixed magnetization direction. The magnetization direction of the fixed layer 128 is controlled in a direction perpendicular to the film surface by the magnetic anisotropy. In addition, the magnetization direction of the fixed layer 128 is configured to be antiparallel to the magnetization direction of the reference layer 125. The leakage magnetic field applied from the reference layer 125 to the storage layer 122 can be canceled by the fixed layer 128. The fixed layer 128 contains Co and at least one element of Ni, Pt, and Pd, and can be formed of an alloy or an artificial lattice of CoPt, CoNi, and CoPd. Figure 3 The fixed layer 128 in [reference] can be made of, for example, PtCo (thickness: 2.0 nm).

[0068] Note that Figure 3 The magnetic storage element 120 in [reference] shows an example of a thumbtack-type configuration, in which the fixed layer 128 is formed above the tunnel barrier layer 124, and the storage layer 122 is formed below the tunnel barrier layer 124. Note that in the bottom-pin type configuration, the fixed layer 128 can be formed below the tunnel barrier layer 124, and the storage layer 122 can be formed above the tunnel barrier layer 124. An example of the bottom-pin type magnetic storage element 120 will be described in the second embodiment.

[0069] The spacer layer 127 is a film that separates the reference layer 125 from the fixed layer 128. The spacer layer 127 can be made of at least one of Ru, Ir, Rh, and Re.

[0070] The capping layer 129 is a layer that prevents the diffusion of metal from the wiring member. The capping layer 129 can be made of a metal such as Cr, Ta, Ru, Au, Ag, Cu, Al, Ti, V, Mo, Zr, Hf, Re, W, Pt, Pd, Ir, or Rh. In addition, the capping layer 129 can also include a layer made of an alloy or a transition metal element containing these metals. In addition, the capping layer 129 can also be configured by stacking them. In addition, the capping layer 129 can also be made of a conductive nitride such as TiN. Figure 3 The capping layer 129 in Figure 3 can be formed of, for example, Ru (thickness: 7 nm) and Ta (thickness: 5 nm) formed in sequence.

[0071] Figure 4 is a diagram showing another configuration example of the magnetic storage element according to the first embodiment of the present disclosure. Similar to Figure 3 Similar, Figure 4 is a cross-sectional view showing a configuration example of the magnetic storage element 120. Figure 4 The magnetic storage element 120 in Figure 3 is different from the magnetic storage element 120 in Figure 3 in that a voltage modulation enhancement layer 131 is provided between the storage layer 122 and the tunnel barrier layer 124.

[0072] The voltage modulation enhancement layer 131 improves the VCMA efficiency. The interfacial magnetic anisotropy energy can also be controlled by providing the voltage modulation enhancement layer 131 between the storage layer 122 and the tunnel barrier layer 124. The voltage modulation enhancement layer 131 can be made of at least one of Ir, Os, Pt, Rh, Hf, Zr, Ti, Ta, W, Re, Au, Mo, Ru, Pd, Y, V, Sc, Gd, Tb, La, Mg, Al, Ag, Cu, Cr, Co, Fe, Ni, etc. or an oxide thereof.

[0073] [Writing]

[0074] Figure 5 is a diagram showing an example of writing in the magnetic storage element according to the embodiment of the present disclosure. Figure 5 is a diagram for explaining writing in the magnetic storage element 120. Figure 5 The upper part of shows the write voltage waveform of the magnetic storage element 120. Figure 5 The middle part of shows the state of the magnetization energy of the storage layer 122 during the writing process. In Figure 5In the middle view, the horizontal axis represents the magnetization direction, and the vertical axis represents the magnetic energy. The curve in this figure represents the magnetization energy curve 304 indicating the relationship between the magnetization direction and the magnetic energy, and the white circle 305 represents the direction in which the magnetization vector points. The two valley regions where the magnetization direction represented by the white circle 305 is perpendicular to the film surface and upward or downward are energy stable regions. In addition, the peak between the regions represents the energy height when the magnetization points in the in-plane direction. Figure 5 The lower part of is a view schematically showing the magnetization movement of the magnetic layer due to the VCMA effect. Note that when a write voltage is applied, a magnetic field Hext is applied in a direction perpendicular to the stacking direction of the storage layer 122 and the reference layer 125.

[0075] (a) shows the standby state before the write voltage is applied ( Figure 5 T1 in the upper part of ). In this state, as Figure 5 shown in the middle part of, the magnetization energy curve 304 is in the shape of having two valleys. In addition, in Figure 5 the lower part of, the direction of the magnetization vector (thick arrow) is S in the positive direction of the z-axis.

[0076] (b) shows the state when the write voltage is applied ( Figure 5 T2 in the upper part of ). In this state, as Figure 5 shown in the middle part of, the magnetization energy curve 304 has a downward convex shape. As a result, the magnetization vector of the storage layer 122 starts to precess. Figure 5 The thin arrow in the lower view of represents the precession trajectory.

[0077] (c) shows the state after writing ( Figure 5 T3 in the upper part of ). This state represents the state where the application of the write voltage is stopped when the direction of the magnetization vector moves across the peak of the magnetization energy curve 304 to the opposite side. The white circle 305 moves to the opposite valley, and the magnetization direction is reversed. In addition, as Figure 5 shown in the lower view of, the magnetization vector is E in the negative direction of the z-axis.

[0078] As described above, writing can be performed in the magnetic storage element 120. Note that the time for applying the write voltage needs to be substantially equal to the time for reversing the magnetization direction.

[0079] [Method of manufacturing a magnetic storage element]

[0080] Figure 6 is a view showing an example of a method for manufacturing a magnetic storage element according to an embodiment of the present disclosure. Figure 6 is a flowchart showing an example of the manufacturing process of the magnetic storage element 120. In Figure 6In [the process], the underlying layer 121 and the like can be formed by known methods such as sputtering. First, the substrate is pre-treated (step S101). This is a step of pre-treating the substrate (wafer) on which the magnetic storage element 120 is formed. This pre-treatment corresponds to the processes of degassing the substrate and pre-cleaning etching.

[0081] Next, the underlying layer 121 is formed on the substrate (step S102). Next, annealing is performed (step S103). This annealing can be performed by heating the substrate to a temperature of 150 °C or higher and 450 °C or lower in a vacuum.

[0082] Next, the substrate is cooled (step S104). This can be performed by cooling the substrate to a temperature of 0 °C or lower. Next, the storage layer 122 is formed (step S105). This can be performed by the above-mentioned cooled sputtering. Next, the tunnel barrier layer 124 is formed (step S106). Next, the substrate is heated (step S107). This can be performed by heating the substrate to a temperature of 100 °C or higher and 300 °C or lower. Note that this substrate heating step can also be performed in the step of step S106.

[0083] Next, the substrate is cooled (step S108). This can be performed by cooling the substrate to a temperature of 0 °C or lower. Next, the reference layer 125 is formed (step S109). Next, the substrate returns to room temperature to form the spacer layer 127 (step S110). Next, the substrate is heated (step S111). This can be performed by heating the substrate to a temperature of 250 °C or higher and 500 °C or lower. Note that this substrate heating step can also be performed in the next step of step S112.

[0084] Next, the fixed layer 128 is formed (step S112). Next, the capping layer 129 is formed (step S113). Next, annealing is performed (step S114). This annealing can be performed by heating the substrate to a temperature of 250 °C or higher and 500 °C or lower.

[0085] [Writing Process Program]

[0086] Figure 7 is a diagram showing an example of the processing procedure of the writing process of the magnetic storage element according to an embodiment of the present disclosure. Figure 7It is a flowchart showing an example of the processing procedure of the write process of the magnetic storage element 120. First, the storage control unit 3 performs an initial read (step S201). This can be performed by reading the data held in the magnetic storage element 120 of the storage cell 100 that is the write target. Next, the storage control unit 3 compares the read data with the write data (step S202). As a result, if they do not match (step S203, no), the storage control unit 3 applies a write voltage to the selected storage cell 100 (step S204). Next, the storage control unit 3 performs a verification read on the storage cell 100 on which the write has been performed (step S205). Next, the storage control unit 3 proceeds to the process of step S202. Note that in step S203, if the read data and the write data match (step S203, yes), the storage control unit 3 ends the write process.

[0087] [Write Process]

[0088] Figure 8 It is a diagram showing an example of the write process of the magnetic storage element according to an embodiment of the present disclosure. Figure 8 It is a timing diagram showing an example of the write process of the magnetic storage element 120. In Figure 8 it, the "read start signal", "write start signal", "bit line control signal", "word line control signal", and "sense amplifier control signal" respectively represent the waveforms of the read start signal, write start signal, bit line control signal, word line control signal, and sense amplifier control signal. In addition, the "applied voltage" represents the waveform of the voltage generated by the voltage generation circuit 90. The "read voltage" represents the waveform of the read voltage of the magnetic storage element 120. The "sense amplifier output" represents the waveform of the signal output from the sense amplifier 40 to the storage control unit 3. The "comparison result" represents the comparison result between the data read from the storage element 120 and the write data of the storage element 120.

[0089] The read start signal and the write start signal are generated by the storage control unit 3. The bit line 12 and the word line 11 are respectively selected by the bit line address decoder 50 and the word line address decoder 60. The bit line control signal and the word line control signal are respectively generated by the bit line control circuit 30 and the word line control circuit 20. The applied voltage corresponds to the voltage of the signal to be input to the sense amplifier 40 during read and write. Note that Figure 8 the read voltage in it schematically represents the difference between the high resistance state (high) and the low resistance state (low) of the magnetic storage element 120 when the voltage is applied. Note that the actual signal waveform is not limited to this diagram.

[0090] The sense amplifier control signal is a signal for controlling the timing of determining the read data. The sense amplifier 40 determines whether the magnetic storage element 120 is in a high resistance state (high) or a low resistance state (low), and outputs the determination result to the storage control unit 3. Based on the determination result, the storage control unit 3 determines whether the written data and the read data match.

[0091] The operations will be described in chronological order. The storage control unit 3 outputs a read start signal and an address to the voltage generation circuit 90, the bit line address decoder 50, and the word line address decoder 60. The bit line address decoder 50 and the word line address decoder 60 decode the address and output control signals to the corresponding bit lines 12 and word lines 11. Then, the voltage generation circuit 90 generates a read voltage and applies the read voltage to the bit lines 12 to perform an initial read. The read voltage changes to high or low according to whether the magnetic storage element 120 has a high resistance or a low resistance. When the sense amplifier control signal is output after determining the read voltage, the read result is output from the sense amplifier 40.

[0092] The storage control unit 3 compares the written data and the read data, and if they match, ends the process. On the other hand, if they do not match, a write signal is output. Figure 8 An example of the case where they do not match is shown. After the corresponding bit line control signal and word line control signal are turned on, a write voltage is applied. In addition, the storage control unit 3 performs a read for verification, and when the read data matches the written data, ends the write process. This verification read control can be the same as the control for the initial read. In addition, the verification read can be performed at a read voltage different from the initial read. In Figure 8 the example, an example where the write is successful with one voltage application has been described, but if the write fails, the write voltage can be applied again.

[0093] Note that the write control is not limited to this example. Depending on the circuit design, the start signal, etc. may also be unnecessary, and the timing for controlling the bit lines and word lines is arbitrary. Although Figure 8 an example of writing is shown, any read method can be applied to the read.

[0094] As described above, in the magnetic storage element 120 according to the first embodiment of the present invention, a film is formed while cooling CoFe, wherein the content of B is about 0% to form the storage layer 122 in an amorphous state. The tunnel barrier layer 124 made of MgO is formed on the storage layer 122. Since the storage layer 122 is in an amorphous state, the tunnel barrier layer 124 grows as a crystal with a (001) orientation of MgO. Thereafter, by performing annealing, the CoFe of the storage layer 122 undergoes solid-phase epitaxial growth with a (001) orientation based on the crystal plane of MgO of the tunnel barrier layer 124. As a result, the content of B in the storage layer 122 can be reduced while improving the crystallinity of the storage layer 122 and maintaining a high resistance ratio, and a decrease in the magnetic anisotropy modulation efficiency can be prevented.

[0095] Note that the method for manufacturing a magnetic layer not including B according to the present disclosure can be applied to elements other than the magnetic storage element 120, such as a magnetic head. By applying the magnetic head to which the method for manufacturing a magnetic layer according to the present disclosure is applied to a hard disk device, the performance of the hard disk device can be improved.

[0096] (2. Second Embodiment)

[0097] A modification of the magnetic storage element 120 of the first embodiment described above will be described.

[0098] [Configuration of Magnetic Storage Element]

[0099] Figure 9 And Figure 10 are diagrams showing a configuration example of a magnetic storage element according to a second embodiment of the present disclosure. Similar to Figure 3 And Figure 4 Similar, Figure 9 And Figure 10 are diagrams showing a configuration example of the magnetic storage element 120. Figure 9 And Figure 10 The magnetic storage element 120 in Figure 3 And Figure 4 is different from the magnetic storage element 120 in Figure 9 And Figure 10 in that it further includes a storage layer 123.

[0100] The storage layer 123 is configured to include at least one of Fe, Co, Ni, and Mn, and may include at least one element of B, C, Mg, Y, Si, Al, Ta, Zr, Hf, and rare earth elements, so as to adjust the saturation magnetization, control the magnetocrystalline anisotropy energy, and adjust the grain size and intergranular bonding. Note that, as described above, in all storage layers including the storage layers 122 and 123, it is desirable that the content of B be set to 10 at%.

[0101] In Figure 9 and Figure 10 , the storage layer 123 may be made of, for example, CoFeB (thickness: 0.5 nm). The storage layer 122 may be made of, for example, CoFe (thickness: 0.5 nm). Other configurations are the same as those in Figure 3 and Figure 4 and thus the description thereof is omitted.

[0102] Figure 11 and Figure 12 are diagrams showing other configuration examples of the magnetic storage element according to the second embodiment of the present disclosure. Similar to Figure 3 and Figure 4 , Figure 11 and Figure 12 are diagrams showing configuration examples of the magnetic storage element 120. Figure 11 and Figure 12 The magnetic storage element 120 in Figure 3 and Figure 4 is different from the magnetic storage element 120 in Figure 3 and Figure 4 in that it further includes a reference layer 126 and an intermediate layer 132.

[0103] Figure 11 and Figure 12 The reference layer 126 in and Figure 12 is configured to include at least one of Fe, Co, Ni, and Mn, and may include at least one element of B, C, Mg, Y, Si, Al, Ta, Zr, Hf, Pt, Pd, and rare earth elements, so as to adjust the saturation magnetization, control the magnetocrystalline anisotropy energy, and adjust the grain size and intergranular bonding.

[0104] The intermediate layer 132 is a layer inserted between the reference layers 125 and 126. The intermediate layer 132 is a layer containing at least one of, for example, Ta, W, Nb, Mo, Cr, V, Re, Ru, Ir, Cu, Rh, Co, Fe, Ni, and B.

[0105] In Figure 11 and Figure 12Among them, the reference layer 125 can be made of, for example, CoFe (thickness: 0.8 nm). The intermediate layer 132 can be made of, for example, Mo (thickness: 0.35 nm). The reference layer 126 can be made of, for example, Co (thickness: 0.7 nm). The fixed layer 128 can be made of, for example, PtCo (thickness: 3.0 nm). Other configurations are the same as those in Figure 3 and Figure 4 and thus the description thereof is omitted.

[0106] Figure 13 and Figure 14 are diagrams showing other configuration examples of the magnetic storage element according to the second embodiment of the present disclosure. Similar to Figure 3 and Figure 4 , Figure 13 and Figure 14 are diagrams showing configuration examples of the magnetic storage element 120. Figure 13 and 14 The magnetic storage element 120 in Figure 3 and Figure 4 is different from the magnetic storage element 120 in

[0107] in that it is configured as a bottom pin type.

[0108] Although the embodiments of the present disclosure have been described above, the technical scope of the present disclosure is not limited to the above embodiments themselves, and various modifications can be made without departing from the gist of the present disclosure. In addition, components of different embodiments and variations can be appropriately combined.

[0109] In addition, the processes described using the flowcharts and sequence diagrams in this specification do not necessarily have to be executed in the order shown. Some processing steps can be executed in parallel. In addition, additional processing steps can be adopted, and some processing steps can be omitted.

[0110] Note that the effects described in this specification are only examples and are not limited, and other effects can be provided.

[0111] Note that the present technology may also have the following configuration.

[0112] (1) A magnetic storage element, comprising:

[0113] A storage layer having a variable magnetization direction and a voltage-controlled magnetic anisotropy effect;

[0114] A reference layer having an invariant magnetization direction;

[0115] A tunnel barrier layer provided between the storage layer and the reference layer; and

[0116] The bottom layer, which is disposed below the storage layer, wherein,

[0117] the storage layer is configured to have a B content of 10 at% or less, and

[0118] the bottom layer is configured to have an orientation different from that of the tunnel barrier layer or to be in an amorphous state.

[0119] (2) The magnetic storage element according to (1) above, wherein the tunnel barrier layer is configured to have a (001) orientation.

[0120] (3) The magnetic storage element according to (1) or (2) above, wherein, in the storage layer, the surface facing the tunnel barrier layer is oriented with (001).

[0121] (4) The magnetic storage element according to (3) above, wherein the storage layer is formed in an amorphous state, and the surface facing the tunnel barrier layer is oriented with (001) by heat treatment.

[0122] (5) The magnetic storage element according to (4) above, wherein the storage layer is formed in an amorphous state by at least one of the following: cooling in the film formation step of the storage layer and cooling of the substrate in the step before the film formation step.

[0123] (6) The magnetic storage element according to (5) above, wherein the storage layer is formed in an amorphous state by cooling at 0 °C or below.

[0124] (7) The magnetic storage element according to any one of (1) to (6) above, wherein the storage layer is configured to contain CoFe.

[0125] (8) The magnetic storage element according to any one of (1) to (7) above, wherein the tunnel barrier layer is made of an oxide of at least one of the following: Mg, Ca, Li, Si, Sr, Zr, Hf, Ti, Sc, La, Ta, Eu, Cu, Ba, Mo, W, V, Y, Ni, Co, Mn, Cr, and Fe.

[0126] (9) The magnetic storage element according to any one of (1) to (8) above, further comprising a voltage modulation enhancement layer disposed between the storage layer and the tunnel barrier layer.

[0127] (10) The magnetic storage element according to (9) above, wherein the voltage modulation enhancement layer is made of at least one of the following or an oxide of at least one of the following: Ir, Os, Pt, Rh, Hf, Zr, Ti, Ta, W, Re, Au, Mo, Ru, Pd, Y, V, Sc, Gd, Tb, La, Mg, Al, Ag, Cu, Cr, Co, Fe, and Ni.

[0128] (11)A storage system, comprising:

[0129] A magnetic storage element, the magnetic storage element comprising:

[0130] A storage layer having a variable magnetization direction and a voltage-controlled magnetic anisotropy effect,

[0131] A reference layer having a constant magnetization direction,

[0132] A tunnel barrier layer disposed between the storage layer and the reference layer, and

[0133] A bottom layer disposed below the storage layer; and

[0134] A storage control unit that controls writing and reading of data in the magnetic storage element, wherein,

[0135] The storage layer is configured to have a B content of 10 at% or less, and

[0136] The bottom layer is configured to have an orientation different from that of the tunnel barrier layer or to be in an amorphous state.

[0137] List of reference numerals

[0138] 1 Storage system

[0139] 3 Storage control unit

[0140] 10 Storage cell array

[0141] 100 Storage cell

[0142] 120 Magnetic storage element

[0143] 121 Bottom layer

[0144] 122, 123 Storage layer

[0145] 124 Tunnel barrier layer

[0146] 125, 126 Reference layer

[0147] 127 Spacer layer

[0148] 128 Fixed layer

[0149] 129 Capping layer

[0150] 131 Voltage modulation enhancement layer

[0151] 132 Intermediate layer.

Claims

1. A magnetic storage element, comprising: A storage layer having a variable magnetization direction and a voltage-controlled magnetic anisotropy effect; A reference layer having an invariant magnetization direction; A tunnel barrier layer disposed between the storage layer and the reference layer; And A bottom layer disposed below the storage layer, wherein, The storage layer is configured to have a B content of 10 at% or less, and The bottom layer is configured to have an orientation different from that of the tunnel barrier layer or to be in an amorphous state.

2. The magnetic storage element according to claim 1, wherein, The tunnel barrier layer is configured to have a (001) orientation.

3. The magnetic storage element according to claim 1, wherein, In the storage layer, the surface facing the tunnel barrier layer has a (001) orientation.

4. The magnetic storage element according to claim 3, wherein The storage layer is formed as an amorphous state, and the surface facing the tunnel barrier layer is (001) oriented by heat treatment.

5. The magnetic storage element according to claim 4, wherein, The storage layer is formed as the amorphous state by at least one of the following: cooling in the film formation step of the storage layer and cooling of the substrate in a step before the film formation step.

6. The magnetic storage element according to claim 5, wherein, The storage layer is formed as the amorphous state by cooling at 0°C or below.

7. The magnetic storage element according to claim 1, wherein, The storage layer is configured to contain CoFe.

8. The magnetic storage element according to claim 1, wherein, The tunnel barrier layer is made of an oxide of at least one of the following: Mg, Ca, Li, Si, Sr, Zr, Hf, Ti, Sc, La, Ta, Eu, Cu, Ba, Mo, W, V, Y, Ni, Co, Mn, Cr, and Fe.

9. The magnetic storage element according to claim 1, further comprising a voltage modulation enhancement layer disposed between the storage layer and the tunnel barrier layer.

10. The magnetic storage element according to claim 9, wherein, The voltage modulation enhancement layer is made of at least one of the following or an oxide of at least one of the following: Ir, Os, Pt, Rh, Hf, Zr, Ti, Ta, W, Re, Au, Mo, Ru, Pd, Y, V, Sc, Gd, Tb, La, Mg, Al, Ag, Cu, Cr, Co, Fe, and Ni.

11. A storage system, comprising: A magnetic storage element, the magnetic storage element comprising: A storage layer having a variable magnetization direction and a voltage-controlled magnetic anisotropy effect, A reference layer having an invariant magnetization direction, A tunnel barrier layer disposed between the storage layer and the reference layer, and A bottom layer disposed below the storage layer; and A storage control unit that controls writing and reading of data in the magnetic storage element, wherein, The storage layer is configured to have a B content of 10 at% or less, and The bottom layer is configured to have an orientation different from that of the tunnel barrier layer or to be in an amorphous state.

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